From d41aa87d6b1164666c9f013a785bc6217ae1ced2 Mon Sep 17 00:00:00 2001 From: Julien Brianceau Date: Fri, 5 Sep 2014 10:44:35 +0200 Subject: [mips] Fix unaligned access in Low Level Interpreter (LLINT). Address loads used with btbxx opcodes were wrongly converted to lw instruction instead of lbu, leading to unaligned access on mips platforms. Change-Id: I7b14aa40215affe582bcadade2f783769a97a7d3 Reviewed-by: Jocelyn Turcotte --- Source/JavaScriptCore/offlineasm/mips.rb | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Source/JavaScriptCore/offlineasm/mips.rb b/Source/JavaScriptCore/offlineasm/mips.rb index c0adfd029..08fd02662 100644 --- a/Source/JavaScriptCore/offlineasm/mips.rb +++ b/Source/JavaScriptCore/offlineasm/mips.rb @@ -231,9 +231,10 @@ def lowerMIPSCondBranch(list, condOp, node) [node.operands[0], MIPS_ZERO_REG, node.operands[-1]], node.annotation) elsif node.operands.size == 3 + tl = condOp[-1, 1] tmp = Tmp.new(node.codeOrigin, :gpr) list << Instruction.new(node.codeOrigin, - "andi", + "and" + tl, [node.operands[0], node.operands[1], tmp], node.annotation) list << Instruction.new(node.codeOrigin, @@ -503,6 +504,10 @@ def mipsLowerMisplacedAddresses(list) newList << Instruction.new(node.codeOrigin, node.opcode, riscAsRegisters(newList, [], node.operands, "b")) + when "andb" + newList << Instruction.new(node.codeOrigin, + "andi", + riscAsRegisters(newList, [], node.operands, "b")) when /^(bz|bnz|bs|bo)/ tl = $~.post_match == "" ? "i" : $~.post_match newList << Instruction.new(node.codeOrigin, -- cgit v1.2.3