diff options
author | Philip Reames <preames@rivosinc.com> | 2024-04-23 07:32:30 -0700 |
---|---|---|
committer | Philip Reames <listmail@philipreames.com> | 2024-04-23 07:36:24 -0700 |
commit | 282ab543a92740100c1119c701258c2900c5d00c (patch) | |
tree | 25bbf96300cb8510ffa352d4aae6fe2e1db04164 | |
parent | b4a0fd40f1b94eac571d29ee7695b492934d9bfc (diff) |
[RISCV] Add additional mul strength reduction coverage with xtheadba
-rw-r--r-- | llvm/test/CodeGen/RISCV/rv64xtheadba.ll | 177 |
1 files changed, 177 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadba.ll b/llvm/test/CodeGen/RISCV/rv64xtheadba.ll index 1450c86c76d0..46e474a2d1ed 100644 --- a/llvm/test/CodeGen/RISCV/rv64xtheadba.ll +++ b/llvm/test/CodeGen/RISCV/rv64xtheadba.ll @@ -252,6 +252,183 @@ define i64 @addmul72(i64 %a, i64 %b) { ret i64 %d } +define i64 @mul11(i64 %a) { +; RV64I-LABEL: mul11: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 11 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64XTHEADBA-LABEL: mul11: +; RV64XTHEADBA: # %bb.0: +; RV64XTHEADBA-NEXT: th.addsl a1, a0, a0, 2 +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a1, 1 +; RV64XTHEADBA-NEXT: ret + %c = mul i64 %a, 11 + ret i64 %c +} + +define i64 @mul19(i64 %a) { +; RV64I-LABEL: mul19: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 19 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64XTHEADBA-LABEL: mul19: +; RV64XTHEADBA: # %bb.0: +; RV64XTHEADBA-NEXT: th.addsl a1, a0, a0, 3 +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a1, 1 +; RV64XTHEADBA-NEXT: ret + %c = mul i64 %a, 19 + ret i64 %c +} + +define i64 @mul13(i64 %a) { +; RV64I-LABEL: mul13: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 13 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64XTHEADBA-LABEL: mul13: +; RV64XTHEADBA: # %bb.0: +; RV64XTHEADBA-NEXT: th.addsl a1, a0, a0, 1 +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a1, 2 +; RV64XTHEADBA-NEXT: ret + %c = mul i64 %a, 13 + ret i64 %c +} + +define i64 @mul21(i64 %a) { +; RV64I-LABEL: mul21: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 21 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64XTHEADBA-LABEL: mul21: +; RV64XTHEADBA: # %bb.0: +; RV64XTHEADBA-NEXT: th.addsl a1, a0, a0, 2 +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a1, 2 +; RV64XTHEADBA-NEXT: ret + %c = mul i64 %a, 21 + ret i64 %c +} + +define i64 @mul37(i64 %a) { +; RV64I-LABEL: mul37: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 37 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64XTHEADBA-LABEL: mul37: +; RV64XTHEADBA: # %bb.0: +; RV64XTHEADBA-NEXT: th.addsl a1, a0, a0, 3 +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a1, 2 +; RV64XTHEADBA-NEXT: ret + %c = mul i64 %a, 37 + ret i64 %c +} + +define i64 @mul25(i64 %a) { +; RV64I-LABEL: mul25: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 25 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64XTHEADBA-LABEL: mul25: +; RV64XTHEADBA: # %bb.0: +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 +; RV64XTHEADBA-NEXT: ret + %c = mul i64 %a, 25 + ret i64 %c +} + +define i64 @mul41(i64 %a) { +; RV64I-LABEL: mul41: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 41 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64XTHEADBA-LABEL: mul41: +; RV64XTHEADBA: # %bb.0: +; RV64XTHEADBA-NEXT: th.addsl a1, a0, a0, 2 +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a1, 3 +; RV64XTHEADBA-NEXT: ret + %c = mul i64 %a, 41 + ret i64 %c +} + +define i64 @mul73(i64 %a) { +; RV64I-LABEL: mul73: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 73 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64XTHEADBA-LABEL: mul73: +; RV64XTHEADBA: # %bb.0: +; RV64XTHEADBA-NEXT: th.addsl a1, a0, a0, 3 +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a1, 3 +; RV64XTHEADBA-NEXT: ret + %c = mul i64 %a, 73 + ret i64 %c +} + +define i64 @mul27(i64 %a) { +; RV64I-LABEL: mul27: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 27 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64XTHEADBA-LABEL: mul27: +; RV64XTHEADBA: # %bb.0: +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a0, 3 +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a0, 1 +; RV64XTHEADBA-NEXT: ret + %c = mul i64 %a, 27 + ret i64 %c +} + +define i64 @mul45(i64 %a) { +; RV64I-LABEL: mul45: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 45 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64XTHEADBA-LABEL: mul45: +; RV64XTHEADBA: # %bb.0: +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a0, 3 +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a0, 2 +; RV64XTHEADBA-NEXT: ret + %c = mul i64 %a, 45 + ret i64 %c +} + +define i64 @mul81(i64 %a) { +; RV64I-LABEL: mul81: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 81 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64XTHEADBA-LABEL: mul81: +; RV64XTHEADBA: # %bb.0: +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a0, 3 +; RV64XTHEADBA-NEXT: th.addsl a0, a0, a0, 3 +; RV64XTHEADBA-NEXT: ret + %c = mul i64 %a, 81 + ret i64 %c +} + + define i64 @mul96(i64 %a) { ; RV64I-LABEL: mul96: ; RV64I: # %bb.0: |