diff options
| author | Craig Topper <craig.topper@sifive.com> | 2024-01-05 09:22:54 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-05 09:22:54 -0800 |
| commit | 4dd5d967975fa8d52b8c60596d892d9dd5615809 (patch) | |
| tree | de2d0e3dc4cce77f905bb5fd6749b2e3d099ea37 | |
| parent | c49965b97e159b7ff92a5fca3e144b2d2574a84d (diff) | |
[RISCV] Don't call use_nodbg_operands for physical registers in RISCVOptWInstrs hasAllNBitUsers. (#77032)
The ADDIW in the new test case was incorrectly removed due to
incorrectly following the x10 register from the return value back to the
argument. This is due to use_nodbg_operands returning every instruction
that uses a physical register regardless of the data flow.
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/opt-w-instrs.mir | 20 |
2 files changed, 25 insertions, 1 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp index 2c2b34bb5b77..c16eee67f3c5 100644 --- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp +++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp @@ -126,7 +126,11 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI, if (MI->getNumExplicitDefs() != 1) return false; - for (auto &UserOp : MRI.use_nodbg_operands(MI->getOperand(0).getReg())) { + Register DestReg = MI->getOperand(0).getReg(); + if (!DestReg.isVirtual()) + return false; + + for (auto &UserOp : MRI.use_nodbg_operands(DestReg)) { const MachineInstr *UserMI = UserOp.getParent(); unsigned OpIdx = UserOp.getOperandNo(); diff --git a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir index 0ecf8fd6bef3..ebac5a42fbcd 100644 --- a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir +++ b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir @@ -28,3 +28,23 @@ body: | $x11 = COPY %4 PseudoRET ... + +--- +name: physreg +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x10, $x11 + + ; CHECK-ZFA-LABEL: name: physreg + ; CHECK-ZFA: liveins: $x10, $x11 + ; CHECK-ZFA-NEXT: {{ $}} + ; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-ZFA-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0 + ; CHECK-ZFA-NEXT: $x10 = COPY [[ADDIW]] + ; CHECK-ZFA-NEXT: PseudoRET + %0:gpr = COPY $x10 + %1:gpr = ADDIW %0, 0 + $x10 = COPY %1 + PseudoRET +... |