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authorEvan Cheng <evan.cheng@apple.com>2008-10-13 18:35:52 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-10-13 18:35:52 +0000
commit4c499c4fa66a4c0557c135337974da5ee424e338 (patch)
tree9d69d7ccdb0f61b606fa90b51620417e8fc8280d /llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
parentb34d5906b86c5e6c0b5cd7cf185d254ee05e2dee (diff)
Also update sub-register intervals after a trivial computation is rematt'ed for a copy instruction. PR2775.
llvm-svn: 57458
Diffstat (limited to 'llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp')
-rw-r--r--llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp10
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp b/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
index bb860d293e55..2f2d549a1952 100644
--- a/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -460,6 +460,16 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
unsigned DefIdx = li_->getDefIndex(CopyIdx);
const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
DLR->valno->copy = NULL;
+ // Don't forget to update sub-register intervals.
+ if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
+ for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
+ if (!li_->hasInterval(*SR))
+ continue;
+ DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
+ if (DLR && DLR->valno->copy == CopyMI)
+ DLR->valno->copy = NULL;
+ }
+ }
MachineBasicBlock::iterator MII = CopyMI;
MachineBasicBlock *MBB = CopyMI->getParent();