diff options
| author | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-05-17 09:32:58 +0000 |
|---|---|---|
| committer | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-05-17 09:32:58 +0000 |
| commit | 6bb068f15cef8fdda748c04e89c3bbba68b09f6a (patch) | |
| tree | e0af6d64bda0c923bf37d943e8a006b987a2d4af /test/MC/Mips/micromips-dspr2 | |
| parent | 4bfd3e29b1dba5869d8b8e83b4147be27707434d (diff) | |
[mips][microMIPS][DSP] Implement BALIGN, BITREV, BPOSGE32, CMP*, CMPGDU*, CMPGU* and CMPU* instructions
Differential Revision: http://reviews.llvm.org/D16182
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269752 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Mips/micromips-dspr2')
| -rw-r--r-- | test/MC/Mips/micromips-dspr2/invalid.s | 4 | ||||
| -rw-r--r-- | test/MC/Mips/micromips-dspr2/valid.s | 14 |
2 files changed, 18 insertions, 0 deletions
diff --git a/test/MC/Mips/micromips-dspr2/invalid.s b/test/MC/Mips/micromips-dspr2/invalid.s index 53ea3f0e514e..e98e5ff2436f 100644 --- a/test/MC/Mips/micromips-dspr2/invalid.s +++ b/test/MC/Mips/micromips-dspr2/invalid.s @@ -1,6 +1,8 @@ # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 2>%t1 # RUN: FileCheck %s < %t1 + balign $2, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate + balign $2, $3, 4 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate shra.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shra.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shra_r.qb $3, $4, 8 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate @@ -13,3 +15,5 @@ mulsa.w.ph $31, $3, $2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction mulsaq_s.w.ph $8, $3, $2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction mulsaq_s.w.ph $31, $3, $2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction + # bposge32 is microMIPS DSP instruction but it is removed in Release 6 + bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/micromips-dspr2/valid.s b/test/MC/Mips/micromips-dspr2/valid.s index fd3e397eb99e..19c91fe7e14c 100644 --- a/test/MC/Mips/micromips-dspr2/valid.s +++ b/test/MC/Mips/micromips-dspr2/valid.s @@ -127,3 +127,17 @@ wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c] append $3, $4, 5 # CHECK: append $3, $4, 5 # encoding: [0x00,0x64,0x2a,0x15] mulsa.w.ph $ac0, $3, $2 # CHECK: mulsa.w.ph $ac0, $3, $2 # encoding: [0x00,0x43,0x2c,0xbc] + balign $2, $3, 3 # CHECK: balign $2, $3, 3 # encoding: [0x00,0x43,0xc8,0xbc] + bitrev $2, $3 # CHECK: bitrev $2, $3 # encoding: [0x00,0x43,0x31,0x3c] + cmp.eq.ph $2, $3 # CHECK: cmp.eq.ph $2, $3 # encoding: [0x00,0x62,0x00,0x05] + cmp.le.ph $2, $3 # CHECK: cmp.le.ph $2, $3 # encoding: [0x00,0x62,0x00,0x85] + cmp.lt.ph $2, $3 # CHECK: cmp.lt.ph $2, $3 # encoding: [0x00,0x62,0x00,0x45] + cmpgdu.eq.qb $1, $2, $3 # CHECK: cmpgdu.eq.qb $1, $2, $3 # encoding: [0x00,0x62,0x09,0x85] + cmpgdu.lt.qb $1, $2, $3 # CHECK: cmpgdu.lt.qb $1, $2, $3 # encoding: [0x00,0x62,0x09,0xc5] + cmpgdu.le.qb $1, $2, $3 # CHECK: cmpgdu.le.qb $1, $2, $3 # encoding: [0x00,0x62,0x0a,0x05] + cmpgu.eq.qb $1, $2, $3 # CHECK: cmpgu.eq.qb $1, $2, $3 # encoding: [0x58,0x62,0x08,0xc5] + cmpgu.lt.qb $1, $2, $3 # CHECK: cmpgu.lt.qb $1, $2, $3 # encoding: [0x58,0x62,0x09,0x05] + cmpgu.le.qb $1, $2, $3 # CHECK: cmpgu.le.qb $1, $2, $3 # encoding: [0x58,0x62,0x09,0x45] + cmpu.eq.qb $1, $2 # CHECK: cmpu.eq.qb $1, $2 # encoding: [0x00,0x41,0x02,0x45] + cmpu.lt.qb $1, $2 # CHECK: cmpu.lt.qb $1, $2 # encoding: [0x00,0x41,0x02,0x85] + cmpu.le.qb $1, $2 # CHECK: cmpu.le.qb $1, $2 # encoding: [0x00,0x41,0x02,0xc5] |