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authorVasileios Kalintiris <Vasileios.Kalintiris@imgtec.com>2015-08-11 08:56:25 +0000
committerVasileios Kalintiris <Vasileios.Kalintiris@imgtec.com>2015-08-11 08:56:25 +0000
commite7b9d6cf4548f09973f4b31bda2d775e0d6fd631 (patch)
treea5b33cf6b08aaf461ab7f0c8e7541da483d8c5b6 /test/MC/Mips/mips3
parent18913db07a603b95b1459ec9112db794dad10fb8 (diff)
[mips] Remap move as or.
Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244579 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Mips/mips3')
-rw-r--r--test/MC/Mips/mips3/valid.s8
1 files changed, 4 insertions, 4 deletions
diff --git a/test/MC/Mips/mips3/valid.s b/test/MC/Mips/mips3/valid.s
index 1c878c97d158..cf51753712e6 100644
--- a/test/MC/Mips/mips3/valid.s
+++ b/test/MC/Mips/mips3/valid.s
@@ -142,10 +142,10 @@ a:
mflo $s1
mov.d $f20,$f14
mov.s $f2,$f27
- move $a0,$a3
- move $s5,$a0
- move $s8,$a0
- move $25,$a2
+ move $a0,$a3 # CHECK: move $4, $7 # encoding: [0x00,0xe0,0x20,0x25]
+ move $s5,$a0 # CHECK: move $21, $4 # encoding: [0x00,0x80,0xa8,0x25]
+ move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25]
+ move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25]
mtc1 $s8,$f9
mthi $s1
mtlo $sp