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path: root/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
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* Only check if coalescing is worthwhile when the result is targeting a more ↵Evan Cheng2009-01-231-1/+6
| | | | | | restrictive register class. llvm-svn: 62837
* Cross register class coalescing. Not yet enabled.Evan Cheng2009-01-231-94/+115
| | | | llvm-svn: 62832
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-28/+34
| | | | | | sub-register indices as well. llvm-svn: 62600
* Refactor code. No functionality change.Evan Cheng2009-01-201-34/+75
| | | | llvm-svn: 62573
* Use assertions to check for conditions that should never happen.Dan Gohman2009-01-131-12/+6
| | | | llvm-svn: 62178
* Un-tabify.Evan Cheng2009-01-131-1/+1
| | | | llvm-svn: 62151
* FIX llvm-gcc bootstrap on x86_64 linux. If a virtual register is copied to a ↵Evan Cheng2009-01-131-0/+13
| | | | | | physical register, it's not necessarily defined by a copy. We have to watch out it doesn't clobber any sub-register that might be live during its live interval. If the live interval crosses a basic block, then it's not safe to check with the less conservative check (by scanning uses and defs) because it's possible a sub-register might be live out of the block. llvm-svn: 62144
* The coalescer does not coalesce a virtual register to a physical register if ↵Evan Cheng2009-01-071-17/+35
| | | | | | | | | | | | | | any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away: v1024 = EDI // not killed = = EDI One possible solution is for the coalescer to examine the sub-register live intervals in the same manner as the physical register. Another possibility is to examine defs and uses (when needed) of sub-registers. Both solutions are too expensive. For now, look for "short virtual intervals" and scan instructions to look for conflict instead. This is a small win on x86-64. e.g. It shaves 403.gcc by ~80 instructions. llvm-svn: 61847
* squash warnings.Devang Patel2009-01-051-1/+1
| | | | llvm-svn: 61707
* Fix PR3149. If an early clobber def is a physical register and it is tied to ↵Evan Cheng2008-12-191-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | an input operand, it effectively extends the live range of the physical register. Currently we do not have a good way to represent this. 172 %ECX<def> = MOV32rr %reg1039<kill> 180 INLINEASM <es:subl $5,$1 sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>, 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0 188 %EAX<def> = MOV32rr %EAX<kill> 196 %ECX<def> = MOV32rr %ECX<kill> 204 %ECX<def> = MOV32rr %ECX<kill> 212 %EAX<def> = MOV32rr %EAX<kill> 220 %EAX<def> = MOV32rr %EAX 228 %reg1039<def> = MOV32rr %ECX<kill> The early clobber operand ties ECX input to the ECX def. The live interval of ECX is represented as this: %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47) The right way to represent this is something like %reg20,inf = [46,47:2)[174,182:1)[181:230:0) 0@174-(182) 1@181-230 @2@46-(47) Of course that won't work since that means overlapping live ranges defined by two val#. The workaround for now is to add a bit to val# which says the val# is redefined by a early clobber def somewhere. This prevents the move at 228 from being optimized away by SimpleRegisterCoalescing::AdjustCopiesBackFrom. llvm-svn: 61259
* Perform this loop only when the -debug flag is specified.Bill Wendling2008-12-191-5/+7
| | | | llvm-svn: 61238
* Remove val# defined by a remat'ed def that is now dead.Evan Cheng2008-10-271-2/+25
| | | | llvm-svn: 58294
* When the coalescer is doing rematerializing, have it removeDan Gohman2008-10-211-2/+3
| | | | | | | | | | | | | | | | | | | | the copy instruction from the instruction list before asking the target to create the new instruction. This gets the old instruction out of the way so that it doesn't interfere with the target's rematerialization code. In the case of x86, this helps it find more cases where EFLAGS is not live. Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check to see if it reached the end of the block after scanning each instruction, instead of just before. This lets it notice when the end of the block is only two instructions away, without doing any additional scanning. These changes allow rematerialization to clobber EFLAGS in more cases, for example using xor instead of mov to set the return value to zero in the included testcase. llvm-svn: 57872
* Also update sub-register intervals after a trivial computation is rematt'ed ↵Evan Cheng2008-10-131-0/+10
| | | | | | for a copy instruction. PR2775. llvm-svn: 57458
* fix typoChris Lattner2008-10-111-1/+1
| | | | llvm-svn: 57388
* Add an option to enable StrongPHIElimination, for ease of testing.Owen Anderson2008-10-071-1/+5
| | | | llvm-svn: 57259
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-5/+5
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Re-apply 56835 along with header file changes.Evan Cheng2008-09-301-1/+2
| | | | llvm-svn: 56848
* Revert commit 56835 since it breaks the build.Duncan Sands2008-09-301-2/+1
| | | | | | | | | | "If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it". llvm-svn: 56837
* If a re-materializable instruction has a register operand, the spiller will ↵Evan Cheng2008-09-301-1/+2
| | | | | | change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it. llvm-svn: 56835
* Next round of earlyclobber handling. Approach theDale Johannesen2008-09-241-12/+0
| | | | | | | | | | RA problem by expanding the live interval of an earlyclobber def back one slot. Remove overlap-earlyclobber throughout. Remove earlyclobber bits and their handling from live internals. llvm-svn: 56539
* Mark several codegen passes as preserving all analysis.Evan Cheng2008-09-221-2/+2
| | | | llvm-svn: 56469
* Teach coalescer about earlyclobber bits.Dale Johannesen2008-09-201-0/+12
| | | | | | Check bits for preferred register. llvm-svn: 56384
* Continue after removing the current MI.Evan Cheng2008-09-191-0/+1
| | | | llvm-svn: 56372
* Re-materalized definition instructions may be dead. Whack them.Evan Cheng2008-09-191-7/+29
| | | | llvm-svn: 56352
* Unallocatable registers do not have live intervals.Evan Cheng2008-09-171-1/+3
| | | | llvm-svn: 56287
* Correctly update kill infos after extending a live range and merge 2 val#'s; ↵Evan Cheng2008-09-151-3/+8
| | | | | | fix 56165 - do not mark val# copy field if the copy does not define the val#. llvm-svn: 56199
* Remove isImm(), isReg(), and friends, in favor of Dan Gohman2008-09-131-2/+2
| | | | | | | | | isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. llvm-svn: 56189
* On some targets, non-move instructions can become move instructions because ↵Evan Cheng2008-09-121-14/+28
| | | | | | | | | | | | of coalescing. e.g. vr2 = OR vr0, vr1 => vr2 = OR vr1, vr1 // after coalescing vr0 with vr1 Update the value# of the destination register with the copy instruction if that happens. llvm-svn: 56165
* Fix PR2748. Avoid coalescing physical register with virtual register which ↵Evan Cheng2008-09-111-0/+63
| | | | | | | | | | | would create illegal extract_subreg. e.g. vr1024 = extract_subreg vr1025, 1 ... vr1024 = mov8rr AH If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH. llvm-svn: 56118
* Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister ↵Evan Cheng2008-09-111-1/+2
| | | | | | check. llvm-svn: 56112
* Fix a bug in the coalescer where it didn't check if a live interval existed ↵Owen Anderson2008-09-101-1/+1
| | | | | | | | before trying to manipulate it. This was exposed by fast isel's handling of shifts on X86-64. With this, FreeBench/pcompress2 passes on X86-64 in fast isel. llvm-svn: 56067
* Fix typo.Evan Cheng2008-09-101-2/+2
| | | | llvm-svn: 56037
* Clear preference when it no longer makes sense.Evan Cheng2008-09-091-0/+8
| | | | llvm-svn: 56019
* Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer ↵Evan Cheng2008-08-301-4/+76
| | | | | | the implicit defs onto the remat'ed instruction. llvm-svn: 55564
* Revert r55467; it causes regressions in UnitTests/Vector/divides,Dan Gohman2008-08-281-61/+4
| | | | | | Benchmarks/sim/sim, and others on x86-64. llvm-svn: 55475
* If a copy isn't coalesced, but its src is defined by trivial computation. ↵Evan Cheng2008-08-281-4/+61
| | | | | | Re-materialize the src to replace the copy. llvm-svn: 55467
* Convert uses of std::vector in TargetInstrInfo to SmallVector. This change ↵Owen Anderson2008-08-141-1/+1
| | | | | | had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
* Use empty() instead of begin() == end().Dan Gohman2008-08-141-2/+2
| | | | llvm-svn: 54780
* Make the allocation of LiveIntervals explicit, rather than holding them in ↵Owen Anderson2008-08-131-2/+2
| | | | | | | | the r2iMap_ by value. This will prevent references to them from being invalidated if the map is changed. llvm-svn: 54763
* Remove #if 0.Evan Cheng2008-08-051-5/+0
| | | | llvm-svn: 54347
* Fix PR2568: Fix bug that cause redudant kill marker after its live interval ↵Evan Cheng2008-08-051-1/+3
| | | | | | has been extended due to coalescing. llvm-svn: 54346
* Fix a compile-time regression introduced by my heuristic-changing patch. I ↵Owen Anderson2008-07-231-1/+1
| | | | | | | | | forgot to multiply the instruction count by a constant factor in a few places, which caused the register allocator to require many more iterations. llvm-svn: 53959
* Change the heuristics used in the coalescer, register allocator, and withinOwen Anderson2008-07-221-8/+8
| | | | | | | live intervals itself to use an instruction count approximation that is not affected by inserting empty indices. llvm-svn: 53937
* Subreg live interval valno may not have a corresponding def machineinstr ↵Evan Cheng2008-07-171-1/+1
| | | | | | since it's less precise. llvm-svn: 53734
* Use getMBBEndIdx rather than assuming that the end is right after the last ↵Owen Anderson2008-06-231-1/+1
| | | | | | instruction in the block. llvm-svn: 52649
* Undo spill weight tweak. Need to investigate the performance regressions.Evan Cheng2008-06-211-2/+1
| | | | llvm-svn: 52572
* Coalesce copy from one register class to a sub register class. e.g. ↵Evan Cheng2008-06-191-22/+85
| | | | | | X86::MOV16to16_. llvm-svn: 52480
* When extending a liveinterval by commuting, don't throw away the live ranges ↵Evan Cheng2008-06-171-2/+13
| | | | | | that are not affected. llvm-svn: 52430
* The coalescer doesn't need LiveVariables now that we have register use ↵Owen Anderson2008-05-301-14/+6
| | | | | | iterators. llvm-svn: 51790
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