| Commit message (Collapse) | Author | Age | Files | Lines |
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This patch adds the single operand form of the not alias to microMIPS and
MIPS along with additional tests.
This partially resolves PR/30381.
Thanks to Sean Bruno for reporting the issue!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@287097 91177308-0d34-0410-b5e6-96231b3b80d8
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Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for
architecture support and register usage.
Reviewers: vkalintiris, zoran.jovanoic
Differential Review: https://reviews.llvm.org/D24499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283334 91177308-0d34-0410-b5e6-96231b3b80d8
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This reverts commit r282485 which contain two patches instead of
one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@283327 91177308-0d34-0410-b5e6-96231b3b80d8
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Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for
architecture support and register usage.
Reviewers: vkalintiris, zoran.jovanoic
Differential Review: https://reviews.llvm.org/D24499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282485 91177308-0d34-0410-b5e6-96231b3b80d8
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This reverts commit r281022. Mips buildbot broke, due to unhandled register
class FCC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281033 91177308-0d34-0410-b5e6-96231b3b80d8
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As part of this effort, remove MipsFCmp nodes and use tablegen
patterns rather than custom lowering through C++.
Unexpectedly, this improves codesize for microMIPS as previous floating
point setcc expansions would materialize 0 and 1 into GPRs before using
the relevant mov[tf].[sd] instruction. Now $zero is used directly.
Reviewers: dsanders, vkalintiris, zoran.jovanovic
Differential Review: https://reviews.llvm.org/D23118
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281022 91177308-0d34-0410-b5e6-96231b3b80d8
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Reviewers: dsanders, vkalintiris
Differential Review: https://reviews.llvm.org/D23121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@278930 91177308-0d34-0410-b5e6-96231b3b80d8
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Add the instruction alias sgtu (register form only), two operand forms of
s[rl]l and sra, and missing single/two operand forms of dnegu/neg.
Reviewers: dsanders
Differential Revision: https://reviews.llvm.org/D22752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276736 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own
($).
This fixes the majority of object differences between -fintegrated-as and
-fno-integrated-as.
Reviewers: sdardis
Subscribers: dsanders, sdardis, llvm-commits
Differential Revision: https://reviews.llvm.org/D22412
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275967 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
The backend has no reason to behave like a driver and should generally do
as it's told (and error out if it can't) instead of trying to figure out
what the API user meant. The default ABI is still derived from the arch
component as a concession to backwards compatibility.
API-users that previously passed an explicit CPU and a triple that was
inconsistent with the CPU (e.g. mips-linux-gnu and mips64r2) may get a
different ABI to what they got before. However, it's expected that there
are no such users on the basis that CodeGen has been asserting that the
triple is consistent with the selected ABI for several releases. API-users
that were consistent or passed '' or 'generic' as the CPU will see no
difference.
Reviewers: sdardis, rafael
Subscribers: rafael, dsanders, sdardis, llvm-commits
Differential Revision: http://reviews.llvm.org/D21466
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273557 91177308-0d34-0410-b5e6-96231b3b80d8
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The isMemWithSimmOffset predicate rejects relocations which is incorrect
behaviour. Linkers and other tools should handle|warn|error when the
field overflows.
Reviewers: dsanders, vkalintiris
Differential Revision: http://reviews.llvm.org/D20727
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270995 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
Reviewers: vkalintiris
Subscribers: llvm-commits, dsanders
Differential Revision: http://reviews.llvm.org/D17725
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@263427 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when
printing assembly. This came up when replacing
MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary
bit widths.
MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been
removed.
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D15521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262231 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
Previously, it would always select DEXT and substitute any invalid matches
for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works
but causes problems when adding range checked immediates to IAS.
Now isel selects the correct variant up front.
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D16810
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262229 91177308-0d34-0410-b5e6-96231b3b80d8
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Author: obucina
Reviewers: dsanders
Differential Revision: http://reviews.llvm.org/D15745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@261529 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
It actually takes an offset into the current PC-region.
This fixes the 'expr' command in lldb.
Reviewers: vkalintiris, jaydeep, bhushan
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D16054
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@257339 91177308-0d34-0410-b5e6-96231b3b80d8
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for EXT and DEXT* instructions
Differential Revision: http://reviews.llvm.org/D15570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256152 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
We don't check the size operand on ext/dext*/ins/dins* yet because the
permitted range depends on the pos argument and we can't check that using
this mechanism.
The bug was that dextu/dinsu accepted 0..31 in the pos operand instead of 32..63.
Reviewers: vkalintiris
Subscribers: llvm-commits, dsanders
Differential Revision: http://reviews.llvm.org/D15190
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255015 91177308-0d34-0410-b5e6-96231b3b80d8
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valid-xfail.s's.
Summary:
valid-xfail.s is for instructions that should be valid in the given ISA but
incorrectly fail. DSP/DSPr2 instructions are correct to fail since DSP/DSPr2 is
not enabled.
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D15072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254911 91177308-0d34-0410-b5e6-96231b3b80d8
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valid-xfail.s is for instructions that should be valid in the given ISA but
incorrectly fail. MSA instructions are correct to fail since MSA is not enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254293 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
The bugs were:
* append, prepend, and balign were not tested
* balign takes a uimm2 not a uimm5.
* drotr32 was correctly implemented with a uimm5 but the tests expected
'52' to be valid.
* li/la were implemented with a uimm5 instead of simm32. simm32 isn't
completely correct either but I'll fix that when I get to simm32.
A notable omission are some of the shift instructions. Several of these
have been implemented using a single uimm6 instruction (rather than two
uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated
in the uimm6 patch.
Reviewers: vkalintiris
Subscribers: llvm-commits, dsanders
Differential Revision: http://reviews.llvm.org/D14712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254164 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
Added support for the following instructions:
CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF
This required adding some infrastructure for the EVA ASE.
Patch by Scott Egerton.
Reviewers: vkalintiris, dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11139
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247669 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or
'addu'. The use of addu/daddu instead of or as move was highlighted as a
performance issue during the analysis of a recent 64bit design. Originally
move was encoded as 'or' by binutils but was changed for the r10k cpu family
due to their pipeline which had 2 arithmetic units and a single logical unit,
and so could issue multiple (d)addu based moves at the same time but only 1
logical move.
This patch preserves the disassembly behaviour so that disassembling a old style
(d)addu move still appears as move, but assembling move always gives an or
Patch by Simon Dardis.
Reviewers: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11796
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244579 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
Previously it (incorrectly) used GPR's.
Patch by Simon Dardis. A couple small corrections by myself.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240883 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
This required adding instruction aliases for dneg.
N64 will be enabled shortly but requires additional bugfixes.
Reviewers: vkalintiris
Reviewed By: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D9341
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236489 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs.
For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D8300
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234398 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58".
This should work for all MIPS ISAs.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D8284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232473 91177308-0d34-0410-b5e6-96231b3b80d8
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mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230500 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228403 91177308-0d34-0410-b5e6-96231b3b80d8
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Patch by Amaury Pouly
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6421
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222899 91177308-0d34-0410-b5e6-96231b3b80d8
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The original commit r221299 was reverted in r221307. I removed the name
"hrw_ulr" ($29) from the original commit because two tests were failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221681 91177308-0d34-0410-b5e6-96231b3b80d8
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This reverts commit r221299.
The tests
LLVM :: MC/Disassembler/Mips/mips32.txt
LLVM :: MC/Disassembler/Mips/mips32_le.txt
were failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221307 91177308-0d34-0410-b5e6-96231b3b80d8
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Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221299 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary: Depends on D5782
Reviewers: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5802
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220042 91177308-0d34-0410-b5e6-96231b3b80d8
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Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220036 91177308-0d34-0410-b5e6-96231b3b80d8
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Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D5751
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219927 91177308-0d34-0410-b5e6-96231b3b80d8
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MipsInstrInfo.td.
Patch by Vasileios Kalintiris.
Differential Revision: http://reviews.llvm.org/D5244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217868 91177308-0d34-0410-b5e6-96231b3b80d8
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Mips64R6.
Patch by Vasileios Kalintiris.
Differential Revision: http://reviews.llvm.org/D5242
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217867 91177308-0d34-0410-b5e6-96231b3b80d8
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Patch by Vasileios Kalintiris.
Differential Revision: http://reviews.llvm.org/D5239
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217770 91177308-0d34-0410-b5e6-96231b3b80d8
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Patch by Vasileios Kalintiris.
Reviewers: dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D5173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217255 91177308-0d34-0410-b5e6-96231b3b80d8
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accept default cc0 register...
It causes a number of regressions when -fintegrated-as is enabled. This happens
because there are codegen-only instructions that incorrectly uses the first
operand as the encoding for the $fcc register. The regressions do not occur when
-via-file-asm is also given.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215847 91177308-0d34-0410-b5e6-96231b3b80d8
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register. This patch enables the instruction to accept other fcc registers. The aliases with default fcc0 registers are also defined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215698 91177308-0d34-0410-b5e6-96231b3b80d8
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.reginfo/.MIPS.options
This abstraction allows us to support the various records that can be placed in
the .MIPS.options section in the future. We currently use it to record register
usage information (the ODK_REGINFO record in our ELF64 spec).
Each .MIPS.options record should subclass MipsOptionRecord and provide an
implementation of EmitMipsOptionRecord.
Patch by Matheus Almeida and Toma Tabacu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213522 91177308-0d34-0410-b5e6-96231b3b80d8
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.data, .reginfo, .MIPS.options, and .MIPS.abiflags
The lld tests will temporarily fail again but Simon Atanasyan will commit a fix for those shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212946 91177308-0d34-0410-b5e6-96231b3b80d8
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.data, .reginfo, .MIPS.options, and .MIPS.abiflags
This commit causes multiple lld tests to fail. Reverting while I investigate the issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212945 91177308-0d34-0410-b5e6-96231b3b80d8
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.reginfo, .MIPS.options, and .MIPS.abiflags
Summary:
.bss, .text, and .data are at least 16-byte aligned.
.reginfo is 4-byte aligned and has a 24-byte EntrySize.
.MIPS.abiflags has an 24-byte EntrySize.
.MIPS.options is 8-byte aligned and has 1-byte EntrySize.
Using a 1-byte EntrySize for .MIPS.options seems strange because the
records are neither 1-byte long nor fixed-length but this matches the value
that GAS emits.
Differential Revision: http://reviews.llvm.org/D4487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212939 91177308-0d34-0410-b5e6-96231b3b80d8
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'.module oddspreg' is used
Differential Revision: http://reviews.llvm.org/D4486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212932 91177308-0d34-0410-b5e6-96231b3b80d8
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obj2yaml and yaml2obj tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212908 91177308-0d34-0410-b5e6-96231b3b80d8
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all new modules. The section contains a versioned data structure which represents essentially information to allow a program loader to determine the requirements of the application. This patch implements mips.abiflags section and provides test cases for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212519 91177308-0d34-0410-b5e6-96231b3b80d8
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Summary:
This instruction is re-encoded in MIPS32r6/MIPS64r6 without changing the
restrictions. We hadn't implemented it for earlier ISA's so it has been added to those too.
Differential Revision: http://reviews.llvm.org/D4265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211590 91177308-0d34-0410-b5e6-96231b3b80d8
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