diff options
author | Chad Rosier <mcrosier@codeaurora.org> | 2013-12-16 18:29:54 +0000 |
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committer | Chad Rosier <mcrosier@codeaurora.org> | 2013-12-16 18:29:54 +0000 |
commit | 707f07ea4c883312abf6f94e74f54d262d7f7309 (patch) | |
tree | d12253a60c5d1b062fcfdf95096049de4d143206 | |
parent | a796d1e86f80cf9e2f84abbbb5bef8e7e5ed3cf8 (diff) |
[AArch64] Fix v1fx patterns for Floating-point Multiply Extend and Floating-point Compare to Zero.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@197403 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r-- | test/CodeGen/aarch64-neon-intrinsics.c | 7 | ||||
-rw-r--r-- | test/CodeGen/aarch64-neon-misc.c | 24 |
2 files changed, 30 insertions, 1 deletions
diff --git a/test/CodeGen/aarch64-neon-intrinsics.c b/test/CodeGen/aarch64-neon-intrinsics.c index cd59ab3aa7..c0bca67aaa 100644 --- a/test/CodeGen/aarch64-neon-intrinsics.c +++ b/test/CodeGen/aarch64-neon-intrinsics.c @@ -3110,7 +3110,6 @@ int32x4_t test_vqrdmulhq_s32(int32x4_t a, int32x4_t b) { // CHECK: sqrdmulh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s } - float32x2_t test_vmulx_f32(float32x2_t a, float32x2_t b) { // CHECK: test_vmulx_f32 return vmulx_f32(a, b); @@ -5694,6 +5693,12 @@ float64_t test_vmulxd_f64(float64_t a, float64_t b) { // CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} } +float64x1_t test_vmulx_f64(float64x1_t a, float64x1_t b) { +// CHECK: test_vmulx_f64 + return vmulx_f64(a, b); +// CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +} + float32_t test_vrecpss_f32(float32_t a, float32_t b) { // CHECK: test_vrecpss_f32 return vrecpss_f32(a, b); diff --git a/test/CodeGen/aarch64-neon-misc.c b/test/CodeGen/aarch64-neon-misc.c index 08174d91f8..8f59f6be7e 100644 --- a/test/CodeGen/aarch64-neon-misc.c +++ b/test/CodeGen/aarch64-neon-misc.c @@ -204,6 +204,12 @@ uint32x2_t test_vcgez_f32(float32x2_t a) { return vcgez_f32(a); } +// CHECK: test_vcgez_f64 +// CHECK: fcmge {{d[0-9]+}}, {{d[0-9]+}}, #0 +uint64x1_t test_vcgez_f64(float64x1_t a) { + return vcgez_f64(a); +} + // CHECK: test_vcgezq_f32 // CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0 uint32x4_t test_vcgezq_f32(float32x4_t a) { @@ -270,6 +276,12 @@ uint32x2_t test_vclez_f32(float32x2_t a) { return vclez_f32(a); } +// CHECK: test_vclez_f64 +// CHECK: fcmle {{d[0-9]+}}, {{d[0-9]+}}, #0 +uint64x1_t test_vclez_f64(float64x1_t a) { + return vclez_f64(a); +} + // CHECK: test_vclezq_f32 // CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0 uint32x4_t test_vclezq_f32(float32x4_t a) { @@ -336,6 +348,12 @@ uint32x2_t test_vcgtz_f32(float32x2_t a) { return vcgtz_f32(a); } +// CHECK: test_vcgtz_f64 +// CHECK: fcmgt {{d[0-9]+}}, {{d[0-9]+}}, #0 +uint64x1_t test_vcgtz_f64(float64x1_t a) { + return vcgtz_f64(a); +} + // CHECK: test_vcgtzq_f32 // CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0 uint32x4_t test_vcgtzq_f32(float32x4_t a) { @@ -401,6 +419,12 @@ uint64x2_t test_vcltzq_s64(int64x2_t a) { uint32x2_t test_vcltz_f32(float32x2_t a) { return vcltz_f32(a); } + +// CHECK: test_vcltz_f64 +// CHECK: fcmlt {{d[0-9]+}}, {{d[0-9]+}}, #0 +uint64x1_t test_vcltz_f64(float64x1_t a) { + return vcltz_f64(a); +} // CHECK: test_vcltzq_f32 // CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0 |