diff options
| author | Craig Topper <craig.topper@intel.com> | 2018-06-07 17:28:03 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-06-07 17:28:03 +0000 |
| commit | 3b4ec91916b5e5ea297fab01be9ebc3d5dcf32f6 (patch) | |
| tree | 72efd09857c3a73859c1fcbb602661d812bf6abf /include/clang/Basic/BuiltinsX86.def | |
| parent | e63bbc3a5282f86265da104a9f8b9a74c41fdf37 (diff) | |
[X86] Add back builtins for _mm_slli_si128/_mm_srli_si128 and similar intrinsics.
We still lower them to native shuffle IR, but we do it in CGBuiltin.cpp now. This allows us to check the target feature and ensure the immediate fits in 8 bits.
This also improves our -O0 codegen slightly because we're able to see the zeroinitializer in the shuffle. It looks like it got lost behind a store+load previously.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@334208 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/clang/Basic/BuiltinsX86.def')
| -rw-r--r-- | include/clang/Basic/BuiltinsX86.def | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/clang/Basic/BuiltinsX86.def b/include/clang/Basic/BuiltinsX86.def index 33dda55fe3..fb284d3de5 100644 --- a/include/clang/Basic/BuiltinsX86.def +++ b/include/clang/Basic/BuiltinsX86.def @@ -358,6 +358,8 @@ TARGET_BUILTIN(__builtin_ia32_psrlqi128, "V2LLiV2LLii", "nc", "sse2") TARGET_BUILTIN(__builtin_ia32_psrawi128, "V8sV8si", "nc", "sse2") TARGET_BUILTIN(__builtin_ia32_psradi128, "V4iV4ii", "nc", "sse2") TARGET_BUILTIN(__builtin_ia32_pmaddwd128, "V4iV8sV8s", "nc", "sse2") +TARGET_BUILTIN(__builtin_ia32_pslldqi128, "V2LLiV2LLiIi", "nc", "sse2") +TARGET_BUILTIN(__builtin_ia32_psrldqi128, "V2LLiV2LLiIi", "nc", "sse2") TARGET_BUILTIN(__builtin_ia32_monitor, "vv*UiUi", "n", "sse3") TARGET_BUILTIN(__builtin_ia32_mwait, "vUiUi", "n", "sse3") @@ -585,6 +587,7 @@ TARGET_BUILTIN(__builtin_ia32_psignw256, "V16sV16sV16s", "nc", "avx2") TARGET_BUILTIN(__builtin_ia32_psignd256, "V8iV8iV8i", "nc", "avx2") TARGET_BUILTIN(__builtin_ia32_psllwi256, "V16sV16si", "nc", "avx2") TARGET_BUILTIN(__builtin_ia32_psllw256, "V16sV16sV8s", "nc", "avx2") +TARGET_BUILTIN(__builtin_ia32_pslldqi256, "V4LLiV4LLiIi", "nc", "avx2") TARGET_BUILTIN(__builtin_ia32_pslldi256, "V8iV8ii", "nc", "avx2") TARGET_BUILTIN(__builtin_ia32_pslld256, "V8iV8iV4i", "nc", "avx2") TARGET_BUILTIN(__builtin_ia32_psllqi256, "V4LLiV4LLii", "nc", "avx2") @@ -593,6 +596,7 @@ TARGET_BUILTIN(__builtin_ia32_psrawi256, "V16sV16si", "nc", "avx2") TARGET_BUILTIN(__builtin_ia32_psraw256, "V16sV16sV8s", "nc", "avx2") TARGET_BUILTIN(__builtin_ia32_psradi256, "V8iV8ii", "nc", "avx2") TARGET_BUILTIN(__builtin_ia32_psrad256, "V8iV8iV4i", "nc", "avx2") +TARGET_BUILTIN(__builtin_ia32_psrldqi256, "V4LLiV4LLiIi", "nc", "avx2") TARGET_BUILTIN(__builtin_ia32_psrlwi256, "V16sV16si", "nc", "avx2") TARGET_BUILTIN(__builtin_ia32_psrlw256, "V16sV16sV8s", "nc", "avx2") TARGET_BUILTIN(__builtin_ia32_psrldi256, "V8iV8ii", "nc", "avx2") @@ -1352,6 +1356,8 @@ TARGET_BUILTIN(__builtin_ia32_psraw512, "V32sV32sV8s", "nc", "avx512bw") TARGET_BUILTIN(__builtin_ia32_psrawi512, "V32sV32si", "nc", "avx512bw") TARGET_BUILTIN(__builtin_ia32_psrlw512, "V32sV32sV8s", "nc", "avx512bw") TARGET_BUILTIN(__builtin_ia32_psrlwi512, "V32sV32si", "nc", "avx512bw") +TARGET_BUILTIN(__builtin_ia32_pslldqi512, "V8LLiV8LLiIi", "nc", "avx512bw") +TARGET_BUILTIN(__builtin_ia32_psrldqi512, "V8LLiV8LLiIi", "nc", "avx512bw") TARGET_BUILTIN(__builtin_ia32_movdqa32load128_mask, "V4iV4i*V4iUc", "n", "avx512vl") TARGET_BUILTIN(__builtin_ia32_movdqa32load256_mask, "V8iV8i*V8iUc", "n", "avx512vl") TARGET_BUILTIN(__builtin_ia32_movdqa32load512_mask, "V16iV16iC*V16iUs", "n", "avx512f") |