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| author | Luke Geeson <luke.geeson@arm.com> | 2018-06-12 09:54:27 +0000 |
|---|---|---|
| committer | Luke Geeson <luke.geeson@arm.com> | 2018-06-12 09:54:27 +0000 |
| commit | 362dc486cc5027ac5562131239604047e1352f50 (patch) | |
| tree | dce5c67ce862794e124e1248e4756cb20255c480 /include/clang/Basic/arm_fp16.td | |
| parent | cabce844f33a56eb517eee37c99192f34c5f9ee6 (diff) | |
[AArch64] Corrected FP16 Intrinsic range checks in Clang + added Sema tests
Summary:
This fixes the ranges for the vcvth family of FP16 intrinsics in the clang front end. Previously it was accepting incorrect ranges
-Changed builtin range checking in SemaChecking
-added tests SemaCheck changes - included in their own file since no similar one exists
-modified existing tests to reflect new ranges
Reviewers: SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Subscribers: kristof.beyls, cfe-commits
Differential Revision: https://reviews.llvm.org/D47592
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@334489 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/clang/Basic/arm_fp16.td')
| -rw-r--r-- | include/clang/Basic/arm_fp16.td | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/include/clang/Basic/arm_fp16.td b/include/clang/Basic/arm_fp16.td index 5c7e437b72..bc15a22d84 100644 --- a/include/clang/Basic/arm_fp16.td +++ b/include/clang/Basic/arm_fp16.td @@ -75,15 +75,15 @@ let ArchGuard = "defined(__ARM_FEATURE_FP16_SCALAR_ARITHMETIC) && defined(__aarc def SCALAR_FCVTPUH : SInst<"vcvtp_u16", "bs", "Sh">; def SCALAR_FCVTPUH1 : SInst<"vcvtp_u32", "Us", "Sh">; def SCALAR_FCVTPUH2 : SInst<"vcvtp_u64", "Os", "Sh">; - - def SCALAR_SCVTFSHO : SInst<"vcvth_n_f16", "Ysi", "silUsUiUl">; - def SCALAR_FCVTZSHO : SInst<"vcvt_n_s16", "$si", "Sh">; - def SCALAR_FCVTZSH1O: SInst<"vcvt_n_s32", "Isi", "Sh">; - def SCALAR_FCVTZSH2O: SInst<"vcvt_n_s64", "Lsi", "Sh">; - def SCALAR_FCVTZUHO : SInst<"vcvt_n_u16", "bsi", "Sh">; - def SCALAR_FCVTZUH1O: SInst<"vcvt_n_u32", "Usi", "Sh">; - def SCALAR_FCVTZUH2O: SInst<"vcvt_n_u64", "Osi", "Sh">; - + let isVCVT_N = 1 in { + def SCALAR_SCVTFSHO : SInst<"vcvth_n_f16", "Ysi", "silUsUiUl">; + def SCALAR_FCVTZSHO : SInst<"vcvt_n_s16", "$si", "Sh">; + def SCALAR_FCVTZSH1O: SInst<"vcvt_n_s32", "Isi", "Sh">; + def SCALAR_FCVTZSH2O: SInst<"vcvt_n_s64", "Lsi", "Sh">; + def SCALAR_FCVTZUHO : SInst<"vcvt_n_u16", "bsi", "Sh">; + def SCALAR_FCVTZUH1O: SInst<"vcvt_n_u32", "Usi", "Sh">; + def SCALAR_FCVTZUH2O: SInst<"vcvt_n_u64", "Osi", "Sh">; + } // Comparison def SCALAR_CMEQRH : SInst<"vceq", "bss", "Sh">; def SCALAR_CMEQZH : SInst<"vceqz", "bs", "Sh">; |