diff options
| author | Ivan A. Kosarev <ikosarev@accesssoftek.com> | 2018-06-02 17:42:59 +0000 |
|---|---|---|
| committer | Ivan A. Kosarev <ikosarev@accesssoftek.com> | 2018-06-02 17:42:59 +0000 |
| commit | ea8877c890e6c13133b7c36837a1dc9a771dc82f (patch) | |
| tree | 46e87c5b9825ecccc23b50f071709ef0a58861cf /include/clang/Basic/arm_neon.td | |
| parent | a07c88c0e8122047e77954a885af7dfc8bcdd87f (diff) | |
[NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)
We currently support them only in AArch64. The NEON Reference,
however, says they are 'ARMv7, ARMv8' intrinsics.
Differential Revision: https://reviews.llvm.org/D47121
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@333829 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/clang/Basic/arm_neon.td')
| -rw-r--r-- | include/clang/Basic/arm_neon.td | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/include/clang/Basic/arm_neon.td b/include/clang/Basic/arm_neon.td index fc9b6a40e5..9c149714f3 100644 --- a/include/clang/Basic/arm_neon.td +++ b/include/clang/Basic/arm_neon.td @@ -338,6 +338,12 @@ def VSLI_N : WInst<"vsli_n", "dddi", // E.3.14 Loads and stores of a single vector def VLD1 : WInst<"vld1", "dc", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; +def VLD1_X2 : WInst<"vld1_x2", "2c", + "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">; +def VLD1_X3 : WInst<"vld1_x3", "3c", + "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">; +def VLD1_X4 : WInst<"vld1_x4", "4c", + "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">; def VLD1_LANE : WInst<"vld1_lane", "dcdi", "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; def VLD1_DUP : WInst<"vld1_dup", "dc", @@ -569,11 +575,11 @@ def ST3 : WInst<"vst3", "vp3", "QUlQldQdPlQPl">; def ST4 : WInst<"vst4", "vp4", "QUlQldQdPlQPl">; def LD1_X2 : WInst<"vld1_x2", "2c", - "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; -def LD3_x3 : WInst<"vld1_x3", "3c", - "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; -def LD4_x4 : WInst<"vld1_x4", "4c", - "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; + "dQdPlQPl">; +def LD1_X3 : WInst<"vld1_x3", "3c", + "dQdPlQPl">; +def LD1_X4 : WInst<"vld1_x4", "4c", + "dQdPlQPl">; def ST1_X2 : WInst<"vst1_x2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; |