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authorAmara Emerson <amara.emerson@arm.com>2017-07-13 15:36:01 +0000
committerAmara Emerson <amara.emerson@arm.com>2017-07-13 15:36:01 +0000
commit5ad4badf506c242b1f135650107706e76d4c679c (patch)
tree992dd51d8eb1ec98e4d6c3de55f0ef12de54e1d8 /lib/Basic/Targets.cpp
parent5e8a1ecbb1a29682c12f7d8048a489ae2dc5ee8d (diff)
[AArch64] Add support for handling the +sve target feature.
This also adds the appropriate predefine for SVE if enabled. Differential Revision: https://reviews.llvm.org/D35118 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@307919 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Basic/Targets.cpp')
-rw-r--r--lib/Basic/Targets.cpp15
1 files changed, 11 insertions, 4 deletions
diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 50b4fc34ad..5418812178 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -6251,7 +6251,8 @@ class AArch64TargetInfo : public TargetInfo {
enum FPUModeEnum {
FPUMode,
- NeonMode
+ NeonMode = (1 << 0),
+ SveMode = (1 << 1)
};
unsigned FPU;
@@ -6385,12 +6386,15 @@ public:
Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
Opts.ShortEnums ? "1" : "4");
- if (FPU == NeonMode) {
+ if (FPU & NeonMode) {
Builder.defineMacro("__ARM_NEON", "1");
// 64-bit NEON supports half, single and double precision operations.
Builder.defineMacro("__ARM_NEON_FP", "0xE");
}
+ if (FPU & SveMode)
+ Builder.defineMacro("__ARM_FEATURE_SVE", "1");
+
if (CRC)
Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
@@ -6426,7 +6430,8 @@ public:
return Feature == "aarch64" ||
Feature == "arm64" ||
Feature == "arm" ||
- (Feature == "neon" && FPU == NeonMode);
+ (Feature == "neon" && (FPU & NeonMode)) ||
+ (Feature == "sve" && (FPU & SveMode));
}
bool handleTargetFeatures(std::vector<std::string> &Features,
@@ -6440,7 +6445,9 @@ public:
for (const auto &Feature : Features) {
if (Feature == "+neon")
- FPU = NeonMode;
+ FPU |= NeonMode;
+ if (Feature == "+sve")
+ FPU |= SveMode;
if (Feature == "+crc")
CRC = 1;
if (Feature == "+crypto")