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| author | Jina Nahias <jina.nahias@intel.com> | 2017-09-19 11:00:27 +0000 |
|---|---|---|
| committer | Jina Nahias <jina.nahias@intel.com> | 2017-09-19 11:00:27 +0000 |
| commit | d304062b8cf0086ef8a3a9b2dad8e41e037f66a5 (patch) | |
| tree | d505fd0427de07e1ef0d961cd12a1cef565e33a2 /lib/Headers/avx512vlbwintrin.h | |
| parent | 8b3beec43959d827795128837b6adc58cae027a2 (diff) | |
Lowering Mask Set1 intrinsics to LLVM IR
This patch, together with a matching llvm patch (https://reviews.llvm.org/D37669), implements the lowering of X86 mask set1 intrinsics to IR.
Differential Revision: https://reviews.llvm.org/D37668
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@313624 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Headers/avx512vlbwintrin.h')
| -rw-r--r-- | lib/Headers/avx512vlbwintrin.h | 50 |
1 files changed, 24 insertions, 26 deletions
diff --git a/lib/Headers/avx512vlbwintrin.h b/lib/Headers/avx512vlbwintrin.h index 3b58d04339..4ab785bdbb 100644 --- a/lib/Headers/avx512vlbwintrin.h +++ b/lib/Headers/avx512vlbwintrin.h @@ -2660,35 +2660,33 @@ _mm256_maskz_mov_epi8 (__mmask32 __U, __m256i __A) static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_mask_set1_epi8 (__m128i __O, __mmask16 __M, char __A) { - return (__m128i) __builtin_ia32_pbroadcastb128_gpr_mask (__A, - (__v16qi) __O, - __M); + return (__m128i) __builtin_ia32_selectb_128(__M, + (__v16qi) _mm_set1_epi8(__A), + (__v16qi) __O); } static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_maskz_set1_epi8 (__mmask16 __M, char __A) { - return (__m128i) __builtin_ia32_pbroadcastb128_gpr_mask (__A, - (__v16qi) - _mm_setzero_si128 (), - __M); + return (__m128i) __builtin_ia32_selectb_128(__M, + (__v16qi) _mm_set1_epi8(__A), + (__v16qi) _mm_setzero_si128()); } static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_mask_set1_epi8 (__m256i __O, __mmask32 __M, char __A) { - return (__m256i) __builtin_ia32_pbroadcastb256_gpr_mask (__A, - (__v32qi) __O, - __M); + return (__m256i) __builtin_ia32_selectb_256(__M, + (__v32qi) _mm256_set1_epi8(__A), + (__v32qi) __O); } static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_set1_epi8 (__mmask32 __M, char __A) { - return (__m256i) __builtin_ia32_pbroadcastb256_gpr_mask (__A, - (__v32qi) - _mm256_setzero_si256 (), - __M); + return (__m256i) __builtin_ia32_selectb_256(__M, + (__v32qi) _mm256_set1_epi8(__A), + (__v32qi) _mm256_setzero_si256()); } static __inline__ __m128i __DEFAULT_FN_ATTRS @@ -3025,33 +3023,33 @@ _mm256_maskz_broadcastw_epi16 (__mmask16 __M, __m128i __A) static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_mask_set1_epi16 (__m256i __O, __mmask16 __M, short __A) { - return (__m256i) __builtin_ia32_pbroadcastw256_gpr_mask (__A, - (__v16hi) __O, - __M); + return (__m256i) __builtin_ia32_selectw_256 (__M, + (__v16hi) _mm256_set1_epi16(__A), + (__v16hi) __O); } static __inline__ __m256i __DEFAULT_FN_ATTRS _mm256_maskz_set1_epi16 (__mmask16 __M, short __A) { - return (__m256i) __builtin_ia32_pbroadcastw256_gpr_mask (__A, - (__v16hi) _mm256_setzero_si256 (), - __M); + return (__m256i) __builtin_ia32_selectw_256(__M, + (__v16hi)_mm256_set1_epi16(__A), + (__v16hi) _mm256_setzero_si256()); } static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_mask_set1_epi16 (__m128i __O, __mmask8 __M, short __A) { - return (__m128i) __builtin_ia32_pbroadcastw128_gpr_mask (__A, - (__v8hi) __O, - __M); + return (__m128i) __builtin_ia32_selectw_128(__M, + (__v8hi) _mm_set1_epi16(__A), + (__v8hi) __O); } static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_maskz_set1_epi16 (__mmask8 __M, short __A) { - return (__m128i) __builtin_ia32_pbroadcastw128_gpr_mask (__A, - (__v8hi) _mm_setzero_si128 (), - __M); + return (__m128i) __builtin_ia32_selectw_128(__M, + (__v8hi) _mm_set1_epi16(__A), + (__v8hi) _mm_setzero_si128()); } static __inline__ __m128i __DEFAULT_FN_ATTRS |