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| author | Ekaterina Romanova <katya_romanova@playstation.sony.com> | 2017-02-01 07:37:40 +0000 |
|---|---|---|
| committer | Ekaterina Romanova <katya_romanova@playstation.sony.com> | 2017-02-01 07:37:40 +0000 |
| commit | 9eabc2fd30ea38ab8c9a308bf74f3c0cbb48a646 (patch) | |
| tree | f3e7a3bef26d08dde208c3ff4810eb37b473391f /lib/Headers | |
| parent | 86f6d4d8b89ad7ee724a4f7c408fe2587594acd2 (diff) | |
Doxygen comments for prfchwintrin.h
Added doxygen comments to prfchwintrin.h's intrinsics.
Note: The doxygen comments are automatically generated based on Sony's intrinsic
s document.
I got an OK from Eric Christopher to commit doxygen comments without prior code
review upstream.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@293745 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Headers')
| -rw-r--r-- | lib/Headers/prfchwintrin.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/lib/Headers/prfchwintrin.h b/lib/Headers/prfchwintrin.h index ba02857518..a3789126ef 100644 --- a/lib/Headers/prfchwintrin.h +++ b/lib/Headers/prfchwintrin.h @@ -29,12 +29,36 @@ #define __PRFCHWINTRIN_H #if defined(__PRFCHW__) || defined(__3dNOW__) +/// \brief Loads a memory sequence containing the specified memory address into +/// all data cache levels. The cache-coherency state is set to exclusive. +/// Data can be read from and written to the cache line without additional +/// delay. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the \c PREFETCHT0 instruction. +/// +/// \param __P +/// A pointer specifying the memory address to be prefetched. static __inline__ void __attribute__((__always_inline__, __nodebug__)) _m_prefetch(void *__P) { __builtin_prefetch (__P, 0, 3 /* _MM_HINT_T0 */); } +/// \brief Loads a memory sequence containing the specified memory address into +/// the L1 data cache and sets the cache-coherency to modified. This +/// provides a hint to the processor that the cache line will be modified. +/// It is intended for use when the cache line will be written to shortly +/// after the prefetch is performed. Note that the effect of this intrinsic +/// is dependent on the processor implementation. +/// +/// \headerfile <x86intrin.h> +/// +/// This intrinsic corresponds to the \c PREFETCHW instruction. +/// +/// \param __P +/// A pointer specifying the memory address to be prefetched. static __inline__ void __attribute__((__always_inline__, __nodebug__)) _m_prefetchw(void *__P) { |