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| author | Sean Fertile <sfertile@ca.ibm.com> | 2016-11-14 18:47:15 +0000 |
|---|---|---|
| committer | Sean Fertile <sfertile@ca.ibm.com> | 2016-11-14 18:47:15 +0000 |
| commit | cb2e39047d0d60947d30ac8fc39b5c758d175522 (patch) | |
| tree | 324c4918d1d139232843a6922574ab92abdd3393 /test/CodeGen/builtins-ppc-p9vector.c | |
| parent | 4fe4b24b2afb9e57f6c112cc327f36400ca097a7 (diff) | |
[PPC] altivec.h functions for converting half precision to single precision.
Adds 2 vector functions for converting from a vector of unsigned short to a
vector of float. One converts the low 4 halfwords and one converts the high
4 halfwords.
Differential Revision: https://reviews.llvm.org/D26534
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@286863 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/builtins-ppc-p9vector.c')
| -rw-r--r-- | test/CodeGen/builtins-ppc-p9vector.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/test/CodeGen/builtins-ppc-p9vector.c b/test/CodeGen/builtins-ppc-p9vector.c index c14ad71ea5..80c6a43e1f 100644 --- a/test/CodeGen/builtins-ppc-p9vector.c +++ b/test/CodeGen/builtins-ppc-p9vector.c @@ -967,3 +967,21 @@ vector bool long long test87(void) { // CHECK-NEXT: ret <2 x i64> return vec_test_data_class(vda, __VEC_CLASS_FP_NOT_NORMAL); } +vector float test88(void) { +// CHECK-BE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 undef, i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3> +// CHECK-BE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}}) +// CHECK-BE-NEXT: ret <4 x float> +// CHECK-LE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef> +// CHECK-LE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}}) +// CHECK-LE-NEXT: ret <4 x float> + return vec_extract_fp32_from_shorth(vusa); +} +vector float test89(void) { +// CHECK-BE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 undef, i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7> +// CHECK-BE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}}) +// CHECK-BE-NEXT: ret <4 x float> +// CHECK-LE: shufflevector <8 x i16> {{.+}}, <8 x i16> {{.+}}, <8 x i32> <i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7, i32 undef> +// CHECK-LE: @llvm.ppc.vsx.xvcvhpsp(<8 x i16> {{.+}}) +// CHECK-LE-NEXT: ret <4 x float> + return vec_extract_fp32_from_shortl(vusa); +} |