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authorYaxun Liu <Yaxun.Liu@amd.com>2017-07-05 04:58:24 +0000
committerYaxun Liu <Yaxun.Liu@amd.com>2017-07-05 04:58:24 +0000
commitaae294bfd9bd98fd91c7a9eb00e09b5198046d87 (patch)
tree48d7b282fc5e4016d571e828482fdd4d76200892 /test/CodeGen
parent16280f9d13d776349f9dacd3378e307d662f4769 (diff)
[AMDGPU] Fix size and alignment of size_t and pointer types
Differential Revision: https://reviews.llvm.org/D34995 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@307121 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
-rw-r--r--test/CodeGen/default-address-space.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/default-address-space.c b/test/CodeGen/default-address-space.c
index fc5f55ffd6..becbc4ac50 100644
--- a/test/CodeGen/default-address-space.c
+++ b/test/CodeGen/default-address-space.c
@@ -50,7 +50,7 @@ void test3() {
// PIZ: %[[arrayidx:.*]] = getelementptr inbounds i32, i32 addrspace(4)* %[[r0]]
// PIZ: store i32 0, i32 addrspace(4)* %[[arrayidx]]
// CHECK-LABEL: define void @test4(i32* %a)
-// CHECK: %[[alloca:.*]] = alloca i32*, align 4, addrspace(5)
+// CHECK: %[[alloca:.*]] = alloca i32*, align 8, addrspace(5)
// CHECK: %[[a_addr:.*]] = addrspacecast{{.*}} %[[alloca]] to i32**
// CHECK: store i32* %a, i32** %[[a_addr]]
// CHECK: %[[r0:.*]] = load i32*, i32** %[[a_addr]]