Update the intel intrinsic headers to use the target attribute support.

This involved removing the conditional inclusion and replacing them
with target attributes matching the original conditional inclusion
and checks. The testcase update removes the macro checks for each
file and replaces them with usage of the __target__ attribute, e.g.:

int __attribute__((__target__(("sse3")))) foo(int a) {
  _mm_mwait(0, 0);
  return 4;
}

This usage does require the enclosing function have the requisite
__target__ attribute for inlining and code generation - also for
any macro intrinsic uses in the enclosing function. There's no change
for existing uses of the intrinsic headers.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@239883 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 144 insertions, 120 deletions

diff --git a/test/Headers/pmmintrin.c b/test/Headers/pmmintrin.c
new file mode 100644
index 0000000000..5b7a3a4ef6
--- /dev/null
+++ b/test/Headers/pmmintrin.c
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -fsyntax-only -ffreestanding %s -verify
+// RUN: %clang_cc1 -fsyntax-only -ffreestanding -x c++ %s -verify
+// expected-no-diagnostics
+
+#if defined(i386) || defined(__x86_64__)
+#include <pmmintrin.h>
+
+int __attribute__((__target__(("sse3")))) foo(int a) {
+  _mm_mwait(0, 0);
+  return 4;
+}
+#endif
diff --git a/test/Headers/x86intrin-2.c b/test/Headers/x86intrin-2.c
new file mode 100644
index 0000000000..cef5e58cde
--- /dev/null
+++ b/test/Headers/x86intrin-2.c
@@ -0,0 +1,131 @@
+// RUN: %clang_cc1 -fsyntax-only -ffreestanding %s -verify
+// RUN: %clang_cc1 -fsyntax-only -ffreestanding -fno-lax-vector-conversions %s -verify
+// RUN: %clang_cc1 -fsyntax-only -ffreestanding -x c++ %s -verify
+// expected-no-diagnostics
+
+#if defined(i386) || defined(__x86_64__)
+
+// Include the metaheader that includes all x86 intrinsic headers.
+#include <x86intrin.h>
+
+void __attribute__((__target__("mmx"))) mm_empty_wrap(void) {
+  _mm_empty();
+}
+
+__m128 __attribute__((__target__("sse"))) mm_add_ss_wrap(__m128 a, __m128 b) {
+  return _mm_add_ss(a, b);
+}
+
+__m128d __attribute__((__target__("sse2"))) mm_sqrt_sd_wrap(__m128d a, __m128d b) {
+  return _mm_sqrt_sd(a, b);
+}
+
+void __attribute__((__target__("sse3"))) mm_mwait_wrap(int a) {
+  _mm_mwait(0, 0);
+}
+
+__m64 __attribute__((__target__("ssse3"))) mm_abs_pi8_wrap(__m64 a) {
+  return _mm_abs_pi8(a);
+}
+
+__m128i __attribute__((__target__("sse4.1"))) mm_minpos_epu16_wrap(__m128i v) {
+  return _mm_minpos_epu16(v);
+}
+
+unsigned int __attribute__((__target__("sse4.2"))) mm_crc32_u8_wrap(unsigned int c, unsigned char d) {
+  return _mm_crc32_u8(c, d);
+}
+
+__m128i __attribute__((__target__("aes"))) mm_aesenc_si128_wrap(__m128i v, __m128i r) {
+  return _mm_aesenc_si128(v, r);
+}
+
+__m256d __attribute__((__target__("avx"))) mm256_add_pd_wrap(__m256d a, __m256d b) {
+  return _mm256_add_pd(a, b);
+}
+
+__m256i __attribute__((__target__("avx2"))) mm256_abs_epi8_wrap(__m256i a) {
+  return _mm256_abs_epi8(a);
+}
+
+unsigned short __attribute__((__target__("bmi"))) tzcnt_u16_wrap(unsigned short x) {
+  return __tzcnt_u16(x);
+}
+
+unsigned int __attribute__((__target__("bmi2"))) bzhi_u32_wrap(unsigned int x, unsigned int y) {
+  return _bzhi_u32(x, y);
+}
+
+unsigned short __attribute__((__target__("lzcnt"))) lzcnt16_wrap(unsigned short x) {
+  return __lzcnt16(x);
+}
+
+__m256d __attribute__((__target__("fma"))) mm256_fmsubadd_pd_wrap(__m256d a, __m256d b, __m256d c) {
+  return _mm256_fmsubadd_pd(a, b, c);
+}
+
+__m512i __attribute__((__target__("avx512f"))) mm512_setzero_si512_wrap(void) {
+  return _mm512_setzero_si512();
+}
+
+__mmask8 __attribute__((__target__("avx512vl"))) mm_cmpeq_epi32_mask_wrap(__m128i a, __m128i b) {
+  return _mm_cmpeq_epi32_mask(a, b);
+}
+
+__v64qi __attribute__((__target__("avx512bw"))) mm512_setzero_qi_wrap(void) {
+  return _mm512_setzero_qi();
+}
+
+__m512i __attribute__((__target__("avx512dq"))) mm512_mullo_epi64_wrap(__m512i a, __m512i b) {
+  return _mm512_mullo_epi64(a, b);
+}
+
+__mmask16 __attribute__((__target__("avx512vl,avx512bw"))) mm_cmpeq_epi8_mask_wrap(__m128i a, __m128i b) {
+  return _mm_cmpeq_epi8_mask(a, b);
+}
+
+__m256i __attribute__((__target__("avx512vl,avx512dq"))) mm256_mullo_epi64_wrap(__m256i a, __m256i b) {
+  return _mm256_mullo_epi64(a, b);
+}
+
+int __attribute__((__target__("rdrnd"))) rdrand16_step_wrap(unsigned short *p) {
+  return _rdrand16_step(p);
+}
+
+unsigned int __attribute__((__target__("fsgsbase"))) readfsbase_u32_wrap(void) {
+  return _readfsbase_u32();
+}
+
+unsigned int __attribute__((__target__("rtm"))) xbegin_wrap(void) {
+  return _xbegin();
+}
+
+__m128i __attribute__((__target__("sha"))) mm_sha1nexte_epu32_wrap(__m128i x, __m128i y) {
+  return _mm_sha1nexte_epu32(x, y);
+}
+
+int __attribute__((__target__("rdseed"))) rdseed16_step_wrap(unsigned short *p) {
+  return _rdseed16_step(p);
+}
+
+__m128i __attribute__((__target__("sse4a"))) mm_extract_si64_wrap(__m128i x, __m128i y) {
+  return _mm_extract_si64(x, y);
+}
+
+__m128 __attribute__((__target__("fma4"))) mm_macc_ps_wrap(__m128 a, __m128 b, __m128 c) {
+  return _mm_macc_ps(a, b, c);
+}
+
+__m256 __attribute__((__target__("xop"))) mm256_frcz_ps_wrap(__m256 a) {
+  return _mm256_frcz_ps(a);
+}
+
+unsigned int __attribute__((__target__("tbm"))) blcfill_u32_wrap(unsigned int a) {
+  return __blcfill_u32(a);
+}
+
+__m128 __attribute__((__target__("f16c"))) mm_cvtph_ps_wrap(__m128i a) {
+  return _mm_cvtph_ps(a);
+}
+
+#endif
diff --git a/test/Headers/x86intrin.c b/test/Headers/x86intrin.c
index 6a1608b756..7c15c4816b 100644
--- a/test/Headers/x86intrin.c
+++ b/test/Headers/x86intrin.c
@@ -5,126 +5,7 @@
 
 #if defined(i386) || defined(__x86_64__)
 
-// Pretend to enable all features.
-#ifndef __3dNOW__
-#define __3dNOW__
-#endif
-#ifndef __BMI__
-#define __BMI__
-#endif
-#ifndef __BMI2__
-#define __BMI2__
-#endif
-#ifndef __LZCNT__
-#define __LZCNT__
-#endif
-#ifndef __POPCNT__
-#define __POPCNT__
-#endif
-#ifndef __RDSEED__
-#define __RDSEED__
-#endif
-#ifndef __PRFCHW__
-#define __PRFCHW__
-#endif
-#ifndef __SSE4A__
-#define __SSE4A__
-#endif
-#ifndef __FMA4__
-#define __FMA4__
-#endif
-#ifndef __XOP__
-#define __XOP__
-#endif
-#ifndef __F16C__
-#define __F16C__
-#endif
-#ifndef __MMX__
-#define __MMX__
-#endif
-#ifndef __SSE__
-#define __SSE__
-#endif
-#ifndef __SSE2__
-#define __SSE2__
-#endif
-#ifndef __SSE3__
-#define __SSE3__
-#endif
-#ifndef __SSSE3__
-#define __SSSE3__
-#endif
-#ifndef __SSE4_1__
-#define __SSE4_1__
-#endif
-#ifndef __SSE4_2__
-#define __SSE4_2__
-#endif
-#ifndef __AES__
-#define __AES__
-#endif
-#ifndef __AVX__
-#define __AVX__
-#endif
-#ifndef __AVX2__
-#define __AVX2__
-#endif
-#ifndef __BMI__
-#define __BMI__
-#endif
-#ifndef __BMI2__
-#define __BMI2__
-#endif
-#ifndef __LZCNT__
-#define __LZCNT__
-#endif
-#ifndef __FMA__
-#define __FMA__
-#endif
-#ifndef __RDRND__
-#define __RDRND__
-#endif
-#ifndef __SHA__
-#define __SHA__
-#endif
-#ifndef __ADX__
-#define __ADX__
-#endif
-#ifndef __TBM__
-#define __TBM__
-#endif
-#ifndef __RTM__
-#define __RTM__
-#endif
-#ifndef __PCLMUL__
-#define __PCLMUL__
-#endif
-#ifndef __FSGSBASE__
-#define __FSGSBASE__
-#endif
-#ifndef __AVX512F__
-#define __AVX512F__
-#endif
-#ifndef __AVX512VL__
-#define __AVX512VL__
-#endif
-#ifndef __AVX512BW__
-#define __AVX512BW__
-#endif
-#ifndef __AVX512ER__
-#define __AVX512ER__
-#endif
-#ifndef __AVX512PF__
-#define __AVX512PF__
-#endif
-#ifndef __AVX512DQ__
-#define __AVX512DQ__
-#endif
-#ifndef __AVX512CD__
-#define __AVX512CD__
-#endif
-
-// Now include the metaheader that includes all x86 intrinsic headers.
+// Include the metaheader that includes all x86 intrinsic headers.
 #include <x86intrin.h>
 
 #endif