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| author | Yaxun Liu <Yaxun.Liu@amd.com> | 2018-02-15 19:12:41 +0000 |
|---|---|---|
| committer | Yaxun Liu <Yaxun.Liu@amd.com> | 2018-02-15 19:12:41 +0000 |
| commit | 05e0241bc830fd7fd5600f798176982757b4ae3b (patch) | |
| tree | a3a0439ba0cb65af1c0ee7463b0b948ed90fef7a /test/Index | |
| parent | 54cd87a7b2e38a93c1bdfc7d6c9a4a0267c55729 (diff) | |
Clean up AMDGCN tests
Differential Revision: https://reviews.llvm.org/D43340
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@325279 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/Index')
| -rw-r--r-- | test/Index/pipe-size.cl | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/Index/pipe-size.cl b/test/Index/pipe-size.cl index cfe97935ee..78a8f43810 100644 --- a/test/Index/pipe-size.cl +++ b/test/Index/pipe-size.cl @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -x cl -O0 -cl-std=CL2.0 -emit-llvm -triple x86_64-unknown-linux-gnu %s -o - | FileCheck %s --check-prefix=X86 // RUN: %clang_cc1 -x cl -O0 -cl-std=CL2.0 -emit-llvm -triple spir-unknown-unknown %s -o - | FileCheck %s --check-prefix=SPIR // RUN: %clang_cc1 -x cl -O0 -cl-std=CL2.0 -emit-llvm -triple spir64-unknown-unknown %s -o - | FileCheck %s --check-prefix=SPIR64 -// RUN: %clang_cc1 -x cl -O0 -cl-std=CL2.0 -emit-llvm -triple amdgcn-amd-amdhsa-amdgizcl %s -o - | FileCheck %s --check-prefix=AMD +// RUN: %clang_cc1 -x cl -O0 -cl-std=CL2.0 -emit-llvm -triple amdgcn-amd-amdhsa %s -o - | FileCheck %s --check-prefix=AMDGCN __kernel void testPipe( pipe int test ) { int s = sizeof(test); @@ -11,6 +11,6 @@ __kernel void testPipe( pipe int test ) // SPIR: store i32 4, i32* %s, align 4 // SPIR64: store %opencl.pipe_t addrspace(1)* %test, %opencl.pipe_t addrspace(1)** %test.addr, align 8 // SPIR64: store i32 8, i32* %s, align 4 - // AMD: store %opencl.pipe_t addrspace(1)* %test, %opencl.pipe_t addrspace(1)* addrspace(5)* %test.addr, align 8 - // AMD: store i32 8, i32 addrspace(5)* %s, align 4 + // AMDGCN: store %opencl.pipe_t addrspace(1)* %test, %opencl.pipe_t addrspace(1)* addrspace(5)* %test.addr, align 8 + // AMDGCN: store i32 8, i32 addrspace(5)* %s, align 4 } |