diff options
| author | Craig Topper <craig.topper@intel.com> | 2017-12-27 22:25:59 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-27 22:25:59 +0000 |
| commit | 2744820c00e7dd7eca67bad080c364775512a7a7 (patch) | |
| tree | 95b85190475370b7bc99c47ccf5ce98424f1bb94 /test | |
| parent | 403ecae674b198e3e94069c1ee84476b936e6005 (diff) | |
[X86] Enable avx512vpopcntdq and clwb for icelake.
Per table 1-1 of the October 2017 edition of Intel® Architecture Instruction Set Extensions and Future Features Programming Reference
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@321502 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/Preprocessor/predefined-arch-macros.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/test/Preprocessor/predefined-arch-macros.c b/test/Preprocessor/predefined-arch-macros.c index bd13daa441..d2314d88e1 100644 --- a/test/Preprocessor/predefined-arch-macros.c +++ b/test/Preprocessor/predefined-arch-macros.c @@ -1060,10 +1060,12 @@ // CHECK_ICL_M32: #define __AVX512VBMI__ 1 // CHECK_ICL_M32: #define __AVX512VL__ 1 // CHECK_ICL_M32: #define __AVX512VNNI__ 1 +// CHECK_ICL_M32: #define __AVX512VPOPCNTDQ__ 1 // CHECK_ICL_M32: #define __AVX__ 1 // CHECK_ICL_M32: #define __BMI2__ 1 // CHECK_ICL_M32: #define __BMI__ 1 // CHECK_ICL_M32: #define __CLFLUSHOPT__ 1 +// CHECK_ICL_M32: #define __CLWB__ 1 // CHECK_ICL_M32: #define __F16C__ 1 // CHECK_ICL_M32: #define __FMA__ 1 // CHECK_ICL_M32: #define __GFNI__ 1 @@ -1111,10 +1113,12 @@ // CHECK_ICL_M64: #define __AVX512VBMI__ 1 // CHECK_ICL_M64: #define __AVX512VL__ 1 // CHECK_ICL_M64: #define __AVX512VNNI__ 1 +// CHECK_ICL_M64: #define __AVX512VPOPCNTDQ__ 1 // CHECK_ICL_M64: #define __AVX__ 1 // CHECK_ICL_M64: #define __BMI2__ 1 // CHECK_ICL_M64: #define __BMI__ 1 // CHECK_ICL_M64: #define __CLFLUSHOPT__ 1 +// CHECK_ICL_M64: #define __CLWB__ 1 // CHECK_ICL_M64: #define __F16C__ 1 // CHECK_ICL_M64: #define __FMA__ 1 // CHECK_ICL_M64: #define __GFNI__ 1 |