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* [MINGW] normalize WIN32 macrosMartell Malone2017-11-211-1/+8
| | | | | | | | | | | | | | move _WIN64 and _WIN32 defines to lib/Basic/Targets/OSTargets.h move WIN32, WIN64 and __MINGW64__ to addMinGWDefines fixes __MINGW64__ not being defined for aarch64 adds WIN32 definition for x64 Reviewers: mstorsjo Differential Revision: https://reviews.llvm.org/D40285 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@318755 91177308-0d34-0410-b5e6-96231b3b80d8
* [Atomic][X8664] set max atomic inline width according to the targetWei Mi2017-09-221-0/+1
| | | | | | | | | | | | This is to fix PR31620. MaxAtomicInlineWidth is set to 128 for x86_64. However for target without cx16 support, 128 atomic operation will generate __sync_* libcalls. The patch set MaxAtomicInlineWidth to 64 if the target doesn't support cx16. Differential Revision: https://reviews.llvm.org/D38046 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@313992 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for a MinGW AArch64 targetMartin Storsjo2017-08-131-1/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D36364 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@310798 91177308-0d34-0410-b5e6-96231b3b80d8
* [Targets] Move addCygMingDefines into the arch-independent Targets.cpp (NFC)Martin Storsjo2017-07-311-0/+24
| | | | | | | | | | | | This fixes a dependency inconsistency, where addMinGWDefines in Targets.cpp (used from other architectures than X86) called the addCygMingDefines function in X86.h. This was inconsistently split in SVN r308791 (D35701). Differential Revision: https://reviews.llvm.org/D36072 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@309598 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove Bitrig: Clang ChangesErich Keane2017-07-211-8/+0
| | | | | | | | | Bitrig code has been merged back to OpenBSD, thus the OS has been abandoned. Differential Revision: https://reviews.llvm.org/D35708 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@308797 91177308-0d34-0410-b5e6-96231b3b80d8
* Break up Targets.cpp into a header/impl pair per target type[NFCI]Erich Keane2017-07-211-9599/+36
| | | | | | | | | | | | | | | | | | Targets.cpp is getting unwieldy, and even minor changes cause the entire thing to cause recompilation for everyone. This patch bites the bullet and breaks it up into a number of files. I tended to keep function definitions in the class declaration unless it caused additional includes to be necessary. In those cases, I pulled it over into the .cpp file. Content is copy/paste for the most part, besides includes/format/etc. Differential Revision: https://reviews.llvm.org/D35701 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@308791 91177308-0d34-0410-b5e6-96231b3b80d8
* [Hexagon] Add inline-asm constraint 'a' for modifier register classKrzysztof Parzyszek2017-07-211-0/+3
| | | | | | | | For example asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory") git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@308763 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add lowering of i128 params.Artem Belevich2017-07-201-2/+2
| | | | | | | | | | | | | | | | | The patch adds support of i128 params lowering. The changes are quite trivial to support i128 as a "special case" of integer type. With this patch, we lower i128 params the same way as aggregates of size 16 bytes: .param .b8 _ [16]. Currently, NVPTX can't deal with the 128 bit integers: * in some cases because of failed assertions like ValVTs.size() == OutVals.size() && "Bad return value decomposition" * in other cases emitting PTX with .i128 or .u128 types (which are not valid [1]) [1] http://docs.nvidia.com/cuda/parallel-thread-execution/index.html#fundamental-types Differential Revision: https://reviews.llvm.org/D34555 Patch by: Denys Zariaiev (denys.zariaiev@gmail.com) git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@308675 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Put avx512vpopcntdq in the right spot in the validateCpuSupports ↵Craig Topper2017-07-191-1/+1
| | | | | | | | string switch. The validateCpuSupports switch is in the order of the enum defined in CGBuiltin.cpp and libgcc/compiler-rt. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@308546 91177308-0d34-0410-b5e6-96231b3b80d8
* Add isValidCPUName and isValidFeature to TargetInfoErich Keane2017-07-191-95/+223
| | | | | | | | These two functions are really useful for implementations of attributes (including attribute-target), so add the functionality. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@308530 91177308-0d34-0410-b5e6-96231b3b80d8
* [COFF, ARM64] Set the data type widths and the data layout stringMandeep Singh Grang2017-07-171-1/+14
| | | | | | | | | | | | | | Summary: COFF ARM64 is LLP64 platform. So int is 4 bytes, long is 4 bytes and long long is 8 bytes. Reviewers: compnerd, ruiu, rnk, efriedma Reviewed By: compnerd, efriedma Subscribers: efriedma, javed.absar, cfe-commits, aemerson, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D34859 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@308222 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for __builtin_ms_va_list on aarch64Martin Storsjo2017-07-171-1/+5
| | | | | | | | | | | Move builtins from the x86 specific scope into the global scope. Their use is still limited to x86_64 and aarch64 though. This allows wine on aarch64 to properly handle variadic functions. Differential Revision: https://reviews.llvm.org/D34475 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@308218 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add support for IBM z14 processor (2/3)Ulrich Weigand2017-07-171-1/+1
| | | | | | | | | | | | This patch extends the -fzvector language feature to enable the new "vector float" data type when compiling at -march=z14. This matches the updated extension definition implemented by other compilers for the platform, which is indicated to applications by pre-defining __VEC__ to 10302 (instead of 10301). git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@308198 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add support for IBM z14 processor (1/3)Ulrich Weigand2017-07-171-0/+4
| | | | | | | | | | | | | This patch series adds support for the IBM z14 processor. This part includes: - Basic support for the new processor and its features. - Support for low-level builtins mapped to new LLVM intrinsics. Support for the -fzvector extension to vector float and the new high-level vector intrinsics is provided by separate patches. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@308197 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable TLS support on OpenBSD, but default to the emulatated TLS model.Brad Smith2017-07-171-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@308155 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Add 'movbe' to btver2 CPU.Craig Topper2017-07-141-0/+1
| | | | | | This probably doesn't change anything because the frotend doesn't do anything with this feature and the backend will infer from the cpu string. So this is just for consistency with other cpus that support movbe. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@308002 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for handling the +sve target feature.Amara Emerson2017-07-131-4/+11
| | | | | | | | This also adds the appropriate predefine for SVE if enabled. Differential Revision: https://reviews.llvm.org/D35118 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@307919 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Create the correct profiling symbol on Linux MIPSSimon Atanasyan2017-07-111-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@307627 91177308-0d34-0410-b5e6-96231b3b80d8
* CodeGen: Fix address space of global variableYaxun Liu2017-07-081-0/+4
| | | | | | | | | | | | | | Certain targets (e.g. amdgcn) require global variable to stay in global or constant address space. In C or C++ global variables are emitted in the default (generic) address space. This patch introduces virtual functions TargetCodeGenInfo::getGlobalVarAddressSpace and TargetInfo::getConstantAddressSpace to handle this in a general approach. It only affects IR generated for amdgcn target. Differential Revision: https://reviews.llvm.org/D33842 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@307470 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Replace 'fallthrough' comments with LLVM_FALLTHROUGH.Craig Topper2017-07-071-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@307420 91177308-0d34-0410-b5e6-96231b3b80d8
* This reverts r305820 (ARMv.2-A FP16 vector intrinsics) because it showsSjoerd Meijer2017-07-061-3/+0
| | | | | | | | | problems in testing, see comments in D34161 for some more details. A fix is in progres in D35011, but a revert seems better now as the fix will probably take some more time to land. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@307277 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Simplify handling of ISA revisionsUlrich Weigand2017-07-051-26/+22
| | | | | | | | | | | | This moves determination of the ISA revision from the CPU name to one single place, removing a bunch of duplicated code. It also makes the supported ISA revisions available as feature strings. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@307156 91177308-0d34-0410-b5e6-96231b3b80d8
* [AMDGPU] Fix size and alignment of size_t and pointer typesYaxun Liu2017-07-051-6/+14
| | | | | | | Differential Revision: https://reviews.llvm.org/D34995 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@307121 91177308-0d34-0410-b5e6-96231b3b80d8
* [AMDGPU] Fix regressions on mesa/clover with libclc due to address spaceYaxun Liu2017-07-041-10/+18
| | | | | | | | | | | Currently AMDGPUTargetInfo does not initialize AddrSpaceMap in constructor, which causes regressions in mesa/clover with libclc. This patch fixes that. Differential Revision: https://reviews.llvm.org/D34987 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@307105 91177308-0d34-0410-b5e6-96231b3b80d8
* fix trivial typos; NFCHiroshi Inoue2017-07-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@306954 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed Opts.EABIVersion type string to llvm::EABI enum classYuka Takahashi2017-07-011-2/+2
| | | | | | | | | | Summary: Changed EABIVersion type from string to llvm::EABI. It seems it was just a typo and this is intended implementation. Differential Revision: https://reviews.llvm.org/D34595 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@306953 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Add RDRND feature to Goldmont. Add MOVBE to all Atom CPUs.Craig Topper2017-06-301-0/+2
| | | | | | Diffential Revision: https://reviews.llvm.org/D34842 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@306851 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Add a break to the last case of a few switches to prevent accidents in ↵Craig Topper2017-06-301-0/+4
| | | | | | the future. NFC git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@306850 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Move all atom CPUs to the same section of the switch and use ↵Craig Topper2017-06-301-3/+6
| | | | | | | | fallthroughs like we do for other CPU generations. NFC This is prep work to add MOVBE to all Atom CPUs. This instruction didn't come in to the Nehalem/Westmere/SandyBridge/etc. line until later so there's no natural place to overlap the Atom CPUs into that part of the switch. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@306849 91177308-0d34-0410-b5e6-96231b3b80d8
* ARMV8-A archkind and target defines helper functionsSjoerd Meijer2017-06-301-12/+47
| | | | | | | | | | | | | This introduces helper functions that set target defines for different ARMV8-A architecture kinds. It fixes an issue that the v8.1 define ARM_FEATURE_QRDMX was not set for v8.2. These helper functions make things more “scalable” if we want to add ARMv8.3 at some point, and a cleanup has been done to hold the architecture kind in one variable (instead of one for each). Differential Revision: https://reviews.llvm.org/D34686 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@306805 91177308-0d34-0410-b5e6-96231b3b80d8
* [Clang][X86][Goldmont]Adding new target-cpu: Goldmont Michael Zuckerman2017-06-291-0/+21
| | | | | | | | | | | | | | | | [Clang-side] Connecting the GoldMont processor to his feature. Reviewers: 1. igorb 2. delena 3. zvi Differential Revision: https://reviews.llvm.org/D34807 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@306673 91177308-0d34-0410-b5e6-96231b3b80d8
* [COFF, ARM64] Add support for Windows ARM64 COFF formatMandeep Singh Grang2017-06-271-0/+39
| | | | | | | | | | | | | | Summary: This is the clang part of the initial implementation to support Windows ARM64 COFF format. Reviewers: ruiu, t.p.northover, rnk, compnerd Reviewed By: ruiu, compnerd Subscribers: aemerson, kristof.beyls, cfe-commits, llvm-commits Differential Revision: https://reviews.llvm.org/D34706 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@306489 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply "Frontend support for Nios2 target"Nikolai Bozhenov2017-06-271-0/+145
| | | | | | | | | | | | | | | | Summary: - Implements TargetInfo class for Nios2 target. - Enables handling of -march and -mcpu options for Nios2 target. - Definition of Nios2 builtin functions. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D33356 Author: belickim <mateusz.belicki@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@306383 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for Ananas platformEd Schouten2017-06-251-0/+19
| | | | | | | | | | | | | | | | | | Ananas is a home-brew operating system, mainly for amd64 machines. After using GCC for quite some time, it has switched to clang and never looked back - yet, having to manually patch things is annoying, so it'd be much nicer if this was in the official tree. More information: https://github.com/zhmu/ananas/ https://rink.nu/projects/ananas.html Submitted by: Rink Springer Differential Revision: https://reviews.llvm.org/D32936 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@306239 91177308-0d34-0410-b5e6-96231b3b80d8
* [MSP430] Fix data layout string.Vadzim Dambrouski2017-06-231-1/+1
| | | | | | | | | | | | | | | | | Summary: Change data layout string so it would be compatible with MSP430 EABI. Depends on D34561 Reviewers: asl, awygle Reviewed By: asl Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D34562 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@306161 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] ADD ARMv.2-A FP16 vector intrinsicsAbderrazek Zaafrani2017-06-201-0/+10
| | | | | | Differential Revision: https://reviews.llvm.org/D34161 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@305820 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Define _GNU_SOURCE for rtems c++"Daniel Jasper2017-06-151-3/+0
| | | | | | | | | | | | | | | | | This reverts commit r305399. This breaks a build in libcxx: libcxx/src/system_error.cpp:90:16: error: assigning to 'int' from incompatible type 'char *' if ((ret = ::strerror_r(ev, buffer, strerror_buff_size)) != 0) { ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. Which makes sense according to: https://linux.die.net/man/3/strerror_r Not entirely sure how this needs to be fixed. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@305456 91177308-0d34-0410-b5e6-96231b3b80d8
* Define _GNU_SOURCE for rtems c++James Y Knight2017-06-141-0/+3
| | | | | | | | | | This is required by the libc++ locale support. Patch by Walter Lee. Differential Revision: https://reviews.llvm.org/D34105 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@305399 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert of r305066 "Reapply Frontend support for Nios2 target"Nikolai Bozhenov2017-06-091-145/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@305068 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply "Frontend support for Nios2 target"Nikolai Bozhenov2017-06-091-0/+145
| | | | | | | | | | | | | | | | Summary: - Implements TargetInfo class for Nios2 target. - Enables handling of -march and -mcpu options for Nios2 target. - Definition of Nios2 builtin functions. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D33356 Author: belickim <mateusz.belicki@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@305066 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Frontend support for Nios2 target"Nikolai Bozhenov2017-06-081-145/+0
| | | | | | | As it breaks many buildbots. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@305002 91177308-0d34-0410-b5e6-96231b3b80d8
* Frontend support for Nios2 target.Nikolai Bozhenov2017-06-081-0/+145
| | | | | | | | | | | | | | | | Summary: - Implements TargetInfo class for Nios2 target. - Enables handling of -march and -mcpu options for Nios2 target. - Definition of Nios2 builtin functions. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D33356 Author: belickim <mateusz.belicki@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304994 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r304929 [mips] Add runtime options to enable/disable madd/sub.fmtPetar Jovanovic2017-06-071-1/+7
| | | | | | | | | | | | | | | | | | The test in r304929 broke multiple buildbots as it expected mips target to be registered and available (which is not necessarily true). Updating the test with this condition. Original commit: [mips] Add runtime options to enable/disable madd.fmt and msub.fmt Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable generation of madd.fmt and similar instructions respectively, as per GCC. Patch by Stefan Maksimovic. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304953 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r304929 [mips] Add runtime options to enable/disable madd/sub.fmtPetar Jovanovic2017-06-071-7/+1
| | | | | | | | | | | | | | | | Revert r304929 since the test broke buildbots. Original commit: [mips] Add runtime options to enable/disable madd.fmt and msub.fmt Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable generation of madd.fmt and similar instructions respectively, as per GCC. Patch by Stefan Maksimovic. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304935 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add runtime options to enable/disable madd.fmt and msub.fmtPetar Jovanovic2017-06-071-1/+7
| | | | | | | | | | | | Add options to clang: -mmadd4 and -mno-madd4, use it to enable or disable generation of madd.fmt and similar instructions respectively, as per GCC. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33401 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304929 91177308-0d34-0410-b5e6-96231b3b80d8
* [CodeGen] Add thumb-mode to target-features for arm/thumb triples.Florian Hahn2017-06-071-0/+7
| | | | | | | | | | | | | | | | | | | | | Summary: The thumb-mode target feature is used to force Thumb or ARM code generation on a per-function basis. Explicitly adding +thumb-mode to functions for thumbxx triples enables mixed ARM/Thumb code generation in places where compilation units with thumbxx and armxx triples are merged together (e.g. the IR linker or LTO). For armxx triples, -thumb-mode is added in a similar fashion. Reviewers: echristo, t.p.northover, kristof.beyls, rengolin Reviewed By: echristo Subscribers: rinon, aemerson, mehdi_amini, javed.absar, cfe-commits Differential Revision: https://reviews.llvm.org/D33448 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304897 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Fix Neon vector type alignment to 64-bitJaved Absar2017-06-071-0/+4
| | | | | | | | | | | | This is restricted version of patch - https://reviews.llvm.org/D33205 that I reverted as it was leading to ABI breaks on darwin etc. This patch restricts the fix to AAPCS (Android remains 128-bit). Reviewed by: Renato Golin, Stephen Hines Differential Revision: https://reviews.llvm.org/D33786 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304889 91177308-0d34-0410-b5e6-96231b3b80d8
* [WebAssembly] Set MaxAtomicInlineWidth to 64.Dan Gohman2017-06-071-1/+1
| | | | | | | | | The WebAssembly threads proposal has changed such that C++ implementations can now declare that atomics up to 64 bits are "lock free" in C++'s terms. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304859 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Add support for target("arm") and target("thumb").Florian Hahn2017-06-061-1/+11
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds support for the target("arm") and target("thumb") attributes, which can be used to force the compiler to generated ARM or Thumb code for a function. In LLVM, ARM or Thumb code generation can be controlled by the thumb-mode target feature. But GCC already uses target("arm") and target("thumb"), so we have to substitute "arm" with -thumb-mode and "thumb" with +thumb-mode. Reviewers: echristo, pcc, kristof.beyls Reviewed By: echristo Subscribers: ahatanak, aemerson, javed.absar, kristof.beyls, cfe-commits Differential Revision: https://reviews.llvm.org/D33721 git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304781 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "[AArch64] Add ARMv8.2-A FP16 vefctor intrinsics"Vedant Kumar2017-06-021-10/+0
| | | | | | | | | | | | This reverts commit r304493. It breaks all the Darwin bots: http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental_check/37168 Failure: Failing Tests (2): Clang :: CodeGen/aarch64-v8.2a-neon-intrinsics.c Clang :: CodeGen/arm_neon_intrinsics.c git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@304509 91177308-0d34-0410-b5e6-96231b3b80d8
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