diff options
| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2023-03-31 10:34:10 +0100 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2023-04-03 21:47:57 -0700 |
| commit | e59e0b9bd37463a2c570a99d5db41ee81ddce3c8 (patch) | |
| tree | 20ce630128bfae322016b3d9a2f81a1abab65c66 | |
| parent | 79e743f16cd9e4187d18dd8320d0144f56695867 (diff) | |
ARMFrameLowering.cpp - fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.
(cherry picked from commit b206145323fafc75d82efcc7e154218e37480953)
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFrameLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index ae5a45ff5985..724705c25e3a 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -363,7 +363,7 @@ static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI, MBBI->getOperand(3).getImm() == -4) { unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) - .addImm(1 << Reg) + .addImm(1ULL << Reg) .addImm(/*Wide=*/1) .setMIFlags(Flags); } else { @@ -377,7 +377,7 @@ static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI, MBBI->getOperand(3).getImm() == 4) { unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) - .addImm(1 << Reg) + .addImm(1ULL << Reg) .addImm(/*Wide=*/1) .setMIFlags(Flags); } else { |