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authorJay Foad <jay.foad@amd.com>2024-01-09 11:52:51 +0000
committerJay Foad <jay.foad@amd.com>2024-01-09 11:53:12 +0000
commit0b9b00c8c86d42f72f8abf379052a451778dcc63 (patch)
tree42aa3008fed8d6fcdb9969f091553550f9dd631f
parente7636b1094ba53fe4edc16dd52ef981c01e35ceb (diff)
[AMDGPU] Make isScalarLoadLegal a member of AMDGPURegisterBankInfo. NFC.
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp2
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h2
2 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index ecb7bb9d1d97..391c2b9ec256 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -441,7 +441,7 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects(
// FIXME: Returns uniform if there's no source value information. This is
// probably wrong.
-static bool isScalarLoadLegal(const MachineInstr &MI) {
+bool AMDGPURegisterBankInfo::isScalarLoadLegal(const MachineInstr &MI) const {
if (!MI.hasOneMemOperand())
return false;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
index 2bb5ef57fe03..5f550b426ec0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
@@ -176,6 +176,8 @@ public:
const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
LLT) const override;
+ bool isScalarLoadLegal(const MachineInstr &MI) const;
+
InstructionMappings
getInstrAlternativeMappings(const MachineInstr &MI) const override;