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| author | Kohei Yamaguchi <fix7211@gmail.com> | 2024-01-09 20:45:40 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-09 11:45:40 +0000 |
| commit | d5985d4c70bad7b25740027cb873c91a31ff0659 (patch) | |
| tree | 983e952212de25895e7341cad7283ce3d5a0adfb | |
| parent | 19870ed9c3238f348bf82dcc2b2e0a2894536874 (diff) | |
[mlir][docs] Fix a broken passes documentation (#77402)
- Add EmitC passes into Pass.md
- Modify header level of the pass description to under the
`LegalizeVectorStorage` pass
| -rw-r--r-- | mlir/docs/Passes.md | 4 | ||||
| -rw-r--r-- | mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/mlir/docs/Passes.md b/mlir/docs/Passes.md index 66e2dc077f98..ee7d47cc0227 100644 --- a/mlir/docs/Passes.md +++ b/mlir/docs/Passes.md @@ -40,6 +40,10 @@ This document describes the available MLIR passes and their contracts. [include "AsyncPasses.md"] +## 'emitc' Dialect Passes + +[include "EmitCPasses.md"] + ## 'func' Dialect Passes [include "FuncPasses.md"] diff --git a/mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td b/mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td index d7cb309db525..b9b06cec1f97 100644 --- a/mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td +++ b/mlir/include/mlir/Dialect/ArmSVE/Transforms/Passes.td @@ -21,7 +21,7 @@ def LegalizeVectorStorage This pass currently addresses two issues. - ## Loading and storing predicate types + #### Loading and storing predicate types It is only legal to load/store predicate types equal to (or greater than) a full predicate register, which in MLIR is `vector<[16]xi1>`. Smaller @@ -49,7 +49,7 @@ def LegalizeVectorStorage %reload = arm_sve.convert_from_svbool %reload_svbool : vector<[4]xi1> ``` - ## Relax alignments for SVE vector allocas + #### Relax alignments for SVE vector allocas The storage for SVE vector types only needs to have an alignment that matches the element type (for example 4 byte alignment for `f32`s). However, |