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| author | Craig Topper <craig.topper@sifive.com> | 2023-11-18 11:45:42 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-11-18 12:29:04 -0800 |
| commit | 8ad4df8327e617c7ef1a727df61e4600ef13ed85 (patch) | |
| tree | a7567e75b951a97f84c35e4e6ff6b5ae67f1bac3 | |
| parent | 48c5c1b1f9ccb1b6ea05153b5a54f691f778c78b (diff) | |
[RISCV][GISel] Add s32 G_SELECT instruction select test for RV64. NFC
| -rw-r--r-- | llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir index 16342a83d227..fc5d54ac0f54 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/select-rv64.mir @@ -1,6 +1,36 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \ # RUN: | FileCheck %s + +--- +name: select_s32 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $x10, $x11, $x12 + + ; CHECK-LABEL: name: select_s32 + ; CHECK: liveins: $x10, $x11, $x12 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12 + ; CHECK-NEXT: [[Select_GPR_Using_CC_GPR:%[0-9]+]]:gpr = Select_GPR_Using_CC_GPR [[COPY]], $x0, 1, [[COPY1]], [[COPY2]] + ; CHECK-NEXT: $x10 = COPY [[Select_GPR_Using_CC_GPR]] + ; CHECK-NEXT: PseudoRET implicit $x10 + %0:gprb(s64) = COPY $x10 + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = COPY $x12 + %3:gprb(s32) = G_TRUNC %1 + %4:gprb(s32) = G_TRUNC %2 + %5:gprb(s32) = G_SELECT %0, %3, %4 + %6:gprb(s64) = G_ANYEXT %5 + $x10 = COPY %6(s64) + PseudoRET implicit $x10 + +... --- name: select_s64 legalized: true |