diff options
author | RolandF77 <55763885+RolandF77@users.noreply.github.com> | 2024-01-23 16:07:18 -0500 |
---|---|---|
committer | GitHub <noreply@github.com> | 2024-01-23 16:07:18 -0500 |
commit | 4beea6b195585e4d9e196a9a2b0bb79a9c040788 (patch) | |
tree | abd246b68e9bbbdf793fdef5205ea13ed82cdaf1 | |
parent | 4fcd7cf22deff4a63d2bac12c909be7266f8b353 (diff) |
[PowerPC] lower partial vector store cost (#78358)
There are matching store opcodes (stfd, stxsiwx) for the load opcodes
that make 32-bit and 64-bit vector operations cheap with VSX, so stores
should also be cheap.
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 5 | ||||
-rw-r--r-- | llvm/test/Analysis/CostModel/PowerPC/load_store.ll | 19 |
2 files changed, 22 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 062b53e24a0d..958353f2b4f6 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -788,9 +788,10 @@ InstructionCost PPCTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, // VSX has 32b/64b load instructions. Legalization can handle loading of // 32b/64b to VSR correctly and cheaply. But BaseT::getMemoryOpCost and // PPCTargetLowering can't compute the cost appropriately. So here we - // explicitly check this case. + // explicitly check this case. There are also corresponding store + // instructions. unsigned MemBytes = Src->getPrimitiveSizeInBits(); - if (Opcode == Instruction::Load && ST->hasVSX() && IsAltivecType && + if (ST->hasVSX() && IsAltivecType && (MemBytes == 64 || (ST->hasP8Vector() && MemBytes == 32))) return 1; diff --git a/llvm/test/Analysis/CostModel/PowerPC/load_store.ll b/llvm/test/Analysis/CostModel/PowerPC/load_store.ll index 574a3d40d273..167cdf9c3330 100644 --- a/llvm/test/Analysis/CostModel/PowerPC/load_store.ll +++ b/llvm/test/Analysis/CostModel/PowerPC/load_store.ll @@ -43,3 +43,22 @@ define i32 @loads(i32 %arg) { ret i32 undef } +define i32 @partialvector32(i32 %arg) #0 { + + ; CHECK: cost of 1 {{.*}} store + store <4 x i8> undef, ptr undef, align 16 + + ret i32 undef +} + +define i32 @partialvector64(i32 %arg) #1 { + + ; CHECK: cost of 1 {{.*}} store + store <4 x i16> undef, ptr undef, align 16 + + ret i32 undef +} + +attributes #0 = { "target-features"="+power8-vector,+vsx" } + +attributes #1 = { "target-features"="+vsx" } |