[RISCV] Add sifive-p670 processor (#79015)

This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p650-670.

Scheduler model and other tuning will come in separate patches.

4 files changed, 88 insertions, 3 deletions

diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 015df83e7780..ff2bd6f7c8ba 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -247,7 +247,54 @@
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb"
 // MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
 // MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
-//
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck -check-prefix=MCPU-SIFIVE-P670 %s
+// MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+m"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+a"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+f"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+d"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+c"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+v"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zic64b"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicbom"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicbop"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicboz"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccamoa"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccif"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicclsm"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccrse"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicsr"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zifencei"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihintntl"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihintpause"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihpm"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+za64rs"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zfhmin"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zba"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zbb"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zbs"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbb"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbc"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32f"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32x"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve64d"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve64f"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve64x"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkg"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkn"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvknc"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkned"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkng"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvknhb"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvks"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksc"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksed"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksg"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksh"
+// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt"
+// MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"
+
 // Check failed cases
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index 48e9f05d9b03..84aed5c9c36f 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 4ef28e277228..7b6a3f10d637 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -180,6 +180,7 @@ Changes to the RISC-V Backend
   and Zic64b extensions which were introduced as a part of the RISC-V Profiles
   specification.
 * The Smepmp 1.0 extension is now supported.
+* ``-mcpu=sifive-p670`` was added.
 
 Changes to the WebAssembly Backend
 ----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index af621de9f802..03ca505d100d 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -245,6 +245,43 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
                                        TuneLUIADDIFusion,
                                        TuneAUIPCADDIFusion]>;
 
+def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel,
+                                      [Feature64Bit,
+                                       FeatureStdExtZifencei,
+                                       FeatureStdExtM,
+                                       FeatureStdExtA,
+                                       FeatureStdExtF,
+                                       FeatureStdExtD,
+                                       FeatureStdExtC,
+                                       FeatureStdExtZa64rs,
+                                       FeatureStdExtZic64b,
+                                       FeatureStdExtZicbop,
+                                       FeatureStdExtZicbom,
+                                       FeatureStdExtZicboz,
+                                       FeatureStdExtZiccamoa,
+                                       FeatureStdExtZiccif,
+                                       FeatureStdExtZicclsm,
+                                       FeatureStdExtZiccrse,
+                                       FeatureStdExtZihintntl,
+                                       FeatureStdExtZihintpause,
+                                       FeatureStdExtZihpm,
+                                       FeatureStdExtZba,
+                                       FeatureStdExtZbb,
+                                       FeatureStdExtZbs,
+                                       FeatureStdExtZfhmin,
+                                       FeatureStdExtV,
+                                       FeatureStdExtZvl128b,
+                                       FeatureStdExtZvbb,
+                                       FeatureStdExtZvknc,
+                                       FeatureStdExtZvkng,
+                                       FeatureStdExtZvksc,
+                                       FeatureStdExtZvksg,
+                                       FeatureFastUnalignedAccess],
+                                      [TuneNoDefaultUnroll,
+                                       TuneConditionalCompressedMoveFusion,
+                                       TuneLUIADDIFusion,
+                                       TuneAUIPCADDIFusion]>;
+
 def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
                                               SyntacoreSCR1Model,
                                               [Feature32Bit,