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authorSimon Pilgrim <llvm-dev@redking.me.uk>2024-04-23 17:31:01 +0100
committerSimon Pilgrim <llvm-dev@redking.me.uk>2024-04-23 17:31:01 +0100
commitc45fbfdb8e5a01cb4473c179dc390e9c039f3f39 (patch)
tree56a254fc66fbb4b9eaa1e15afb45075655a67034
parent143be6a60186d6c1a6a298d0b7acdc1a4d69a321 (diff)
[VectorCombine][X86] shuffle-of-binops.ll - adjust no matching operand test to use FDIV
Use of FDIV allows us to show a definite cost improvement with #88899
-rw-r--r--llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll12
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll
index 5c4ad4f1fcc4..a19b205e68a6 100644
--- a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll
@@ -170,16 +170,16 @@ define <4 x i32> @shuf_mul_v4i32_yy_use2(<4 x i32> %x, <4 x i32> %y, <4 x i32> %
; negative test - must have matching operand
-define <4 x float> @shuf_fadd_v4f32_no_common_op(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %w) {
-; CHECK-LABEL: define <4 x float> @shuf_fadd_v4f32_no_common_op(
+define <4 x float> @shuf_fdiv_v4f32_no_common_op(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %w) {
+; CHECK-LABEL: define <4 x float> @shuf_fdiv_v4f32_no_common_op(
; CHECK-SAME: <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]], <4 x float> [[Z:%.*]], <4 x float> [[W:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[B0:%.*]] = fadd <4 x float> [[X]], [[Y]]
-; CHECK-NEXT: [[B1:%.*]] = fadd <4 x float> [[Z]], [[W]]
+; CHECK-NEXT: [[B0:%.*]] = fdiv <4 x float> [[X]], [[Y]]
+; CHECK-NEXT: [[B1:%.*]] = fdiv <4 x float> [[Z]], [[W]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[B0]], <4 x float> [[B1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>
; CHECK-NEXT: ret <4 x float> [[R]]
;
- %b0 = fadd <4 x float> %x, %y
- %b1 = fadd <4 x float> %z, %w
+ %b0 = fdiv <4 x float> %x, %y
+ %b1 = fdiv <4 x float> %z, %w
%r = shufflevector <4 x float> %b0, <4 x float> %b1, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
ret <4 x float> %r
}