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| author | Philip Reames <preames@rivosinc.com> | 2024-04-23 08:50:12 -0700 |
|---|---|---|
| committer | Philip Reames <listmail@philipreames.com> | 2024-04-23 08:51:23 -0700 |
| commit | c793f4a4dab058cee4f283100946a1bb8e465f59 (patch) | |
| tree | 4970fe23b42c3f61e2c23456d31e79357ac5f9f8 | |
| parent | 03c8a29d1061c9dd47953c21aae70f46075f1b0c (diff) | |
[RISCV] Add test coverage for mul (zext), 2^N + 2/4/8 [nfc]
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rv64zba.ll | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll index f31de84b8b04..4eb493d642e8 100644 --- a/llvm/test/CodeGen/RISCV/rv64zba.ll +++ b/llvm/test/CodeGen/RISCV/rv64zba.ll @@ -753,6 +753,25 @@ define i64 @mul288(i64 %a) { ret i64 %c } +define i64 @zext_mul68(i32 signext %a) { +; RV64I-LABEL: zext_mul68: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 17 +; RV64I-NEXT: slli a1, a1, 34 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: mulhu a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: zext_mul68: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: slli.uw a1, a0, 6 +; RV64ZBA-NEXT: sh2add.uw a0, a0, a1 +; RV64ZBA-NEXT: ret + %b = zext i32 %a to i64 + %c = mul i64 %b, 68 + ret i64 %c +} + define i64 @zext_mul96(i32 signext %a) { ; RV64I-LABEL: zext_mul96: ; RV64I: # %bb.0: |