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| author | Hal Finkel <hfinkel@anl.gov> | 2014-12-09 02:43:05 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2014-12-09 02:43:05 +0000 |
| commit | e354bf82bab9daf0671f76b110a832679fa58b65 (patch) | |
| tree | 4b10273a2432179b65579f7e650e673e453ffe8e | |
| parent | 651925a49600deed1a3183c5d1c5d71e9a884674 (diff) | |
Fixup backport of r223318upstream/llvmorg-3.5.1-rc1llvmorg-3.5.1-rc1
TM.getSubtargetImpl()->getRegisterInfo() needs to be TM.getRegisterInfo() in 3.5.
llvm-svn: 223749
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 4c7dabba2bb7..57960598c83f 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -177,7 +177,7 @@ namespace { std::vector<SDValue> &OutOps) override { // We need to make sure that this one operand does not end up in r0 // (because we might end up lowering this as 0(%op)). - const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *TRI = TM.getRegisterInfo(); const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1); SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); SDValue NewOp = |