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| author | Shengchen Kan <shengchen.kan@intel.com> | 2024-02-01 14:03:05 +0800 |
|---|---|---|
| committer | Shengchen Kan <shengchen.kan@intel.com> | 2024-02-01 14:13:29 +0800 |
| commit | 1395e582f334f3db354b6e999d86a8662819e890 (patch) | |
| tree | 94e0704adf414cca2b8f13059ffc24b5dff79f0c | |
| parent | 6ff431b01e29e99c7dbfcda96bdefdff91dcdf7f (diff) | |
[X86][CodeGen] Set mayLoad = 1 for LZCNT/POPCNT/TZCNTrm_(EVEX|NF)
Promoted and NF LZCNT/POPCNT/TZCNT were supported in #79954.
B/c null_frag is used in the patterns for these variants, tablgen can
not infer mayLoad = 1 for them.
This can be tested by MCA tests, which will be added after
-mcpu=<cpu_with_apx> is supported.
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrMisc.td | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index a39b80592713..496a7e6b2943 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1166,11 +1166,12 @@ multiclass Lzcnt<bits<8> o, string m, SDPatternOperator node, X86TypeInfo t, [(set t.RegClass:$dst, (node t.RegClass:$src1)), (implicit EFLAGS)]>, TB, Sched<[schedrr]>; - def rm#suffix : ITy<o, MRMSrcMem, t, (outs t.RegClass:$dst), - (ins t.MemOperand:$src1), m, unaryop_ndd_args, - [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1))), - (implicit EFLAGS)]>, - TB, Sched<[schedrm]>; + let mayLoad = 1 in + def rm#suffix : ITy<o, MRMSrcMem, t, (outs t.RegClass:$dst), + (ins t.MemOperand:$src1), m, unaryop_ndd_args, + [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1))), + (implicit EFLAGS)]>, + TB, Sched<[schedrm]>; } let Predicates = [HasLZCNT], Defs = [EFLAGS] in { |