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path: root/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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* [RISCV] Make more vector pseudos commutablePengcheng Wang2024-04-161-0/+66
* [RISCV] Fix assertion failure in `genShXAddAddShift` (#88757)Yingwei Zheng2024-04-161-1/+1
* [RISCV] Support uimm32 immediates in RISCVInstrInfo::movImm for RV32. (#88464)Craig Topper2024-04-121-2/+9
* [RISCV] Split widening floating point fused multiple-add pseudo instructions ...Michael Maitland2024-04-121-2/+2
* [RISCV] Split single width floating point fused multiple-add pseudo instructi...Michael Maitland2024-04-121-92/+162
* [RISCV] Split PseudoVFWADD, PseudoVFWSUB, and PseudoVFWMUL by SEWMichael Maitland2024-04-121-6/+40
* [MachineCombiner][NFC] Split target-dependent patternsPengcheng Wang2024-04-111-37/+46
* [RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#7...Sacha Coppey2024-04-111-2/+5
* [RISCV] Add MachineCombiner to fold (sh3add Z, (add X, (slli Y, 6))) -> (sh3a...Craig Topper2024-04-101-0/+151
* [RISCV] Eliminate getVLENFactoredAmount and expose muladd [nfc] (#87881)Philip Reames2024-04-081-35/+24
* [RISCV] Store VLMul/NF into RegisterClass's TSFlagsPengcheng Wang2024-04-081-89/+17
* [RISCV] Use larger copies when register tuples are alignedPengcheng Wang2024-04-081-82/+100
* [RISCV] Add validation of SPIMM for cm.push/pop. (#84989)Craig Topper2024-03-281-0/+3
* [RISCV][NFC] Pass LMUL to copyPhysRegVectorWang Pengcheng2024-03-251-26/+26
* [CodeGen] Use LocationSize for MMO getSize (#84751)David Green2024-03-171-2/+2
* [Codegen] Make Width in getMemOperandsWithOffsetWidth a LocationSize. (#83875)David Green2024-03-061-5/+6
* [RISCV] Slightly improve expanded multiply emulation in getVLENFactoredAmount...Craig Topper2024-03-061-11/+17
* [RISCV] Use uint32_t for NumOfVReg in getVLENFactoredAmount. (#84110)Craig Topper2024-03-051-4/+4
* [RISCV] Remove X0 handling from RISCVInstrInfo::optimizeCondBranch. (#81931)Craig Topper2024-02-151-7/+1
* [RISCV] Make sure ADDI replacement in optimizeCondBranch has a virtual reg de...Craig Topper2024-02-151-1/+2
* [RISCV] Exclude X1 and X5 from register scavenging for long branch. (#80215)Craig Topper2024-02-121-1/+1
* [RISCV][NFC] Use maybe_unused instead of casting to void to fix unused variab...Yeting Kuo2024-02-061-1/+0
* [TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#80339)Philip Reames2024-02-011-4/+4
* [RISCV] Support TLSDESC in the RISC-V backend (#66915)Paul Kirth2024-01-231-1/+5
* [MachineOutliner] Refactor iterating over Candidate's instructions (#78972)Anatoly Trosinenko2024-01-231-4/+2
* Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.Simon Pilgrim2024-01-231-1/+1
* [RISCV] Fix stack size computation when M extension disabled (#78602)Simeon K2024-01-221-6/+27
* Revert "[RISCV] Implement RISCVInsrInfo::getConstValDefinedInReg"Alex Bradbury2024-01-171-33/+0
* [RISCV] Implement RISCVInsrInfo::getConstValDefinedInReg (#77610)Alex Bradbury2024-01-161-0/+33
* [RISCV] Refactor GPRF64 register class to make it usable for Zacas. (#77408)Craig Topper2024-01-091-8/+9
* [RISCV] Add support predicating for ANDN/ORN/XNOR with short-forward-branch-o...Jim Lin2024-01-091-0/+4
* [RISCV] Add branch+c.mv macrofusion for sifive-p450. (#76169)Craig Topper2024-01-081-0/+2
* [RISCV] Merge machine operand flag MO_PLT into MO_CALL (#77253)Fangrui Song2024-01-071-1/+0
* Revert "[RISCV] Refactor subreg indices. (#77173)"Craig Topper2024-01-061-7/+6
* [RISCV] Refactor subreg indices. (#77173)Craig Topper2024-01-061-6/+7
* [RISCV] Change heuristic used for load clustering (#75341)Alex Bradbury2024-01-021-3/+8
* [MachineScheduler][NFCI] Add Offset and OffsetIsScalable args to shouldCluste...Alex Bradbury2023-12-061-2/+3
* [RISCV] Support FrameIndex operands in getMemOperandsWithOffsetWidth / getMem...Alex Bradbury2023-12-051-1/+2
* [RISCV] Support load clustering in the MachineScheduler (off by default) (#73...Alex Bradbury2023-11-291-0/+55
* [RISCV] Implement RISCVInstrInfo::getMemOperandsWithOffsetWidth (#73681)Alex Bradbury2023-11-291-0/+40
* [AArch64] Use the same fast math preservation for MachineCombiner reassociati...Craig Topper2023-11-221-18/+0
* [RISCV] Don't set nsw/nuw/exact flag after MachineCombiner reassociation.Craig Topper2023-11-191-0/+9
* [RISCV] Implement RISCVInstrInfo::isAddImmediate (#72356)Alex Bradbury2023-11-161-0/+17
* [RISCV][NFC] Rewrite doc comment for RISCVInstrInfo::getMemOperandWithOffsetW...Alex Bradbury2023-11-151-3/+6
* [RISCV][GISel] Select G_BRCOND and G_ICMP together when possible.Craig Topper2023-11-121-7/+11
* [RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#7...Wang Pengcheng2023-11-091-2/+1
* [RISCV] CSE by swapping conditional branches (#71111)Min-Yih Hsu2023-11-031-0/+119
* [RISCV] Teach copyPhysReg to allow copies between GPR<->FPR32/FPR64 (#70525)Craig Topper2023-10-301-0/+30
* [RISCV][NFC] Move getRVVMCOpcode to RISCVInstrInfo (#70637)Wang Pengcheng2023-10-301-0/+8
* [RISCV] Reduce the number of parameters to copyPhysRegVector. NFC (#70502)Craig Topper2023-10-271-77/+86
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