diff options
author | Changpeng Fang <changpeng.fang@amd.com> | 2024-04-03 11:35:09 -0700 |
---|---|---|
committer | GitHub <noreply@github.com> | 2024-04-03 11:35:09 -0700 |
commit | 7c68a958e2213a5190d91ce6dddddb72ce732f1e (patch) | |
tree | 2a8016be05b4fb940a7a3e02407e509814e6d23b | |
parent | 52ae02db4044b5d6e55b48133ac641b0c998ef49 (diff) |
AMDGPU: Use PseudoInstr to name SIMCInstr for DSDIR and SOPs, NFC (#87537)
We should consistently use PseudoInstr instead of Mnemonic to name
SIMCInstr, even though they may be the same in most cases
-rw-r--r-- | llvm/lib/Target/AMDGPU/DSDIRInstructions.td | 2 | ||||
-rw-r--r-- | llvm/lib/Target/AMDGPU/SOPInstructions.td | 78 |
2 files changed, 40 insertions, 40 deletions
diff --git a/llvm/lib/Target/AMDGPU/DSDIRInstructions.td b/llvm/lib/Target/AMDGPU/DSDIRInstructions.td index f4f02d2cebfd..0541f0f65632 100644 --- a/llvm/lib/Target/AMDGPU/DSDIRInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSDIRInstructions.td @@ -112,7 +112,7 @@ class DSDIR_Real<DSDIR_Pseudo lds, dag ins, string asm, int subtarget> : lds.Mnemonic # asm, ins, lds.is_direct>, - SIMCInstr <lds.Mnemonic, subtarget> { + SIMCInstr <lds.PseudoInstr, subtarget> { let isPseudo = 0; let isCodeGenOnly = 0; diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index d34ee34e5bbf..0b7d45ee8c02 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -1972,7 +1972,7 @@ class Select_gfx6_gfx7<string opName> : SIMCInstr<opName, SIEncodingFamily.SI> { multiclass SOP1_Real_gfx11<bits<8> op, string name = !tolower(NAME)> { defvar ps = !cast<SOP1_Pseudo>(NAME); def _gfx11 : SOP1_Real<op, ps, name>, - Select_gfx11<ps.Mnemonic>; + Select_gfx11<ps.PseudoInstr>; if !ne(ps.Mnemonic, name) then def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>; } @@ -1980,14 +1980,14 @@ multiclass SOP1_Real_gfx11<bits<8> op, string name = !tolower(NAME)> { multiclass SOP1_Real_gfx12<bits<8> op, string name = !tolower(NAME)> { defvar ps = !cast<SOP1_Pseudo>(NAME); def _gfx12 : SOP1_Real<op, ps, name>, - Select_gfx12<ps.Mnemonic>; + Select_gfx12<ps.PseudoInstr>; if !ne(ps.Mnemonic, name) then def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>; } multiclass SOP1_M0_Real_gfx12<bits<8> op> { def _gfx12 : SOP1_Real<op, !cast<SOP1_Pseudo>(NAME)>, - Select_gfx12<!cast<SOP1_Pseudo>(NAME).Mnemonic> { + Select_gfx12<!cast<SOP1_Pseudo>(NAME).PseudoInstr> { let Inst{7-0} = M0_gfx11plus.HWEncoding{7-0}; // Set Src0 encoding to M0 } } @@ -1995,7 +1995,7 @@ multiclass SOP1_M0_Real_gfx12<bits<8> op> { multiclass SOP1_IMM_Real_gfx12<bits<8> op> { defvar ps = !cast<SOP1_Pseudo>(NAME); def _gfx12 : SOP1_Real<op, ps>, - Select_gfx12<ps.Mnemonic>; + Select_gfx12<ps.PseudoInstr>; } multiclass SOP1_Real_gfx11_gfx12<bits<8> op, string name = !tolower(NAME)> : @@ -2106,7 +2106,7 @@ defm S_RNDNE_F16 : SOP1_Real_gfx11_gfx12<0x06e>; multiclass SOP1_Real_gfx10<bits<8> op> { defvar ps = !cast<SOP1_Pseudo>(NAME); def _gfx10 : SOP1_Real<op, ps>, - Select_gfx10<ps.Mnemonic>; + Select_gfx10<ps.PseudoInstr>; } multiclass SOP1_Real_gfx10_gfx11_gfx12<bits<8> op> : @@ -2139,7 +2139,7 @@ defm S_MOVRELSD_2_B32 : SOP1_Real_gfx10<0x049>; multiclass SOP1_Real_gfx6_gfx7<bits<8> op> { defvar ps = !cast<SOP1_Pseudo>(NAME); def _gfx6_gfx7 : SOP1_Real<op, ps>, - Select_gfx6_gfx7<ps.Mnemonic>; + Select_gfx6_gfx7<ps.PseudoInstr>; } multiclass SOP1_Real_gfx6_gfx7_gfx10<bits<8> op> : @@ -2205,7 +2205,7 @@ defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>; multiclass SOP2_Real_gfx12<bits<7> op, string name = !tolower(NAME)> { defvar ps = !cast<SOP2_Pseudo>(NAME); def _gfx12 : SOP2_Real32<op, ps, name>, - Select_gfx12<ps.Mnemonic>; + Select_gfx12<ps.PseudoInstr>; if !ne(ps.Mnemonic, name) then def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>; } @@ -2222,7 +2222,7 @@ defm S_MAXIMUM_F16 : SOP2_Real_gfx12<0x052>; multiclass SOP2_Real_gfx11<bits<7> op, string name = !tolower(NAME)> { defvar ps = !cast<SOP2_Pseudo>(NAME); def _gfx11 : SOP2_Real32<op, ps, name>, - Select_gfx11<ps.Mnemonic>; + Select_gfx11<ps.PseudoInstr>; if !ne(ps.Mnemonic, name) then def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>; } @@ -2283,12 +2283,12 @@ defm S_MUL_U64 : SOP2_Real_gfx12<0x055>; multiclass SOP2_Real_FMAK_gfx12<bits<7> op> { def _gfx12 : SOP2_Real64<op, !cast<SOP2_Pseudo>(NAME)>, - Select_gfx12<!cast<SOP2_Pseudo>(NAME).Mnemonic>; + Select_gfx12<!cast<SOP2_Pseudo>(NAME).PseudoInstr>; } multiclass SOP2_Real_FMAK_gfx11<bits<7> op> { def _gfx11 : SOP2_Real64<op, !cast<SOP2_Pseudo>(NAME)>, - Select_gfx11<!cast<SOP2_Pseudo>(NAME).Mnemonic>; + Select_gfx11<!cast<SOP2_Pseudo>(NAME).PseudoInstr>; } multiclass SOP2_Real_FMAK_gfx11_gfx12<bits<7> op> : @@ -2325,7 +2325,7 @@ defm S_MAX_F16 : SOP2_Real_gfx11_Renamed_gfx12<0x04c, "s_max_num_f16">; multiclass SOP2_Real_gfx10<bits<7> op> { defvar ps = !cast<SOP2_Pseudo>(NAME); def _gfx10 : SOP2_Real32<op, ps>, - Select_gfx10<ps.Mnemonic>; + Select_gfx10<ps.PseudoInstr>; } multiclass SOP2_Real_gfx10_gfx11_gfx12<bits<7> op> : @@ -2348,7 +2348,7 @@ defm S_MUL_HI_I32 : SOP2_Real_gfx10<0x036>; multiclass SOP2_Real_gfx6_gfx7<bits<7> op> { defvar ps = !cast<SOP2_Pseudo>(NAME); def _gfx6_gfx7 : SOP2_Real32<op, ps>, - Select_gfx6_gfx7<ps.Mnemonic>; + Select_gfx6_gfx7<ps.PseudoInstr>; } multiclass SOP2_Real_gfx6_gfx7_gfx10<bits<7> op> : @@ -2410,24 +2410,24 @@ defm S_ABSDIFF_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x02c>; multiclass SOPK_Real32_gfx12<bits<5> op, string name = !tolower(NAME)> { defvar ps = !cast<SOPK_Pseudo>(NAME); def _gfx12 : SOPK_Real32<op, ps, name>, - Select_gfx12<ps.Mnemonic>; + Select_gfx12<ps.PseudoInstr>; if !ne(ps.Mnemonic, name) then def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>; } multiclass SOPK_Real32_gfx11<bits<5> op> { def _gfx11 : SOPK_Real32<op, !cast<SOPK_Pseudo>(NAME)>, - Select_gfx11<!cast<SOPK_Pseudo>(NAME).Mnemonic>; + Select_gfx11<!cast<SOPK_Pseudo>(NAME).PseudoInstr>; } multiclass SOPK_Real64_gfx12<bits<5> op> { def _gfx12 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>, - Select_gfx12<!cast<SOPK_Pseudo>(NAME).Mnemonic>; + Select_gfx12<!cast<SOPK_Pseudo>(NAME).PseudoInstr>; } multiclass SOPK_Real64_gfx11<bits<5> op> { def _gfx11 : SOPK_Real64<op, !cast<SOPK_Pseudo>(NAME)>, - Select_gfx11<!cast<SOPK_Pseudo>(NAME).Mnemonic>; + Select_gfx11<!cast<SOPK_Pseudo>(NAME).PseudoInstr>; } multiclass SOPK_Real32_gfx11_gfx12<bits<5> op> : @@ -2454,13 +2454,13 @@ defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx11<0x01b>; multiclass SOPK_Real32_gfx10<bits<5> op> { defvar ps = !cast<SOPK_Pseudo>(NAME); def _gfx10 : SOPK_Real32<op, ps>, - Select_gfx10<ps.Mnemonic>; + Select_gfx10<ps.PseudoInstr>; } multiclass SOPK_Real64_gfx10<bits<5> op> { defvar ps = !cast<SOPK_Pseudo>(NAME); def _gfx10 : SOPK_Real64<op, ps>, - Select_gfx10<ps.Mnemonic>; + Select_gfx10<ps.PseudoInstr>; } multiclass SOPK_Real32_gfx10_gfx11<bits<5> op> : @@ -2485,13 +2485,13 @@ defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx10<0x01c>; multiclass SOPK_Real32_gfx6_gfx7<bits<5> op> { defvar ps = !cast<SOPK_Pseudo>(NAME); def _gfx6_gfx7 : SOPK_Real32<op, ps>, - Select_gfx6_gfx7<ps.Mnemonic>; + Select_gfx6_gfx7<ps.PseudoInstr>; } multiclass SOPK_Real64_gfx6_gfx7<bits<5> op> { defvar ps = !cast<SOPK_Pseudo>(NAME); def _gfx6_gfx7 : SOPK_Real64<op, ps>, - Select_gfx6_gfx7<ps.Mnemonic>; + Select_gfx6_gfx7<ps.PseudoInstr>; } multiclass SOPK_Real32_gfx6_gfx7_gfx10<bits<5> op> : @@ -2539,7 +2539,7 @@ defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>; multiclass SOPP_Real_32_gfx12<bits<7> op, string name = !tolower(NAME)> { defvar ps = !cast<SOPP_Pseudo>(NAME); def _gfx12 : SOPP_Real_32<op, ps, name>, - Select_gfx12<ps.Mnemonic>; + Select_gfx12<ps.PseudoInstr>; if !ne(ps.Mnemonic, name) then def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX12Plus]>; } @@ -2564,7 +2564,7 @@ defm S_WAIT_STORECNT_DSCNT : SOPP_Real_32_gfx12<0x049>; multiclass SOPP_Real_32_gfx11<bits<7> op, string name = !tolower(NAME)> { defvar ps = !cast<SOPP_Pseudo>(NAME); def _gfx11 : SOPP_Real_32<op, ps, name>, - Select_gfx11<ps.Mnemonic>, + Select_gfx11<ps.PseudoInstr>, SOPPRelaxTable<0, ps.KeyName, "_gfx11">; if !ne(ps.Mnemonic, name) then def : MnemonicAlias<ps.Mnemonic, name>, Requires<[isGFX11Only]>; @@ -2572,13 +2572,13 @@ multiclass SOPP_Real_32_gfx11<bits<7> op, string name = !tolower(NAME)> { multiclass SOPP_Real_64_gfx12<bits<7> op> { def _gfx12 : SOPP_Real_64<op, !cast<SOPP_Pseudo>(NAME), !cast<SOPP_Pseudo>(NAME).Mnemonic>, - Select_gfx12<!cast<SOPP_Pseudo>(NAME).Mnemonic>, + Select_gfx12<!cast<SOPP_Pseudo>(NAME).PseudoInstr>, SOPPRelaxTable<1, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx12">; } multiclass SOPP_Real_64_gfx11<bits<7> op> { def _gfx11 : SOPP_Real_64<op, !cast<SOPP_Pseudo>(NAME), !cast<SOPP_Pseudo>(NAME).Mnemonic>, - Select_gfx11<!cast<SOPP_Pseudo>(NAME).Mnemonic>, + Select_gfx11<!cast<SOPP_Pseudo>(NAME).PseudoInstr>, SOPPRelaxTable<1, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx11">; } @@ -2654,21 +2654,21 @@ defm S_SINGLEUSE_VDST : SOPP_Real_32_gfx11_gfx12<0x013>; multiclass SOPP_Real_32_gfx6_gfx7<bits<7> op> { defvar ps = !cast<SOPP_Pseudo>(NAME); def _gfx6_gfx7 : SOPP_Real_32<op, ps, !cast<SOPP_Pseudo>(NAME).Mnemonic>, - Select_gfx6_gfx7<ps.Mnemonic>, + Select_gfx6_gfx7<ps.PseudoInstr>, SOPPRelaxTable<0, ps.KeyName, "_gfx6_gfx7">; } multiclass SOPP_Real_32_gfx8_gfx9<bits<7> op> { defvar ps = !cast<SOPP_Pseudo>(NAME); def _vi : SOPP_Real_32<op, ps>, - Select_vi<ps.Mnemonic>, + Select_vi<ps.PseudoInstr>, SOPPRelaxTable<0, ps.KeyName, "_vi">; } multiclass SOPP_Real_32_gfx10<bits<7> op> { defvar ps = !cast<SOPP_Pseudo>(NAME); def _gfx10 : SOPP_Real_32<op, ps>, - Select_gfx10<ps.Mnemonic>, + Select_gfx10<ps.PseudoInstr>, SOPPRelaxTable<0, ps.KeyName, "_gfx10">; } @@ -2691,21 +2691,21 @@ multiclass SOPP_Real_32_gfx10_gfx11_gfx12<bits<7> op> : multiclass SOPP_Real_64_gfx6_gfx7<bits<7> op> { defvar ps = !cast<SOPP_Pseudo>(NAME); def _gfx6_gfx7 : SOPP_Real_64<op, ps>, - Select_gfx6_gfx7<ps.Mnemonic>, + Select_gfx6_gfx7<ps.PseudoInstr>, SOPPRelaxTable<1, ps.KeyName, "_gfx6_gfx7">; } multiclass SOPP_Real_64_gfx8_gfx9<bits<7> op> { defvar ps = !cast<SOPP_Pseudo>(NAME); def _vi : SOPP_Real_64<op, ps>, - Select_vi<ps.Mnemonic>, + Select_vi<ps.PseudoInstr>, SOPPRelaxTable<1, ps.KeyName, "_vi">; } multiclass SOPP_Real_64_gfx10<bits<7> op> { defvar ps = !cast<SOPP_Pseudo>(NAME); def _gfx10 : SOPP_Real_64<op, ps>, - Select_gfx10<ps.Mnemonic>, + Select_gfx10<ps.PseudoInstr>, SOPPRelaxTable<1, ps.KeyName, "_gfx10">; } @@ -2771,12 +2771,12 @@ defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_ multiclass SOPC_Real_gfx12<bits<7> op> { def _gfx12 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>, - Select_gfx12<!cast<SOPC_Pseudo>(NAME).Mnemonic>; + Select_gfx12<!cast<SOPC_Pseudo>(NAME).PseudoInstr>; } multiclass SOPC_Real_gfx11<bits<7> op> { def _gfx11 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>, - Select_gfx11<!cast<SOPC_Pseudo>(NAME).Mnemonic>; + Select_gfx11<!cast<SOPC_Pseudo>(NAME).PseudoInstr>; } multiclass SOPC_Real_gfx11_gfx12<bits<7> op> : @@ -2826,19 +2826,19 @@ defm S_CMP_NLT_F16 : SOPC_Real_gfx11_gfx12<0x5e>; multiclass SOPC_Real_gfx6_gfx7<bits<7> op> { defvar ps = !cast<SOPC_Pseudo>(NAME); def _gfx6_gfx7 : SOPC_Real<op, ps>, - Select_gfx6_gfx7<ps.Mnemonic>; + Select_gfx6_gfx7<ps.PseudoInstr>; } multiclass SOPC_Real_gfx8_gfx9<bits<7> op> { defvar ps = !cast<SOPC_Pseudo>(NAME); def _vi : SOPC_Real<op, ps>, - Select_vi<ps.Mnemonic>; + Select_vi<ps.PseudoInstr>; } multiclass SOPC_Real_gfx10<bits<7> op> { defvar ps = !cast<SOPC_Pseudo>(NAME); def _gfx10 : SOPC_Real<op, ps>, - Select_gfx10<ps.Mnemonic>; + Select_gfx10<ps.PseudoInstr>; } multiclass SOPC_Real_gfx8_gfx9_gfx10<bits<7> op> : @@ -2878,15 +2878,15 @@ defm S_CMP_LG_U64 : SOPC_Real_gfx8_gfx9_gfx10<0x13>; class SOP1_Real_vi<bits<8> op, SOP1_Pseudo ps> : SOP1_Real<op, ps>, - Select_vi<ps.Mnemonic>; + Select_vi<ps.PseudoInstr>; class SOP2_Real_vi<bits<7> op, SOP2_Pseudo ps> : SOP2_Real32<op, ps>, - Select_vi<ps.Mnemonic>; + Select_vi<ps.PseudoInstr>; class SOPK_Real_vi<bits<5> op, SOPK_Pseudo ps> : SOPK_Real32<op, ps>, - Select_vi<ps.Mnemonic>; + Select_vi<ps.PseudoInstr>; def S_MOV_B32_vi : SOP1_Real_vi <0x00, S_MOV_B32>; def S_MOV_B64_vi : SOP1_Real_vi <0x01, S_MOV_B64>; @@ -3007,7 +3007,7 @@ def S_GETREG_B32_vi : SOPK_Real_vi <0x11, S_GETREG_B32>; def S_SETREG_B32_vi : SOPK_Real_vi <0x12, S_SETREG_B32>; //def S_GETREG_REGRD_B32_vi : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments def S_SETREG_IMM32_B32_vi : SOPK_Real64<0x14, S_SETREG_IMM32_B32>, - Select_vi<S_SETREG_IMM32_B32.Mnemonic>; + Select_vi<S_SETREG_IMM32_B32.PseudoInstr>; def S_CALL_B64_vi : SOPK_Real_vi <0x15, S_CALL_B64>; |