diff options
author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2024-04-03 19:29:01 +0100 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2024-04-03 19:29:15 +0100 |
commit | b15d27e24902444129bfec4095d68bf80f3af700 (patch) | |
tree | 65ce7d52605be092fd9486d8bb34b276277391fb | |
parent | d57884011e8c57b118b831614b692ba4bc8b5aca (diff) |
[VectorCombine][X86] Add additional tests for #87510
Add zext nneg tests and check we don't fold casts with different src types
-rw-r--r-- | llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll index 3a7c3318d2d9..b922528c2209 100644 --- a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll +++ b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll @@ -17,6 +17,33 @@ define <16 x i32> @concat_zext_v8i16_v16i32(<8 x i16> %a0, <8 x i16> %a1) { ret <16 x i32> %r } +define <16 x i32> @concat_zext_nneg_v8i8_v16i32(<8 x i8> %a0, <8 x i8> %a1) { +; CHECK-LABEL: @concat_zext_nneg_v8i8_v16i32( +; CHECK-NEXT: [[X0:%.*]] = zext nneg <8 x i8> [[A0:%.*]] to <8 x i32> +; CHECK-NEXT: [[X1:%.*]] = zext nneg <8 x i8> [[A1:%.*]] to <8 x i32> +; CHECK-NEXT: [[R:%.*]] = shufflevector <8 x i32> [[X0]], <8 x i32> [[X1]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +; CHECK-NEXT: ret <16 x i32> [[R]] +; + %x0 = zext nneg <8 x i8> %a0 to <8 x i32> + %x1 = zext nneg <8 x i8> %a1 to <8 x i32> + %r = shufflevector <8 x i32> %x0, <8 x i32> %x1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + ret <16 x i32> %r +} + +; TODO - sext + zext nneg -> sext +define <8 x i32> @concat_sext_zext_nneg_v4i8_v8i32(<4 x i8> %a0, <4 x i8> %a1) { +; CHECK-LABEL: @concat_sext_zext_nneg_v4i8_v8i32( +; CHECK-NEXT: [[X0:%.*]] = sext <4 x i8> [[A0:%.*]] to <4 x i32> +; CHECK-NEXT: [[X1:%.*]] = zext nneg <4 x i8> [[A1:%.*]] to <4 x i32> +; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[X0]], <4 x i32> [[X1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> +; CHECK-NEXT: ret <8 x i32> [[R]] +; + %x0 = sext <4 x i8> %a0 to <4 x i32> + %x1 = zext nneg <4 x i8> %a1 to <4 x i32> + %r = shufflevector <4 x i32> %x0, <4 x i32> %x1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + ret <8 x i32> %r +} + define <16 x i32> @concat_sext_v8i16_v16i32(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: @concat_sext_v8i16_v16i32( ; CHECK-NEXT: [[X0:%.*]] = sext <8 x i16> [[A0:%.*]] to <8 x i32> @@ -170,6 +197,21 @@ define <8 x float> @concat_bitcast_v4i32_v8f32(<4 x i32> %a0, <4 x i32> %a1) { ret <8 x float> %r } +; negative - src type mismatch + +define <8 x i32> @concat_sext_v4i8_v4i16_v8i32(<4 x i8> %a0, <4 x i16> %a1) { +; CHECK-LABEL: @concat_sext_v4i8_v4i16_v8i32( +; CHECK-NEXT: [[X0:%.*]] = sext <4 x i8> [[A0:%.*]] to <4 x i32> +; CHECK-NEXT: [[X1:%.*]] = sext <4 x i16> [[A1:%.*]] to <4 x i32> +; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[X0]], <4 x i32> [[X1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> +; CHECK-NEXT: ret <8 x i32> [[R]] +; + %x0 = sext <4 x i8> %a0 to <4 x i32> + %x1 = sext <4 x i16> %a1 to <4 x i32> + %r = shufflevector <4 x i32> %x0, <4 x i32> %x1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + ret <8 x i32> %r +} + ; negative - castop mismatch define <16 x i32> @concat_sext_zext_v8i16_v16i32(<8 x i16> %a0, <8 x i16> %a1) { |