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authorMalay Sanghi <malay.sanghi@intel.com>2024-04-08 20:31:51 +0800
committerGitHub <noreply@github.com>2024-04-08 20:31:51 +0800
commit38f996bb2bc4f922c7b441d730ab3a3ad2fa1506 (patch)
treeff93386d8590717dfc8fd7968e70f5310ebc68cf
parentfc9a5076c31139878da2fa12ef16090a58d55782 (diff)
Replace copy with a reference. (#87975)
-rw-r--r--llvm/lib/CodeGen/MachinePipeliner.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index b9c6765be445..930504067832 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -1247,7 +1247,7 @@ private:
for (auto &MI : *OrigMBB) {
if (MI.isDebugInstr())
continue;
- for (auto Use : ROMap[&MI].Uses) {
+ for (auto &Use : ROMap[&MI].Uses) {
auto Reg = Use.RegUnit;
// Ignore the variable that appears only on one side of phi instruction
// because it's used only at the first iteration.
@@ -1345,7 +1345,7 @@ private:
DenseMap<Register, MachineInstr *> LastUseMI;
for (MachineInstr *MI : llvm::reverse(OrderedInsts)) {
- for (auto Use : ROMap.find(MI)->getSecond().Uses) {
+ for (auto &Use : ROMap.find(MI)->getSecond().Uses) {
auto Reg = Use.RegUnit;
if (!TargetRegs.contains(Reg))
continue;