diff options
| author | David Green <david.green@arm.com> | 2024-04-08 08:44:13 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-08 08:44:13 +0100 |
| commit | ac321cbb0350996ceef4e6d9e8a1035880609288 (patch) | |
| tree | c149af9ab20749b9ba69df92d705ab33b3745df1 | |
| parent | 2084a07087a55b55bb3c2a8aafbe1c4464fdf796 (diff) | |
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
This attempts to standardize and extend some of the insert vector
element lowering. Most notably:
- More types are handled by splitting illegal vectors.
- The index type for G_INSERT_VECTOR_ELT is canonicalized to
TLI.getVectorIdxTy(), similar to extact_vector_element.
- Some of the existing patterns now have the index type specified to
make sure they can apply to GISel too.
- The C++ selection code has been removed, relying on tablegen patterns.
- G_INSERT_VECTOR_ELT with small GPR input elements are pre-selected to
use a i32 type, allowing the existing patterns to apply.
- Variable index inserts are lowered in post-legalizer lowering,
expanding into a stack store and reload.
37 files changed, 1759 insertions, 1319 deletions
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index 4c9d85fd9f51..be39eb7891f3 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -17,6 +17,7 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/IR/DebugLoc.h" #include "llvm/IR/Module.h" @@ -1300,8 +1301,10 @@ public: MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res, const SrcOp &Val, const int Idx) { - return buildExtractVectorElement(Res, Val, - buildConstant(LLT::scalar(64), Idx)); + auto TLI = getMF().getSubtarget().getTargetLowering(); + unsigned VecIdxWidth = TLI->getVectorIdxTy(getDataLayout()).getSizeInBits(); + return buildExtractVectorElement( + Res, Val, buildConstant(LLT::scalar(VecIdxWidth), Idx)); } /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td index 3208c63fb42d..dd4e7d790bc6 100644 --- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td +++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td @@ -142,6 +142,7 @@ def : GINodeEquiv<G_CTLZ_ZERO_UNDEF, ctlz_zero_undef>; def : GINodeEquiv<G_CTTZ_ZERO_UNDEF, cttz_zero_undef>; def : GINodeEquiv<G_CTPOP, ctpop>; def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, extractelt>; +def : GINodeEquiv<G_INSERT_VECTOR_ELT, vector_insert>; def : GINodeEquiv<G_CONCAT_VECTORS, concat_vectors>; def : GINodeEquiv<G_BUILD_VECTOR, build_vector>; def : GINodeEquiv<G_FCEIL, fceil>; diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 47e980e05281..312e564f5d80 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -3087,7 +3087,21 @@ bool IRTranslator::translateInsertElement(const User &U, Register Res = getOrCreateVReg(U); Register Val = getOrCreateVReg(*U.getOperand(0)); Register Elt = getOrCreateVReg(*U.getOperand(1)); - Register Idx = getOrCreateVReg(*U.getOperand(2)); + unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits(); + Register Idx; + if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(2))) { + if (CI->getBitWidth() != PreferredVecIdxWidth) { + APInt NewIdx = CI->getValue().zextOrTrunc(PreferredVecIdxWidth); + auto *NewIdxCI = ConstantInt::get(CI->getContext(), NewIdx); + Idx = getOrCreateVReg(*NewIdxCI); + } + } + if (!Idx) + Idx = getOrCreateVReg(*U.getOperand(2)); + if (MRI->getType(Idx).getSizeInBits() != PreferredVecIdxWidth) { + const LLT VecIdxTy = LLT::scalar(PreferredVecIdxWidth); + Idx = MIRBuilder.buildZExtOrTrunc(VecIdxTy, Idx).getReg(0); + } MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx); return true; } diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index fd7ea2842647..074408948631 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -55,6 +55,7 @@ #include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/StackMaps.h" #include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" @@ -1788,6 +1789,60 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) { break; } + case TargetOpcode::G_EXTRACT_VECTOR_ELT: { + LLT DstTy = MRI->getType(MI->getOperand(0).getReg()); + LLT SrcTy = MRI->getType(MI->getOperand(1).getReg()); + LLT IdxTy = MRI->getType(MI->getOperand(2).getReg()); + + if (!DstTy.isScalar() && !DstTy.isPointer()) { + report("Destination type must be a scalar or pointer", MI); + break; + } + + if (!SrcTy.isVector()) { + report("First source must be a vector", MI); + break; + } + + auto TLI = MF->getSubtarget().getTargetLowering(); + if (IdxTy.getSizeInBits() != + TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) { + report("Index type must match VectorIdxTy", MI); + break; + } + + break; + } + case TargetOpcode::G_INSERT_VECTOR_ELT: { + LLT DstTy = MRI->getType(MI->getOperand(0).getReg()); + LLT VecTy = MRI->getType(MI->getOperand(1).getReg()); + LLT ScaTy = MRI->getType(MI->getOperand(2).getReg()); + LLT IdxTy = MRI->getType(MI->getOperand(3).getReg()); + + if (!DstTy.isVector()) { + report("Destination type must be a vector", MI); + break; + } + + if (VecTy != DstTy) { + report("Destination type and vector type must match", MI); + break; + } + + if (!ScaTy.isScalar() && !ScaTy.isPointer()) { + report("Inserted element must be a scalar or pointer", MI); + break; + } + + auto TLI = MF->getSubtarget().getTargetLowering(); + if (IdxTy.getSizeInBits() != + TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) { + report("Index type must match VectorIdxTy", MI); + break; + } + + break; + } case TargetOpcode::G_DYN_STACKALLOC: { const MachineOperand &DstOp = MI->getOperand(0); const MachineOperand &AllocOp = MI->getOperand(1); diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td index 1e1c6ece85b2..10cad6d19244 100644 --- a/llvm/lib/Target/AArch64/AArch64Combine.td +++ b/llvm/lib/Target/AArch64/AArch64Combine.td @@ -114,6 +114,13 @@ def ext: GICombineRule < (apply [{ applyEXT(*${root}, ${matchinfo}); }]) >; +def insertelt_nonconst: GICombineRule < + (defs root:$root, shuffle_matchdata:$matchinfo), + (match (wip_match_opcode G_INSERT_VECTOR_ELT):$root, + [{ return matchNonConstInsert(*${root}, MRI); }]), + (apply [{ applyNonConstInsert(*${root}, MRI, B); }]) +>; + def shuf_to_ins_matchdata : GIDefMatchData<"std::tuple<Register, int, Register, int>">; def shuf_to_ins: GICombineRule < (defs root:$root, shuf_to_ins_matchdata:$matchinfo), @@ -140,8 +147,7 @@ def form_duplane : GICombineRule < >; def shuffle_vector_lowering : GICombineGroup<[dup, rev, ext, zip, uzp, trn, - form_duplane, - shuf_to_ins]>; + form_duplane, shuf_to_ins]>; // Turn G_UNMERGE_VALUES -> G_EXTRACT_VECTOR_ELT's def vector_unmerge_lowering : GICombineRule < @@ -269,7 +275,7 @@ def AArch64PostLegalizerLowering lower_vector_fcmp, form_truncstore, vector_sext_inreg_to_shift, unmerge_ext_to_unmerge, lower_mull, - vector_unmerge_lowering]> { + vector_unmerge_lowering, insertelt_nonconst]> { } // Post-legalization combines which are primarily optimizations. diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td index 0002db52b199..de94cf64c980 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td +++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td @@ -547,10 +547,10 @@ let Predicates = [HasLSE] in { let Predicates = [HasRCPC3, HasNEON] in { // LDAP1 loads def : Pat<(vector_insert (v2i64 VecListOne128:$Rd), - (i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)), VectorIndexD:$idx), + (i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)), (i64 VectorIndexD:$idx)), (LDAP1 VecListOne128:$Rd, VectorIndexD:$idx, GPR64sp:$Rn)>; def : Pat<(vector_insert (v2f64 VecListOne128:$Rd), - (f64 (bitconvert (i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)))), VectorIndexD:$idx), + (f64 (bitconvert (i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)))), (i64 VectorIndexD:$idx)), (LDAP1 VecListOne128:$Rd, VectorIndexD:$idx, GPR64sp:$Rn)>; def : Pat<(v1i64 (scalar_to_vector (i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)))), diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 8360bef8e2f8..1f437d0ed6f8 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -7983,7 +7983,7 @@ class SIMDInsFromMain<string size, ValueType vectype, "|" # size # "\t$Rd$idx, $Rn}", "$Rd = $dst", [(set V128:$dst, - (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> { + (vector_insert (vectype V128:$Rd), regtype:$Rn, (i64 idxtype:$idx)))]> { let Inst{14-11} = 0b0011; } @@ -7997,8 +7997,8 @@ class SIMDInsFromElement<string size, ValueType vectype, [(set V128:$dst, (vector_insert (vectype V128:$Rd), - (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)), - idxtype:$idx))]>; + (elttype (vector_extract (vectype V128:$Rn), (i64 idxtype:$idx2))), + (i64 idxtype:$idx)))]>; class SIMDInsMainMovAlias<string size, Instruction inst, RegisterClass regtype, Operand idxtype> diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index b1f514f75207..e1624f70185e 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -6601,6 +6601,15 @@ def : Pat<(v8i8 (vector_insert (v8i8 V64:$Rn), (i32 GPR32:$Rm), (i64 VectorIndex VectorIndexB:$imm, GPR32:$Rm), dsub)>; +def : Pat<(v8i8 (vector_insert (v8i8 V64:$Rn), (i8 FPR8:$Rm), (i64 VectorIndexB:$imm))), + (EXTRACT_SUBREG + (INSvi8lane (v16i8 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), V64:$Rn, dsub)), + VectorIndexB:$imm, (v16i8 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR8:$Rm, bsub)), (i64 0)), + dsub)>; +def : Pat<(v16i8 (vector_insert (v16i8 V128:$Rn), (i8 FPR8:$Rm), (i64 VectorIndexB:$imm))), + (INSvi8lane V128:$Rn, VectorIndexB:$imm, + (v16i8 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR8:$Rm, bsub)), (i64 0))>; + // Copy an element at a constant index in one vector into a constant indexed // element of another. // FIXME refactor to a shared class/dev parameterized on vector type, vector @@ -6633,26 +6642,26 @@ def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64, ValueType VTScal, Instruction INS> { def : Pat<(VT128 (vector_insert V128:$src, - (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)), - imm:$Immd)), + (VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))), + (i64 imm:$Immd))), (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>; def : Pat<(VT128 (vector_insert V128:$src, - (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)), - imm:$Immd)), + (VTScal (vector_extract (VT64 V64:$Rn), (i64 imm:$Immn))), + (i64 imm:$Immd))), (INS V128:$src, imm:$Immd, (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>; def : Pat<(VT64 (vector_insert V64:$src, - (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)), - imm:$Immd)), + (VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))), + (i64 imm:$Immd))), (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd, V128:$Rn, imm:$Immn), dsub)>; def : Pat<(VT64 (vector_insert V64:$src, - (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)), - imm:$Immd)), + (VTScal (vector_extract (VT64 V64:$Rn), (i64 imm:$Immn))), + (i64 imm:$Immd))), (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd, (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn), @@ -6671,14 +6680,14 @@ defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi64lane>; // Insert from bitcast // vector_insert(bitcast(f32 src), n, lane) -> INSvi32lane(src, lane, INSERT_SUBREG(-, n), 0) -def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), imm:$Immd)), +def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))), (INSvi32lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0)>; -def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), imm:$Immd)), +def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))), (EXTRACT_SUBREG (INSvi32lane (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$src, dsub)), imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0), dsub)>; -def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 (bitconvert (f64 FPR64:$Sn))), imm:$Immd)), +def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 (bitconvert (f64 FPR64:$Sn))), (i64 imm:$Immd))), (INSvi64lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$Sn, dsub), 0)>; // bitcast of an extract @@ -8100,7 +8109,7 @@ def : Pat<(v8bf16 (AArch64dup (bf16 (load GPR64sp:$Rn)))), class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex, ValueType VTy, ValueType STy, Instruction LD1> : Pat<(vector_insert (VTy VecListOne128:$Rd), - (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), + (STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)), (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>; def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>; @@ -8123,14 +8132,14 @@ class Ld1Lane128IdxOpPat<SDPatternOperator scalar_load, Operand VecIndex, ValueType VTy, ValueType STy, Instruction LD1, SDNodeXForm IdxOp> : Pat<(vector_insert (VTy VecListOne128:$Rd), - (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), + (STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)), (LD1 VecListOne128:$Rd, (IdxOp VecIndex:$idx), GPR64sp:$Rn)>; class Ld1Lane64IdxOpPat<SDPatternOperator scalar_load, Operand VecIndex, ValueType VTy, ValueType STy, Instruction LD1, SDNodeXForm IdxOp> : Pat<(vector_insert (VTy VecListOne64:$Rd), - (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), + (STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)), (EXTRACT_SUBREG (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub), (IdxOp VecIndex:$idx), GPR64sp:$Rn), @@ -8170,7 +8179,7 @@ let Predicates = [IsNeonAvailable] in { class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex, ValueType VTy, ValueType STy, Instruction LD1> : Pat<(vector_insert (VTy VecListOne64:$Rd), - (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), + (STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)), (EXTRACT_SUBREG (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub), VecIndex:$idx, GPR64sp:$Rn), diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index d4daf17a39d5..61f5bc2464ee 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -191,7 +191,6 @@ private: MachineInstr *tryAdvSIMDModImmFP(Register Dst, unsigned DstSize, APInt Bits, MachineIRBuilder &MIRBuilder); - bool selectInsertElt(MachineInstr &I, MachineRegisterInfo &MRI); bool tryOptConstantBuildVec(MachineInstr &MI, LLT DstTy, MachineRegisterInfo &MRI); /// \returns true if a G_BUILD_VECTOR instruction \p MI can be selected as a @@ -3498,8 +3497,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { return selectShuffleVector(I, MRI); case TargetOpcode::G_EXTRACT_VECTOR_ELT: return selectExtractElt(I, MRI); - case TargetOpcode::G_INSERT_VECTOR_ELT: - return selectInsertElt(I, MRI); case TargetOpcode::G_CONCAT_VECTORS: return selectConcatVectors(I, MRI); case TargetOpcode::G_JUMP_TABLE: @@ -5330,65 +5327,6 @@ bool AArch64InstructionSelector::selectUSMovFromExtend( return true; } -bool AArch64InstructionSelector::selectInsertElt(MachineInstr &I, - MachineRegisterInfo &MRI) { - assert(I.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT); - - // Get information on the destination. - Register DstReg = I.getOperand(0).getReg(); - const LLT DstTy = MRI.getType(DstReg); - unsigned VecSize = DstTy.getSizeInBits(); - - // Get information on the element we want to insert into the destination. - Register EltReg = I.getOperand(2).getReg(); - const LLT EltTy = MRI.getType(EltReg); - unsigned EltSize = EltTy.getSizeInBits(); - if (EltSize < 8 || EltSize > 64) - return false; - - // Find the definition of the index. Bail out if it's not defined by a - // G_CONSTANT. - Register IdxReg = I.getOperand(3).getReg(); - auto VRegAndVal = getIConstantVRegValWithLookThrough(IdxReg, MRI); - if (!VRegAndVal) - return false; - unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); - - // Perform the lane insert. - Register SrcReg = I.getOperand(1).getReg(); - const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); - - if (VecSize < 128) { - // If the vector we're inserting into is smaller than 128 bits, widen it - // to 128 to do the insert. - MachineInstr *ScalarToVec = - emitScalarToVector(VecSize, &AArch64::FPR128RegClass, SrcReg, MIB); - if (!ScalarToVec) - return false; - SrcReg = ScalarToVec->getOperand(0).getReg(); - } - - // Create an insert into a new FPR128 register. - // Note that if our vector is already 128 bits, we end up emitting an extra - // register. - MachineInstr *InsMI = - emitLaneInsert(std::nullopt, SrcReg, EltReg, LaneIdx, EltRB, MIB); - - if (VecSize < 128) { - // If we had to widen to perform the insert, then we have to demote back to - // the original size to get the result we want. - if (!emitNarrowVector(DstReg, InsMI->getOperand(0).getReg(), MIB, MRI)) - return false; - } else { - // No widening needed. - InsMI->getOperand(0).setReg(DstReg); - constrainSelectedInstRegOperands(*InsMI, TII, TRI, RBI); - } - - I.eraseFromParent(); - return true; -} - MachineInstr *AArch64InstructionSelector::tryAdvSIMDModImm8( Register Dst, unsigned DstSize, APInt Bits, MachineIRBuilder &Builder) { unsigned int Op; diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index 043f142f3099..96ded69905f7 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -886,9 +886,15 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) .clampMaxNumElements(1, p0, 2); getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT) - .legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64})) + .legalIf( + typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64, v2p0})) .moreElementsToNextPow2(0) - .widenVectorEltsToVectorMinSize(0, 64); + .widenVectorEltsToVectorMinSize(0, 64) + .clampNumElements(0, v8s8, v16s8) + .clampNumElements(0, v4s16, v8s16) + .clampNumElements(0, v2s32, v4s32) + .clampMaxNumElements(0, s64, 2) + .clampMaxNumElements(0, p0, 2); getActionDefinitionsBuilder(G_BUILD_VECTOR) .legalFor({{v8s8, s8}, diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp index 3cee2de4f5df..b571f56bf9e1 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp @@ -36,6 +36,7 @@ #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" #include "llvm/CodeGen/GlobalISel/Utils.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -475,6 +476,55 @@ void applyEXT(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) { MI.eraseFromParent(); } +bool matchNonConstInsert(MachineInstr &MI, MachineRegisterInfo &MRI) { + assert(MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT); + + auto ValAndVReg = + getIConstantVRegValWithLookThrough(MI.getOperand(3).getReg(), MRI); + return !ValAndVReg; +} + +void applyNonConstInsert(MachineInstr &MI, MachineRegisterInfo &MRI, + MachineIRBuilder &Builder) { + auto &Insert = cast<GInsertVectorElement>(MI); + Builder.setInstrAndDebugLoc(Insert); + + Register Offset = Insert.getIndexReg(); + LLT VecTy = MRI.getType(Insert.getReg(0)); + LLT EltTy = MRI.getType(Insert.getElementReg()); + LLT IdxTy = MRI.getType(Insert.getIndexReg()); + + // Create a stack slot and store the vector into it + MachineFunction &MF = Builder.getMF(); + Align Alignment( + std::min<uint64_t>(VecTy.getSizeInBytes().getKnownMinValue(), 16)); + int FrameIdx = MF.getFrameInfo().CreateStackObject(VecTy.getSizeInBytes(), + Alignment, false); + LLT FramePtrTy = LLT::pointer(0, 64); + MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIdx); + auto StackTemp = Builder.buildFrameIndex(FramePtrTy, FrameIdx); + + Builder.buildStore(Insert.getOperand(1), StackTemp, PtrInfo, Align(8)); + + // Get the pointer to the element, and be sure not to hit undefined behavior + // if the index is out of bounds. + assert(isPowerOf2_64(VecTy.getNumElements()) && + "Expected a power-2 vector size"); + auto Mask = Builder.buildConstant(IdxTy, VecTy.getNumElements() - 1); + Register And = Builder.buildAnd(IdxTy, Offset, Mask).getReg(0); + auto EltSize = Builder.buildConstant(IdxTy, EltTy.getSizeInBytes()); + Register Mul = Builder.buildMul(IdxTy, And, EltSize).getReg(0); + Register EltPtr = + Builder.buildPtrAdd(MRI.getType(StackTemp.getReg(0)), StackTemp, Mul) + .getReg(0); + + // Write the inserted element + Builder.buildStore(Insert.getElementReg(), EltPtr, PtrInfo, Align(1)); + // Reload the whole vector. + Builder.buildLoad(Insert.getReg(0), StackTemp, PtrInfo, Align(8)); + Insert.eraseFromParent(); +} + /// Match a G_SHUFFLE_VECTOR with a mask which corresponds to a /// G_INSERT_VECTOR_ELT and G_EXTRACT_VECTOR_ELT pair. /// diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp index 0fc4d7f19910..58d000b6b2a9 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp @@ -17,6 +17,7 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h" +#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" #include "llvm/CodeGen/GlobalISel/Utils.h" #include "llvm/CodeGen/LowLevelTypeUtils.h" #include "llvm/CodeGen/MachineFunction.h" @@ -398,7 +399,10 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings( void AArch64RegisterBankInfo::applyMappingImpl( MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const { - switch (OpdMapper.getMI().getOpcode()) { + MachineInstr &MI = OpdMapper.getMI(); + MachineRegisterInfo &MRI = OpdMapper.getMRI(); + + switch (MI.getOpcode()) { case TargetOpcode::G_OR: case TargetOpcode::G_BITCAST: case TargetOpcode::G_LOAD: @@ -407,6 +411,14 @@ void AArch64RegisterBankInfo::applyMappingImpl( OpdMapper.getInstrMapping().getID() <= 4) && "Don't know how to handle that ID"); return applyDefaultMapping(OpdMapper); + case TargetOpcode::G_INSERT_VECTOR_ELT: { + // Extend smaller gpr operands to 32 bit. + Builder.setInsertPt(*MI.getParent(), MI.getIterator()); + auto Ext = Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(2).getReg()); + MRI.setRegBank(Ext.getReg(0), getRegBank(AArch64::GPRRegBankID)); + MI.getOperand(2).setReg(Ext.getReg(0)); + return applyDefaultMapping(OpdMapper); + } default: llvm_unreachable("Don't know how to handle that operation"); } @@ -752,6 +764,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { } unsigned NumOperands = MI.getNumOperands(); + unsigned MappingID = DefaultMappingID; // Track the size and bank of each register. We don't do partial mappings. SmallVector<unsigned, 4> OpSize(NumOperands); @@ -1002,8 +1015,14 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // The element may be either a GPR or FPR. Preserve that behaviour. if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank) OpRegBankIdx[2] = PMI_FirstFPR; - else + else { + // If the type is i8/i16, and the regank will be GPR, then we change the + // type to i32 in applyMappingImpl. + LLT Ty = MRI.getType(MI.getOperand(2).getReg()); + if (Ty.getSizeInBits() == 8 || Ty.getSizeInBits() == 16) + MappingID = 1; OpRegBankIdx[2] = PMI_FirstGPR; + } // Index needs to be a GPR. OpRegBankIdx[3] = PMI_FirstGPR; @@ -1124,6 +1143,6 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { } } - return getInstructionMapping(DefaultMappingID, Cost, - getOperandsMapping(OpdsMapping), NumOperands); + return getInstructionMapping(MappingID, Cost, getOperandsMapping(OpdsMapping), + NumOperands); } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll index 0a2d695acb4e..29c320da6c0a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -27,22 +27,6 @@ define void @test_write_register_intrin() { @_ZTIi = external global ptr declare i32 @__gxx_personality_v0(...) -; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(<2 x p0>) = G_INSERT_VECTOR_ELT %0:_, %{{[0-9]+}}:_(p0), %{{[0-9]+}}:_(s32) (in function: vector_of_pointers_insertelement) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement -; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement: -define void @vector_of_pointers_insertelement() { - br label %end - -block: - %dummy = insertelement <2 x ptr> %vec, ptr null, i32 0 - store <2 x ptr> %dummy, ptr undef - ret void - -end: - %vec = load <2 x ptr>, ptr undef - br label %block -} - ; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: cannot select: RET_ReallyLR implicit $x0 (in function: strict_align_feature) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for strict_align_feature ; FALLBACK-WITH-REPORT-OUT-LABEL: strict_align_feature diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 92ddc6309546..a131f35e66d0 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -1538,7 +1538,8 @@ define <2 x i32> @test_insertelement(<2 x i32> %vec, i32 %elt, i32 %idx){ ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0 ; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY $w1 -; CHECK: [[RES:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX]](s32) +; CHECK: [[IDX2:%[0-9]+]]:_(s64) = G_ZEXT [[IDX]] +; CHECK: [[RES:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX2]](s64) ; CHECK: $d0 = COPY [[RES]](<2 x s32>) %res = insertelement <2 x i32> %vec, i32 %elt, i32 %idx ret <2 x i32> %res diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir index 2d36fb3df033..93f6051c3bd3 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir @@ -25,11 +25,11 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 - %one:_(s32) = G_CONSTANT i32 1 + %zero:_(s64) = G_CONSTANT i64 0 + %one:_(s64) = G_CONSTANT i64 1 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) - %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) + %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s64) $x0 = COPY %extract(s64) $x1 = COPY %extract2(s64) RET_ReallyLR implicit $x0 @@ -55,22 +55,22 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %arg1:_(s64) = COPY $x0 ; CHECK-NEXT: %arg2:_(s64) = COPY $x1 - ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: %one:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) - ; CHECK-NEXT: %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s32) + ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) + ; CHECK-NEXT: %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s64) ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: $x1 = COPY %extract2(s64) ; CHECK-NEXT: $q0 = COPY %bv(<2 x s64>) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 - %one:_(s32) = G_CONSTANT i32 1 + %zero:_(s64) = G_CONSTANT i64 0 + %one:_(s64) = G_CONSTANT i64 1 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) - %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) + %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s64) $x0 = COPY %extract(s64) $x1 = COPY %extract2(s64) $q0 = COPY %bv(<2 x s64>) @@ -103,12 +103,12 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 - %one:_(s32) = G_CONSTANT i32 1 + %zero:_(s64) = G_CONSTANT i64 0 + %one:_(s64) = G_CONSTANT i64 1 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) - %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s32) - %extract3:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) + %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s64) + %extract3:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s64) $x0 = COPY %extract(s64) $x1 = COPY %extract2(s64) $x2 = COPY %extract3(s64) @@ -140,12 +140,12 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 - %one:_(s32) = G_CONSTANT i32 1 - %two:_(s32) = G_CONSTANT i32 2 + %zero:_(s64) = G_CONSTANT i64 0 + %one:_(s64) = G_CONSTANT i64 1 + %two:_(s64) = G_CONSTANT i64 2 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) - %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %two(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) + %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %two(s64) $x0 = COPY %extract(s64) $x1 = COPY %extract2(s64) RET_ReallyLR implicit $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir index a65b43d33e49..587d53c300f8 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir @@ -23,9 +23,9 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 + %zero:_(s64) = G_CONSTANT i64 0 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -55,10 +55,10 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 + %zero:_(s64) = G_CONSTANT i64 0 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) %truncbv:_(<2 x s32>) = G_TRUNC %bv - %extract:_(s32) = G_EXTRACT_VECTOR_ELT %truncbv(<2 x s32>), %zero(s32) + %extract:_(s32) = G_EXTRACT_VECTOR_ELT %truncbv(<2 x s32>), %zero(s64) %zext:_(s64) = G_ZEXT %extract $x0 = COPY %zext(s64) RET_ReallyLR implicit $x0 @@ -87,9 +87,9 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %one:_(s32) = G_CONSTANT i32 1 + %one:_(s64) = G_CONSTANT i64 1 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -117,9 +117,9 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %idx:_(s32) = G_CONSTANT i32 4 + %idx:_(s64) = G_CONSTANT i64 4 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -148,9 +148,9 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $w0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 + %zero:_(s64) = G_CONSTANT i64 0 %bv:_(<2 x s32>) = G_BUILD_VECTOR_TRUNC %arg1(s64), %arg2(s64) - %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %zero(s32) + %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %zero(s64) $w0 = COPY %extract(s32) RET_ReallyLR implicit $w0 @@ -175,17 +175,17 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %arg1:_(s64) = COPY $x0 ; CHECK-NEXT: %arg2:_(s64) = COPY $x1 - ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0 ; CHECK-NEXT: %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) + ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: $q0 = COPY %bv(<2 x s64>) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 + %zero:_(s64) = G_CONSTANT i64 0 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) $x0 = COPY %extract(s64) $q0 = COPY %bv(<2 x s64>) RET_ReallyLR implicit $x0 @@ -212,11 +212,11 @@ body: | %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 %undef:_(<2 x s64>) = G_IMPLICIT_DEF - %zero:_(s32) = G_CONSTANT i32 0 - %one:_(s32) = G_CONSTANT i32 1 - %ins1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %undef, %arg1(s64), %zero(s32) - %ins2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %ins1, %arg2(s64), %one(s32) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %ins2(<2 x s64>), %zero(s32) + %zero:_(s64) = G_CONSTANT i64 0 + %one:_(s64) = G_CONSTANT i64 1 + %ins1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %undef, %arg1(s64), %zero(s64) + %ins2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %ins1, %arg2(s64), %one(s64) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %ins2(<2 x s64>), %zero(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -244,10 +244,10 @@ body: | %arg0:_(<2 x s64>) = COPY $q0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 - %one:_(s32) = G_CONSTANT i32 1 - %ins1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %arg0, %arg1(s64), %zero(s32) - %ins2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %ins1, %arg2(s64), %one(s32) + %zero:_(s64) = G_CONSTANT i64 0 + %one:_(s64) = G_CONSTANT i64 1 + %ins1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %arg0, %arg1(s64), %zero(s64) + %ins2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %ins1, %arg2(s64), %one(s64) $q0 = COPY %ins2(<2 x s64>) RET_ReallyLR implicit $q0 @@ -270,8 +270,8 @@ body: | ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = G_CONSTANT i32 -2 - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s32) + %idx:_(s64) = G_CONSTANT i64 -2 + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -294,8 +294,8 @@ body: | ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = G_IMPLICIT_DEF - %idx:_(s32) = G_CONSTANT i32 -2 - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s32) + %idx:_(s64) = G_CONSTANT i64 -2 + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -315,8 +315,8 @@ body: | ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = G_IMPLICIT_DEF - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s32) + %idx:_(s64) = G_IMPLICIT_DEF + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -339,8 +339,8 @@ body: | ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = G_CONSTANT i32 3000 - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s32) + %idx:_(s64) = G_CONSTANT i64 3000 + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -360,15 +360,15 @@ body: | ; CHECK: liveins: $x0, $x1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %vec:_(<2 x s64>) = COPY $q0 - ; CHECK-NEXT: %idx:_(s32) = COPY $w1 - ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s32) + ; CHECK-NEXT: %idx:_(s64) = COPY $x1 + ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s64) ; CHECK-NEXT: %extract:_(s64) = G_FREEZE [[EVEC]] ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = COPY $w1 + %idx:_(s64) = COPY $x1 %fvec:_(<2 x s64>) = G_FREEZE %vec - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %fvec(<2 x s64>), %idx(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %fvec(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -391,10 +391,10 @@ body: | ; CHECK-NEXT: $x0 = COPY %element(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = COPY $w1 + %idx:_(s64) = COPY $x1 %element:_(s64) = COPY $x1 - %invec:_(<2 x s64>) = G_INSERT_VECTOR_ELT %vec(<2 x s64>), %element(s64), %idx(s32) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %invec(<2 x s64>), %idx(s32) + %invec:_(<2 x s64>) = G_INSERT_VECTOR_ELT %vec(<2 x s64>), %element(s64), %idx(s64) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %invec(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -414,16 +414,16 @@ body: | ; CHECK: liveins: $x0, $x1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %vec:_(<2 x s64>) = COPY $q0 - ; CHECK-NEXT: %idx2:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx2(s32) + ; CHECK-NEXT: %idx2:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx2(s64) ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = G_CONSTANT i32 0 - %idx2:_(s32) = G_CONSTANT i32 1 + %idx:_(s64) = G_CONSTANT i64 0 + %idx2:_(s64) = G_CONSTANT i64 1 %element:_(s64) = COPY $x1 - %invec:_(<2 x s64>) = G_INSERT_VECTOR_ELT %vec(<2 x s64>), %element(s64), %idx(s32) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %invec(<2 x s64>), %idx2(s32) + %invec:_(<2 x s64>) = G_INSERT_VECTOR_ELT %vec(<2 x s64>), %element(s64), %idx(s64) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %invec(<2 x s64>), %idx2(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -442,19 +442,19 @@ body: | ; CHECK-LABEL: name: extract_from_build_vector_non_const ; CHECK: liveins: $x0, $x1 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %idx:_(s32) = COPY $w0 + ; CHECK-NEXT: %idx:_(s64) = COPY $x0 ; CHECK-NEXT: %arg1:_(s64) = COPY $x0 ; CHECK-NEXT: %arg2:_(s64) = COPY $x1 ; CHECK-NEXT: %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s32) + ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s64) ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = COPY $w0 + %idx:_(s64) = COPY $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -477,11 +477,11 @@ body: | ; CHECK-NEXT: $x0 = COPY %arg1(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = G_CONSTANT i32 0 + %idx:_(s64) = G_CONSTANT i64 0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -509,9 +509,9 @@ body: | %arg2:_(s64) = COPY $x1 %arg3:_(s64) = COPY $x0 %arg4:_(s64) = COPY $x1 - %idx:_(s32) = G_CONSTANT i32 0 + %idx:_(s64) = G_CONSTANT i64 0 %bv:_(<4 x s32>) = G_BUILD_VECTOR_TRUNC %arg1(s64), %arg2(s64), %arg3(s64), %arg4(s64) - %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<4 x s32>), %idx(s32) + %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<4 x s32>), %idx(s64) $w0 = COPY %extract(s32) RET_ReallyLR implicit $x0 ... @@ -531,16 +531,16 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %arg1:_(s64) = COPY $x0 ; CHECK-NEXT: %arg2:_(s64) = COPY $x1 - ; CHECK-NEXT: %idx:_(s32) = COPY $w0 + ; CHECK-NEXT: %idx:_(s64) = COPY $x0 ; CHECK-NEXT: %bv:_(<2 x s32>) = G_BUILD_VECTOR_TRUNC %arg1(s64), %arg2(s64) - ; CHECK-NEXT: %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %idx(s32) + ; CHECK-NEXT: %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %idx(s64) ; CHECK-NEXT: $w0 = COPY %extract(s32) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %idx:_(s32) = COPY $w0 + %idx:_(s64) = COPY $x0 %bv:_(<2 x s32>) = G_BUILD_VECTOR_TRUNC %arg1(s64), %arg2(s64) - %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %idx(s32) + %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %idx(s64) $w0 = COPY %extract(s32) RET_ReallyLR implicit $x0 ... @@ -564,9 +564,9 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s128) = COPY $q0 %arg2:_(s128) = COPY $q1 - %idx:_(s32) = G_CONSTANT i32 0 + %idx:_(s64) = G_CONSTANT i64 0 %bv:_(<2 x s64>) = G_BUILD_VECTOR_TRUNC %arg1(s128), %arg2(s128) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir index fb072fbe97c1..63343dd8ad93 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir @@ -129,25 +129,28 @@ body: | ; CHECK-LABEL: name: dont_apply_vector ; CHECK: liveins: $x0 - ; CHECK: %x:_(<2 x s32>) = COPY $x0 - ; CHECK: %one:_(s32) = G_CONSTANT i32 1 - ; CHECK: %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one(s32), %one(s32) - ; CHECK: %vec_and:_(<2 x s32>) = G_AND %x, %one_vec - ; CHECK: %zero:_(s32) = G_CONSTANT i32 0 - ; CHECK: %zero_vec:_(<2 x s32>) = G_BUILD_VECTOR %zero(s32), %zero(s32) - ; CHECK: %cmp:_(<2 x s1>) = G_ICMP intpred(ne), %vec_and(<2 x s32>), %zero_vec - ; CHECK: %elt:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %zero(s32) - ; CHECK: %ext:_(s32) = G_ZEXT %elt(s1) - ; CHECK: $w0 = COPY %ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:_(<2 x s32>) = COPY $x0 + ; CHECK-NEXT: %one:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one(s32), %one(s32) + ; CHECK-NEXT: %vec_and:_(<2 x s32>) = G_AND %x, %one_vec + ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: %zero64:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: %zero_vec:_(<2 x s32>) = G_BUILD_VECTOR %zero(s32), %zero(s32) + ; CHECK-NEXT: %cmp:_(<2 x s1>) = G_ICMP intpred(ne), %vec_and(<2 x s32>), %zero_vec + ; CHECK-NEXT: %elt:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %zero64(s64) + ; CHECK-NEXT: %ext:_(s32) = G_ZEXT %elt(s1) + ; CHECK-NEXT: $w0 = COPY %ext(s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %x:_(<2 x s32>) = COPY $x0 %one:_(s32) = G_CONSTANT i32 1 %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one, %one %vec_and:_(<2 x s32>) = G_AND %x, %one_vec %zero:_(s32) = G_CONSTANT i32 0 + %zero64:_(s64) = G_CONSTANT i64 0 %zero_vec:_(<2 x s32>) = G_BUILD_VECTOR %zero, %zero %cmp:_(<2 x s1>) = G_ICMP intpred(ne), %vec_and(<2 x s32>), %zero_vec - %elt:_(s1) = G_EXTRACT_VECTOR_ELT %cmp, %zero + %elt:_(s1) = G_EXTRACT_VECTOR_ELT %cmp, %zero64 %ext:_(s32) = G_ZEXT %elt(s1) $w0 = COPY %ext(s32) RET_ReallyLR implicit $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir index 254467192fb3..06fb2ce161c2 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir @@ -16,10 +16,10 @@ body: | %0:_(s32) = COPY $w0 %1:_(s32) = COPY $w1 %2:_(<2 x s32>) = G_IMPLICIT_DEF - %7:_(s32) = G_CONSTANT i32 0 - %8:_(s32) = G_CONSTANT i32 1 - %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32) - %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s32) + %7:_(s64) = G_CONSTANT i64 0 + %8:_(s64) = G_CONSTANT i64 1 + %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s64) + %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s64) $x0 = COPY %4 ... --- @@ -38,10 +38,10 @@ body: | %0:_(s32) = COPY $w0 %1:_(s32) = COPY $w1 %2:_(<2 x s32>) = G_IMPLICIT_DEF - %7:_(s32) = G_CONSTANT i32 1 - %8:_(s32) = G_CONSTANT i32 0 - %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32) - %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s32) + %7:_(s64) = G_CONSTANT i64 1 + %8:_(s64) = G_CONSTANT i64 0 + %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s64) + %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s64) $x0 = COPY %4 ... --- @@ -63,8 +63,8 @@ body: | %6:_(s32) = COPY $w2 %7:_(s32) = COPY $w3 %2:_(<4 x s32>) = G_BUILD_VECTOR %0, %1, %6, %7 - %3:_(s32) = G_CONSTANT i32 1 - %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 1 + %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) $q0 = COPY %4 ... --- @@ -83,33 +83,33 @@ body: | %6:_(s32) = COPY $w2 %7:_(s32) = COPY $w3 %2:_(<4 x s32>) = G_BUILD_VECTOR %0, %1, %6, %7 - %3:_(s32) = G_CONSTANT i32 4 - %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 4 + %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) $q0 = COPY %4 ... --- name: test_combine_insert_vec_build_vec_variable body: | bb.1: - liveins: $w0, $w1, $w2, $w3 + liveins: $x0, $w1, $w2, $w3 ; CHECK-LABEL: name: test_combine_insert_vec_build_vec_variable - ; CHECK: liveins: $w0, $w1, $w2, $w3 + ; CHECK: liveins: $x0, $w1, $w2, $w3 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3 - ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY]](s32), [[COPY]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY1]](s32), [[COPY]](s64) ; CHECK-NEXT: $q0 = COPY [[IVEC]](<4 x s32>) - %0:_(s32) = COPY $w0 + %0:_(s64) = COPY $x0 %1:_(s32) = COPY $w1 %6:_(s32) = COPY $w2 %7:_(s32) = COPY $w3 - %2:_(<4 x s32>) = G_BUILD_VECTOR %0, %1, %6, %7 - %3:_(s32) = COPY %0 - %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %2:_(<4 x s32>) = G_BUILD_VECTOR %1, %1, %6, %7 + %3:_(s64) = COPY %0 + %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %1(s32), %3(s64) $q0 = COPY %4 ... --- @@ -128,11 +128,11 @@ body: | %0:_(s32) = COPY $w0 %1:_(s32) = COPY $w1 %2:_(<2 x s32>) = G_IMPLICIT_DEF - %7:_(s32) = G_CONSTANT i32 0 - %8:_(s32) = G_CONSTANT i32 1 - %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32) - %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s32) - %5:_(<2 x s32>) = G_INSERT_VECTOR_ELT %4, %1(s32), %8(s32) + %7:_(s64) = G_CONSTANT i64 0 + %8:_(s64) = G_CONSTANT i64 1 + %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s64) + %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s64) + %5:_(<2 x s32>) = G_INSERT_VECTOR_ELT %4, %1(s32), %8(s64) $x0 = COPY %5 ... --- @@ -150,11 +150,11 @@ body: | %0:_(s32) = COPY $w0 %1:_(s32) = COPY $w1 %2:_(<2 x s32>) = G_IMPLICIT_DEF - %7:_(s32) = G_CONSTANT i32 0 - %8:_(s32) = G_CONSTANT i32 1 - %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32) - %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %7(s32) - %5:_(<2 x s32>) = G_INSERT_VECTOR_ELT %4, %1(s32), %8(s32) + %7:_(s64) = G_CONSTANT i64 0 + %8:_(s64) = G_CONSTANT i64 1 + %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s64) + %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %7(s64) + %5:_(<2 x s32>) = G_INSERT_VECTOR_ELT %4, %1(s32), %8(s64) $x0 = COPY %5 ... --- @@ -174,12 +174,12 @@ body: | %0:_(s32) = COPY $w0 %1:_(s32) = COPY $w1 %2:_(<4 x s32>) = G_IMPLICIT_DEF - %7:_(s32) = G_CONSTANT i32 0 - %8:_(s32) = G_CONSTANT i32 2 - %9:_(s32) = G_CONSTANT i32 3 - %10:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32) - %11:_(<4 x s32>) = G_INSERT_VECTOR_ELT %10, %1(s32), %8(s32) - %12:_(<4 x s32>) = G_INSERT_VECTOR_ELT %11, %0(s32), %9(s32) + %7:_(s64) = G_CONSTANT i64 0 + %8:_(s64) = G_CONSTANT i64 2 + %9:_(s64) = G_CONSTANT i64 3 + %10:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s64) + %11:_(<4 x s32>) = G_INSERT_VECTOR_ELT %10, %1(s32), %8(s64) + %12:_(<4 x s32>) = G_INSERT_VECTOR_ELT %11, %0(s32), %9(s64) $q0 = COPY %12 ... --- diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir index 542cf018a6c0..5883da137a24 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir @@ -352,8 +352,8 @@ body: | %rhs:_(<3 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32) %lhs:_(<3 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32) %cmp:_(<3 x s32>) = G_ICMP intpred(eq), %lhs(<3 x s32>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s32) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s32>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s32) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s32>), %1(s64) $w0 = COPY %2(s32) RET_ReallyLR ... @@ -386,8 +386,8 @@ body: | %rhs:_(<3 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16) %lhs:_(<3 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16) %cmp:_(<3 x s16>) = G_ICMP intpred(eq), %lhs(<3 x s16>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s16) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s16>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s16) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s16>), %1(s64) %zext:_(s32) = G_ZEXT %2(s16) $w0 = COPY %zext(s32) RET_ReallyLR @@ -422,8 +422,8 @@ body: | %rhs:_(<3 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8) %lhs:_(<3 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8) %cmp:_(<3 x s8>) = G_ICMP intpred(eq), %lhs(<3 x s8>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s8) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s8>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s8) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s8>), %1(s64) %zext:_(s32) = G_ZEXT %2(s8) $w0 = COPY %zext(s32) RET_ReallyLR @@ -449,8 +449,8 @@ body: | %rhs:_(<3 x s64>) = G_BUILD_VECTOR %const(s64), %const(s64), %const(s64) %lhs:_(<3 x s64>) = G_BUILD_VECTOR %const(s64), %const(s64), %const(s64) %cmp:_(<3 x s64>) = G_ICMP intpred(eq), %lhs(<3 x s64>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s64) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s64>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s64) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s64>), %1(s64) $x0 = COPY %2(s64) RET_ReallyLR ... @@ -475,8 +475,8 @@ body: | %rhs:_(<5 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32), %const(s32) %lhs:_(<5 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32), %const(s32) %cmp:_(<5 x s32>) = G_ICMP intpred(eq), %lhs(<5 x s32>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s32) = G_EXTRACT_VECTOR_ELT %cmp(<5 x s32>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s32) = G_EXTRACT_VECTOR_ELT %cmp(<5 x s32>), %1(s64) $w0 = COPY %2(s32) RET_ReallyLR ... @@ -502,8 +502,8 @@ body: | %rhs:_(<7 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16) %lhs:_(<7 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16) %cmp:_(<7 x s16>) = G_ICMP intpred(eq), %lhs(<7 x s16>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s16) = G_EXTRACT_VECTOR_ELT %cmp(<7 x s16>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s16) = G_EXTRACT_VECTOR_ELT %cmp(<7 x s16>), %1(s64) %zext:_(s32) = G_ZEXT %2(s16) $w0 = COPY %zext(s32) RET_ReallyLR @@ -530,8 +530,8 @@ body: | %rhs:_(<9 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8) %lhs:_(<9 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8) %cmp:_(<9 x s8>) = G_ICMP intpred(eq), %lhs(<9 x s8>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s8) = G_EXTRACT_VECTOR_ELT %cmp(<9 x s8>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s8) = G_EXTRACT_VECTOR_ELT %cmp(<9 x s8>), %1(s64) %zext:_(s32) = G_ZEXT %2(s8) $w0 = COPY %zext(s32) RET_ReallyLR diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir index 2209287284b7..c03f51a89dfb 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir @@ -13,8 +13,8 @@ body: | ; CHECK-NEXT: $x0 = COPY [[EVEC]](s64) ; CHECK-NEXT: RET_ReallyLR %0:_(<2 x s64>) = COPY $q0 - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %1(s64) $x0 = COPY %2(s64) RET_ReallyLR ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir index d3db2432e84c..a74bf9a5438b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir @@ -9,16 +9,16 @@ body: | ; CHECK: liveins: $d0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s64) ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>) ; CHECK-NEXT: RET_ReallyLR implicit $d0 %1:_(<2 x s32>) = COPY $d0 %0:_(<2 x s16>) = G_TRUNC %1(<2 x s32>) - %4:_(s32) = G_CONSTANT i32 0 + %4:_(s64) = G_CONSTANT i64 0 %3:_(s16) = G_CONSTANT i16 1 - %2:_(<2 x s16>) = G_INSERT_VECTOR_ELT %0, %3(s16), %4(s32) + %2:_(<2 x s16>) = G_INSERT_VECTOR_ELT %0, %3(s16), %4(s64) %5:_(<2 x s32>) = G_ANYEXT %2(<2 x s16>) $d0 = COPY %5(<2 x s32>) RET_ReallyLR implicit $d0 @@ -32,16 +32,16 @@ body: | ; CHECK: liveins: $d0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s64) ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>) ; CHECK-NEXT: RET_ReallyLR implicit $d0 %1:_(<2 x s32>) = COPY $d0 %0:_(<2 x s8>) = G_TRUNC %1(<2 x s32>) - %4:_(s32) = G_CONSTANT i32 0 + %4:_(s64) = G_CONSTANT i64 0 %3:_(s8) = G_CONSTANT i8 1 - %2:_(<2 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s32) + %2:_(<2 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s64) %5:_(<2 x s32>) = G_ANYEXT %2(<2 x s8>) $d0 = COPY %5(<2 x s32>) RET_ReallyLR implicit $d0 @@ -55,16 +55,16 @@ body: | ; CHECK: liveins: $d0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s16), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s16), [[C]](s64) ; CHECK-NEXT: $d0 = COPY [[IVEC]](<4 x s16>) ; CHECK-NEXT: RET_ReallyLR implicit $d0 %1:_(<4 x s16>) = COPY $d0 %0:_(<4 x s8>) = G_TRUNC %1(<4 x s16>) - %4:_(s32) = G_CONSTANT i32 0 + %4:_(s64) = G_CONSTANT i64 0 %3:_(s8) = G_CONSTANT i8 1 - %2:_(<4 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s32) + %2:_(<4 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s64) %5:_(<4 x s16>) = G_ANYEXT %2(<4 x s8>) $d0 = COPY %5(<4 x s16>) RET_ReallyLR implicit $d0 @@ -78,15 +78,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s8) = G_CONSTANT i8 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s64) ; CHECK-NEXT: $d0 = COPY [[IVEC]](<8 x s8>) ; CHECK-NEXT: RET_ReallyLR %0:_(<8 x s8>) = COPY $d0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s8) = G_CONSTANT i8 42 - %2:_(<8 x s8>) = G_INSERT_VECTOR_ELT %0(<8 x s8>), %val(s8), %1(s32) + %2:_(<8 x s8>) = G_INSERT_VECTOR_ELT %0(<8 x s8>), %val(s8), %1(s64) $d0 = COPY %2(<8 x s8>) RET_ReallyLR ... @@ -99,15 +99,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s8) = G_CONSTANT i8 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<16 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<16 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s64) ; CHECK-NEXT: $q0 = COPY [[IVEC]](<16 x s8>) ; CHECK-NEXT: RET_ReallyLR %0:_(<16 x s8>) = COPY $q0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s8) = G_CONSTANT i8 42 - %2:_(<16 x s8>) = G_INSERT_VECTOR_ELT %0(<16 x s8>), %val(s8), %1(s32) + %2:_(<16 x s8>) = G_INSERT_VECTOR_ELT %0(<16 x s8>), %val(s8), %1(s64) $q0 = COPY %2(<16 x s8>) RET_ReallyLR ... @@ -120,15 +120,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s16) = G_CONSTANT i16 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s64) ; CHECK-NEXT: $d0 = COPY [[IVEC]](<4 x s16>) ; CHECK-NEXT: RET_ReallyLR %0:_(<4 x s16>) = COPY $d0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s16) = G_CONSTANT i16 42 - %2:_(<4 x s16>) = G_INSERT_VECTOR_ELT %0(<4 x s16>), %val(s16), %1(s32) + %2:_(<4 x s16>) = G_INSERT_VECTOR_ELT %0(<4 x s16>), %val(s16), %1(s64) $d0 = COPY %2(<4 x s16>) RET_ReallyLR ... @@ -141,15 +141,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s16) = G_CONSTANT i16 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s64) ; CHECK-NEXT: $q0 = COPY [[IVEC]](<8 x s16>) ; CHECK-NEXT: RET_ReallyLR %0:_(<8 x s16>) = COPY $q0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s16) = G_CONSTANT i16 42 - %2:_(<8 x s16>) = G_INSERT_VECTOR_ELT %0(<8 x s16>), %val(s16), %1(s32) + %2:_(<8 x s16>) = G_INSERT_VECTOR_ELT %0(<8 x s16>), %val(s16), %1(s64) $q0 = COPY %2(<8 x s16>) RET_ReallyLR ... @@ -162,15 +162,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s32) = G_CONSTANT i32 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s64) ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>) ; CHECK-NEXT: RET_ReallyLR %0:_(<2 x s32>) = COPY $d0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s32) = G_CONSTANT i32 42 - %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %val(s32), %1(s32) + %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %val(s32), %1(s64) $d0 = COPY %2(<2 x s32>) RET_ReallyLR ... @@ -183,15 +183,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s32) = G_CONSTANT i32 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s64) ; CHECK-NEXT: $q0 = COPY [[IVEC]](<4 x s32>) ; CHECK-NEXT: RET_ReallyLR %0:_(<4 x s32>) = COPY $q0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s32) = G_CONSTANT i32 42 - %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0(<4 x s32>), %val(s32), %1(s32) + %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0(<4 x s32>), %val(s32), %1(s64) $q0 = COPY %2(<4 x s32>) RET_ReallyLR ... @@ -204,15 +204,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s64) = G_CONSTANT i64 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s64), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s64), [[C]](s64) ; CHECK-NEXT: $q0 = COPY [[IVEC]](<2 x s64>) ; CHECK-NEXT: RET_ReallyLR %0:_(<2 x s64>) = COPY $q0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s64) = G_CONSTANT i64 42 - %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %0(<2 x s64>), %val(s64), %1(s32) + %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %0(<2 x s64>), %val(s64), %1(s64) $q0 = COPY %2(<2 x s64>) RET_ReallyLR ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir index 8803da265aa1..8bd62c592254 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir @@ -782,8 +782,8 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<4 x s32>) = G_PHI [[BUILD_VECTOR1]](<4 x s32>), %bb.1, [[BUILD_VECTOR]](<4 x s32>), %bb.0 - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK-NEXT: %extract:_(s32) = G_EXTRACT_VECTOR_ELT [[PHI]](<4 x s32>), [[C1]](s64) + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: %extract:_(s32) = G_EXTRACT_VECTOR_ELT [[PHI]](<4 x s32>), %one(s64) ; CHECK-NEXT: $w0 = COPY %extract(s32) ; CHECK-NEXT: RET_ReallyLR implicit $w0 bb.0: @@ -797,8 +797,8 @@ body: | %val_2:_(<8 x s32>) = G_IMPLICIT_DEF bb.2: %phi:_(<8 x s32>) = G_PHI %val_2(<8 x s32>), %bb.1, %val_1(<8 x s32>), %bb.0 - %one:_(s32) = G_CONSTANT i32 1 - %extract:_(s32) = G_EXTRACT_VECTOR_ELT %phi(<8 x s32>), %one(s32) + %one:_(s64) = G_CONSTANT i64 1 + %extract:_(s32) = G_EXTRACT_VECTOR_ELT %phi(<8 x s32>), %one(s64) $w0 = COPY %extract RET_ReallyLR implicit $w0 ... @@ -828,8 +828,8 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<8 x s16>) = G_PHI [[BUILD_VECTOR1]](<8 x s16>), %bb.1, [[BUILD_VECTOR]](<8 x s16>), %bb.0 - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK-NEXT: %extract:_(s16) = G_EXTRACT_VECTOR_ELT [[PHI]](<8 x s16>), [[C1]](s64) + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: %extract:_(s16) = G_EXTRACT_VECTOR_ELT [[PHI]](<8 x s16>), %one(s64) ; CHECK-NEXT: $h0 = COPY %extract(s16) ; CHECK-NEXT: RET_ReallyLR implicit $h0 bb.0: @@ -843,8 +843,8 @@ body: | %val_2:_(<16 x s16>) = G_IMPLICIT_DEF bb.2: %phi:_(<16 x s16>) = G_PHI %val_2(<16 x s16>), %bb.1, %val_1(<16 x s16>), %bb.0 - %one:_(s16) = G_CONSTANT i16 1 - %extract:_(s16) = G_EXTRACT_VECTOR_ELT %phi(<16 x s16>), %one(s16) + %one:_(s64) = G_CONSTANT i64 1 + %extract:_(s16) = G_EXTRACT_VECTOR_ELT %phi(<16 x s16>), %one(s64) $h0 = COPY %extract RET_ReallyLR implicit $h0 ... @@ -874,8 +874,8 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<16 x s8>) = G_PHI [[BUILD_VECTOR1]](<16 x s8>), %bb.1, [[BUILD_VECTOR]](<16 x s8>), %bb.0 - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK-NEXT: %extract:_(s8) = G_EXTRACT_VECTOR_ELT [[PHI]](<16 x s8>), [[C1]](s64) + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: %extract:_(s8) = G_EXTRACT_VECTOR_ELT [[PHI]](<16 x s8>), %one(s64) ; CHECK-NEXT: $b0 = COPY %extract(s8) ; CHECK-NEXT: RET_ReallyLR implicit $b0 bb.0: @@ -889,8 +889,8 @@ body: | %val_2:_(<32 x s8>) = G_IMPLICIT_DEF bb.2: %phi:_(<32 x s8>) = G_PHI %val_2(<32 x s8>), %bb.1, %val_1(<32 x s8>), %bb.0 - %one:_(s8) = G_CONSTANT i8 1 - %extract:_(s8) = G_EXTRACT_VECTOR_ELT %phi(<32 x s8>), %one(s8) + %one:_(s64) = G_CONSTANT i64 1 + %extract:_(s8) = G_EXTRACT_VECTOR_ELT %phi(<32 x s8>), %one(s64) $b0 = COPY %extract RET_ReallyLR implicit $b0 ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir index f4374feadcdf..9d12c3c32c7f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir @@ -19,8 +19,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s32) = COPY $w0 %2:_(<4 x s32>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, 0, 0, 0) $q0 = COPY %4(<4 x s32>) RET_ReallyLR implicit $q0 @@ -44,8 +44,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s64) = COPY $x0 %2:_(<2 x s64>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64) %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 0) $q0 = COPY %4(<2 x s64>) RET_ReallyLR implicit $q0 @@ -69,8 +69,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:_(s32) = COPY $w0 %2:_(<2 x s32>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) %4:_(<2 x s32>) = G_SHUFFLE_VECTOR %1(<2 x s32>), %2, shufflemask(0, 0) $d0 = COPY %4(<2 x s32>) RET_ReallyLR implicit $d0 @@ -94,8 +94,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s32) = COPY $s0 %2:_(<4 x s32>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, 0, 0, 0) $q0 = COPY %4(<4 x s32>) RET_ReallyLR implicit $q0 @@ -119,8 +119,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s64) = COPY $d0 %2:_(<2 x s64>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64) %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 0) $q0 = COPY %4(<2 x s64>) RET_ReallyLR implicit $q0 @@ -144,8 +144,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:_(s32) = COPY $s0 %2:_(<2 x s32>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) %4:_(<2 x s32>) = G_SHUFFLE_VECTOR %1(<2 x s32>), %2, shufflemask(0, 0) $d0 = COPY %4(<2 x s32>) RET_ReallyLR implicit $d0 @@ -172,8 +172,8 @@ body: | %0:_(s64) = COPY $d0 %2:_(<2 x s64>) = G_IMPLICIT_DEF %6:_(<2 x s64>) = COPY %2 - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %6, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %6, %0(s64), %3(s64) %7:_(<2 x s64>) = COPY %1 %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %7(<2 x s64>), %2, shufflemask(0, 0) $q0 = COPY %4(<2 x s64>) @@ -194,15 +194,15 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY [[IVEC]](<2 x s64>) ; CHECK-NEXT: $q0 = COPY [[COPY1]](<2 x s64>) ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s64) = COPY $x0 %2:_(<2 x s64>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64) %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 1) $q0 = COPY %4(<2 x s64>) RET_ReallyLR implicit $q0 @@ -230,8 +230,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s64) = COPY $x0 %2:_(<2 x s64>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64) %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(-1, -1) $q0 = COPY %4(<2 x s64>) RET_ReallyLR implicit $q0 @@ -258,8 +258,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s32) = COPY $s0 %2:_(<4 x s32>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, -1, 0, 0) $q0 = COPY %4(<4 x s32>) RET_ReallyLR implicit $q0 @@ -273,22 +273,20 @@ tracksRegLiveness: true body: | bb.1.entry: liveins: $s0 - ; Check a non-splat mask with an undef value. We shouldn't get a G_DUP here. - ; ; CHECK-LABEL: name: not_all_zeros_with_undefs ; CHECK: liveins: $s0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s64) ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemask(undef, 0, 0, 3) ; CHECK-NEXT: $q0 = COPY [[SHUF]](<4 x s32>) ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s32) = COPY $s0 %2:_(<4 x s32>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(-1, 0, 0, 3) $q0 = COPY %4(<4 x s32>) RET_ReallyLR implicit $q0 @@ -311,8 +309,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $d0 %copy:_(s16) = COPY $h0 %undef:_(<4 x s16>) = G_IMPLICIT_DEF - %cst:_(s32) = G_CONSTANT i32 0 - %ins:_(<4 x s16>) = G_INSERT_VECTOR_ELT %undef, %copy(s16), %cst(s32) + %cst:_(s64) = G_CONSTANT i64 0 + %ins:_(<4 x s16>) = G_INSERT_VECTOR_ELT %undef, %copy(s16), %cst(s64) %splat:_(<4 x s16>) = G_SHUFFLE_VECTOR %ins(<4 x s16>), %undef, shufflemask(0, 0, 0, 0) $d0 = COPY %splat(<4 x s16>) RET_ReallyLR implicit $d0 @@ -335,8 +333,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $d0 %copy:_(s32) = COPY $w0 %undef:_(<8 x s8>) = G_IMPLICIT_DEF - %cst:_(s32) = G_CONSTANT i32 0 - %ins:_(<8 x s8>) = G_INSERT_VECTOR_ELT %undef, %copy(s32), %cst(s32) + %cst:_(s64) = G_CONSTANT i64 0 + %ins:_(<8 x s8>) = G_INSERT_VECTOR_ELT %undef, %copy(s32), %cst(s64) %splat:_(<8 x s8>) = G_SHUFFLE_VECTOR %ins(<8 x s8>), %undef, shufflemask(0, 0, 0, 0, 0, 0, 0, 0) $d0 = COPY %splat(<8 x s8>) RET_ReallyLR implicit $d0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir index 7666b2fb8368..8adf5b2d26bf 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir @@ -534,18 +534,20 @@ body: | liveins: $x0 ; CHECK-LABEL: name: vector_true ; CHECK: liveins: $x0 - ; CHECK: %cst:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true - ; CHECK: %cmp:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1) - ; CHECK: %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32) - ; CHECK: %extract_ext:_(s32) = G_ZEXT %extract(s1) - ; CHECK: $w0 = COPY %extract_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %cst64:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; CHECK-NEXT: %cmp:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1) + ; CHECK-NEXT: %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst64(s64) + ; CHECK-NEXT: %extract_ext:_(s32) = G_ZEXT %extract(s1) + ; CHECK-NEXT: $w0 = COPY %extract_ext(s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %ptr:_(p0) = COPY $x0 %cst:_(s32) = G_CONSTANT i32 1 + %cst64:_(s64) = G_CONSTANT i64 1 %bv:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst %cmp:_(<2 x s1>) = G_ICMP intpred(eq), %bv(<2 x s32>), %bv - %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32) + %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst64(s64) %extract_ext:_(s32) = G_ZEXT %extract(s1) $w0 = COPY %extract_ext(s32) RET_ReallyLR implicit $w0 @@ -559,18 +561,20 @@ body: | liveins: $x0 ; CHECK-LABEL: name: vector_false ; CHECK: liveins: $x0 - ; CHECK: %cst:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; CHECK: %cmp:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1) - ; CHECK: %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32) - ; CHECK: %extract_ext:_(s32) = G_ZEXT %extract(s1) - ; CHECK: $w0 = COPY %extract_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %cst64:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false + ; CHECK-NEXT: %cmp:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1) + ; CHECK-NEXT: %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst64(s64) + ; CHECK-NEXT: %extract_ext:_(s32) = G_ZEXT %extract(s1) + ; CHECK-NEXT: $w0 = COPY %extract_ext(s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %ptr:_(p0) = COPY $x0 %cst:_(s32) = G_CONSTANT i32 1 + %cst64:_(s64) = G_CONSTANT i64 1 %bv:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst %cmp:_(<2 x s1>) = G_ICMP intpred(ne), %bv(<2 x s32>), %bv - %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32) + %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst64(s64) %extract_ext:_(s32) = G_ZEXT %extract(s1) $w0 = COPY %extract_ext(s32) RET_ReallyLR implicit $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir index eb539aacc4bf..b0620a8f81dc 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir @@ -24,14 +24,14 @@ body: | ; CHECK: liveins: $q1, $s0 ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q1 - ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 - ; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32) + ; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1 + ; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s64) ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>) ; CHECK: RET_ReallyLR implicit $q0 %0:_(s32) = COPY $s0 %1:_(<4 x s32>) = COPY $q1 - %3:_(s32) = G_CONSTANT i32 1 - %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 1 + %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $q0 = COPY %2(<4 x s32>) RET_ReallyLR implicit $q0 @@ -47,16 +47,17 @@ body: | ; CHECK-LABEL: name: v4s32_gpr ; CHECK: liveins: $q0, $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0 - ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 - ; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32) - ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>) - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0 + ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s64) + ; CHECK-NEXT: $q0 = COPY [[IVEC]](<4 x s32>) + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s32) = COPY $w0 %1:_(<4 x s32>) = COPY $q0 - %3:_(s32) = G_CONSTANT i32 1 - %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 1 + %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $q0 = COPY %2(<4 x s32>) RET_ReallyLR implicit $q0 @@ -72,16 +73,17 @@ body: | ; CHECK-LABEL: name: v2s64_fpr ; CHECK: liveins: $d0, $q1 - ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q1 - ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 - ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s32) - ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>) - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q1 + ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s64) + ; CHECK-NEXT: $q0 = COPY [[IVEC]](<2 x s64>) + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s64) = COPY $d0 %1:_(<2 x s64>) = COPY $q1 - %3:_(s32) = G_CONSTANT i32 1 - %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 1 + %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64) $q0 = COPY %2(<2 x s64>) RET_ReallyLR implicit $q0 @@ -97,16 +99,17 @@ body: | ; CHECK-LABEL: name: v2s64_gpr ; CHECK: liveins: $q0, $x0 - ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0 - ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0 - ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s32) - ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>) - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0 + ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s64) + ; CHECK-NEXT: $q0 = COPY [[IVEC]](<2 x s64>) + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s64) = COPY $x0 %1:_(<2 x s64>) = COPY $q0 - %3:_(s32) = G_CONSTANT i32 0 - %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64) $q0 = COPY %2(<2 x s64>) RET_ReallyLR implicit $q0 @@ -122,16 +125,17 @@ body: | ; CHECK-LABEL: name: v2s32_fpr ; CHECK: liveins: $d1, $s0 - ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d1 - ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 - ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32) - ; CHECK: $d0 = COPY [[IVEC]](<2 x s32>) - ; CHECK: RET_ReallyLR implicit $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d1 + ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s64) + ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>) + ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:_(s32) = COPY $s0 %1:_(<2 x s32>) = COPY $d1 - %3:_(s32) = G_CONSTANT i32 1 - %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 1 + %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $d0 = COPY %2(<2 x s32>) RET_ReallyLR implicit $d0 @@ -147,16 +151,17 @@ body: | ; CHECK-LABEL: name: v2s32_gpr ; CHECK: liveins: $d0, $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0 - ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 - ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32) - ; CHECK: $d0 = COPY [[IVEC]](<2 x s32>) - ; CHECK: RET_ReallyLR implicit $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0 + ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s64) + ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>) + ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:_(s32) = COPY $w0 %1:_(<2 x s32>) = COPY $d0 - %3:_(s32) = G_CONSTANT i32 1 - %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 1 + %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $d0 = COPY %2(<2 x s32>) RET_ReallyLR implicit $d0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir index d6618d440f42..33f7e58804f1 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir @@ -21,8 +21,9 @@ body: | %0:gpr(s32) = COPY $w0 %trunc:gpr(s8) = G_TRUNC %0 %1:fpr(<16 x s8>) = COPY $q1 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<16 x s8>) = G_INSERT_VECTOR_ELT %1, %trunc:gpr(s8), %3:gpr(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %4:gpr(s32) = G_ANYEXT %trunc + %2:fpr(<16 x s8>) = G_INSERT_VECTOR_ELT %1, %4:gpr(s32), %3:gpr(s64) $q0 = COPY %2(<16 x s8>) RET_ReallyLR implicit $q0 @@ -51,8 +52,9 @@ body: | %0:gpr(s32) = COPY $w0 %trunc:gpr(s8) = G_TRUNC %0 %1:fpr(<8 x s8>) = COPY $d0 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<8 x s8>) = G_INSERT_VECTOR_ELT %1, %trunc(s8), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %4:gpr(s32) = G_ANYEXT %trunc + %2:fpr(<8 x s8>) = G_INSERT_VECTOR_ELT %1, %4(s32), %3(s64) $d0 = COPY %2(<8 x s8>) RET_ReallyLR implicit $d0 @@ -78,8 +80,9 @@ body: | %0:gpr(s32) = COPY $w0 %trunc:gpr(s16) = G_TRUNC %0 %1:fpr(<8 x s16>) = COPY $q1 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %trunc:gpr(s16), %3:gpr(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %4:gpr(s32) = G_ANYEXT %trunc + %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %4:gpr(s32), %3:gpr(s64) $q0 = COPY %2(<8 x s16>) RET_ReallyLR implicit $q0 @@ -106,8 +109,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:fpr(s16) = COPY $h0 %1:fpr(<8 x s16>) = COPY $q1 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s64) $q0 = COPY %2(<8 x s16>) RET_ReallyLR implicit $q0 @@ -134,8 +137,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:fpr(s32) = COPY $s0 %1:fpr(<4 x s32>) = COPY $q1 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $q0 = COPY %2(<4 x s32>) RET_ReallyLR implicit $q0 @@ -160,8 +163,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:gpr(s32) = COPY $w0 %1:fpr(<4 x s32>) = COPY $q0 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $q0 = COPY %2(<4 x s32>) RET_ReallyLR implicit $q0 @@ -190,8 +193,9 @@ body: | %0:gpr(s32) = COPY $w0 %trunc:gpr(s16) = G_TRUNC %0 %1:fpr(<4 x s16>) = COPY $d0 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<4 x s16>) = G_INSERT_VECTOR_ELT %1, %trunc(s16), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %4:gpr(s32) = G_ANYEXT %trunc + %2:fpr(<4 x s16>) = G_INSERT_VECTOR_ELT %1, %4(s32), %3(s64) $d0 = COPY %2(<4 x s16>) RET_ReallyLR implicit $d0 @@ -218,8 +222,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:fpr(s64) = COPY $d0 %1:fpr(<2 x s64>) = COPY $q1 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64) $q0 = COPY %2(<2 x s64>) RET_ReallyLR implicit $q0 @@ -244,8 +248,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:gpr(s64) = COPY $x0 %1:fpr(<2 x s64>) = COPY $q0 - %3:gpr(s32) = G_CONSTANT i32 0 - %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 0 + %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64) $q0 = COPY %2(<2 x s64>) RET_ReallyLR implicit $q0 @@ -266,17 +270,17 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub - ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub + ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub ; CHECK-NEXT: $d0 = COPY [[COPY2]] ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:fpr(s32) = COPY $s0 %1:fpr(<2 x s32>) = COPY $d1 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $d0 = COPY %2(<2 x s32>) RET_ReallyLR implicit $d0 @@ -304,8 +308,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:gpr(s32) = COPY $w0 %1:fpr(<2 x s32>) = COPY $d0 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $d0 = COPY %2(<2 x s32>) RET_ReallyLR implicit $d0 diff --git a/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll b/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll index 5c006508d284..3a17a95ed71d 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD -; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=2 < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI - -; CHECK-GI: warning: Instruction selection used fallback path for test_bit_sink_operand +; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI ; BIT Bitwise Insert if True ; @@ -200,34 +198,63 @@ define <16 x i8> @test_bit_v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) { } define <4 x i32> @test_bit_sink_operand(<4 x i32> %src, <4 x i32> %dst, <4 x i32> %mask, i32 %scratch) { -; CHECK-LABEL: test_bit_sink_operand: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #32 -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: cmp w0, #0 -; CHECK-NEXT: mov w9, wzr -; CHECK-NEXT: cinc w8, w0, lt -; CHECK-NEXT: asr w8, w8, #1 -; CHECK-NEXT: .LBB11_1: // %do.body -; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: bit v1.16b, v0.16b, v2.16b -; CHECK-NEXT: add x10, sp, #16 -; CHECK-NEXT: mov x11, sp -; CHECK-NEXT: bfi x10, x9, #2, #2 -; CHECK-NEXT: bfi x11, x9, #2, #2 -; CHECK-NEXT: add w9, w9, #1 -; CHECK-NEXT: cmp w9, #5 -; CHECK-NEXT: str q1, [sp, #16] -; CHECK-NEXT: str w0, [x10] -; CHECK-NEXT: ldr q1, [sp, #16] -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: str w8, [x11] -; CHECK-NEXT: ldr q0, [sp] -; CHECK-NEXT: b.ne .LBB11_1 -; CHECK-NEXT: // %bb.2: // %do.end -; CHECK-NEXT: mov v0.16b, v1.16b -; CHECK-NEXT: add sp, sp, #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_bit_sink_operand: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #32 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: cmp w0, #0 +; CHECK-SD-NEXT: mov w9, wzr +; CHECK-SD-NEXT: cinc w8, w0, lt +; CHECK-SD-NEXT: asr w8, w8, #1 +; CHECK-SD-NEXT: .LBB11_1: // %do.body +; CHECK-SD-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-SD-NEXT: bit v1.16b, v0.16b, v2.16b +; CHECK-SD-NEXT: add x10, sp, #16 +; CHECK-SD-NEXT: mov x11, sp +; CHECK-SD-NEXT: bfi x10, x9, #2, #2 +; CHECK-SD-NEXT: bfi x11, x9, #2, #2 +; CHECK-SD-NEXT: add w9, w9, #1 +; CHECK-SD-NEXT: cmp w9, #5 +; CHECK-SD-NEXT: str q1, [sp, #16] +; CHECK-SD-NEXT: str w0, [x10] +; CHECK-SD-NEXT: ldr q1, [sp, #16] +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: str w8, [x11] +; CHECK-SD-NEXT: ldr q0, [sp] +; CHECK-SD-NEXT: b.ne .LBB11_1 +; CHECK-SD-NEXT: // %bb.2: // %do.end +; CHECK-SD-NEXT: mov v0.16b, v1.16b +; CHECK-SD-NEXT: add sp, sp, #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_bit_sink_operand: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #32 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 32 +; CHECK-GI-NEXT: asr w9, w0, #31 +; CHECK-GI-NEXT: mov w8, wzr +; CHECK-GI-NEXT: add x10, sp, #16 +; CHECK-GI-NEXT: mov x11, sp +; CHECK-GI-NEXT: add w9, w0, w9, lsr #31 +; CHECK-GI-NEXT: asr w9, w9, #1 +; CHECK-GI-NEXT: .LBB11_1: // %do.body +; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-GI-NEXT: bit v1.16b, v0.16b, v2.16b +; CHECK-GI-NEXT: mov w12, w8 +; CHECK-GI-NEXT: add w8, w8, #1 +; CHECK-GI-NEXT: and x12, x12, #0x3 +; CHECK-GI-NEXT: cmp w8, #5 +; CHECK-GI-NEXT: str q1, [sp, #16] +; CHECK-GI-NEXT: str w0, [x10, x12, lsl #2] +; CHECK-GI-NEXT: ldr q1, [sp, #16] +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: str w9, [x11, x12, lsl #2] +; CHECK-GI-NEXT: ldr q0, [sp] +; CHECK-GI-NEXT: b.ne .LBB11_1 +; CHECK-GI-NEXT: // %bb.2: // %do.end +; CHECK-GI-NEXT: mov v0.16b, v1.16b +; CHECK-GI-NEXT: add sp, sp, #32 +; CHECK-GI-NEXT: ret entry: %0 = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1> diff --git a/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll b/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll index 76790d128d06..f7aa57a068a4 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll @@ -1,14 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 ; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD -; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI +; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" -; CHECK-GI: warning: Instruction selection used fallback path for sminv_v3i64 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for smaxv_v3i64 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uminv_v3i64 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for umaxv_v3i64 - declare i8 @llvm.vector.reduce.smin.v2i8(<2 x i8>) declare i8 @llvm.vector.reduce.smin.v3i8(<3 x i8>) declare i8 @llvm.vector.reduce.smin.v4i8(<4 x i8>) @@ -713,21 +708,39 @@ entry: } define i64 @sminv_v3i64(<3 x i64> %a) { -; CHECK-LABEL: sminv_v3i64: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: mov v2.d[1], x8 -; CHECK-NEXT: cmgt v1.2d, v2.2d, v0.2d -; CHECK-NEXT: bif v0.16b, v2.16b, v1.16b -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-NEXT: cmgt d2, d1, d0 -; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b -; CHECK-NEXT: fmov x0, d0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: sminv_v3i64: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: mov v2.d[1], x8 +; CHECK-SD-NEXT: cmgt v1.2d, v2.2d, v0.2d +; CHECK-SD-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-SD-NEXT: cmgt d2, d1, d0 +; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b +; CHECK-SD-NEXT: fmov x0, d0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: sminv_v3i64: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] +; CHECK-GI-NEXT: mov v2.d[1], x8 +; CHECK-GI-NEXT: cmgt v1.2d, v2.2d, v0.2d +; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-GI-NEXT: mov d1, v0.d[1] +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: fmov x9, d1 +; CHECK-GI-NEXT: cmp x8, x9 +; CHECK-GI-NEXT: fcsel d0, d0, d1, lt +; CHECK-GI-NEXT: fmov x0, d0 +; CHECK-GI-NEXT: ret entry: %arg1 = call i64 @llvm.vector.reduce.smin.v3i64(<3 x i64> %a) ret i64 %arg1 @@ -1056,21 +1069,39 @@ entry: } define i64 @smaxv_v3i64(<3 x i64> %a) { -; CHECK-LABEL: smaxv_v3i64: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: mov v2.d[1], x8 -; CHECK-NEXT: cmgt v1.2d, v0.2d, v2.2d -; CHECK-NEXT: bif v0.16b, v2.16b, v1.16b -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-NEXT: cmgt d2, d0, d1 -; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b -; CHECK-NEXT: fmov x0, d0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: smaxv_v3i64: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: mov v2.d[1], x8 +; CHECK-SD-NEXT: cmgt v1.2d, v0.2d, v2.2d +; CHECK-SD-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-SD-NEXT: cmgt d2, d0, d1 +; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b +; CHECK-SD-NEXT: fmov x0, d0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: smaxv_v3i64: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-GI-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000 +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] +; CHECK-GI-NEXT: mov v2.d[1], x8 +; CHECK-GI-NEXT: cmgt v1.2d, v0.2d, v2.2d +; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-GI-NEXT: mov d1, v0.d[1] +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: fmov x9, d1 +; CHECK-GI-NEXT: cmp x8, x9 +; CHECK-GI-NEXT: fcsel d0, d0, d1, gt +; CHECK-GI-NEXT: fmov x0, d0 +; CHECK-GI-NEXT: ret entry: %arg1 = call i64 @llvm.vector.reduce.smax.v3i64(<3 x i64> %a) ret i64 %arg1 @@ -1397,21 +1428,39 @@ entry: } define i64 @uminv_v3i64(<3 x i64> %a) { -; CHECK-LABEL: uminv_v3i64: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: mov v2.d[1], x8 -; CHECK-NEXT: cmhi v1.2d, v2.2d, v0.2d -; CHECK-NEXT: bif v0.16b, v2.16b, v1.16b -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-NEXT: cmhi d2, d1, d0 -; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b -; CHECK-NEXT: fmov x0, d0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: uminv_v3i64: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov x8, #-1 // =0xffffffffffffffff +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: mov v2.d[1], x8 +; CHECK-SD-NEXT: cmhi v1.2d, v2.2d, v0.2d +; CHECK-SD-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-SD-NEXT: cmhi d2, d1, d0 +; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b +; CHECK-SD-NEXT: fmov x0, d0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: uminv_v3i64: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] +; CHECK-GI-NEXT: mov v2.d[1], x8 +; CHECK-GI-NEXT: cmhi v1.2d, v2.2d, v0.2d +; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-GI-NEXT: mov d1, v0.d[1] +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: fmov x9, d1 +; CHECK-GI-NEXT: cmp x8, x9 +; CHECK-GI-NEXT: fcsel d0, d0, d1, lo +; CHECK-GI-NEXT: fmov x0, d0 +; CHECK-GI-NEXT: ret entry: %arg1 = call i64 @llvm.vector.reduce.umin.v3i64(<3 x i64> %a) ret i64 %arg1 @@ -1736,22 +1785,39 @@ entry: } define i64 @umaxv_v3i64(<3 x i64> %a) { -; CHECK-LABEL: umaxv_v3i64: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2 -; CHECK-NEXT: mov v3.16b, v2.16b -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: mov v3.d[1], xzr -; CHECK-NEXT: cmhi v3.2d, v0.2d, v3.2d -; CHECK-NEXT: ext v4.16b, v3.16b, v3.16b, #8 -; CHECK-NEXT: bif v0.16b, v2.16b, v3.16b -; CHECK-NEXT: and v1.8b, v1.8b, v4.8b -; CHECK-NEXT: cmhi d2, d0, d1 -; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b -; CHECK-NEXT: fmov x0, d0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: umaxv_v3i64: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-SD-NEXT: mov v3.16b, v2.16b +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: mov v3.d[1], xzr +; CHECK-SD-NEXT: cmhi v3.2d, v0.2d, v3.2d +; CHECK-SD-NEXT: ext v4.16b, v3.16b, v3.16b, #8 +; CHECK-SD-NEXT: bif v0.16b, v2.16b, v3.16b +; CHECK-SD-NEXT: and v1.8b, v1.8b, v4.8b +; CHECK-SD-NEXT: cmhi d2, d0, d1 +; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b +; CHECK-SD-NEXT: fmov x0, d0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: umaxv_v3i64: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] +; CHECK-GI-NEXT: mov v2.d[1], xzr +; CHECK-GI-NEXT: cmhi v1.2d, v0.2d, v2.2d +; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-GI-NEXT: mov d1, v0.d[1] +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: fmov x9, d1 +; CHECK-GI-NEXT: cmp x8, x9 +; CHECK-GI-NEXT: fcsel d0, d0, d1, hi +; CHECK-GI-NEXT: fmov x0, d0 +; CHECK-GI-NEXT: ret entry: %arg1 = call i64 @llvm.vector.reduce.umax.v3i64(<3 x i64> %a) ret i64 %arg1 diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll index d282bee81827..749d6071c98d 100644 --- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll +++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll @@ -4,9 +4,6 @@ ; CHECK-GI: warning: Instruction selection used fallback path for test_bitcastv2f32tov1f64 ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_bitcastv1f64tov2f32 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_extracts_inserts_varidx_insert -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_v1i32_undef -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_diff_v1i32_v1i32 define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) { ; CHECK-LABEL: ins16bw: @@ -96,36 +93,22 @@ define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) { } define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) { -; CHECK-SD-LABEL: ins8h8: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: mov v1.h[7], v0.h[2] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins8h8: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: mov h2, v0.h[2] -; CHECK-GI-NEXT: mov v0.16b, v1.16b -; CHECK-GI-NEXT: mov v0.h[7], v2.h[0] -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins8h8: +; CHECK: // %bb.0: +; CHECK-NEXT: mov v1.h[7], v0.h[2] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret %tmp3 = extractelement <8 x i16> %tmp1, i32 2 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7 ret <8 x i16> %tmp4 } define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) { -; CHECK-SD-LABEL: ins4s4: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: mov v1.s[1], v0.s[2] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins4s4: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: mov s2, v0.s[2] -; CHECK-GI-NEXT: mov v0.16b, v1.16b -; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins4s4: +; CHECK: // %bb.0: +; CHECK-NEXT: mov v1.s[1], v0.s[2] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret %tmp3 = extractelement <4 x i32> %tmp1, i32 2 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1 ret <4 x i32> %tmp4 @@ -143,18 +126,11 @@ define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) { } define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) { -; CHECK-SD-LABEL: ins4f4: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: mov v1.s[1], v0.s[2] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins4f4: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: mov s2, v0.s[2] -; CHECK-GI-NEXT: mov v0.16b, v1.16b -; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins4f4: +; CHECK: // %bb.0: +; CHECK-NEXT: mov v1.s[1], v0.s[2] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret %tmp3 = extractelement <4 x float> %tmp1, i32 2 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1 ret <4 x float> %tmp4 @@ -192,40 +168,24 @@ define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) { } define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) { -; CHECK-SD-LABEL: ins4h8: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-SD-NEXT: mov v1.h[7], v0.h[2] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins4h8: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-GI-NEXT: mov h2, v0.h[2] -; CHECK-GI-NEXT: mov v0.16b, v1.16b -; CHECK-GI-NEXT: mov v0.h[7], v2.h[0] -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins4h8: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v1.h[7], v0.h[2] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret %tmp3 = extractelement <4 x i16> %tmp1, i32 2 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7 ret <8 x i16> %tmp4 } define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) { -; CHECK-SD-LABEL: ins2s4: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-SD-NEXT: mov v1.s[1], v0.s[1] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins2s4: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-GI-NEXT: mov s2, v0.s[1] -; CHECK-GI-NEXT: mov v0.16b, v1.16b -; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins2s4: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v1.s[1], v0.s[1] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret %tmp3 = extractelement <2 x i32> %tmp1, i32 1 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1 ret <4 x i32> %tmp4 @@ -244,20 +204,12 @@ define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) { } define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) { -; CHECK-SD-LABEL: ins2f4: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-SD-NEXT: mov v1.s[1], v0.s[1] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins2f4: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-GI-NEXT: mov s2, v0.s[1] -; CHECK-GI-NEXT: mov v0.16b, v1.16b -; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins2f4: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v1.s[1], v0.s[1] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret %tmp3 = extractelement <2 x float> %tmp1, i32 1 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1 ret <4 x float> %tmp4 @@ -307,40 +259,24 @@ define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) { } define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) { -; CHECK-SD-LABEL: ins8h4: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-SD-NEXT: mov v1.h[3], v0.h[2] -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins8h4: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: mov h2, v0.h[2] -; CHECK-GI-NEXT: fmov d0, d1 -; CHECK-GI-NEXT: mov v0.h[3], v2.h[0] -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins8h4: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: mov v1.h[3], v0.h[2] +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret %tmp3 = extractelement <8 x i16> %tmp1, i32 2 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3 ret <4 x i16> %tmp4 } define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) { -; CHECK-SD-LABEL: ins4s2: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-SD-NEXT: mov v1.s[1], v0.s[2] -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins4s2: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: mov s2, v0.s[2] -; CHECK-GI-NEXT: fmov d0, d1 -; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins4s2: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: mov v1.s[1], v0.s[2] +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret %tmp3 = extractelement <4 x i32> %tmp1, i32 2 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1 ret <2 x i32> %tmp4 @@ -357,20 +293,12 @@ define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) { } define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) { -; CHECK-SD-LABEL: ins4f2: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-SD-NEXT: mov v1.s[1], v0.s[2] -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins4f2: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: mov s2, v0.s[2] -; CHECK-GI-NEXT: fmov d0, d1 -; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins4f2: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: mov v1.s[1], v0.s[2] +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret %tmp3 = extractelement <4 x float> %tmp1, i32 2 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1 ret <2 x float> %tmp4 @@ -415,22 +343,13 @@ define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) { } define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) { -; CHECK-SD-LABEL: ins4h4: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-SD-NEXT: mov v1.h[3], v0.h[2] -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins4h4: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-GI-NEXT: mov h2, v0.h[2] -; CHECK-GI-NEXT: fmov d0, d1 -; CHECK-GI-NEXT: mov v0.h[3], v2.h[0] -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins4h4: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v1.h[3], v0.h[2] +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret %tmp3 = extractelement <4 x i16> %tmp1, i32 2 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3 ret <4 x i16> %tmp4 @@ -1516,21 +1435,38 @@ define <4 x i16> @test_extracts_inserts_varidx_extract(<8 x i16> %x, i32 %idx) { } define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) { -; CHECK-LABEL: test_extracts_inserts_varidx_insert: -; CHECK: // %bb.0: -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: add x8, sp, #8 -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: bfi x8, x0, #1, #2 -; CHECK-NEXT: str h0, [x8] -; CHECK-NEXT: ldr d1, [sp, #8] -; CHECK-NEXT: mov v1.h[1], v0.h[1] -; CHECK-NEXT: mov v1.h[2], v0.h[2] -; CHECK-NEXT: mov v1.h[3], v0.h[3] -; CHECK-NEXT: fmov d0, d1 -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_extracts_inserts_varidx_insert: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: add x8, sp, #8 +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: bfi x8, x0, #1, #2 +; CHECK-SD-NEXT: str h0, [x8] +; CHECK-SD-NEXT: ldr d1, [sp, #8] +; CHECK-SD-NEXT: mov v1.h[1], v0.h[1] +; CHECK-SD-NEXT: mov v1.h[2], v0.h[2] +; CHECK-SD-NEXT: mov v1.h[3], v0.h[3] +; CHECK-SD-NEXT: fmov d0, d1 +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_extracts_inserts_varidx_insert: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w8, w0 +; CHECK-GI-NEXT: add x9, sp, #8 +; CHECK-GI-NEXT: str d0, [sp, #8] +; CHECK-GI-NEXT: and x8, x8, #0x3 +; CHECK-GI-NEXT: str h0, [x9, x8, lsl #1] +; CHECK-GI-NEXT: ldr d1, [sp, #8] +; CHECK-GI-NEXT: mov v1.h[1], v0.h[1] +; CHECK-GI-NEXT: mov v1.h[2], v0.h[2] +; CHECK-GI-NEXT: mov v1.h[3], v0.h[3] +; CHECK-GI-NEXT: fmov d0, d1 +; CHECK-GI-NEXT: add sp, sp, #16 +; CHECK-GI-NEXT: ret %tmp = extractelement <8 x i16> %x, i32 0 %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 %idx %tmp3 = extractelement <8 x i16> %x, i32 1 diff --git a/llvm/test/CodeGen/AArch64/insertextract.ll b/llvm/test/CodeGen/AArch64/insertextract.ll index 5c2dd761bdc0..c6b2d07231bf 100644 --- a/llvm/test/CodeGen/AArch64/insertextract.ll +++ b/llvm/test/CodeGen/AArch64/insertextract.ll @@ -1,44 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD -; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI - -; CHECK-GI: warning: Instruction selection used fallback path for insert_v2f64_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v3f64_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4f64_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4f64_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4f64_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v2f32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v3f32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4f32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8f32_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8f32_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8f32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4f16_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8f16_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16f16_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16f16_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16f16_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8i8_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16i8_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v32i8_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v32i8_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v32i8_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4i16_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8i16_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16i16_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16i16_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16i16_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v2i32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v3i32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4i32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8i32_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8i32_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8i32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v2i64_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v3i64_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4i64_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4i64_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4i64_c +; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI define <2 x double> @insert_v2f64_0(<2 x double> %a, double %b, i32 %c) { ; CHECK-LABEL: insert_v2f64_0: @@ -63,17 +25,29 @@ entry: } define <2 x double> @insert_v2f64_c(<2 x double> %a, double %b, i32 %c) { -; CHECK-LABEL: insert_v2f64_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x0, #3, #1 -; CHECK-NEXT: str d1, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v2f64_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x0, #3, #1 +; CHECK-SD-NEXT: str d1, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v2f64_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w0 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x1 +; CHECK-GI-NEXT: str d1, [x8, x9, lsl #3] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <2 x double> %a, double %b, i32 %c ret <2 x double> %d @@ -111,25 +85,51 @@ entry: } define <3 x double> @insert_v3f64_c(<3 x double> %a, double %b, i32 %c) { -; CHECK-LABEL: insert_v3f64_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: stp q0, q2, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: and x9, x0, #0x3 -; CHECK-NEXT: str d3, [x8, x9, lsl #3] -; CHECK-NEXT: ldr q0, [sp] -; CHECK-NEXT: ldr d2, [sp, #16] -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1 -; CHECK-NEXT: add sp, sp, #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v3f64_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: stp q0, q2, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: and x9, x0, #0x3 +; CHECK-SD-NEXT: str d3, [x8, x9, lsl #3] +; CHECK-SD-NEXT: ldr q0, [sp] +; CHECK-SD-NEXT: ldr d2, [sp, #16] +; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1 +; CHECK-SD-NEXT: add sp, sp, #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v3f64_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov w8, w0 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] +; CHECK-GI-NEXT: and x8, x8, #0x3 +; CHECK-GI-NEXT: stp q0, q2, [sp] +; CHECK-GI-NEXT: str d3, [x9, x8, lsl #3] +; CHECK-GI-NEXT: ldp q0, q2, [sp] +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 killed $q2 +; CHECK-GI-NEXT: mov d1, v0.d[1] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <3 x double> %a, double %b, i32 %c ret <3 x double> %d @@ -158,16 +158,35 @@ entry: } define <4 x double> @insert_v4f64_c(<4 x double> %a, double %b, i32 %c) { -; CHECK-LABEL: insert_v4f64_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x0, #0x3 -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: str d2, [x9, x8, lsl #3] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v4f64_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x0, #0x3 +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: str d2, [x9, x8, lsl #3] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v4f64_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w0 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0x3 +; CHECK-GI-NEXT: str d2, [x9, x8, lsl #3] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <4 x double> %a, double %b, i32 %c ret <4 x double> %d @@ -200,18 +219,31 @@ entry: } define <2 x float> @insert_v2f32_c(<2 x float> %a, float %b, i32 %c) { -; CHECK-LABEL: insert_v2f32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: add x8, sp, #8 -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: str d0, [sp, #8] -; CHECK-NEXT: bfi x8, x0, #2, #1 -; CHECK-NEXT: str s1, [x8] -; CHECK-NEXT: ldr d0, [sp, #8] -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v2f32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: add x8, sp, #8 +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: str d0, [sp, #8] +; CHECK-SD-NEXT: bfi x8, x0, #2, #1 +; CHECK-SD-NEXT: str s1, [x8] +; CHECK-SD-NEXT: ldr d0, [sp, #8] +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v2f32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w0 +; CHECK-GI-NEXT: add x8, sp, #8 +; CHECK-GI-NEXT: str d0, [sp, #8] +; CHECK-GI-NEXT: and x9, x9, #0x1 +; CHECK-GI-NEXT: str s1, [x8, x9, lsl #2] +; CHECK-GI-NEXT: ldr d0, [sp, #8] +; CHECK-GI-NEXT: add sp, sp, #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <2 x float> %a, float %b, i32 %c ret <2 x float> %d @@ -260,17 +292,29 @@ entry: } define <3 x float> @insert_v3f32_c(<3 x float> %a, float %b, i32 %c) { -; CHECK-LABEL: insert_v3f32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x0, #2, #2 -; CHECK-NEXT: str s1, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v3f32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x0, #2, #2 +; CHECK-SD-NEXT: str s1, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v3f32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w0 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x3 +; CHECK-GI-NEXT: str s1, [x8, x9, lsl #2] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <3 x float> %a, float %b, i32 %c ret <3 x float> %d @@ -299,17 +343,29 @@ entry: } define <4 x float> @insert_v4f32_c(<4 x float> %a, float %b, i32 %c) { -; CHECK-LABEL: insert_v4f32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x0, #2, #2 -; CHECK-NEXT: str s1, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v4f32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x0, #2, #2 +; CHECK-SD-NEXT: str s1, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v4f32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w0 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x3 +; CHECK-GI-NEXT: str s1, [x8, x9, lsl #2] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <4 x float> %a, float %b, i32 %c ret <4 x float> %d @@ -338,16 +394,35 @@ entry: } define <8 x float> @insert_v8f32_c(<8 x float> %a, float %b, i32 %c) { -; CHECK-LABEL: insert_v8f32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x0, #0x7 -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: str s2, [x9, x8, lsl #2] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v8f32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x0, #0x7 +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: str s2, [x9, x8, lsl #2] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v8f32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w0 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0x7 +; CHECK-GI-NEXT: str s2, [x9, x8, lsl #2] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <8 x float> %a, float %b, i32 %c ret <8 x float> %d @@ -380,18 +455,31 @@ entry: } define <4 x half> @insert_v4f16_c(<4 x half> %a, half %b, i32 %c) { -; CHECK-LABEL: insert_v4f16_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: add x8, sp, #8 -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: str d0, [sp, #8] -; CHECK-NEXT: bfi x8, x0, #1, #2 -; CHECK-NEXT: str h1, [x8] -; CHECK-NEXT: ldr d0, [sp, #8] -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v4f16_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: add x8, sp, #8 +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: str d0, [sp, #8] +; CHECK-SD-NEXT: bfi x8, x0, #1, #2 +; CHECK-SD-NEXT: str h1, [x8] +; CHECK-SD-NEXT: ldr d0, [sp, #8] +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v4f16_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w0 +; CHECK-GI-NEXT: add x8, sp, #8 +; CHECK-GI-NEXT: str d0, [sp, #8] +; CHECK-GI-NEXT: and x9, x9, #0x3 +; CHECK-GI-NEXT: str h1, [x8, x9, lsl #1] +; CHECK-GI-NEXT: ldr d0, [sp, #8] +; CHECK-GI-NEXT: add sp, sp, #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <4 x half> %a, half %b, i32 %c ret <4 x half> %d @@ -420,17 +508,29 @@ entry: } define <8 x half> @insert_v8f16_c(<8 x half> %a, half %b, i32 %c) { -; CHECK-LABEL: insert_v8f16_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x0, #1, #3 -; CHECK-NEXT: str h1, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v8f16_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x0, #1, #3 +; CHECK-SD-NEXT: str h1, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v8f16_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w0 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x7 +; CHECK-GI-NEXT: str h1, [x8, x9, lsl #1] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <8 x half> %a, half %b, i32 %c ret <8 x half> %d @@ -459,16 +559,35 @@ entry: } define <16 x half> @insert_v16f16_c(<16 x half> %a, half %b, i32 %c) { -; CHECK-LABEL: insert_v16f16_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x0, #0xf -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: str h2, [x9, x8, lsl #1] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v16f16_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x0, #0xf +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: str h2, [x9, x8, lsl #1] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v16f16_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w0 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0xf +; CHECK-GI-NEXT: str h2, [x9, x8, lsl #1] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <16 x half> %a, half %b, i32 %c ret <16 x half> %d @@ -499,18 +618,33 @@ entry: } define <8 x i8> @insert_v8i8_c(<8 x i8> %a, i8 %b, i32 %c) { -; CHECK-LABEL: insert_v8i8_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: add x8, sp, #8 -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str d0, [sp, #8] -; CHECK-NEXT: bfxil x8, x1, #0, #3 -; CHECK-NEXT: strb w0, [x8] -; CHECK-NEXT: ldr d0, [sp, #8] -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v8i8_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: add x8, sp, #8 +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str d0, [sp, #8] +; CHECK-SD-NEXT: bfxil x8, x1, #0, #3 +; CHECK-SD-NEXT: strb w0, [x8] +; CHECK-SD-NEXT: ldr d0, [sp, #8] +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v8i8_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: mov w8, #1 // =0x1 +; CHECK-GI-NEXT: str d0, [sp, #8] +; CHECK-GI-NEXT: and x9, x9, #0x7 +; CHECK-GI-NEXT: mul x8, x9, x8 +; CHECK-GI-NEXT: add x9, sp, #8 +; CHECK-GI-NEXT: strb w0, [x9, x8] +; CHECK-GI-NEXT: ldr d0, [sp, #8] +; CHECK-GI-NEXT: add sp, sp, #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <8 x i8> %a, i8 %b, i32 %c ret <8 x i8> %d @@ -537,17 +671,31 @@ entry: } define <16 x i8> @insert_v16i8_c(<16 x i8> %a, i8 %b, i32 %c) { -; CHECK-LABEL: insert_v16i8_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfxil x8, x1, #0, #4 -; CHECK-NEXT: strb w0, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v16i8_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfxil x8, x1, #0, #4 +; CHECK-SD-NEXT: strb w0, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v16i8_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: mov w8, #1 // =0x1 +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0xf +; CHECK-GI-NEXT: mul x8, x9, x8 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: strb w0, [x9, x8] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <16 x i8> %a, i8 %b, i32 %c ret <16 x i8> %d @@ -574,16 +722,37 @@ entry: } define <32 x i8> @insert_v32i8_c(<32 x i8> %a, i8 %b, i32 %c) { -; CHECK-LABEL: insert_v32i8_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x1, #0x1f -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: strb w0, [x9, x8] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v32i8_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x1, #0x1f +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: strb w0, [x9, x8] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v32i8_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w1 +; CHECK-GI-NEXT: mov x10, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0x1f +; CHECK-GI-NEXT: lsl x9, x8, #1 +; CHECK-GI-NEXT: sub x8, x9, x8 +; CHECK-GI-NEXT: strb w0, [x10, x8] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <32 x i8> %a, i8 %b, i32 %c ret <32 x i8> %d @@ -614,18 +783,31 @@ entry: } define <4 x i16> @insert_v4i16_c(<4 x i16> %a, i16 %b, i32 %c) { -; CHECK-LABEL: insert_v4i16_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: add x8, sp, #8 -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str d0, [sp, #8] -; CHECK-NEXT: bfi x8, x1, #1, #2 -; CHECK-NEXT: strh w0, [x8] -; CHECK-NEXT: ldr d0, [sp, #8] -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v4i16_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: add x8, sp, #8 +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str d0, [sp, #8] +; CHECK-SD-NEXT: bfi x8, x1, #1, #2 +; CHECK-SD-NEXT: strh w0, [x8] +; CHECK-SD-NEXT: ldr d0, [sp, #8] +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v4i16_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: add x8, sp, #8 +; CHECK-GI-NEXT: str d0, [sp, #8] +; CHECK-GI-NEXT: and x9, x9, #0x3 +; CHECK-GI-NEXT: strh w0, [x8, x9, lsl #1] +; CHECK-GI-NEXT: ldr d0, [sp, #8] +; CHECK-GI-NEXT: add sp, sp, #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <4 x i16> %a, i16 %b, i32 %c ret <4 x i16> %d @@ -652,17 +834,29 @@ entry: } define <8 x i16> @insert_v8i16_c(<8 x i16> %a, i16 %b, i32 %c) { -; CHECK-LABEL: insert_v8i16_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x1, #1, #3 -; CHECK-NEXT: strh w0, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v8i16_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x1, #1, #3 +; CHECK-SD-NEXT: strh w0, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v8i16_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x7 +; CHECK-GI-NEXT: strh w0, [x8, x9, lsl #1] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <8 x i16> %a, i16 %b, i32 %c ret <8 x i16> %d @@ -689,16 +883,35 @@ entry: } define <16 x i16> @insert_v16i16_c(<16 x i16> %a, i16 %b, i32 %c) { -; CHECK-LABEL: insert_v16i16_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x1, #0xf -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: strh w0, [x9, x8, lsl #1] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v16i16_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x1, #0xf +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: strh w0, [x9, x8, lsl #1] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v16i16_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w1 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0xf +; CHECK-GI-NEXT: strh w0, [x9, x8, lsl #1] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <16 x i16> %a, i16 %b, i32 %c ret <16 x i16> %d @@ -729,18 +942,31 @@ entry: } define <2 x i32> @insert_v2i32_c(<2 x i32> %a, i32 %b, i32 %c) { -; CHECK-LABEL: insert_v2i32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: add x8, sp, #8 -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str d0, [sp, #8] -; CHECK-NEXT: bfi x8, x1, #2, #1 -; CHECK-NEXT: str w0, [x8] -; CHECK-NEXT: ldr d0, [sp, #8] -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v2i32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: add x8, sp, #8 +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str d0, [sp, #8] +; CHECK-SD-NEXT: bfi x8, x1, #2, #1 +; CHECK-SD-NEXT: str w0, [x8] +; CHECK-SD-NEXT: ldr d0, [sp, #8] +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v2i32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: add x8, sp, #8 +; CHECK-GI-NEXT: str d0, [sp, #8] +; CHECK-GI-NEXT: and x9, x9, #0x1 +; CHECK-GI-NEXT: str w0, [x8, x9, lsl #2] +; CHECK-GI-NEXT: ldr d0, [sp, #8] +; CHECK-GI-NEXT: add sp, sp, #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <2 x i32> %a, i32 %b, i32 %c ret <2 x i32> %d @@ -789,17 +1015,29 @@ entry: } define <3 x i32> @insert_v3i32_c(<3 x i32> %a, i32 %b, i32 %c) { -; CHECK-LABEL: insert_v3i32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x1, #2, #2 -; CHECK-NEXT: str w0, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v3i32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x1, #2, #2 +; CHECK-SD-NEXT: str w0, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v3i32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x3 +; CHECK-GI-NEXT: str w0, [x8, x9, lsl #2] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <3 x i32> %a, i32 %b, i32 %c ret <3 x i32> %d @@ -826,17 +1064,29 @@ entry: } define <4 x i32> @insert_v4i32_c(<4 x i32> %a, i32 %b, i32 %c) { -; CHECK-LABEL: insert_v4i32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x1, #2, #2 -; CHECK-NEXT: str w0, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v4i32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x1, #2, #2 +; CHECK-SD-NEXT: str w0, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v4i32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x3 +; CHECK-GI-NEXT: str w0, [x8, x9, lsl #2] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <4 x i32> %a, i32 %b, i32 %c ret <4 x i32> %d @@ -863,16 +1113,35 @@ entry: } define <8 x i32> @insert_v8i32_c(<8 x i32> %a, i32 %b, i32 %c) { -; CHECK-LABEL: insert_v8i32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x1, #0x7 -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: str w0, [x9, x8, lsl #2] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v8i32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x1, #0x7 +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: str w0, [x9, x8, lsl #2] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v8i32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w1 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0x7 +; CHECK-GI-NEXT: str w0, [x9, x8, lsl #2] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <8 x i32> %a, i32 %b, i32 %c ret <8 x i32> %d @@ -899,17 +1168,29 @@ entry: } define <2 x i64> @insert_v2i64_c(<2 x i64> %a, i64 %b, i32 %c) { -; CHECK-LABEL: insert_v2i64_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x1, #3, #1 -; CHECK-NEXT: str x0, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v2i64_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x1, #3, #1 +; CHECK-SD-NEXT: str x0, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v2i64_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x1 +; CHECK-GI-NEXT: str x0, [x8, x9, lsl #3] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <2 x i64> %a, i64 %b, i32 %c ret <2 x i64> %d @@ -946,25 +1227,51 @@ entry: } define <3 x i64> @insert_v3i64_c(<3 x i64> %a, i64 %b, i32 %c) { -; CHECK-LABEL: insert_v3i64_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: stp q0, q2, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: and x9, x1, #0x3 -; CHECK-NEXT: str x0, [x8, x9, lsl #3] -; CHECK-NEXT: ldr q0, [sp] -; CHECK-NEXT: ldr d2, [sp, #16] -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1 -; CHECK-NEXT: add sp, sp, #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v3i64_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: stp q0, q2, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: and x9, x1, #0x3 +; CHECK-SD-NEXT: str x0, [x8, x9, lsl #3] +; CHECK-SD-NEXT: ldr q0, [sp] +; CHECK-SD-NEXT: ldr d2, [sp, #16] +; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1 +; CHECK-SD-NEXT: add sp, sp, #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v3i64_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov w8, w1 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] +; CHECK-GI-NEXT: and x8, x8, #0x3 +; CHECK-GI-NEXT: stp q0, q2, [sp] +; CHECK-GI-NEXT: str x0, [x9, x8, lsl #3] +; CHECK-GI-NEXT: ldp q0, q2, [sp] +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 killed $q2 +; CHECK-GI-NEXT: mov d1, v0.d[1] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <3 x i64> %a, i64 %b, i32 %c ret <3 x i64> %d @@ -991,16 +1298,35 @@ entry: } define <4 x i64> @insert_v4i64_c(<4 x i64> %a, i64 %b, i32 %c) { -; CHECK-LABEL: insert_v4i64_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x1, #0x3 -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: str x0, [x9, x8, lsl #3] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v4i64_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x1, #0x3 +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: str x0, [x9, x8, lsl #3] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v4i64_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w1 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0x3 +; CHECK-GI-NEXT: str x0, [x9, x8, lsl #3] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <4 x i64> %a, i64 %b, i32 %c ret <4 x i64> %d diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir index b49f51609851..0a2b3da7f7d9 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir @@ -28,16 +28,13 @@ tracksRegLiveness: true body: | bb.0: ; CHECK-LABEL: name: test_ptradd_crash__offset_wider - ; CHECK: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 3 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[C]](s128) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C1]](s64) - ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[SHL]](s64) + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12 + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[C]](s64) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[INTTOPTR]](p1) :: (load (s32), addrspace 1) ; CHECK-NEXT: $sgpr0 = COPY [[LOAD]](s32) ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 %1:_(p1) = G_CONSTANT i64 0 - %3:_(s128) = G_CONSTANT i128 3 + %3:_(s32) = G_CONSTANT i32 3 %0:_(<4 x s32>) = G_LOAD %1 :: (load (<4 x s32>) from `ptr addrspace(1) null`, addrspace 1) %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %3 $sgpr0 = COPY %2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll index ae0556c1b21f..c509cf4b1bf3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll @@ -48,10 +48,10 @@ define <2 x ptr addrspace(7)> @gep_vector_splat(<2 x ptr addrspace(7)> %ptrs, i6 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11 ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY10]](s32), [[COPY11]](s32) ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<2 x p8>) = G_IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV2]](s64), [[C]](s64) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV2]](s64), [[C]](s32) ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[IVEC]](<2 x s64>), [[DEF]], shufflemask(0, 0) ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[SHUF]](<2 x s64>) ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s32>) = G_ADD [[BUILD_VECTOR1]], [[TRUNC]] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir index af03b3e20ecb..93155335e208 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir @@ -294,7 +294,8 @@ body: | ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32) %0:_(<2 x s1>) = G_IMPLICIT_DEF %1:_(s1) = G_CONSTANT i1 false - %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1 + %4:_(s32) = G_ZEXT %1 + %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %4 %3:_(s32) = G_ANYEXT %2 $vgpr0 = COPY %3 ... @@ -948,7 +949,8 @@ body: | ; CHECK-NEXT: $vgpr0 = COPY [[EVEC]](s32) %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(s64) = COPY $vgpr2_vgpr3 - %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1 + %3:_(s32) = G_TRUNC %1 + %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %3 $vgpr0 = COPY %2 ... --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir index b5dca793bc50..805890a75d40 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir @@ -18,8 +18,9 @@ body: | %7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %6(s32), %5(s32) %8:_(s1) = G_CONSTANT i1 1 - %9:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %8(s1) - %10:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %9(s32), %8(s1) + %11:_(s32) = G_ZEXT %8 + %9:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %11(s32) + %10:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %9(s32), %11(s32) SI_RETURN ... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir index 1dcb2bf3e42a..b57dd396ae35 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir @@ -82,7 +82,8 @@ body: | %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(s32) = COPY $vgpr2 %2:_(s64) = COPY $vgpr3_vgpr4 - %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 + %4:_(s32) = G_TRUNC %2 + %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4 $vgpr0_vgpr1 = COPY %3 ... @@ -105,7 +106,8 @@ body: | %0:_(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 %1:_(s32) = COPY $vgpr16 %2:_(s64) = COPY $vgpr17_vgpr18 - %3:_(<16 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 + %4:_(s32) = G_TRUNC %2 + %3:_(<16 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4 S_ENDPGM 0, implicit %3 ... @@ -132,28 +134,6 @@ body: | ... --- -name: insert_vector_elt_0_v2s32_s8 - -body: | - bb.0: - liveins: $vgpr0_vgpr1, $vgpr2 - - ; CHECK-LABEL: name: insert_vector_elt_0_v2s32_s8 - ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 - ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) - ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[UV1]](s32) - ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) - %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 - %1:_(s32) = COPY $vgpr2 - %2:_(s8) = G_CONSTANT i8 0 - %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 - $vgpr0_vgpr1 = COPY %3 -... - ---- name: insert_vector_elt_0_v2i8_i32 body: | diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll index c23d1e7c7099..a1347d2306ca 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll @@ -18,8 +18,8 @@ define <vscale x 1 x i1> @insertelement_nxv1i1_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 1 x i1> poison, i1 0, i32 0 @@ -40,8 +40,8 @@ define <vscale x 1 x i1> @insertelement_nxv1i1_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 1 x i1> poison, i1 -1, i32 0 @@ -70,7 +70,8 @@ define <vscale x 1 x i1> @insertelement_nxv1i1_2(i1 %x, i32 %idx) { ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[TRUNC1]](s32) + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 1 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 1 x i1> poison, i1 %x, i32 %idx @@ -91,8 +92,8 @@ define <vscale x 2 x i1> @insertelement_nxv2i1_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 2 x i1> poison, i1 0, i32 1 @@ -113,8 +114,8 @@ define <vscale x 2 x i1> @insertelement_nxv2i1_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0 @@ -143,7 +144,8 @@ define <vscale x 2 x i1> @insertelement_nxv2i1_2(i1 %x, i32 %idx) { ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[TRUNC1]](s32) + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 2 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 2 x i1> poison, i1 %x, i32 %idx @@ -164,8 +166,8 @@ define <vscale x 4 x i1> @insertelement_nxv4i1_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 4 x i1> poison, i1 0, i32 2 @@ -186,8 +188,8 @@ define <vscale x 4 x i1> @insertelement_nxv4i1_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 4 x i1> poison, i1 -1, i32 0 @@ -214,8 +216,8 @@ define <vscale x 4 x i1> @insertelement_nxv4i1_2(i1 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 4 x i1> poison, i1 %x, i32 0 @@ -236,8 +238,8 @@ define <vscale x 8 x i1> @insertelement_nxv8i1_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 8 x i1> poison, i1 0, i32 0 @@ -258,8 +260,8 @@ define <vscale x 8 x i1> @insertelement_nxv8i1_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 8 x i1> poison, i1 -1, i32 0 @@ -288,7 +290,8 @@ define <vscale x 8 x i1> @insertelement_nxv8i1_2(i1 %x, i32 %idx) { ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[TRUNC1]](s32) + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 8 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 8 x i1> poison, i1 %x, i32 %idx @@ -309,8 +312,8 @@ define <vscale x 16 x i1> @insertelement_nxv16i1_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 16 x i1> poison, i1 0, i32 15 @@ -331,8 +334,8 @@ define <vscale x 16 x i1> @insertelement_nxv16i1_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 16 x i1> poison, i1 -1, i32 0 @@ -361,7 +364,8 @@ define <vscale x 16 x i1> @insertelement_nxv16i1_2(i1 %x, i32 %idx) { ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[TRUNC1]](s32) + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 16 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 16 x i1> poison, i1 %x, i32 %idx @@ -388,8 +392,8 @@ define <vscale x 4 x i1> @insertelement_nxv4i1_3(<vscale x 4 x i1> %v, i1 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s64) - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s1), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s1), [[C]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]](<vscale x 4 x s1>) ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement <vscale x 4 x i1> %v, i1 %x, i32 0 @@ -410,8 +414,8 @@ define <vscale x 1 x i8> @insertelement_nxv1i8_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 1 x i8> poison, i8 0, i32 0 @@ -432,8 +436,8 @@ define <vscale x 1 x i8> @insertelement_nxv1i8_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 1 x i8> poison, i8 -1, i32 0 @@ -460,8 +464,8 @@ define <vscale x 1 x i8> @insertelement_nxv1i8_2(i8 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s8>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 1 x i8> poison, i8 %x, i32 0 @@ -482,8 +486,8 @@ define <vscale x 2 x i8> @insertelement_nxv2i8_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 2 x i8> poison, i8 0, i32 0 @@ -504,8 +508,8 @@ define <vscale x 2 x i8> @insertelement_nxv2i8_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 2 x i8> poison, i8 -1, i32 0 @@ -532,8 +536,8 @@ define <vscale x 2 x i8> @insertelement_nxv2i8_2(i8 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s8>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 2 x i8> poison, i8 %x, i32 0 @@ -554,8 +558,8 @@ define <vscale x 4 x i8> @insertelement_nxv4i8_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 4 x i8> poison, i8 0, i32 0 @@ -576,8 +580,8 @@ define <vscale x 4 x i8> @insertelement_nxv4i8_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 4 x i8> poison, i8 -1, i32 0 @@ -604,8 +608,8 @@ define <vscale x 4 x i8> @insertelement_nxv4i8_2(i8 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 4 x i8> poison, i8 %x, i32 0 @@ -626,8 +630,8 @@ define <vscale x 8 x i8> @insertelement_nxv8i8_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 8 x i8> poison, i8 0, i32 0 @@ -648,8 +652,8 @@ define <vscale x 8 x i8> @insertelement_nxv8i8_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 8 x i8> poison, i8 -1, i32 0 @@ -676,8 +680,8 @@ define <vscale x 8 x i8> @insertelement_nxv8i8_2(i8 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 8 x s8>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 8 x i8> poison, i8 %x, i32 0 @@ -689,8 +693,8 @@ define <vscale x 16 x i8> @insertelement_nxv16i8_0() { ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 - ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>) ; RV32-NEXT: PseudoRET implicit $v8m2 ; @@ -720,8 +724,8 @@ define <vscale x 16 x i8> @insertelement_nxv16i8_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>) ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement <vscale x 16 x i8> poison, i8 -1, i32 0 @@ -739,7 +743,8 @@ define <vscale x 16 x i8> @insertelement_nxv16i8_2(i8 %x, i64 %idx) { ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[MV]](s64) + ; RV32-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MV]](s64) + ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[TRUNC1]](s32) ; RV32-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>) ; RV32-NEXT: PseudoRET implicit $v8m2 ; @@ -778,8 +783,8 @@ define <vscale x 4 x i8> @insertelement_nxv4i8_3(<vscale x 4 x i8> %v, i8 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s64) - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s8), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s8), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s8>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 4 x i8> %v, i8 %x, i32 0 @@ -800,8 +805,8 @@ define <vscale x 1 x i16> @insertelement_nxv1i16_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 1 x i16> poison, i16 0, i32 0 @@ -822,8 +827,8 @@ define <vscale x 1 x i16> @insertelement_nxv1i16_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 1 x i16> poison, i16 -1, i32 0 @@ -850,8 +855,8 @@ define <vscale x 1 x i16> @insertelement_nxv1i16_2(i16 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s16>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 1 x i16> poison, i16 %x, i32 0 @@ -863,8 +868,8 @@ define <vscale x 2 x i16> @insertelement_nxv2i16_0() { ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) ; RV32-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>) ; RV32-NEXT: PseudoRET implicit $v8 ; @@ -894,8 +899,8 @@ define <vscale x 2 x i16> @insertelement_nxv2i16_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 2 x i16> poison, i16 -1, i32 0 @@ -922,8 +927,8 @@ define <vscale x 2 x i16> @insertelement_nxv2i16_2(i16 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s16>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 2 x i16> poison, i16 %x, i32 0 @@ -944,8 +949,8 @@ define <vscale x 4 x i16> @insertelement_nxv4i16_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 4 x i16> poison, i16 0, i32 0 @@ -966,8 +971,8 @@ define <vscale x 4 x i16> @insertelement_nxv4i16_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 4 x i16> poison, i16 -1, i32 0 @@ -994,8 +999,8 @@ define <vscale x 4 x i16> @insertelement_nxv4i16_2(i16 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 4 x i16> poison, i16 %x, i32 0 @@ -1016,8 +1021,8 @@ define <vscale x 8 x i16> @insertelement_nxv8i16_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>) ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement <vscale x 8 x i16> poison, i16 0, i32 0 @@ -1038,8 +1043,8 @@ define <vscale x 8 x i16> @insertelement_nxv8i16_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>) ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement <vscale x 8 x i16> poison, i16 -1, i32 0 @@ -1066,8 +1071,8 @@ define <vscale x 8 x i16> @insertelement_nxv8i16_2(i16 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>) ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement <vscale x 8 x i16> poison, i16 %x, i32 0 @@ -1088,8 +1093,8 @@ define <vscale x 16 x i16> @insertelement_nxv16i16_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>) ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement <vscale x 16 x i16> poison, i16 0, i32 0 @@ -1110,8 +1115,8 @@ define <vscale x 16 x i16> @insertelement_nxv16i16_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>) ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement <vscale x 16 x i16> poison, i16 -1, i32 0 @@ -1138,8 +1143,8 @@ define <vscale x 16 x i16> @insertelement_nxv16i16_2(i16 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>) ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement <vscale x 16 x i16> poison, i16 %x, i32 0 @@ -1166,8 +1171,8 @@ define <vscale x 4 x i16> @insertelement_nxv4i16(<vscale x 4 x i16> %v, i16 %x) ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64) - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s16), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s16), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 4 x s16>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 4 x i16> %v, i16 %x, i32 0 @@ -1187,7 +1192,8 @@ define <vscale x 1 x i32> @insertelement_nxv1i32_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 1 x i32> poison, i32 0, i32 0 @@ -1208,8 +1214,8 @@ define <vscale x 1 x i32> @insertelement_nxv1i32_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 1 x i32> poison, i32 -1, i32 0 @@ -1235,8 +1241,8 @@ define <vscale x 1 x i32> @insertelement_nxv1i32_2(i32 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s32>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 1 x i32> poison, i32 %x, i32 0 @@ -1256,7 +1262,8 @@ define <vscale x 2 x i32> @insertelement_nxv2i32_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 2 x i32> poison, i32 0, i32 0 @@ -1277,8 +1284,8 @@ define <vscale x 2 x i32> @insertelement_nxv2i32_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 2 x i32> poison, i32 -1, i32 0 @@ -1304,8 +1311,8 @@ define <vscale x 2 x i32> @insertelement_nxv2i32_2(i32 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 2 x s32>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 2 x i32> poison, i32 %x, i32 0 @@ -1325,7 +1332,8 @@ define <vscale x 4 x i32> @insertelement_nxv4i32_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>) ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement <vscale x 4 x i32> poison, i32 0, i32 0 @@ -1346,8 +1354,8 @@ define <vscale x 4 x i32> @insertelement_nxv4i32_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>) ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement <vscale x 4 x i32> poison, i32 -1, i32 0 @@ -1373,8 +1381,8 @@ define <vscale x 4 x i32> @insertelement_nxv4i32_2(i32 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>) ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement <vscale x 4 x i32> poison, i32 %x, i32 0 @@ -1394,7 +1402,8 @@ define <vscale x 8 x i32> @insertelement_nxv8i32_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>) ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement <vscale x 8 x i32> poison, i32 0, i32 0 @@ -1415,8 +1424,8 @@ define <vscale x 8 x i32> @insertelement_nxv8i32_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>) ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0 @@ -1442,8 +1451,8 @@ define <vscale x 8 x i32> @insertelement_nxv8i32_2(i32 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>) ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement <vscale x 8 x i32> poison, i32 %x, i32 0 @@ -1463,7 +1472,8 @@ define <vscale x 16 x i32> @insertelement_nxv16i32_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>) ; RV64-NEXT: PseudoRET implicit $v8m8 %a = insertelement <vscale x 16 x i32> poison, i32 0, i32 0 @@ -1484,8 +1494,8 @@ define <vscale x 16 x i32> @insertelement_nxv16i32_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>) ; RV64-NEXT: PseudoRET implicit $v8m8 %a = insertelement <vscale x 16 x i32> poison, i32 -1, i32 0 @@ -1511,8 +1521,8 @@ define <vscale x 16 x i32> @insertelement_nxv16i32_2(i32 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) ; RV64-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>) ; RV64-NEXT: PseudoRET implicit $v8m8 %a = insertelement <vscale x 16 x i32> poison, i32 %x, i32 0 @@ -1538,8 +1548,8 @@ define <vscale x 4 x i32> @insertelement_nxv4i32(<vscale x 4 x i32> %v, i32 %x) ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s32), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s32), [[C]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>) ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement <vscale x 4 x i32> %v, i32 %x, i32 0 @@ -1560,8 +1570,7 @@ define <vscale x 1 x i64> @insertelement_nxv1i64_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 1 x i64> poison, i64 0, i32 0 @@ -1582,8 +1591,8 @@ define <vscale x 1 x i64> @insertelement_nxv1i64_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 1 x i64> poison, i64 -1, i32 0 @@ -1610,8 +1619,8 @@ define <vscale x 1 x i64> @insertelement_nxv1i64_2(i64 %x) { ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]](<vscale x 1 x s64>) ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement <vscale x 1 x i64> poison, i64 %x, i32 0 @@ -1632,8 +1641,7 @@ define <vscale x 2 x i64> @insertelement_nxv2i64_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>) ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement <vscale x 2 x i64> poison, i64 0, i32 0 @@ -1654,8 +1662,8 @@ define <vscale x 2 x i64> @insertelement_nxv2i64_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>) ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement <vscale x 2 x i64> poison, i64 -1, i32 0 @@ -1682,8 +1690,8 @@ define <vscale x 2 x i64> @insertelement_nxv2i64_2(i64 %x) { ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>) ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement <vscale x 2 x i64> poison, i64 %x, i32 0 @@ -1704,8 +1712,7 @@ define <vscale x 4 x i64> @insertelement_nxv4i64_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>) ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement <vscale x 4 x i64> poison, i64 0, i32 0 @@ -1726,8 +1733,8 @@ define <vscale x 4 x i64> @insertelement_nxv4i64_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>) ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement <vscale x 4 x i64> poison, i64 -1, i32 0 @@ -1754,8 +1761,8 @@ define <vscale x 4 x i64> @insertelement_nxv4i64_2(i64 %x) { ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>) ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement <vscale x 4 x i64> poison, i64 %x, i32 0 @@ -1776,8 +1783,7 @@ define <vscale x 8 x i64> @insertelement_nxv8i64_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) ; RV64-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>) ; RV64-NEXT: PseudoRET implicit $v8m8 %a = insertelement <vscale x 8 x i64> poison, i64 0, i32 0 @@ -1798,8 +1804,8 @@ define <vscale x 8 x i64> @insertelement_nxv8i64_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) ; RV64-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>) ; RV64-NEXT: PseudoRET implicit $v8m8 %a = insertelement <vscale x 8 x i64> poison, i64 -1, i32 0 @@ -1826,8 +1832,8 @@ define <vscale x 8 x i64> @insertelement_nxv8i64_2(i64 %x) { ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) ; RV64-NEXT: $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>) ; RV64-NEXT: PseudoRET implicit $v8m8 %a = insertelement <vscale x 8 x i64> poison, i64 %x, i32 0 @@ -1850,8 +1856,7 @@ define <vscale x 16 x i64> @insertelement_nxv16i64_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) ; RV64-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>) ; RV64-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>) ; RV64-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>) @@ -1876,8 +1881,8 @@ define <vscale x 16 x i64> @insertelement_nxv16i64_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) ; RV64-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>) ; RV64-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>) ; RV64-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>) @@ -1908,8 +1913,8 @@ define <vscale x 16 x i64> @insertelement_nxv16i64_2(i64 %x) { ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) ; RV64-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>) ; RV64-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>) ; RV64-NEXT: $v16m8 = COPY [[UV1]](<vscale x 8 x s64>) @@ -1938,8 +1943,8 @@ define <vscale x 4 x i64> @insertelement_nxv4i64(<vscale x 4 x i64> %v, i64 %x) ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s64), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s64), [[C]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>) ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement <vscale x 4 x i64> %v, i64 %x, i32 0 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll index df7778899b0d..7ea67073bc28 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll @@ -8,8 +8,8 @@ define <vscale x 1 x i1> @shufflevector_nxv1i1_0() { ; RV32-LABEL: name: shufflevector_nxv1i1_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -30,8 +30,8 @@ define <vscale x 1 x i1> @shufflevector_nxv1i1_1() { ; RV32-LABEL: name: shufflevector_nxv1i1_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -54,8 +54,8 @@ define <vscale x 1 x i1> @shufflevector_nxv1i1_2(<vscale x 1 x i1> %a) { ; RV32-NEXT: liveins: $v0 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 1 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 1 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -78,8 +78,8 @@ define <vscale x 2 x i1> @shufflevector_nxv2i1_0() { ; RV32-LABEL: name: shufflevector_nxv2i1_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -100,8 +100,8 @@ define <vscale x 2 x i1> @shufflevector_nxv2i1_1() { ; RV32-LABEL: name: shufflevector_nxv2i1_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -124,8 +124,8 @@ define <vscale x 2 x i1> @shufflevector_nxv2i1_2(<vscale x 2 x i1> %a) { ; RV32-NEXT: liveins: $v0 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 2 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 2 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -148,8 +148,8 @@ define <vscale x 4 x i1> @shufflevector_nxv4i1_0() { ; RV32-LABEL: name: shufflevector_nxv4i1_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -170,8 +170,8 @@ define <vscale x 4 x i1> @shufflevector_nxv4i1_1() { ; RV32-LABEL: name: shufflevector_nxv4i1_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -194,8 +194,8 @@ define <vscale x 4 x i1> @shufflevector_nxv4i1_2(<vscale x 4 x i1> %a) { ; RV32-NEXT: liveins: $v0 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -218,8 +218,8 @@ define <vscale x 8 x i1> @shufflevector_nxv8i1_0() { ; RV32-LABEL: name: shufflevector_nxv8i1_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -240,8 +240,8 @@ define <vscale x 8 x i1> @shufflevector_nxv8i1_1() { ; RV32-LABEL: name: shufflevector_nxv8i1_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -264,8 +264,8 @@ define <vscale x 8 x i1> @shufflevector_nxv8i1_2(<vscale x 8 x i1> %a) { ; RV32-NEXT: liveins: $v0 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 8 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 8 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -288,8 +288,8 @@ define <vscale x 16 x i1> @shufflevector_nxv16i1_0() { ; RV32-LABEL: name: shufflevector_nxv16i1_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -310,8 +310,8 @@ define <vscale x 16 x i1> @shufflevector_nxv16i1_1() { ; RV32-LABEL: name: shufflevector_nxv16i1_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -334,8 +334,8 @@ define <vscale x 16 x i1> @shufflevector_nxv16i1_2(<vscale x 16 x i1> %a) { ; RV32-NEXT: liveins: $v0 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 16 x s1>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 16 x s1>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s1>) ; RV32-NEXT: PseudoRET implicit $v0 @@ -358,8 +358,8 @@ define <vscale x 1 x i8> @shufflevector_nxv1i8_0() { ; RV32-LABEL: name: shufflevector_nxv1i8_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s8>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -380,8 +380,8 @@ define <vscale x 1 x i8> @shufflevector_nxv1i8_1() { ; RV32-LABEL: name: shufflevector_nxv1i8_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s8>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -404,8 +404,8 @@ define <vscale x 1 x i8> @shufflevector_nxv1i8_2(<vscale x 1 x i8> %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 1 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 1 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s8>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -428,8 +428,8 @@ define <vscale x 2 x i8> @shufflevector_nxv2i8_0() { ; RV32-LABEL: name: shufflevector_nxv2i8_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s8>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -450,8 +450,8 @@ define <vscale x 2 x i8> @shufflevector_nxv2i8_1() { ; RV32-LABEL: name: shufflevector_nxv2i8_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s8>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -474,8 +474,8 @@ define <vscale x 2 x i8> @shufflevector_nxv2i8_2(<vscale x 2 x i8> %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 2 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 2 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s8>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -498,8 +498,8 @@ define <vscale x 4 x i8> @shufflevector_nxv4i8_0() { ; RV32-LABEL: name: shufflevector_nxv4i8_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s8>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -520,8 +520,8 @@ define <vscale x 4 x i8> @shufflevector_nxv4i8_1() { ; RV32-LABEL: name: shufflevector_nxv4i8_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s8>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -544,8 +544,8 @@ define <vscale x 4 x i8> @shufflevector_nxv4i8_2(<vscale x 4 x i8> %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s8>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -568,8 +568,8 @@ define <vscale x 8 x i8> @shufflevector_nxv8i8_0() { ; RV32-LABEL: name: shufflevector_nxv8i8_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s8>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -590,8 +590,8 @@ define <vscale x 8 x i8> @shufflevector_nxv8i8_1() { ; RV32-LABEL: name: shufflevector_nxv8i8_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s8>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -614,8 +614,8 @@ define <vscale x 8 x i8> @shufflevector_nxv8i8_2(<vscale x 8 x i8> %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 8 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 8 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s8>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -638,8 +638,8 @@ define <vscale x 16 x i8> @shufflevector_nxv16i8_0() { ; RV32-LABEL: name: shufflevector_nxv16i8_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s8>) ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -660,8 +660,8 @@ define <vscale x 16 x i8> @shufflevector_nxv16i8_1() { ; RV32-LABEL: name: shufflevector_nxv16i8_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s8>) ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -684,8 +684,8 @@ define <vscale x 16 x i8> @shufflevector_nxv16i8_2(<vscale x 16 x i8> %a) { ; RV32-NEXT: liveins: $v8m2 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m2 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 16 x s8>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 16 x s8>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s8>) ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -708,8 +708,8 @@ define <vscale x 1 x i16> @shufflevector_nxv1i16_0() { ; RV32-LABEL: name: shufflevector_nxv1i16_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s16>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -730,8 +730,8 @@ define <vscale x 1 x i16> @shufflevector_nxv1i16_1() { ; RV32-LABEL: name: shufflevector_nxv1i16_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s16>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -754,8 +754,8 @@ define <vscale x 1 x i16> @shufflevector_nxv1i16_2(<vscale x 1 x i16> %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 1 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 1 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s16>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -778,8 +778,8 @@ define <vscale x 2 x i16> @shufflevector_nxv2i16_0() { ; RV32-LABEL: name: shufflevector_nxv2i16_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s16>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -800,8 +800,8 @@ define <vscale x 2 x i16> @shufflevector_nxv2i16_1() { ; RV32-LABEL: name: shufflevector_nxv2i16_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s16>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -824,8 +824,8 @@ define <vscale x 2 x i16> @shufflevector_nxv2i16_2(<vscale x 2 x i16> %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 2 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 2 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s16>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -848,8 +848,8 @@ define <vscale x 4 x i16> @shufflevector_nxv4i16_0() { ; RV32-LABEL: name: shufflevector_nxv4i16_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s16>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -870,8 +870,8 @@ define <vscale x 4 x i16> @shufflevector_nxv4i16_1() { ; RV32-LABEL: name: shufflevector_nxv4i16_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s16>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -894,8 +894,8 @@ define <vscale x 4 x i16> @shufflevector_nxv4i16_2(<vscale x 4 x i16> %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s16>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -918,8 +918,8 @@ define <vscale x 8 x i16> @shufflevector_nxv8i16_0() { ; RV32-LABEL: name: shufflevector_nxv8i16_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s16>) ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -940,8 +940,8 @@ define <vscale x 8 x i16> @shufflevector_nxv8i16_1() { ; RV32-LABEL: name: shufflevector_nxv8i16_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s16>) ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -964,8 +964,8 @@ define <vscale x 8 x i16> @shufflevector_nxv8i16_2(<vscale x 8 x i16> %a) { ; RV32-NEXT: liveins: $v8m2 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 8 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 8 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s16>) ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -988,8 +988,8 @@ define <vscale x 16 x i16> @shufflevector_nxv16i16_0() { ; RV32-LABEL: name: shufflevector_nxv16i16_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s16>) ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1010,8 +1010,8 @@ define <vscale x 16 x i16> @shufflevector_nxv16i16_1() { ; RV32-LABEL: name: shufflevector_nxv16i16_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s16>) ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1034,8 +1034,8 @@ define <vscale x 16 x i16> @shufflevector_nxv16i16_2(<vscale x 16 x i16> %a) { ; RV32-NEXT: liveins: $v8m4 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 16 x s16>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 16 x s16>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s16>) ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1058,8 +1058,8 @@ define <vscale x 1 x i32> @shufflevector_nxv1i32_0() { ; RV32-LABEL: name: shufflevector_nxv1i32_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s32>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -1080,8 +1080,8 @@ define <vscale x 1 x i32> @shufflevector_nxv1i32_1() { ; RV32-LABEL: name: shufflevector_nxv1i32_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s32>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -1104,8 +1104,8 @@ define <vscale x 1 x i32> @shufflevector_nxv1i32_2(<vscale x 1 x i32> %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 1 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 1 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s32>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -1128,8 +1128,8 @@ define <vscale x 2 x i32> @shufflevector_nxv2i32_0() { ; RV32-LABEL: name: shufflevector_nxv2i32_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s32>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -1150,8 +1150,8 @@ define <vscale x 2 x i32> @shufflevector_nxv2i32_1() { ; RV32-LABEL: name: shufflevector_nxv2i32_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s32>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -1174,8 +1174,8 @@ define <vscale x 2 x i32> @shufflevector_nxv2i32_2(<vscale x 2 x i32> %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 2 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 2 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s32>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -1198,8 +1198,8 @@ define <vscale x 4 x i32> @shufflevector_nxv4i32_0() { ; RV32-LABEL: name: shufflevector_nxv4i32_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s32>) ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -1220,8 +1220,8 @@ define <vscale x 4 x i32> @shufflevector_nxv4i32_1() { ; RV32-LABEL: name: shufflevector_nxv4i32_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s32>) ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -1244,8 +1244,8 @@ define <vscale x 4 x i32> @shufflevector_nxv4i32_2(<vscale x 4 x i32> %a) { ; RV32-NEXT: liveins: $v8m2 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s32>) ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -1268,8 +1268,8 @@ define <vscale x 8 x i32> @shufflevector_nxv8i32_0() { ; RV32-LABEL: name: shufflevector_nxv8i32_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s32>) ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1290,8 +1290,8 @@ define <vscale x 8 x i32> @shufflevector_nxv8i32_1() { ; RV32-LABEL: name: shufflevector_nxv8i32_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s32>) ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1314,8 +1314,8 @@ define <vscale x 8 x i32> @shufflevector_nxv8i32_2(<vscale x 8 x i32> %a) { ; RV32-NEXT: liveins: $v8m4 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 8 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 8 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s32>) ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1338,8 +1338,8 @@ define <vscale x 16 x i32> @shufflevector_nxv16i32_0() { ; RV32-LABEL: name: shufflevector_nxv16i32_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s32>) ; RV32-NEXT: PseudoRET implicit $v8m8 @@ -1360,8 +1360,8 @@ define <vscale x 16 x i32> @shufflevector_nxv16i32_1() { ; RV32-LABEL: name: shufflevector_nxv16i32_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s32>) ; RV32-NEXT: PseudoRET implicit $v8m8 @@ -1384,8 +1384,8 @@ define <vscale x 16 x i32> @shufflevector_nxv16i32_2(<vscale x 16 x i32> %a) { ; RV32-NEXT: liveins: $v8m8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 16 x s32>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 16 x s32>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s32>) ; RV32-NEXT: PseudoRET implicit $v8m8 @@ -1408,8 +1408,8 @@ define <vscale x 1 x i64> @shufflevector_nxv1i64_0() { ; RV32-LABEL: name: shufflevector_nxv1i64_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s64>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -1430,8 +1430,8 @@ define <vscale x 1 x i64> @shufflevector_nxv1i64_1() { ; RV32-LABEL: name: shufflevector_nxv1i64_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 1 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s64>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -1454,8 +1454,8 @@ define <vscale x 1 x i64> @shufflevector_nxv1i64_2(<vscale x 1 x i64> %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 1 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 1 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s64>) ; RV32-NEXT: PseudoRET implicit $v8 @@ -1478,8 +1478,8 @@ define <vscale x 2 x i64> @shufflevector_nxv2i64_0() { ; RV32-LABEL: name: shufflevector_nxv2i64_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s64>) ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -1500,8 +1500,8 @@ define <vscale x 2 x i64> @shufflevector_nxv2i64_1() { ; RV32-LABEL: name: shufflevector_nxv2i64_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 2 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s64>) ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -1524,8 +1524,8 @@ define <vscale x 2 x i64> @shufflevector_nxv2i64_2(<vscale x 2 x i64> %a) { ; RV32-NEXT: liveins: $v8m2 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 2 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 2 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s64>) ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -1548,8 +1548,8 @@ define <vscale x 4 x i64> @shufflevector_nxv4i64_0() { ; RV32-LABEL: name: shufflevector_nxv4i64_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s64>) ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1570,8 +1570,8 @@ define <vscale x 4 x i64> @shufflevector_nxv4i64_1() { ; RV32-LABEL: name: shufflevector_nxv4i64_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 4 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s64>) ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1594,8 +1594,8 @@ define <vscale x 4 x i64> @shufflevector_nxv4i64_2(<vscale x 4 x i64> %a) { ; RV32-NEXT: liveins: $v8m4 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 4 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s64>) ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1618,8 +1618,8 @@ define <vscale x 8 x i64> @shufflevector_nxv8i64_0() { ; RV32-LABEL: name: shufflevector_nxv8i64_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s64>) ; RV32-NEXT: PseudoRET implicit $v8m8 @@ -1640,8 +1640,8 @@ define <vscale x 8 x i64> @shufflevector_nxv8i64_1() { ; RV32-LABEL: name: shufflevector_nxv8i64_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 8 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s64>) ; RV32-NEXT: PseudoRET implicit $v8m8 @@ -1664,8 +1664,8 @@ define <vscale x 8 x i64> @shufflevector_nxv8i64_2(<vscale x 8 x i64> %a) { ; RV32-NEXT: liveins: $v8m8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 8 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<vscale x 8 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s64>) ; RV32-NEXT: PseudoRET implicit $v8m8 @@ -1688,8 +1688,8 @@ define <vscale x 16 x i64> @shufflevector_nxv16i64_0() { ; RV32-LABEL: name: shufflevector_nxv16i64_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[SPLAT_VECTOR]](<vscale x 16 x s64>) ; RV32-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>) @@ -1714,8 +1714,8 @@ define <vscale x 16 x i64> @shufflevector_nxv16i64_1() { ; RV32-LABEL: name: shufflevector_nxv16i64_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](<vscale x 16 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[SPLAT_VECTOR]](<vscale x 16 x s64>) ; RV32-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>) @@ -1744,8 +1744,8 @@ define <vscale x 16 x i64> @shufflevector_nxv16i64_2(<vscale x 16 x i64> %a) { ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v16m8 ; RV32-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<vscale x 16 x s64>) = G_CONCAT_VECTORS [[COPY]](<vscale x 8 x s64>), [[COPY1]](<vscale x 8 x s64>) - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[CONCAT_VECTORS]](<vscale x 16 x s64>), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[CONCAT_VECTORS]](<vscale x 16 x s64>), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s64>) = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[SPLAT_VECTOR]](<vscale x 16 x s64>) ; RV32-NEXT: $v8m8 = COPY [[UV]](<vscale x 8 x s64>) |