diff options
author | Luke Lau <luke@igalia.com> | 2024-03-29 18:42:05 +0800 |
---|---|---|
committer | Luke Lau <luke@igalia.com> | 2024-03-29 19:11:26 +0800 |
commit | 131be5de90dac9f54a8213a1aab66a75c62890ec (patch) | |
tree | 347fa88c861d6ed74138885ef963530cd680e920 | |
parent | 316634ff5925481201a7b27d5f806cc2361cf4f2 (diff) |
[RISCV] Add more disjoint or tests for vwadd[u].{w,v}v. NFC
-rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll | 60 |
1 files changed, 58 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll index 36bc10f055b8..ed12afdd9595 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll @@ -1396,8 +1396,8 @@ define <vscale x 1 x i64> @i1_zext(<vscale x 1 x i1> %va, <vscale x 1 x i64> %vb ; %x.i32 and %y.i32 are disjoint, so DAGCombiner will combine it into an or. ; FIXME: We should be able to recover the or into vwaddu.vv if the disjoint ; flag is set. -define <vscale x 2 x i32> @disjoint_or(<vscale x 2 x i8> %x.i8, <vscale x 2 x i8> %y.i8) { -; CHECK-LABEL: disjoint_or: +define <vscale x 2 x i32> @vwaddu_vv_disjoint_or_add(<vscale x 2 x i8> %x.i8, <vscale x 2 x i8> %y.i8) { +; CHECK-LABEL: vwaddu_vv_disjoint_or_add: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vzext.vf2 v10, v8 @@ -1414,3 +1414,59 @@ define <vscale x 2 x i32> @disjoint_or(<vscale x 2 x i8> %x.i8, <vscale x 2 x i8 %add = add <vscale x 2 x i32> %x.i32, %y.i32 ret <vscale x 2 x i32> %add } + +; TODO: We could select vwaddu.vv, but when both arms of the or are the same +; DAGCombiner::hoistLogicOpWithSameOpcodeHands moves the zext above the or. +define <vscale x 2 x i32> @vwaddu_vv_disjoint_or(<vscale x 2 x i16> %x.i16, <vscale x 2 x i16> %y.i16) { +; CHECK-LABEL: vwaddu_vv_disjoint_or: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma +; CHECK-NEXT: vor.vv v9, v8, v9 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; CHECK-NEXT: vzext.vf2 v8, v9 +; CHECK-NEXT: ret + %x.i32 = zext <vscale x 2 x i16> %x.i16 to <vscale x 2 x i32> + %y.i32 = zext <vscale x 2 x i16> %y.i16 to <vscale x 2 x i32> + %or = or disjoint <vscale x 2 x i32> %x.i32, %y.i32 + ret <vscale x 2 x i32> %or +} + +; TODO: We could select vwadd.vv, but when both arms of the or are the same +; DAGCombiner::hoistLogicOpWithSameOpcodeHands moves the zext above the or. +define <vscale x 2 x i32> @vwadd_vv_disjoint_or(<vscale x 2 x i16> %x.i16, <vscale x 2 x i16> %y.i16) { +; CHECK-LABEL: vwadd_vv_disjoint_or: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma +; CHECK-NEXT: vor.vv v9, v8, v9 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; CHECK-NEXT: vsext.vf2 v8, v9 +; CHECK-NEXT: ret + %x.i32 = sext <vscale x 2 x i16> %x.i16 to <vscale x 2 x i32> + %y.i32 = sext <vscale x 2 x i16> %y.i16 to <vscale x 2 x i32> + %or = or disjoint <vscale x 2 x i32> %x.i32, %y.i32 + ret <vscale x 2 x i32> %or +} + +define <vscale x 2 x i32> @vwaddu_wv_disjoint_or(<vscale x 2 x i32> %x.i32, <vscale x 2 x i16> %y.i16) { +; CHECK-LABEL: vwaddu_wv_disjoint_or: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma +; CHECK-NEXT: vzext.vf2 v10, v9 +; CHECK-NEXT: vor.vv v8, v8, v10 +; CHECK-NEXT: ret + %y.i32 = zext <vscale x 2 x i16> %y.i16 to <vscale x 2 x i32> + %or = or disjoint <vscale x 2 x i32> %x.i32, %y.i32 + ret <vscale x 2 x i32> %or +} + +define <vscale x 2 x i32> @vwadd_wv_disjoint_or(<vscale x 2 x i32> %x.i32, <vscale x 2 x i16> %y.i16) { +; CHECK-LABEL: vwadd_wv_disjoint_or: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma +; CHECK-NEXT: vsext.vf2 v10, v9 +; CHECK-NEXT: vor.vv v8, v8, v10 +; CHECK-NEXT: ret + %y.i32 = sext <vscale x 2 x i16> %y.i16 to <vscale x 2 x i32> + %or = or disjoint <vscale x 2 x i32> %x.i32, %y.i32 + ret <vscale x 2 x i32> %or +} |