[SLP][NFC]Add a test with the incorrect sign extension of first ext

node.

1 files changed, 29 insertions, 0 deletions

diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/init-ext-node-not-truncable.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/init-ext-node-not-truncable.ll
new file mode 100644
index 000000000000..f6d1baf44a76
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/init-ext-node-not-truncable.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux-gnu -mattr="+v" < %s | FileCheck %s
+
+@h = global [16 x i64] zeroinitializer
+
+define void @test() {
+; CHECK-LABEL: define void @test(
+; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    store <2 x i64> <i64 1, i64 0>, ptr @h, align 8
+; CHECK-NEXT:    ret void
+;
+entry:
+  %sext.0 = sext i8 0 to i32
+  %sext.1 = sext i8 0 to i32
+
+  %lshr.0 = lshr i32 0, %sext.0
+  %lshr.1 = lshr i32 0, %sext.1
+
+  %or.0 = or i32 %lshr.0, -1
+  %or.1 = or i32 %lshr.1, 0
+
+  %zext.0 = zext i32 %or.0 to i64
+  %zext.1 = zext i32 %or.1 to i64
+
+  store i64 %zext.0, ptr @h, align 8
+  store i64 %zext.1, ptr getelementptr inbounds ([16 x i64], ptr @h, i64 0, i64 1), align 8
+  ret void
+}