diff options
author | Nikita Popov <npopov@redhat.com> | 2024-05-02 09:38:09 +0900 |
---|---|---|
committer | GitHub <noreply@github.com> | 2024-05-02 09:38:09 +0900 |
commit | d484c4d3501a7ff3d00a6e0cfad026a3b01d320c (patch) | |
tree | 54f0725bba8f93d16ccd6fb40371446a714bf198 | |
parent | 4b75fcf0a50f4be955b611e8e20d84d90ea133c8 (diff) |
[InterleavedLoadCombine] Bail out on non-byte-sized vector element type (#90705)
Vectors are always tightly packed, and elements of non-byte-sized
usually do not have a well-defined (byte) offset.
Fixes https://github.com/llvm/llvm-project/issues/90695.
-rw-r--r-- | llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp | 3 | ||||
-rw-r--r-- | llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll | 19 |
2 files changed, 22 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp index e5f164b18272..a9b59e738c00 100644 --- a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp +++ b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp @@ -877,6 +877,9 @@ public: if (LI->isAtomic()) return false; + if (!DL.typeSizeEqualsStoreSize(Result.VTy->getElementType())) + return false; + // Get the base polynomial computePolynomialFromPointer(*LI->getPointerOperand(), Offset, BasePtr, DL); diff --git a/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll new file mode 100644 index 000000000000..ee75b3a083f7 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/interleaved-load-combine-pr90695.ll @@ -0,0 +1,19 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S -passes=interleaved-load-combine < %s | FileCheck %s + +target triple = "aarch64-unknown-windows-gnu" + +; Make sure we don't crash on loads of vectors of non-byte-sized types. +define <4 x i1> @test(ptr %p) { +; CHECK-LABEL: define <4 x i1> @test( +; CHECK-SAME: ptr [[P:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[LOAD:%.*]] = load <2 x i1>, ptr [[P]], align 1 +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i1> [[LOAD]], <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2> +; CHECK-NEXT: ret <4 x i1> [[SHUF]] +; +entry: + %load = load <2 x i1>, ptr %p, align 1 + %shuf = shufflevector <2 x i1> %load, <2 x i1> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2> + ret <4 x i1> %shuf +} |