summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorFlorian Mayer <fmayer@google.com>2024-03-14 15:04:08 -0700
committerFlorian Mayer <fmayer@google.com>2024-03-14 15:04:08 -0700
commitcb639875ea85cd1242b15450911461a8a6b4f017 (patch)
treee9d9632ceab60023776c0d4642f45831981f4148
parentde96c71240c4c1021d8267cd8ccee4abc9299257 (diff)
Created using spr 1.3.4
-rw-r--r--llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
index 0c15941dda8b..0656960df534 100644
--- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
@@ -1255,12 +1255,12 @@ Value *HWAddressSanitizer::getFrameRecordInfo(IRBuilder<> &IRB) {
Value *PC = memtag::getPC(TargetTriple, IRB);
Value *FP = getCachedFP(IRB);
- // Mix SP and PC.
+ // Mix FP and PC.
// Assumptions:
// PC is 0x0000PPPPPPPPPPPP (48 bits are meaningful, others are zero)
- // SP is 0xsssssssssssSSSS0 (4 lower bits are zero)
- // We only really need ~20 lower non-zero bits (SSSS), so we mix like this:
- // 0xSSSSPPPPPPPPPPPP
+ // FP is 0xfffffffffffFFFF0 (4 lower bits are zero)
+ // We only really need ~20 lower non-zero bits (FFFF), so we mix like this:
+ // 0xFFFFPPPPPPPPPPPP
FP = IRB.CreateShl(FP, 44);
return IRB.CreateOr(PC, FP);
}