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| author | Paul Kirth <paulkirth@google.com> | 2024-05-09 17:21:38 -0700 |
|---|---|---|
| committer | Paul Kirth <paulkirth@google.com> | 2024-05-09 17:21:38 -0700 |
| commit | 4c05dc95110ec9e96cbab4956fdce203abb76a0e (patch) | |
| tree | 0fa354bc882e2b3f1f862c8693981710ae29e3c4 | |
| parent | e7d6f33ca0c9ed8f26255b0334da09b15e0aac44 (diff) | |
| parent | 0a3874226b4dbef5e695e10e96564a39bfba08fd (diff) | |
Created using spr 1.3.4
| -rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVFeatures.td | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/attributes.ll | 4 |
3 files changed, 7 insertions, 3 deletions
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp index adb17cec28c2..ffedbcf7ac5f 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -76,7 +76,8 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI, emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString()); } - if (STI.hasFeature(RISCV::FeatureStdExtA)) { + if (STI.hasFeature(RISCV::FeatureAbiAttributes) && + STI.hasFeature(RISCV::FeatureStdExtA)) { unsigned AtomicABITag = STI.hasFeature(RISCV::FeatureNoTrailingSeqCstFence) ? RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6C : RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6S; diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index deb983528f32..128174a5f535 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1221,6 +1221,9 @@ def FeatureNoTrailingSeqCstFence : SubtargetFeature<"no-trailing-seq-cst-fence", "false", "Disable trailing fence for seq-cst store.">; +def FeatureAbiAttributes : SubtargetFeature<"abi-attr", "EnableAbiAttributes", + "true", "Enable emitting RISC-V ABI attributes">; + def FeatureUnalignedScalarMem : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem", "true", "Has reasonably performant unaligned scalar " diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 61b5e50c6d52..b6a87ae4607a 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -129,8 +129,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s -; RUN: llc -mtriple=riscv64 -mattr=+a,no-trailing-seq-cst-fence %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s -; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s +; RUN: llc -mtriple=riscv64 -mattr=+a,no-trailing-seq-cst-fence,+abi-attr %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s +; RUN: llc -mtriple=riscv64 -mattr=+a,+abi-attr %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV64C %s |