diff options
| author | Jay Foad <jay.foad@amd.com> | 2024-05-03 15:32:09 +0100 |
|---|---|---|
| committer | Jay Foad <jay.foad@amd.com> | 2024-05-03 15:32:47 +0100 |
| commit | 1cde1240ed6e45012d7510f4aa39badbdb4a4721 (patch) | |
| tree | ee676e3d3853efb2828b6c298686029bcd67bb7f | |
| parent | 5fc576956e3b47708e8b405d57cefddd945a43d9 (diff) | |
[AMDGPU] Use replaceOpcodeWith instead of applyCombine_s_mul_u64. NFC.
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUCombine.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp | 8 |
2 files changed, 2 insertions, 8 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td index 9218760538dc..5b52a1a872b9 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td @@ -115,7 +115,7 @@ def smulu64 : GICombineRule< (defs root:$smul, unsigned_matchinfo:$matchinfo), (match (wip_match_opcode G_MUL):$smul, [{ return matchCombine_s_mul_u64(*${smul}, ${matchinfo}); }]), - (apply [{ applyCombine_s_mul_u64(*${smul}, ${matchinfo}); }])>; + (apply [{ Helper.replaceOpcodeWith(*${smul}, ${matchinfo}); }])>; def sign_exension_in_reg_matchdata : GIDefMatchData<"std::pair<MachineInstr *, unsigned>">; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp index c403c3c70479..ff7cf9c8d6dc 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp @@ -107,11 +107,10 @@ public: // Find the s_mul_u64 instructions where the higher bits are either // zero-extended or sign-extended. - bool matchCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const; // Replace the s_mul_u64 instructions with S_MUL_I64_I32_PSEUDO if the higher // 33 bits are sign extended and with S_MUL_U64_U32_PSEUDO if the higher 32 // bits are zero extended. - void applyCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const; + bool matchCombine_s_mul_u64(MachineInstr &MI, unsigned &NewOpcode) const; private: #define GET_GICOMBINER_CLASS_MEMBERS @@ -438,11 +437,6 @@ bool AMDGPUPostLegalizerCombinerImpl::matchCombine_s_mul_u64( return false; } -void AMDGPUPostLegalizerCombinerImpl::applyCombine_s_mul_u64( - MachineInstr &MI, unsigned &NewOpcode) const { - Helper.replaceOpcodeWith(MI, NewOpcode); -} - // Pass boilerplate // ================ |