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| author | Craig Topper <craig.topper@sifive.com> | 2024-05-03 09:59:33 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-05-03 09:59:33 -0700 |
| commit | 3563af6c06ebc92bcaacef0e33285148ef0f75bd (patch) | |
| tree | 197dbd52949c5b8500617c8f5801627de7734c52 | |
| parent | a657440bc695a98c54cd95bb7cc4cec5ab811d17 (diff) | |
[DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939)
When looking through a right shift, we need to make sure that all of
the bits we are using from the shift come from the shift input and
not the sign or zero bits that are shifted in.
Fixes #90936.
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/pr90936.ll | 6 |
2 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index c0bbea16a642..fc6bbc119d3c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -8840,6 +8840,10 @@ SDValue DAGCombiner::mergeTruncStores(StoreSDNode *N) { if (ShiftAmtC % NarrowNumBits != 0) return SDValue(); + // Make sure we aren't reading bits that are shifted in. + if (ShiftAmtC > WideVal.getScalarValueSizeInBits() - NarrowNumBits) + return SDValue(); + Offset = ShiftAmtC / NarrowNumBits; WideVal = WideVal.getOperand(0); } diff --git a/llvm/test/CodeGen/AArch64/pr90936.ll b/llvm/test/CodeGen/AArch64/pr90936.ll index 62c18fa52187..38cda8d38894 100644 --- a/llvm/test/CodeGen/AArch64/pr90936.ll +++ b/llvm/test/CodeGen/AArch64/pr90936.ll @@ -3,8 +3,10 @@ define void @f(i16 %arg, ptr %arg1) { ; CHECK-LABEL: f: -; CHECK: // %bb.0: // %bb -; CHECK-NEXT: strh w0, [x1] +; CHECK: // %bb.0: +; CHECK-NEXT: ubfx w8, w0, #8, #6 +; CHECK-NEXT: strb w0, [x1] +; CHECK-NEXT: strb w8, [x1, #1] ; CHECK-NEXT: ret bb: %i = trunc i16 %arg to i8 |