diff options
| author | Vitaly Buka <vitalybuka@google.com> | 2023-12-13 11:24:06 -0800 |
|---|---|---|
| committer | Vitaly Buka <vitalybuka@google.com> | 2023-12-13 11:24:06 -0800 |
| commit | 7b95f93b998aac4ef218ccacbfa52860f98384cd (patch) | |
| tree | 6a6b86ebc5edce167703db41ca14f9602f0e27d9 | |
| parent | ff467df0d78d8e8fb51f68ab896dd521bacc78c2 (diff) | |
| parent | 64fa90bf8966cb886463840e5c85b9602cbbdc52 (diff) | |
[𝘀𝗽𝗿] changes introduced through rebaseupstream/users/vitalybuka/spr/main.lsan-install-pthread_atfork
Created using spr 1.3.4
[skip ci]
683 files changed, 26811 insertions, 6998 deletions
diff --git a/bolt/test/X86/dwarf-test-df-logging.test b/bolt/test/X86/dwarf-test-df-logging.test index ca5e578a0845..6126e9628a31 100644 --- a/bolt/test/X86/dwarf-test-df-logging.test +++ b/bolt/test/X86/dwarf-test-df-logging.test @@ -6,7 +6,7 @@ ; RUN: -split-dwarf-file=main.dwo -o main.o ; RUN: llvm-mc -dwarf-version=4 -filetype=obj -triple x86_64-unknown-linux %p/Inputs/dwarf4-df-dualcu-helper.s \ ; RUN: -split-dwarf-file=helper.dwo -o helper.o -; RUN: %clang %cflags -gdwarf-5 -gsplit-dwarf=split main.o helper.o -o main.exe +; RUN: %clang %cflags -gdwarf-5 -gsplit-dwarf=split main.o helper.o -o main.exe -fno-pic -no-pie ; RUN: llvm-bolt main.exe -o main.exe.bolt --update-debug-sections | FileCheck -check-prefix=BOLT %s ; BOLT: BOLT-INFO: processing split DWARF diff --git a/bolt/test/X86/dwarf4-df-dualcu.test b/bolt/test/X86/dwarf4-df-dualcu.test index 5564d9ff2645..91b3e9e4cf09 100644 --- a/bolt/test/X86/dwarf4-df-dualcu.test +++ b/bolt/test/X86/dwarf4-df-dualcu.test @@ -5,7 +5,7 @@ ; RUN: -split-dwarf-file=main.dwo -o main.o ; RUN: llvm-mc -dwarf-version=4 -filetype=obj -triple x86_64-unknown-linux %p/Inputs/dwarf4-df-dualcu-helper.s \ ; RUN: -split-dwarf-file=helper.dwo -o helper.o -; RUN: %clang %cflags -gdwarf-5 -gsplit-dwarf=split main.o helper.o -o main.exe +; RUN: %clang %cflags -gdwarf-5 -gsplit-dwarf=split main.o helper.o -o main.exe -fno-pic -no-pie ; RUN: llvm-bolt main.exe -o main.exe.bolt --update-debug-sections --always-convert-to-ranges ; RUN: llvm-dwarfdump --show-form --verbose --debug-info main.exe | FileCheck -check-prefix=PRE-BOLT %s ; RUN: llvm-dwarfdump --show-form --verbose --debug-ranges main.exe.bolt &> %t/foo.txt diff --git a/bolt/test/X86/dwarf4-split-dwarf-no-address.test b/bolt/test/X86/dwarf4-split-dwarf-no-address.test index 5baef9238e90..753fad06eb06 100644 --- a/bolt/test/X86/dwarf4-split-dwarf-no-address.test +++ b/bolt/test/X86/dwarf4-split-dwarf-no-address.test @@ -5,7 +5,7 @@ ; RUN: --filetype=obj %p/Inputs/dwarf4-split-dwarf-no-address-main.s -o=main.o ; RUN: llvm-mc --split-dwarf-file=helper.dwo --triple=x86_64-unknown-linux-gnu \ ; RUN: --filetype=obj %p/Inputs/dwarf4-split-dwarf-no-address-helper.s -o=helper.o -; RUN: %clang %cflags -gdwarf-4 -gsplit-dwarf=split main.o helper.o -o main.exe +; RUN: %clang %cflags -gdwarf-4 -gsplit-dwarf=split main.o helper.o -o main.exe -fno-pic -no-pie ; RUN: llvm-bolt main.exe -o main.exe.bolt --update-debug-sections ; RUN: llvm-dwarfdump --show-form --verbose --debug-info main.exe.bolt | FileCheck -check-prefix=BOLT %s diff --git a/bolt/test/X86/dwarf5-df-dualcu.test b/bolt/test/X86/dwarf5-df-dualcu.test index 15d458d1c025..deaeea036690 100644 --- a/bolt/test/X86/dwarf5-df-dualcu.test +++ b/bolt/test/X86/dwarf5-df-dualcu.test @@ -5,7 +5,7 @@ ; RUN: -split-dwarf-file=main.dwo -o main.o ; RUN: llvm-mc -dwarf-version=5 -filetype=obj -triple x86_64-unknown-linux %p/Inputs/dwarf5-df-dualcu-helper.s \ ; RUN: -split-dwarf-file=helper.dwo -o helper.o -; RUN: %clang %cflags -gdwarf-5 -gsplit-dwarf=split main.o helper.o -o main.exe +; RUN: %clang %cflags -gdwarf-5 -gsplit-dwarf=split main.o helper.o -o main.exe -fno-pic -no-pie ; RUN: llvm-bolt main.exe -o main.exe.bolt --update-debug-sections --always-convert-to-ranges ; RUN: llvm-dwarfdump --show-form --verbose --debug-info main.exe | FileCheck -check-prefix=PRE-BOLT %s ; RUN: llvm-dwarfdump --show-form --verbose --debug-addr main.exe.bolt &> %t/foo.txt diff --git a/bolt/test/X86/dwarf5-df-mono-dualcu.test b/bolt/test/X86/dwarf5-df-mono-dualcu.test index a6024997ba72..12269287ef13 100644 --- a/bolt/test/X86/dwarf5-df-mono-dualcu.test +++ b/bolt/test/X86/dwarf5-df-mono-dualcu.test @@ -4,7 +4,7 @@ ; RUN: llvm-mc -dwarf-version=5 -filetype=obj -triple x86_64-unknown-linux %p/Inputs/dwarf5-df-mono-main.s \ ; RUN: -split-dwarf-file=main.dwo -o main.o ; RUN: llvm-mc -filetype=obj -triple x86_64-unknown-linux-gnu %p/Inputs/dwarf5-df-mono-helper.s -o=helper.o -; RUN: %clang %cflags -gdwarf-5 main.o helper.o -o main.exe +; RUN: %clang %cflags -gdwarf-5 main.o helper.o -o main.exe -fno-pic -no-pie ; RUN: llvm-bolt main.exe -o main.exe.bolt --update-debug-sections --always-convert-to-ranges ; RUN: llvm-dwarfdump --show-form --verbose --debug-info main.exe | FileCheck -check-prefix=PRE-BOLT %s ; RUN: llvm-dwarfdump --show-form --verbose --debug-addr main.exe.bolt &> %t/foo.txt diff --git a/bolt/test/X86/dwarf5-locaddrx.test b/bolt/test/X86/dwarf5-locaddrx.test index a1d66bb359d2..00e15101f853 100644 --- a/bolt/test/X86/dwarf5-locaddrx.test +++ b/bolt/test/X86/dwarf5-locaddrx.test @@ -3,7 +3,7 @@ ; RUN: cd %t ; RUN: llvm-mc -dwarf-version=5 -filetype=obj -triple x86_64-unknown-linux %p/Inputs/dwarf5-locaddrx.s \ ; RUN: -split-dwarf-file=mainlocadddrx.dwo -o mainlocadddrx.o -; RUN: %clang %cflags -gdwarf-5 -gsplit-dwarf=split mainlocadddrx.o -o mainlocadddrx.exe +; RUN: %clang %cflags -gdwarf-5 -gsplit-dwarf=split mainlocadddrx.o -o mainlocadddrx.exe -fno-pic -no-pie ; RUN: llvm-bolt mainlocadddrx.exe -o mainlocadddrx.exe.bolt --update-debug-sections --always-convert-to-ranges ; RUN: llvm-dwarfdump --show-form --verbose --debug-info mainlocadddrx.exe | FileCheck -check-prefix=PRE-BOLT %s ; RUN: llvm-dwarfdump --show-form --verbose --debug-addr mainlocadddrx.exe.bolt &> %t/foo.txt diff --git a/clang/cmake/caches/Fuchsia-stage2.cmake b/clang/cmake/caches/Fuchsia-stage2.cmake index 4b9085d99378..c4673c8a54c5 100644 --- a/clang/cmake/caches/Fuchsia-stage2.cmake +++ b/clang/cmake/caches/Fuchsia-stage2.cmake @@ -336,6 +336,7 @@ set(LLVM_TOOLCHAIN_TOOLS llvm-symbolizer llvm-undname llvm-xray + opt-viewer sancov scan-build-py CACHE STRING "") diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 066e4ac5b9e5..05d59d0da264 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -685,6 +685,9 @@ Bug Fixes in This Version (`#62157 <https://github.com/llvm/llvm-project/issues/62157>`_) and (`#64885 <https://github.com/llvm/llvm-project/issues/64885>`_) and (`#65568 <https://github.com/llvm/llvm-project/issues/65568>`_) +- Fixed false positive error emitted when templated alias inside a class + used private members of the same class. + Fixes (`#41693 <https://github.com/llvm/llvm-project/issues/41693>`_) Bug Fixes to Compiler Builtins ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 0d94ea2851c9..c8b17cbe8ab7 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -2878,7 +2878,7 @@ def Target : InheritableAttr { for (auto &Feature : AttrFeatures) { Feature = Feature.trim(); - if (Feature.startswith("arch=")) + if (Feature.starts_with("arch=")) return Feature.drop_front(sizeof("arch=") - 1); } return ""; @@ -2896,8 +2896,8 @@ def Target : InheritableAttr { for (auto &Feature : AttrFeatures) { Feature = Feature.trim(); - if (!Feature.startswith("no-") && !Feature.startswith("arch=") && - !Feature.startswith("fpmath=") && !Feature.startswith("tune=")) + if (!Feature.starts_with("no-") && !Feature.starts_with("arch=") && + !Feature.starts_with("fpmath=") && !Feature.starts_with("tune=")) Out.push_back(Feature); } } diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def b/clang/include/clang/Basic/BuiltinsAMDGPU.def index 8b59b3790d7b..7465f13d552d 100644 --- a/clang/include/clang/Basic/BuiltinsAMDGPU.def +++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def @@ -406,5 +406,21 @@ TARGET_BUILTIN(__builtin_amdgcn_cvt_pk_fp8_f32, "iffiIb", "nc", "fp8-insts") TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf8_f32, "ifiiIi", "nc", "fp8-insts") TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_fp8_f32, "ifiiIi", "nc", "fp8-insts") +//===----------------------------------------------------------------------===// +// GFX12+ only builtins. +//===----------------------------------------------------------------------===// + +TARGET_BUILTIN(__builtin_amdgcn_s_barrier_signal, "vIi", "n", "gfx12-insts") +TARGET_BUILTIN(__builtin_amdgcn_s_barrier_signal_var, "vi", "n", "gfx12-insts") +TARGET_BUILTIN(__builtin_amdgcn_s_barrier_wait, "vIs", "n", "gfx12-insts") +TARGET_BUILTIN(__builtin_amdgcn_s_barrier_signal_isfirst, "bIi", "n", "gfx12-insts") +TARGET_BUILTIN(__builtin_amdgcn_s_barrier_signal_isfirst_var, "bi", "n", "gfx12-insts") +TARGET_BUILTIN(__builtin_amdgcn_s_barrier_init, "vii", "n", "gfx12-insts") +TARGET_BUILTIN(__builtin_amdgcn_s_barrier_join, "vi", "n", "gfx12-insts") +TARGET_BUILTIN(__builtin_amdgcn_s_wakeup_barrier, "vi", "n", "gfx12-insts") +TARGET_BUILTIN(__builtin_amdgcn_s_barrier_leave, "b", "n", "gfx12-insts") +TARGET_BUILTIN(__builtin_amdgcn_s_get_barrier_state, "Uii", "n", "gfx12-insts") + + #undef BUILTIN #undef TARGET_BUILTIN diff --git a/clang/include/clang/Basic/Features.def b/clang/include/clang/Basic/Features.def index 7473e00a7bd8..06efac0cf1ab 100644 --- a/clang/include/clang/Basic/Features.def +++ b/clang/include/clang/Basic/Features.def @@ -282,7 +282,6 @@ EXTENSION(matrix_types_scalar_division, true) EXTENSION(cxx_attributes_on_using_declarations, LangOpts.CPlusPlus11) EXTENSION(datasizeof, LangOpts.CPlusPlus) -FEATURE(builtin_headers_in_system_modules, LangOpts.BuiltinHeadersInSystemModules) FEATURE(cxx_abi_relative_vtable, LangOpts.CPlusPlus && LangOpts.RelativeCXXABIVTables) // CUDA/HIP Features diff --git a/clang/include/clang/Basic/IdentifierTable.h b/clang/include/clang/Basic/IdentifierTable.h index 0898e7d39dd7..1ac182d4fce2 100644 --- a/clang/include/clang/Basic/IdentifierTable.h +++ b/clang/include/clang/Basic/IdentifierTable.h @@ -511,7 +511,7 @@ public: /// function(<#int x#>); /// \endcode bool isEditorPlaceholder() const { - return getName().startswith("<#") && getName().endswith("#>"); + return getName().starts_with("<#") && getName().ends_with("#>"); } /// Determine whether \p this is a name reserved for the implementation (C99 diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h index 8f7881abf26f..c9f9cbec7493 100644 --- a/clang/include/clang/Basic/TargetBuiltins.h +++ b/clang/include/clang/Basic/TargetBuiltins.h @@ -309,7 +309,7 @@ namespace clang { bool isTupleSet() const { return Flags & IsTupleSet; } bool isReadZA() const { return Flags & IsReadZA; } bool isWriteZA() const { return Flags & IsWriteZA; } - + bool isReductionQV() const { return Flags & IsReductionQV; } uint64_t getBits() const { return Flags; } bool isFlagSet(uint64_t Flag) const { return Flags & Flag; } }; diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index aa9b105364a5..db6f17d1c493 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -1946,6 +1946,23 @@ def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone, "", def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone, "", [IsStreamingCompatible], []>; } +// Standalone sve2.1 builtins +let TargetGuard = "sve2p1" in { +def SVORQV : SInst<"svorqv[_{d}]", "{Pd", "csilUcUsUiUl", MergeNone, "aarch64_sve_orqv", [IsReductionQV]>; +def SVEORQV : SInst<"sveorqv[_{d}]", "{Pd", "csilUcUsUiUl", MergeNone, "aarch64_sve_eorqv", [IsReductionQV]>; +def SVADDQV : SInst<"svaddqv[_{d}]", "{Pd", "hfdcsilUcUsUiUl", MergeNone, "aarch64_sve_addqv", [IsReductionQV]>; +def SVANDQV : SInst<"svandqv[_{d}]", "{Pd", "csilUcUsUiUl", MergeNone, "aarch64_sve_andqv", [IsReductionQV]>; +def SVSMAXQV : SInst<"svmaxqv[_{d}]", "{Pd", "csil", MergeNone, "aarch64_sve_smaxqv", [IsReductionQV]>; +def SVUMAXQV : SInst<"svmaxqv[_{d}]", "{Pd", "UcUsUiUl", MergeNone, "aarch64_sve_umaxqv", [IsReductionQV]>; +def SVSMINQV : SInst<"svminqv[_{d}]", "{Pd", "csil", MergeNone, "aarch64_sve_sminqv", [IsReductionQV]>; +def SVUMINQV : SInst<"svminqv[_{d}]", "{Pd", "UcUsUiUl", MergeNone, "aarch64_sve_uminqv", [IsReductionQV]>; + +def SVFMAXNMQV: SInst<"svmaxnmqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fmaxnmqv", [IsReductionQV]>; +def SVFMINNMQV: SInst<"svminnmqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fminnmqv", [IsReductionQV]>; +def SVFMAXQV: SInst<"svmaxqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fmaxqv", [IsReductionQV]>; +def SVFMINQV: SInst<"svminqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fminqv", [IsReductionQV]>; +} + let TargetGuard = "sve2p1|sme2" in { //FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when available def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone, "aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1, ImmCheck0_3>]>; diff --git a/clang/include/clang/Basic/arm_sve_sme_incl.td b/clang/include/clang/Basic/arm_sve_sme_incl.td index 040ce95a57de..0dba8493bad2 100644 --- a/clang/include/clang/Basic/arm_sve_sme_incl.td +++ b/clang/include/clang/Basic/arm_sve_sme_incl.td @@ -129,6 +129,7 @@ // Z: const pointer to uint64_t // Prototype modifiers added for SVE2p1 +// {: 128b vector // }: svcount_t class MergeType<int val, string suffix=""> { @@ -225,6 +226,7 @@ def IsSharedZA : FlagType<0x8000000000>; def IsPreservesZA : FlagType<0x10000000000>; def IsReadZA : FlagType<0x20000000000>; def IsWriteZA : FlagType<0x40000000000>; +def IsReductionQV : FlagType<0x80000000000>; // These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h class ImmCheckType<int val> { diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 25c76cf2ad2c..1b02087425b7 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -2896,9 +2896,11 @@ defm asm_blocks : BoolFOption<"asm-blocks", LangOpts<"AsmBlocks">, Default<fms_extensions.KeyPath>, PosFlag<SetTrue, [], [ClangOption, CC1Option]>, NegFlag<SetFalse>>; -def fms_volatile : Flag<["-"], "fms-volatile">, Group<f_Group>, - Visibility<[ClangOption, CC1Option]>, - MarshallingInfoFlag<LangOpts<"MSVolatile">>; +defm ms_volatile : BoolFOption<"ms-volatile", + LangOpts<"MSVolatile">, DefaultFalse, + PosFlag<SetTrue, [], [ClangOption, CC1Option], + "Volatile loads and stores have acquire and release semantics">, + NegFlag<SetFalse>>; def fmsc_version : Joined<["-"], "fmsc-version=">, Group<f_Group>, Visibility<[ClangOption, CLOption]>, HelpText<"Microsoft compiler version number to report in _MSC_VER (0 = don't define it (default))">; @@ -8217,7 +8219,7 @@ def _SLASH_winsysroot : CLJoinedOrSeparate<"winsysroot">, HelpText<"Same as \"/diasdkdir <dir>/DIA SDK\" /vctoolsdir <dir>/VC/Tools/MSVC/<vctoolsversion> \"/winsdkdir <dir>/Windows Kits/10\"">, MetaVarName<"<dir>">; def _SLASH_volatile_iso : Option<["/", "-"], "volatile:iso", KIND_FLAG>, - Group<_SLASH_volatile_Group>, Flags<[NoXarchOption]>, Visibility<[CLOption]>, + Visibility<[CLOption]>, Alias<fno_ms_volatile>, HelpText<"Volatile loads and stores have standard semantics">; def _SLASH_vmb : CLFlag<"vmb">, HelpText<"Use a best-case representation method for member pointers">; @@ -8232,7 +8234,7 @@ def _SLASH_vmv : CLFlag<"vmv">, HelpText<"Set the default most-general representation to " "virtual inheritance">; def _SLASH_volatile_ms : Option<["/", "-"], "volatile:ms", KIND_FLAG>, - Group<_SLASH_volatile_Group>, Flags<[NoXarchOption]>, Visibility<[CLOption]>, + Visibility<[CLOption]>, Alias<fms_volatile>, HelpText<"Volatile loads and stores have acquire and release semantics">; def _SLASH_clang : CLJoined<"clang:">, HelpText<"Pass <arg> to the clang driver">, MetaVarName<"<arg>">; diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 1d7b4c729ce8..7e89e74733a0 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -8737,7 +8737,7 @@ public: SourceLocation IILoc, bool DeducedTSTContext = true); - + bool RebuildingTypesInCurrentInstantiation = false; TypeSourceInfo *RebuildTypeInCurrentInstantiation(TypeSourceInfo *T, SourceLocation Loc, DeclarationName Name); diff --git a/clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h b/clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h index a947bd086702..276d11e80a5b 100644 --- a/clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h +++ b/clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.h @@ -409,8 +409,8 @@ AnalyzerOptions::getRegisteredCheckers(bool IncludeExperimental) { }; std::vector<StringRef> Checkers; for (StringRef CheckerName : StaticAnalyzerCheckerNames) { - if (!CheckerName.startswith("debug.") && - (IncludeExperimental || !CheckerName.startswith("alpha."))) + if (!CheckerName.starts_with("debug.") && + (IncludeExperimental || !CheckerName.starts_with("alpha."))) Checkers.push_back(CheckerName); } return Checkers; diff --git a/clang/lib/APINotes/APINotesManager.cpp b/clang/lib/APINotes/APINotesManager.cpp index ec1fb3ffa961..a921c8b9fce3 100644 --- a/clang/lib/APINotes/APINotesManager.cpp +++ b/clang/lib/APINotes/APINotesManager.cpp @@ -198,7 +198,7 @@ static void checkPrivateAPINotesName(DiagnosticsEngine &Diags, StringRef RealFileName = llvm::sys::path::filename(File->tryGetRealPathName()); StringRef RealStem = llvm::sys::path::stem(RealFileName); - if (RealStem.endswith("_private")) + if (RealStem.ends_with("_private")) return; unsigned DiagID = diag::warn_apinotes_private_case; diff --git a/clang/lib/APINotes/APINotesYAMLCompiler.cpp b/clang/lib/APINotes/APINotesYAMLCompiler.cpp index 4dfd01dae05f..57d6da7a1775 100644 --- a/clang/lib/APINotes/APINotesYAMLCompiler.cpp +++ b/clang/lib/APINotes/APINotesYAMLCompiler.cpp @@ -745,7 +745,7 @@ public: convertCommonEntity(M, MI, M.Selector); // Check if the selector ends with ':' to determine if it takes arguments. - bool takesArguments = M.Selector.endswith(":"); + bool takesArguments = M.Selector.ends_with(":"); // Split the selector into pieces. llvm::SmallVector<StringRef, 4> Args; diff --git a/clang/lib/ARCMigrate/ARCMT.cpp b/clang/lib/ARCMigrate/ARCMT.cpp index 8e398977dcd6..b410d5f3b42a 100644 --- a/clang/lib/ARCMigrate/ARCMT.cpp +++ b/clang/lib/ARCMigrate/ARCMT.cpp @@ -201,7 +201,7 @@ createInvocationForMigration(CompilerInvocation &origCI, for (std::vector<std::string>::iterator I = CInvok->getDiagnosticOpts().Warnings.begin(), E = CInvok->getDiagnosticOpts().Warnings.end(); I != E; ++I) { - if (!StringRef(*I).startswith("error")) + if (!StringRef(*I).starts_with("error")) WarnOpts.push_back(*I); } WarnOpts.push_back("error=arc-unsafe-retained-assign"); diff --git a/clang/lib/ARCMigrate/ObjCMT.cpp b/clang/lib/ARCMigrate/ObjCMT.cpp index 5a25c88c65f6..ed363a46a200 100644 --- a/clang/lib/ARCMigrate/ObjCMT.cpp +++ b/clang/lib/ARCMigrate/ObjCMT.cpp @@ -562,7 +562,7 @@ static void rewriteToObjCProperty(const ObjCMethodDecl *Getter, static bool IsCategoryNameWithDeprecatedSuffix(ObjCContainerDecl *D) { if (ObjCCategoryDecl *CatDecl = dyn_cast<ObjCCategoryDecl>(D)) { StringRef Name = CatDecl->getName(); - return Name.endswith("Deprecated"); + return Name.ends_with("Deprecated"); } return false; } @@ -1176,12 +1176,12 @@ bool ObjCMigrateASTConsumer::migrateProperty(ASTContext &Ctx, if (!SetterMethod) { // try a different naming convention for getter: isXxxxx StringRef getterNameString = getterName->getName(); - bool IsPrefix = getterNameString.startswith("is"); + bool IsPrefix = getterNameString.starts_with("is"); // Note that we don't want to change an isXXX method of retainable object // type to property (readonly or otherwise). if (IsPrefix && GRT->isObjCRetainableType()) return false; - if (IsPrefix || getterNameString.startswith("get")) { + if (IsPrefix || getterNameString.starts_with("get")) { LengthOfPrefix = (IsPrefix ? 2 : 3); const char *CGetterName = getterNameString.data() + LengthOfPrefix; // Make sure that first character after "is" or "get" prefix can @@ -1320,11 +1320,11 @@ void ObjCMigrateASTConsumer::migrateFactoryMethod(ASTContext &Ctx, if (OIT_Family == OIT_Singleton || OIT_Family == OIT_ReturnsSelf) { StringRef STRefMethodName(MethodName); size_t len = 0; - if (STRefMethodName.startswith("standard")) + if (STRefMethodName.starts_with("standard")) len = strlen("standard"); - else if (STRefMethodName.startswith("shared")) + else if (STRefMethodName.starts_with("shared")) len = strlen("shared"); - else if (STRefMethodName.startswith("default")) + else if (STRefMethodName.starts_with("default")) len = strlen("default"); else return; @@ -1341,7 +1341,7 @@ void ObjCMigrateASTConsumer::migrateFactoryMethod(ASTContext &Ctx, StringRef LoweredMethodName(MethodName); std::string StringLoweredMethodName = LoweredMethodName.lower(); LoweredMethodName = StringLoweredMethodName; - if (!LoweredMethodName.startswith(ClassNamePostfix)) + if (!LoweredMethodName.starts_with(ClassNamePostfix)) return; if (OIT_Family == OIT_ReturnsSelf) ReplaceWithClasstype(*this, OM); diff --git a/clang/lib/ARCMigrate/TransUnbridgedCasts.cpp b/clang/lib/ARCMigrate/TransUnbridgedCasts.cpp index 40220a2eef49..1e6354f71e29 100644 --- a/clang/lib/ARCMigrate/TransUnbridgedCasts.cpp +++ b/clang/lib/ARCMigrate/TransUnbridgedCasts.cpp @@ -146,7 +146,7 @@ private: ento::cocoa::isRefType(E->getSubExpr()->getType(), "CF", FD->getIdentifier()->getName())) { StringRef fname = FD->getIdentifier()->getName(); - if (fname.endswith("Retain") || fname.contains("Create") || + if (fname.ends_with("Retain") || fname.contains("Create") || fname.contains("Copy")) { // Do not migrate to couple of bridge transfer casts which // cancel each other out. Leave it unchanged so error gets user diff --git a/clang/lib/ARCMigrate/TransformActions.cpp b/clang/lib/ARCMigrate/TransformActions.cpp index bd5c79356867..6bc6fed1a903 100644 --- a/clang/lib/ARCMigrate/TransformActions.cpp +++ b/clang/lib/ARCMigrate/TransformActions.cpp @@ -431,7 +431,7 @@ bool TransformActionsImpl::canReplaceText(SourceLocation loc, StringRef text) { if (invalidTemp) return false; - return file.substr(locInfo.second).startswith(text); + return file.substr(locInfo.second).starts_with(text); } void TransformActionsImpl::commitInsert(SourceLocation loc, StringRef text) { diff --git a/clang/lib/ARCMigrate/Transforms.cpp b/clang/lib/ARCMigrate/Transforms.cpp index 90b2b32b6b1b..2808e35135dc 100644 --- a/clang/lib/ARCMigrate/Transforms.cpp +++ b/clang/lib/ARCMigrate/Transforms.cpp @@ -95,7 +95,7 @@ bool trans::isPlusOne(const Expr *E) { ento::cocoa::isRefType(callE->getType(), "CF", FD->getIdentifier()->getName())) { StringRef fname = FD->getIdentifier()->getName(); - if (fname.endswith("Retain") || fname.contains("Create") || + if (fname.ends_with("Retain") || fname.contains("Create") || fname.contains("Copy")) return true; } diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index e877f903b34c..0395b3e47ab6 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -8223,7 +8223,7 @@ void ASTContext::getObjCEncodingForTypeImpl(QualType T, std::string &S, // Another legacy compatibility encoding. Some ObjC qualifier and type // combinations need to be rearranged. // Rewrite "in const" from "nr" to "rn" - if (StringRef(S).endswith("nr")) + if (StringRef(S).ends_with("nr")) S.replace(S.end()-2, S.end(), "rn"); } @@ -13519,7 +13519,7 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap, Target->getTargetOpts().FeaturesAsWritten.begin(), Target->getTargetOpts().FeaturesAsWritten.end()); } else { - if (VersionStr.startswith("arch=")) + if (VersionStr.starts_with("arch=")) TargetCPU = VersionStr.drop_front(sizeof("arch=") - 1); else if (VersionStr != "default") Features.push_back((StringRef{"+"} + VersionStr).str()); diff --git a/clang/lib/AST/DeclPrinter.cpp b/clang/lib/AST/DeclPrinter.cpp index 30a26d518386..24da6f2ef32b 100644 --- a/clang/lib/AST/DeclPrinter.cpp +++ b/clang/lib/AST/DeclPrinter.cpp @@ -1728,7 +1728,7 @@ void DeclPrinter::VisitObjCPropertyDecl(ObjCPropertyDecl *PDecl) { std::string TypeStr = PDecl->getASTContext().getUnqualifiedObjCPointerType(T). getAsString(Policy); Out << ' ' << TypeStr; - if (!StringRef(TypeStr).endswith("*")) + if (!StringRef(TypeStr).ends_with("*")) Out << ' '; Out << *PDecl; if (Policy.PolishForDeclaration) diff --git a/clang/lib/AST/Interp/Interp.cpp b/clang/lib/AST/Interp/Interp.cpp index 13b77e9a8772..a82d1c3c7c62 100644 --- a/clang/lib/AST/Interp/Interp.cpp +++ b/clang/lib/AST/Interp/Interp.cpp @@ -350,11 +350,6 @@ bool CheckCallable(InterpState &S, CodePtr OpPC, const Function *F) { } if (!F->isConstexpr()) { - // Don't emit anything if we're checking for a potential constant - // expression. That will happen later when actually executing. - if (S.checkingPotentialConstantExpression()) - return false; - const SourceLocation &Loc = S.Current->getLocation(OpPC); if (S.getLangOpts().CPlusPlus11) { const FunctionDecl *DiagDecl = F->getDecl(); @@ -371,13 +366,21 @@ bool CheckCallable(InterpState &S, CodePtr OpPC, const Function *F) { // FIXME: If DiagDecl is an implicitly-declared special member function // or an inheriting constructor, we should be much more explicit about why // it's not constexpr. - if (CD && CD->isInheritingConstructor()) + if (CD && CD->isInheritingConstructor()) { S.FFDiag(Loc, diag::note_constexpr_invalid_inhctor, 1) << CD->getInheritedConstructor().getConstructor()->getParent(); - else + S.Note(DiagDecl->getLocation(), diag::note_declared_at); + } else { + // Don't emit anything if the function isn't defined and we're checking + // for a constant expression. It might be defined at the point we're + // actually calling it. + if (!DiagDecl->isDefined() && S.checkingPotentialConstantExpression()) + return false; + S.FFDiag(Loc, diag::note_constexpr_invalid_function, 1) << DiagDecl->isConstexpr() << (bool)CD << DiagDecl; - S.Note(DiagDecl->getLocation(), diag::note_declared_at); + S.Note(DiagDecl->getLocation(), diag::note_declared_at); + } } else { S.FFDiag(Loc, diag::note_invalid_subexpr_in_const_expr); } diff --git a/clang/lib/AST/Mangle.cpp b/clang/lib/AST/Mangle.cpp index 64c971912a91..d3a6b61fd2be 100644 --- a/clang/lib/AST/Mangle.cpp +++ b/clang/lib/AST/Mangle.cpp @@ -147,7 +147,7 @@ void MangleContext::mangleName(GlobalDecl GD, raw_ostream &Out) { // If the label isn't literal, or if this is an alias for an LLVM intrinsic, // do not add a "\01" prefix. - if (!ALA->getIsLiteralLabel() || ALA->getLabel().startswith("llvm.")) { + if (!ALA->getIsLiteralLabel() || ALA->getLabel().starts_with("llvm.")) { Out << ALA->getLabel(); return; } diff --git a/clang/lib/AST/MicrosoftMangle.cpp b/clang/lib/AST/MicrosoftMangle.cpp index c59a66e103a6..8346ad87b409 100644 --- a/clang/lib/AST/MicrosoftMangle.cpp +++ b/clang/lib/AST/MicrosoftMangle.cpp @@ -63,7 +63,7 @@ struct msvc_hashing_ostream : public llvm::raw_svector_ostream { : llvm::raw_svector_ostream(Buffer), OS(OS) {} ~msvc_hashing_ostream() override { StringRef MangledName = str(); - bool StartsWithEscape = MangledName.startswith("\01"); + bool StartsWithEscape = MangledName.starts_with("\01"); if (StartsWithEscape) MangledName = MangledName.drop_front(1); if (MangledName.size() < 4096) { diff --git a/clang/lib/AST/PrintfFormatString.cpp b/clang/lib/AST/PrintfFormatString.cpp index f0b9d0ecaf23..3b09ca40bd2a 100644 --- a/clang/lib/AST/PrintfFormatString.cpp +++ b/clang/lib/AST/PrintfFormatString.cpp @@ -140,7 +140,7 @@ static PrintfSpecifierResult ParsePrintfSpecifier(FormatStringHandler &H, // Set the privacy flag if the privacy annotation in the // comma-delimited segment is at least as strict as the privacy // annotations in previous comma-delimited segments. - if (MatchedStr.startswith("mask")) { + if (MatchedStr.starts_with("mask")) { StringRef MaskType = MatchedStr.substr(sizeof("mask.") - 1); unsigned Size = MaskType.size(); if (Warn && (Size == 0 || Size > 8)) diff --git a/clang/lib/AST/RawCommentList.cpp b/clang/lib/AST/RawCommentList.cpp index c3beb2322888..dffa007b6588 100644 --- a/clang/lib/AST/RawCommentList.cpp +++ b/clang/lib/AST/RawCommentList.cpp @@ -141,8 +141,8 @@ RawComment::RawComment(const SourceManager &SourceMgr, SourceRange SR, Kind = K.first; IsTrailingComment |= K.second; - IsAlmostTrailingComment = RawText.startswith("//<") || - RawText.startswith("/*<"); + IsAlmostTrailingComment = + RawText.starts_with("//<") || RawText.starts_with("/*<"); } else { Kind = RCK_Merged; IsTrailingComment = diff --git a/clang/lib/AST/Stmt.cpp b/clang/lib/AST/Stmt.cpp index c31fb48a2add..afd05881cb16 100644 --- a/clang/lib/AST/Stmt.cpp +++ b/clang/lib/AST/Stmt.cpp @@ -811,11 +811,12 @@ std::string MSAsmStmt::generateAsmString(const ASTContext &C) const { StringRef Instruction = Pieces[I]; // For vex/vex2/vex3/evex masm style prefix, convert it to att style // since we don't support masm style prefix in backend. - if (Instruction.startswith("vex ")) + if (Instruction.starts_with("vex ")) MSAsmString += '{' + Instruction.substr(0, 3).str() + '}' + Instruction.substr(3).str(); - else if (Instruction.startswith("vex2 ") || - Instruction.startswith("vex3 ") || Instruction.startswith("evex ")) + else if (Instruction.starts_with("vex2 ") || + Instruction.starts_with("vex3 ") || + Instruction.starts_with("evex ")) MSAsmString += '{' + Instruction.substr(0, 4).str() + '}' + Instruction.substr(4).str(); else diff --git a/clang/lib/ASTMatchers/ASTMatchersInternal.cpp b/clang/lib/ASTMatchers/ASTMatchersInternal.cpp index 435bbdeda220..8ed213ca2ce0 100644 --- a/clang/lib/ASTMatchers/ASTMatchersInternal.cpp +++ b/clang/lib/ASTMatchers/ASTMatchersInternal.cpp @@ -480,11 +480,11 @@ HasNameMatcher::HasNameMatcher(std::vector<std::string> N) static bool consumeNameSuffix(StringRef &FullName, StringRef Suffix) { StringRef Name = FullName; - if (!Name.endswith(Suffix)) + if (!Name.ends_with(Suffix)) return false; Name = Name.drop_back(Suffix.size()); if (!Name.empty()) { - if (!Name.endswith("::")) + if (!Name.ends_with("::")) return false; Name = Name.drop_back(2); } @@ -530,7 +530,7 @@ public: PatternSet(ArrayRef<std::string> Names) { Patterns.reserve(Names.size()); for (StringRef Name : Names) - Patterns.push_back({Name, Name.startswith("::")}); + Patterns.push_back({Name, Name.starts_with("::")}); } /// Consumes the name suffix from each pattern in the set and removes the ones @@ -652,11 +652,11 @@ bool HasNameMatcher::matchesNodeFullSlow(const NamedDecl &Node) const { const StringRef FullName = OS.str(); for (const StringRef Pattern : Names) { - if (Pattern.startswith("::")) { + if (Pattern.starts_with("::")) { if (FullName == Pattern) return true; - } else if (FullName.endswith(Pattern) && - FullName.drop_back(Pattern.size()).endswith("::")) { + } else if (FullName.ends_with(Pattern) && + FullName.drop_back(Pattern.size()).ends_with("::")) { return true; } } diff --git a/clang/lib/ASTMatchers/Dynamic/Parser.cpp b/clang/lib/ASTMatchers/Dynamic/Parser.cpp index 33a10fe838a6..27096a83b8dd 100644 --- a/clang/lib/ASTMatchers/Dynamic/Parser.cpp +++ b/clang/lib/ASTMatchers/Dynamic/Parser.cpp @@ -187,10 +187,10 @@ private: break; ++TokenLength; } - if (TokenLength == 4 && Code.startswith("true")) { + if (TokenLength == 4 && Code.starts_with("true")) { Result.Kind = TokenInfo::TK_Literal; Result.Value = true; - } else if (TokenLength == 5 && Code.startswith("false")) { + } else if (TokenLength == 5 && Code.starts_with("false")) { Result.Kind = TokenInfo::TK_Literal; Result.Value = false; } else { @@ -737,7 +737,7 @@ bool Parser::parseMatcherExpressionImpl(const TokenInfo &NameToken, // Completions minus the prefix. void Parser::addCompletion(const TokenInfo &CompToken, const MatcherCompletion& Completion) { - if (StringRef(Completion.TypedText).startswith(CompToken.Text) && + if (StringRef(Completion.TypedText).starts_with(CompToken.Text) && Completion.Specificity > 0) { Completions.emplace_back(Completion.TypedText.substr(CompToken.Text.size()), Completion.MatcherDecl, Completion.Specificity); diff --git a/clang/lib/Analysis/BodyFarm.cpp b/clang/lib/Analysis/BodyFarm.cpp index 13ec9b65c9f0..127e843d4ead 100644 --- a/clang/lib/Analysis/BodyFarm.cpp +++ b/clang/lib/Analysis/BodyFarm.cpp @@ -726,8 +726,8 @@ Stmt *BodyFarm::getBody(const FunctionDecl *D) { FF = nullptr; break; } - } else if (Name.startswith("OSAtomicCompareAndSwap") || - Name.startswith("objc_atomicCompareAndSwap")) { + } else if (Name.starts_with("OSAtomicCompareAndSwap") || + Name.starts_with("objc_atomicCompareAndSwap")) { FF = create_OSAtomicCompareAndSwap; } else if (Name == "call_once" && D->getDeclContext()->isStdNamespace()) { FF = create_call_once; diff --git a/clang/lib/Analysis/CallGraph.cpp b/clang/lib/Analysis/CallGraph.cpp index 59cc939b6fd1..f892980ed313 100644 --- a/clang/lib/Analysis/CallGraph.cpp +++ b/clang/lib/Analysis/CallGraph.cpp @@ -168,7 +168,7 @@ bool CallGraph::includeCalleeInGraph(const Decl *D) { return false; IdentifierInfo *II = FD->getIdentifier(); - if (II && II->getName().startswith("__inline")) + if (II && II->getName().starts_with("__inline")) return false; } diff --git a/clang/lib/Analysis/CalledOnceCheck.cpp b/clang/lib/Analysis/CalledOnceCheck.cpp index 5b4fc24b6f0e..04c5f6aa9c74 100644 --- a/clang/lib/Analysis/CalledOnceCheck.cpp +++ b/clang/lib/Analysis/CalledOnceCheck.cpp @@ -973,7 +973,7 @@ private: /// Return true if the given name has conventional suffixes. static bool hasConventionalSuffix(llvm::StringRef Name) { return llvm::any_of(CONVENTIONAL_SUFFIXES, [Name](llvm::StringRef Suffix) { - return Name.endswith(Suffix); + return Name.ends_with(Suffix); }); } diff --git a/clang/lib/Analysis/CocoaConventions.cpp b/clang/lib/Analysis/CocoaConventions.cpp index 571d72e1a841..836859c22345 100644 --- a/clang/lib/Analysis/CocoaConventions.cpp +++ b/clang/lib/Analysis/CocoaConventions.cpp @@ -26,10 +26,10 @@ bool cocoa::isRefType(QualType RetTy, StringRef Prefix, // Recursively walk the typedef stack, allowing typedefs of reference types. while (const TypedefType *TD = RetTy->getAs<TypedefType>()) { StringRef TDName = TD->getDecl()->getIdentifier()->getName(); - if (TDName.startswith(Prefix) && TDName.endswith("Ref")) + if (TDName.starts_with(Prefix) && TDName.ends_with("Ref")) return true; // XPC unfortunately uses CF-style function names, but aren't CF types. - if (TDName.startswith("xpc_")) + if (TDName.starts_with("xpc_")) return false; RetTy = TD->getDecl()->getUnderlyingType(); } @@ -43,7 +43,7 @@ bool cocoa::isRefType(QualType RetTy, StringRef Prefix, return false; // Does the name start with the prefix? - return Name.startswith(Prefix); + return Name.starts_with(Prefix); } /// Returns true when the passed-in type is a CF-style reference-counted @@ -127,10 +127,9 @@ bool coreFoundation::followsCreateRule(const FunctionDecl *fn) { // Scan for *lowercase* 'reate' or 'opy', followed by no lowercase // character. StringRef suffix = functionName.substr(it - start); - if (suffix.startswith("reate")) { + if (suffix.starts_with("reate")) { it += 5; - } - else if (suffix.startswith("opy")) { + } else if (suffix.starts_with("opy")) { it += 3; } else { // Keep scanning. diff --git a/clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp b/clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp index f49087ababc4..5ac71e1d6bf6 100644 --- a/clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp +++ b/clang/lib/Analysis/FlowSensitive/Models/ChromiumCheckModel.cpp @@ -43,7 +43,7 @@ bool isCheckLikeMethod(llvm::SmallDenseSet<const CXXMethodDecl *> &CheckDecls, return false; for (const CXXMethodDecl *M : ParentClass->methods()) - if (M->getDeclName().isIdentifier() && M->getName().endswith("Check")) + if (M->getDeclName().isIdentifier() && M->getName().ends_with("Check")) CheckDecls.insert(M); } diff --git a/clang/lib/Analysis/RetainSummaryManager.cpp b/clang/lib/Analysis/RetainSummaryManager.cpp index 4cbeb0c35b6f..6f50d95b179f 100644 --- a/clang/lib/Analysis/RetainSummaryManager.cpp +++ b/clang/lib/Analysis/RetainSummaryManager.cpp @@ -174,7 +174,7 @@ static bool isOSObjectPtr(QualType QT) { } static bool isISLObjectRef(QualType Ty) { - return StringRef(Ty.getAsString()).startswith("isl_"); + return StringRef(Ty.getAsString()).starts_with("isl_"); } static bool isOSIteratorSubclass(const Decl *D) { @@ -255,13 +255,13 @@ RetainSummaryManager::getSummaryForOSObject(const FunctionDecl *FD, // TODO: Add support for the slightly common *Matching(table) idiom. // Cf. IOService::nameMatching() etc. - these function have an unusual // contract of returning at +0 or +1 depending on their last argument. - if (FName.endswith("Matching")) { + if (FName.ends_with("Matching")) { return getPersistentStopSummary(); } // All objects returned with functions *not* starting with 'get', // or iterators, are returned at +1. - if ((!FName.startswith("get") && !FName.startswith("Get")) || + if ((!FName.starts_with("get") && !FName.starts_with("Get")) || isOSIteratorSubclass(PD)) { return getOSSummaryCreateRule(FD); } else { @@ -392,9 +392,9 @@ const RetainSummary *RetainSummaryManager::getSummaryForObjCOrCFObject( return getPersistentSummary(RetEffect::MakeNoRet(), ScratchArgs, ArgEffect(DoNothing), ArgEffect(DoNothing)); - } else if (FName.startswith("NSLog")) { + } else if (FName.starts_with("NSLog")) { return getDoNothingSummary(); - } else if (FName.startswith("NS") && FName.contains("Insert")) { + } else if (FName.starts_with("NS") && FName.contains("Insert")) { // Allowlist NSXXInsertXX, for example NSMapInsertIfAbsent, since they can // be deallocated by NSMapRemove. ScratchArgs = AF.add(ScratchArgs, 1, ArgEffect(StopTracking)); @@ -453,9 +453,9 @@ const RetainSummary *RetainSummaryManager::getSummaryForObjCOrCFObject( // Check for release functions, the only kind of functions that we care // about that don't return a pointer type. - if (FName.startswith("CG") || FName.startswith("CF")) { + if (FName.starts_with("CG") || FName.starts_with("CF")) { // Test for 'CGCF'. - FName = FName.substr(FName.startswith("CGCF") ? 4 : 2); + FName = FName.substr(FName.starts_with("CGCF") ? 4 : 2); if (isRelease(FD, FName)) return getUnarySummary(FT, DecRef); diff --git a/clang/lib/Basic/Attributes.cpp b/clang/lib/Basic/Attributes.cpp index bb495216ca93..44a4f1890d39 100644 --- a/clang/lib/Basic/Attributes.cpp +++ b/clang/lib/Basic/Attributes.cpp @@ -33,7 +33,7 @@ int clang::hasAttribute(AttributeCommonInfo::Syntax Syntax, const TargetInfo &Target, const LangOptions &LangOpts) { StringRef Name = Attr->getName(); // Normalize the attribute name, __foo__ becomes foo. - if (Name.size() >= 4 && Name.startswith("__") && Name.endswith("__")) + if (Name.size() >= 4 && Name.starts_with("__") && Name.ends_with("__")) Name = Name.substr(2, Name.size() - 4); // Normalize the scope name, but only for gnu and clang attributes. @@ -103,8 +103,8 @@ static StringRef normalizeAttrName(const IdentifierInfo *Name, (NormalizedScopeName.empty() || NormalizedScopeName == "gnu" || NormalizedScopeName == "clang")); StringRef AttrName = Name->getName(); - if (ShouldNormalize && AttrName.size() >= 4 && AttrName.startswith("__") && - AttrName.endswith("__")) + if (ShouldNormalize && AttrName.size() >= 4 && AttrName.starts_with("__") && + AttrName.ends_with("__")) AttrName = AttrName.slice(2, AttrName.size() - 2); return AttrName; diff --git a/clang/lib/Basic/DiagnosticIDs.cpp b/clang/lib/Basic/DiagnosticIDs.cpp index e5667d57f8cf..6c7bd50eefb7 100644 --- a/clang/lib/Basic/DiagnosticIDs.cpp +++ b/clang/lib/Basic/DiagnosticIDs.cpp @@ -853,5 +853,5 @@ bool DiagnosticIDs::isUnrecoverable(unsigned DiagID) const { bool DiagnosticIDs::isARCDiagnostic(unsigned DiagID) { unsigned cat = getCategoryNumberForDiag(DiagID); - return DiagnosticIDs::getCategoryNameFromID(cat).startswith("ARC "); + return DiagnosticIDs::getCategoryNameFromID(cat).starts_with("ARC "); } diff --git a/clang/lib/Basic/IdentifierTable.cpp b/clang/lib/Basic/IdentifierTable.cpp index 38150d1640d7..5902c6dc3ce0 100644 --- a/clang/lib/Basic/IdentifierTable.cpp +++ b/clang/lib/Basic/IdentifierTable.cpp @@ -604,7 +604,7 @@ LLVM_DUMP_METHOD void Selector::dump() const { print(llvm::errs()); } static bool startsWithWord(StringRef name, StringRef word) { if (name.size() < word.size()) return false; return ((name.size() == word.size() || !isLowercase(name[word.size()])) && - name.startswith(word)); + name.starts_with(word)); } ObjCMethodFamily Selector::getMethodFamilyImpl(Selector sel) { @@ -742,7 +742,7 @@ SelectorTable::constructSetterSelector(IdentifierTable &Idents, std::string SelectorTable::getPropertyNameFromSetterSelector(Selector Sel) { StringRef Name = Sel.getNameForSlot(0); - assert(Name.startswith("set") && "invalid setter name"); + assert(Name.starts_with("set") && "invalid setter name"); return (Twine(toLowercase(Name[3])) + Name.drop_front(4)).str(); } diff --git a/clang/lib/Basic/Module.cpp b/clang/lib/Basic/Module.cpp index 7523e509a471..925217431d4d 100644 --- a/clang/lib/Basic/Module.cpp +++ b/clang/lib/Basic/Module.cpp @@ -166,7 +166,8 @@ bool Module::isForBuilding(const LangOptions &LangOpts) const { // for either. if (!LangOpts.isCompilingModule() && getTopLevelModule()->IsFramework && CurrentModule == LangOpts.ModuleName && - !CurrentModule.endswith("_Private") && TopLevelName.endswith("_Private")) + !CurrentModule.ends_with("_Private") && + TopLevelName.ends_with("_Private")) TopLevelName = TopLevelName.drop_back(8); return TopLevelName == CurrentModule; diff --git a/clang/lib/Basic/Sarif.cpp b/clang/lib/Basic/Sarif.cpp index 3476103cc39d..1cae7b937bc6 100644 --- a/clang/lib/Basic/Sarif.cpp +++ b/clang/lib/Basic/Sarif.cpp @@ -74,7 +74,7 @@ static std::string fileNameToURI(StringRef Filename) { // Get the root name to see if it has a URI authority. StringRef Root = sys::path::root_name(Filename); - if (Root.startswith("//")) { + if (Root.starts_with("//")) { // There is an authority, so add it to the URI. Ret += Root.drop_front(2).str(); } else if (!Root.empty()) { diff --git a/clang/lib/Basic/TargetInfo.cpp b/clang/lib/Basic/TargetInfo.cpp index 6cd5d618a4ac..96b3ad9ba2f2 100644 --- a/clang/lib/Basic/TargetInfo.cpp +++ b/clang/lib/Basic/TargetInfo.cpp @@ -551,26 +551,26 @@ ParsedTargetAttr TargetInfo::parseTargetAttr(StringRef Features) const { // TODO: Support the fpmath option. It will require checking // overall feature validity for the function with the rest of the // attributes on the function. - if (Feature.startswith("fpmath=")) + if (Feature.starts_with("fpmath=")) continue; - if (Feature.startswith("branch-protection=")) { + if (Feature.starts_with("branch-protection=")) { Ret.BranchProtection = Feature.split('=').second.trim(); continue; } // While we're here iterating check for a different target cpu. - if (Feature.startswith("arch=")) { + if (Feature.starts_with("arch=")) { if (!Ret.CPU.empty()) Ret.Duplicate = "arch="; else Ret.CPU = Feature.split("=").second.trim(); - } else if (Feature.startswith("tune=")) { + } else if (Feature.starts_with("tune=")) { if (!Ret.Tune.empty()) Ret.Duplicate = "tune="; else Ret.Tune = Feature.split("=").second.trim(); - } else if (Feature.startswith("no-")) + } else if (Feature.starts_with("no-")) Ret.Features.push_back("-" + Feature.split("-").second.str()); else Ret.Features.push_back("+" + Feature.str()); diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index e3e08b571667..def16c032c86 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -1062,7 +1062,7 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const { else // Pushing the original feature string to give a sema error later on // when they get checked. - if (Feature.startswith("no")) + if (Feature.starts_with("no")) Features.push_back("-" + Feature.drop_front(2).str()); else Features.push_back("+" + Feature.str()); @@ -1071,15 +1071,15 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const { for (auto &Feature : AttrFeatures) { Feature = Feature.trim(); - if (Feature.startswith("fpmath=")) + if (Feature.starts_with("fpmath=")) continue; - if (Feature.startswith("branch-protection=")) { + if (Feature.starts_with("branch-protection=")) { Ret.BranchProtection = Feature.split('=').second.trim(); continue; } - if (Feature.startswith("arch=")) { + if (Feature.starts_with("arch=")) { if (FoundArch) Ret.Duplicate = "arch="; FoundArch = true; @@ -1095,7 +1095,7 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const { Ret.Features.push_back(AI->ArchFeature.str()); // Add any extra features, after the + SplitAndAddFeatures(Split.second, Ret.Features); - } else if (Feature.startswith("cpu=")) { + } else if (Feature.starts_with("cpu=")) { if (!Ret.CPU.empty()) Ret.Duplicate = "cpu="; else { @@ -1106,14 +1106,14 @@ ParsedTargetAttr AArch64TargetInfo::parseTargetAttr(StringRef Features) const { Ret.CPU = Split.first; SplitAndAddFeatures(Split.second, Ret.Features); } - } else if (Feature.startswith("tune=")) { + } else if (Feature.starts_with("tune=")) { if (!Ret.Tune.empty()) Ret.Duplicate = "tune="; else Ret.Tune = Feature.split("=").second.trim(); - } else if (Feature.startswith("+")) { + } else if (Feature.starts_with("+")) { SplitAndAddFeatures(Feature, Ret.Features); - } else if (Feature.startswith("no-")) { + } else if (Feature.starts_with("no-")) { StringRef FeatureName = llvm::AArch64::getArchExtFeature(Feature.split("-").second); if (!FeatureName.empty()) diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp b/clang/lib/Basic/Targets/AMDGPU.cpp index 719fc51bfc28..b064ec2b3c9a 100644 --- a/clang/lib/Basic/Targets/AMDGPU.cpp +++ b/clang/lib/Basic/Targets/AMDGPU.cpp @@ -279,7 +279,7 @@ void AMDGPUTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro(Twine("__") + Twine(CanonName) + Twine("__")); // Emit macros for gfx family e.g. gfx906 -> __GFX9__, gfx1030 -> __GFX10___ if (isAMDGCN(getTriple())) { - assert(CanonName.startswith("gfx") && "Invalid amdgcn canonical name"); + assert(CanonName.starts_with("gfx") && "Invalid amdgcn canonical name"); Builder.defineMacro(Twine("__") + Twine(CanonName.drop_back(2).upper()) + Twine("__")); } diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp index bc90d1b93d53..3a65f53c5248 100644 --- a/clang/lib/Basic/Targets/Mips.cpp +++ b/clang/lib/Basic/Targets/Mips.cpp @@ -196,7 +196,7 @@ void MipsTargetInfo::getTargetDefines(const LangOptions &Opts, else Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); - if (StringRef(CPU).startswith("octeon")) + if (StringRef(CPU).starts_with("octeon")) Builder.defineMacro("__OCTEON__"); if (CPU != "mips1") { diff --git a/clang/lib/Basic/Targets/NVPTX.cpp b/clang/lib/Basic/Targets/NVPTX.cpp index 5c601812f617..c0b5db795e27 100644 --- a/clang/lib/Basic/Targets/NVPTX.cpp +++ b/clang/lib/Basic/Targets/NVPTX.cpp @@ -42,7 +42,7 @@ NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple, PTXVersion = 32; for (const StringRef Feature : Opts.FeaturesAsWritten) { int PTXV; - if (!Feature.startswith("+ptx") || + if (!Feature.starts_with("+ptx") || Feature.drop_front(4).getAsInteger(10, PTXV)) continue; PTXVersion = PTXV; // TODO: should it be max(PTXVersion, PTXV)? diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index 45d23022b530..60a4e0ed69c3 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -434,14 +434,14 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const { Feature = Feature.trim(); StringRef AttrString = Feature.split("=").second.trim(); - if (Feature.startswith("arch=")) { + if (Feature.starts_with("arch=")) { // Override last features Ret.Features.clear(); if (FoundArch) Ret.Duplicate = "arch="; FoundArch = true; - if (AttrString.startswith("+")) { + if (AttrString.starts_with("+")) { // EXTENSION like arch=+v,+zbb SmallVector<StringRef, 1> Exts; AttrString.split(Exts, ","); @@ -461,7 +461,7 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const { // full-arch-string like arch=rv64gcv handleFullArchString(AttrString, Ret.Features); } - } else if (Feature.startswith("cpu=")) { + } else if (Feature.starts_with("cpu=")) { if (!Ret.CPU.empty()) Ret.Duplicate = "cpu="; @@ -475,7 +475,7 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const { handleFullArchString(MarchFromCPU, Ret.Features); } } - } else if (Feature.startswith("tune=")) { + } else if (Feature.starts_with("tune=")) { if (!Ret.Tune.empty()) Ret.Duplicate = "tune="; diff --git a/clang/lib/Basic/Warnings.cpp b/clang/lib/Basic/Warnings.cpp index cc8c138233ca..cb23d844ef8f 100644 --- a/clang/lib/Basic/Warnings.cpp +++ b/clang/lib/Basic/Warnings.cpp @@ -97,7 +97,7 @@ void clang::ProcessWarningOptions(DiagnosticsEngine &Diags, // Check to see if this warning starts with "no-", if so, this is a // negative form of the option. bool isPositive = true; - if (Opt.startswith("no-")) { + if (Opt.starts_with("no-")) { isPositive = false; Opt = Opt.substr(3); } @@ -133,7 +133,7 @@ void clang::ProcessWarningOptions(DiagnosticsEngine &Diags, // table. It also has the "specifier" form of -Werror=foo. GCC supports // the deprecated -Werror-implicit-function-declaration which is used by // a few projects. - if (Opt.startswith("error")) { + if (Opt.starts_with("error")) { StringRef Specifier; if (Opt.size() > 5) { // Specifier must be present. if (Opt[5] != '=' && @@ -162,7 +162,7 @@ void clang::ProcessWarningOptions(DiagnosticsEngine &Diags, } // -Wfatal-errors is yet another special case. - if (Opt.startswith("fatal-errors")) { + if (Opt.starts_with("fatal-errors")) { StringRef Specifier; if (Opt.size() != 12) { if ((Opt[12] != '=' && Opt[12] != '-') || Opt.size() == 13) { @@ -204,7 +204,7 @@ void clang::ProcessWarningOptions(DiagnosticsEngine &Diags, // Check to see if this warning starts with "no-", if so, this is a // negative form of the option. - bool IsPositive = !Opt.startswith("no-"); + bool IsPositive = !Opt.starts_with("no-"); if (!IsPositive) Opt = Opt.substr(3); auto Severity = IsPositive ? diag::Severity::Remark diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 83d0a72aac54..353b7930b3c1 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -9985,6 +9985,10 @@ CodeGenFunction::getSVEOverloadTypes(const SVETypeFlags &TypeFlags, if (TypeFlags.isOverloadCvt()) return {Ops[0]->getType(), Ops.back()->getType()}; + if (TypeFlags.isReductionQV() && !ResultType->isScalableTy() && + ResultType->isVectorTy()) + return {ResultType, Ops[1]->getType()}; + assert(TypeFlags.isOverloadDefault() && "Unexpected value for overloads"); return {DefaultType}; } diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index a24aeea7ae32..51a43b5f85b3 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -5609,7 +5609,7 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, EmitBlock(Cont); } if (CI->getCalledFunction() && CI->getCalledFunction()->hasName() && - CI->getCalledFunction()->getName().startswith("_Z4sqrt")) { + CI->getCalledFunction()->getName().starts_with("_Z4sqrt")) { SetSqrtFPAccuracy(CI); } if (callOrInvoke) diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp index 37d7a6755d39..236d53bee4e8 100644 --- a/clang/lib/CodeGen/CGDebugInfo.cpp +++ b/clang/lib/CodeGen/CGDebugInfo.cpp @@ -637,7 +637,8 @@ void CGDebugInfo::CreateCompileUnit() { Sysroot = CGM.getHeaderSearchOpts().Sysroot; auto B = llvm::sys::path::rbegin(Sysroot); auto E = llvm::sys::path::rend(Sysroot); - auto It = std::find_if(B, E, [](auto SDK) { return SDK.endswith(".sdk"); }); + auto It = + std::find_if(B, E, [](auto SDK) { return SDK.ends_with(".sdk"); }); if (It != E) SDK = *It; } @@ -2885,7 +2886,7 @@ llvm::DIModule *CGDebugInfo::getOrCreateModuleRef(ASTSourceDescriptor Mod, // clang::Module object, but it won't actually be built or imported; it will // be textual. if (CreateSkeletonCU && IsRootModule && Mod.getASTFile().empty() && M) - assert(StringRef(M->Name).startswith(CGM.getLangOpts().ModuleName) && + assert(StringRef(M->Name).starts_with(CGM.getLangOpts().ModuleName) && "clang module without ASTFile must be specified by -fmodule-name"); // Return a StringRef to the remapped Path. @@ -4249,7 +4250,7 @@ void CGDebugInfo::emitFunctionStart(GlobalDecl GD, SourceLocation Loc, Flags |= llvm::DINode::FlagPrototyped; } - if (Name.startswith("\01")) + if (Name.starts_with("\01")) Name = Name.substr(1); assert((!D || !isa<VarDecl>(D) || diff --git a/clang/lib/CodeGen/CGException.cpp b/clang/lib/CodeGen/CGException.cpp index bae8babb8efe..0d507da5c1ba 100644 --- a/clang/lib/CodeGen/CGException.cpp +++ b/clang/lib/CodeGen/CGException.cpp @@ -277,7 +277,7 @@ static bool LandingPadHasOnlyCXXUses(llvm::LandingPadInst *LPI) { if (llvm::GlobalVariable *GV = dyn_cast<llvm::GlobalVariable>(Val)) // ObjC EH selector entries are always global variables with // names starting like this. - if (GV->getName().startswith("OBJC_EHTYPE")) + if (GV->getName().starts_with("OBJC_EHTYPE")) return false; } else { // Check if any of the filter values have the ObjC prefix. @@ -288,7 +288,7 @@ static bool LandingPadHasOnlyCXXUses(llvm::LandingPadInst *LPI) { cast<llvm::GlobalVariable>((*II)->stripPointerCasts())) // ObjC EH selector entries are always global variables with // names starting like this. - if (GV->getName().startswith("OBJC_EHTYPE")) + if (GV->getName().starts_with("OBJC_EHTYPE")) return false; } } @@ -1917,7 +1917,7 @@ void CodeGenFunction::EmitCapturedLocals(CodeGenFunction &ParentCGF, const VarDecl *D = cast<VarDecl>(I.first); if (isa<ImplicitParamDecl>(D) && D->getType() == getContext().VoidPtrTy) { - assert(D->getName().startswith("frame_pointer")); + assert(D->getName().starts_with("frame_pointer")); FramePtrAddrAlloca = cast<llvm::AllocaInst>(I.second.getPointer()); break; } diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index 69cf7f76be9a..ed9aaa28c257 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -431,7 +431,7 @@ static Address createReferenceTemporary(CodeGenFunction &CGF, /// Helper method to check if the underlying ABI is AAPCS static bool isAAPCS(const TargetInfo &TargetInfo) { - return TargetInfo.getABI().startswith("aapcs"); + return TargetInfo.getABI().starts_with("aapcs"); } LValue CodeGenFunction:: @@ -3156,7 +3156,7 @@ LValue CodeGenFunction::EmitPredefinedLValue(const PredefinedExpr *E) { auto SL = E->getFunctionName(); assert(SL != nullptr && "No StringLiteral name in PredefinedExpr"); StringRef FnName = CurFn->getName(); - if (FnName.startswith("\01")) + if (FnName.starts_with("\01")) FnName = FnName.substr(1); StringRef NameItems[] = { PredefinedExpr::getIdentKindName(E->getIdentKind()), FnName}; diff --git a/clang/lib/CodeGen/CGObjCMac.cpp b/clang/lib/CodeGen/CGObjCMac.cpp index ba52b23be018..517f7cddebc1 100644 --- a/clang/lib/CodeGen/CGObjCMac.cpp +++ b/clang/lib/CodeGen/CGObjCMac.cpp @@ -1850,7 +1850,7 @@ static bool hasObjCExceptionAttribute(ASTContext &Context, static llvm::GlobalValue::LinkageTypes getLinkageTypeForObjCMetadata(CodeGenModule &CGM, StringRef Section) { if (CGM.getTriple().isOSBinFormatMachO() && - (Section.empty() || Section.startswith("__DATA"))) + (Section.empty() || Section.starts_with("__DATA"))) return llvm::GlobalValue::InternalLinkage; return llvm::GlobalValue::PrivateLinkage; } @@ -6162,7 +6162,7 @@ void CGObjCNonFragileABIMac::AddModuleClassList( // Section name is obtained by calling GetSectionName, which returns // sections in the __DATA segment on MachO. assert((!CGM.getTriple().isOSBinFormatMachO() || - SectionName.startswith("__DATA")) && + SectionName.starts_with("__DATA")) && "SectionName expected to start with __DATA on MachO"); llvm::GlobalVariable *GV = new llvm::GlobalVariable( CGM.getModule(), Init->getType(), false, diff --git a/clang/lib/CodeGen/CGRecordLayoutBuilder.cpp b/clang/lib/CodeGen/CGRecordLayoutBuilder.cpp index cbfa79e10bfe..868ef810f3c4 100644 --- a/clang/lib/CodeGen/CGRecordLayoutBuilder.cpp +++ b/clang/lib/CodeGen/CGRecordLayoutBuilder.cpp @@ -111,7 +111,7 @@ struct CGRecordLowering { /// Helper function to check if we are targeting AAPCS. bool isAAPCS() const { - return Context.getTargetInfo().getABI().startswith("aapcs"); + return Context.getTargetInfo().getABI().starts_with("aapcs"); } /// Helper function to check if the target machine is BigEndian. diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp index a5cb80640641..0f79a2e861d2 100644 --- a/clang/lib/CodeGen/CGStmt.cpp +++ b/clang/lib/CodeGen/CGStmt.cpp @@ -2548,7 +2548,7 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt &S) { ResultRegQualTys.push_back(QTy); ResultRegDests.push_back(Dest); - bool IsFlagReg = llvm::StringRef(OutputConstraint).startswith("{@cc"); + bool IsFlagReg = llvm::StringRef(OutputConstraint).starts_with("{@cc"); ResultRegIsFlagReg.push_back(IsFlagReg); llvm::Type *Ty = ConvertTypeForMem(QTy); diff --git a/clang/lib/CodeGen/CodeGenAction.cpp b/clang/lib/CodeGen/CodeGenAction.cpp index bb6b1a3bc228..753a8fd74fa6 100644 --- a/clang/lib/CodeGen/CodeGenAction.cpp +++ b/clang/lib/CodeGen/CodeGenAction.cpp @@ -1139,7 +1139,7 @@ CodeGenAction::loadModule(MemoryBufferRef MBRef) { // Strip off a leading diagnostic code if there is one. StringRef Msg = Err.getMessage(); - if (Msg.startswith("error: ")) + if (Msg.starts_with("error: ")) Msg = Msg.substr(7); unsigned DiagID = diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index b931a81bc008..7ad26ace328a 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -225,9 +225,9 @@ createTargetCodeGenInfo(CodeGenModule &CGM) { StringRef ABIStr = Target.getABI(); unsigned XLen = Target.getPointerWidth(LangAS::Default); unsigned ABIFLen = 0; - if (ABIStr.endswith("f")) + if (ABIStr.ends_with("f")) ABIFLen = 32; - else if (ABIStr.endswith("d")) + else if (ABIStr.ends_with("d")) ABIFLen = 64; return createRISCVTargetCodeGenInfo(CGM, XLen, ABIFLen); } @@ -308,9 +308,9 @@ createTargetCodeGenInfo(CodeGenModule &CGM) { case llvm::Triple::loongarch64: { StringRef ABIStr = Target.getABI(); unsigned ABIFRLen = 0; - if (ABIStr.endswith("f")) + if (ABIStr.ends_with("f")) ABIFRLen = 32; - else if (ABIStr.endswith("d")) + else if (ABIStr.ends_with("d")) ABIFRLen = 64; return createLoongArchTargetCodeGenInfo( CGM, Target.getPointerWidth(LangAS::Default), ABIFRLen); @@ -1715,7 +1715,7 @@ static void AppendTargetMangling(const CodeGenModule &CGM, llvm::sort(Info.Features, [&Target](StringRef LHS, StringRef RHS) { // Multiversioning doesn't allow "no-${feature}", so we can // only have "+" prefixes here. - assert(LHS.startswith("+") && RHS.startswith("+") && + assert(LHS.starts_with("+") && RHS.starts_with("+") && "Features should always have a prefix."); return Target.multiVersionSortPriority(LHS.substr(1)) > Target.multiVersionSortPriority(RHS.substr(1)); @@ -1769,7 +1769,7 @@ static void AppendTargetClonesMangling(const CodeGenModule &CGM, } else { Out << '.'; StringRef FeatureStr = Attr->getFeatureStr(VersionIndex); - if (FeatureStr.startswith("arch=")) + if (FeatureStr.starts_with("arch=")) Out << "arch_" << FeatureStr.substr(sizeof("arch=") - 1); else Out << FeatureStr; @@ -3828,7 +3828,7 @@ namespace { if (!BuiltinID || !BI.isLibFunction(BuiltinID)) return false; StringRef BuiltinName = BI.getName(BuiltinID); - if (BuiltinName.startswith("__builtin_") && + if (BuiltinName.starts_with("__builtin_") && Name == BuiltinName.slice(strlen("__builtin_"), StringRef::npos)) { return true; } @@ -4164,7 +4164,7 @@ void CodeGenModule::emitMultiVersionFunctions() { Feature.push_back(CurFeat.trim()); } } else { - if (Version.startswith("arch=")) + if (Version.starts_with("arch=")) Architecture = Version.drop_front(sizeof("arch=") - 1); else if (Version != "default") Feature.push_back(Version); diff --git a/clang/lib/CodeGen/Targets/SPIR.cpp b/clang/lib/CodeGen/Targets/SPIR.cpp index 8bacba65617e..cf068cbc4fcd 100644 --- a/clang/lib/CodeGen/Targets/SPIR.cpp +++ b/clang/lib/CodeGen/Targets/SPIR.cpp @@ -146,14 +146,14 @@ static llvm::Type *getSPIRVImageType(llvm::LLVMContext &Ctx, StringRef BaseType, // Choose the dimension of the image--this corresponds to the Dim enum in // SPIR-V (first integer parameter of OpTypeImage). - if (OpenCLName.startswith("image2d")) + if (OpenCLName.starts_with("image2d")) IntParams[0] = 1; // 1D - else if (OpenCLName.startswith("image3d")) + else if (OpenCLName.starts_with("image3d")) IntParams[0] = 2; // 2D else if (OpenCLName == "image1d_buffer") IntParams[0] = 5; // Buffer else - assert(OpenCLName.startswith("image1d") && "Unknown image type"); + assert(OpenCLName.starts_with("image1d") && "Unknown image type"); // Set the other integer parameters of OpTypeImage if necessary. Note that the // OpenCL image types don't provide any information for the Sampled or diff --git a/clang/lib/Driver/Distro.cpp b/clang/lib/Driver/Distro.cpp index 36f828f8cae2..a7e7f169dc14 100644 --- a/clang/lib/Driver/Distro.cpp +++ b/clang/lib/Driver/Distro.cpp @@ -34,7 +34,7 @@ static Distro::DistroType DetectOsRelease(llvm::vfs::FileSystem &VFS) { // Obviously this can be improved a lot. for (StringRef Line : Lines) - if (Version == Distro::UnknownDistro && Line.startswith("ID=")) + if (Version == Distro::UnknownDistro && Line.starts_with("ID=")) Version = llvm::StringSwitch<Distro::DistroType>(Line.substr(3)) .Case("alpine", Distro::AlpineLinux) .Case("fedora", Distro::Fedora) @@ -60,7 +60,7 @@ static Distro::DistroType DetectLsbRelease(llvm::vfs::FileSystem &VFS) { for (StringRef Line : Lines) if (Version == Distro::UnknownDistro && - Line.startswith("DISTRIB_CODENAME=")) + Line.starts_with("DISTRIB_CODENAME=")) Version = llvm::StringSwitch<Distro::DistroType>(Line.substr(17)) .Case("hardy", Distro::UbuntuHardy) .Case("intrepid", Distro::UbuntuIntrepid) @@ -119,10 +119,10 @@ static Distro::DistroType DetectDistro(llvm::vfs::FileSystem &VFS) { if (File) { StringRef Data = File.get()->getBuffer(); - if (Data.startswith("Fedora release")) + if (Data.starts_with("Fedora release")) return Distro::Fedora; - if (Data.startswith("Red Hat Enterprise Linux") || - Data.startswith("CentOS") || Data.startswith("Scientific Linux")) { + if (Data.starts_with("Red Hat Enterprise Linux") || + Data.starts_with("CentOS") || Data.starts_with("Scientific Linux")) { if (Data.contains("release 7")) return Distro::RHEL7; else if (Data.contains("release 6")) @@ -182,7 +182,7 @@ static Distro::DistroType DetectDistro(llvm::vfs::FileSystem &VFS) { SmallVector<StringRef, 8> Lines; Data.split(Lines, "\n"); for (const StringRef &Line : Lines) { - if (!Line.trim().startswith("VERSION")) + if (!Line.trim().starts_with("VERSION")) continue; std::pair<StringRef, StringRef> SplitLine = Line.split('='); // Old versions have split VERSION and PATCHLEVEL diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index f392f6794f85..ff95c899c5f3 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -1451,7 +1451,7 @@ Compilation *Driver::BuildCompilation(ArrayRef<const char *> ArgList) { case llvm::Triple::aarch64: case llvm::Triple::aarch64_be: case llvm::Triple::aarch64_32: - if (TC.getTriple().getEnvironmentName().startswith("eabi")) { + if (TC.getTriple().getEnvironmentName().starts_with("eabi")) { Diag(diag::warn_target_unrecognized_env) << TargetTriple << (TC.getTriple().getArchName().str() + "-none-elf"); @@ -1540,7 +1540,7 @@ bool Driver::getCrashDiagnosticFile(StringRef ReproCrashFilename, for (fs::directory_iterator File(CrashDiagDir, EC), FileEnd; File != FileEnd && !EC; File.increment(EC)) { StringRef FileName = path::filename(File->path()); - if (!FileName.startswith(Name)) + if (!FileName.starts_with(Name)) continue; if (fs::status(File->path(), FileStatus)) continue; @@ -1551,7 +1551,7 @@ bool Driver::getCrashDiagnosticFile(StringRef ReproCrashFilename, // The first line should start with "Process:", otherwise this isn't a real // .crash file. StringRef Data = CrashFile.get()->getBuffer(); - if (!Data.startswith("Process:")) + if (!Data.starts_with("Process:")) continue; // Parse parent process pid line, e.g: "Parent Process: clang-4.0 [79141]" size_t ParentProcPos = Data.find("Parent Process:"); @@ -1780,7 +1780,7 @@ void Driver::generateCompilationDiagnostics( ReproCrashFilename = TempFile; llvm::sys::path::replace_extension(ReproCrashFilename, ".crash"); } - if (StringRef(TempFile).endswith(".cache")) { + if (StringRef(TempFile).ends_with(".cache")) { // In some cases (modules) we'll dump extra data to help with reproducing // the crash into a directory next to the output. VFS = llvm::sys::path::filename(TempFile); @@ -2001,7 +2001,7 @@ void Driver::HandleAutocompletions(StringRef PassedFlags) const { // Distinguish "--autocomplete=-someflag" and "--autocomplete=-someflag," // because the latter indicates that the user put space before pushing tab // which should end up in a file completion. - const bool HasSpace = PassedFlags.endswith(","); + const bool HasSpace = PassedFlags.ends_with(","); // Parse PassedFlags by "," as all the command-line flags are passed to this // function separated by "," @@ -2041,7 +2041,7 @@ void Driver::HandleAutocompletions(StringRef PassedFlags) const { // When flag ends with '=' and there was no value completion, return empty // string and fall back to the file autocompletion. - if (SuggestedCompletions.empty() && !Cur.endswith("=")) { + if (SuggestedCompletions.empty() && !Cur.ends_with("=")) { // If the flag is in the form of "--autocomplete=-foo", // we were requested to print out all option names that start with "-foo". // For example, "--autocomplete=-fsyn" is expanded to "-fsyntax-only". @@ -2053,7 +2053,7 @@ void Driver::HandleAutocompletions(StringRef PassedFlags) const { // TODO: Find a good way to add them to OptTable instead and them remove // this code. for (StringRef S : DiagnosticIDs::getDiagnosticFlags()) - if (S.startswith(Cur)) + if (S.starts_with(Cur)) SuggestedCompletions.push_back(std::string(S)); } @@ -2535,7 +2535,7 @@ bool Driver::DiagnoseInputExistence(const DerivedArgList &Args, StringRef Value, // so we can't downgrade diagnostics for `/GR-` from an error to a warning // in cc mode. (We can in cl mode because cl.exe itself only warns on // unknown flags.) - if (IsCLMode() && Ty == types::TY_Object && !Value.startswith("/")) + if (IsCLMode() && Ty == types::TY_Object && !Value.starts_with("/")) return true; Diag(clang::diag::err_drv_no_such_file) << Value; @@ -6565,7 +6565,7 @@ llvm::StringRef clang::driver::getDriverMode(StringRef ProgName, getDriverOptTable().getOption(options::OPT_driver_mode).getPrefixedName(); llvm::StringRef Opt; for (StringRef Arg : Args) { - if (!Arg.startswith(OptName)) + if (!Arg.starts_with(OptName)) continue; Opt = Arg; } @@ -6606,7 +6606,7 @@ llvm::Error driver::expandResponseFiles(SmallVectorImpl<const char *> &Args, else Tokenizer = &llvm::cl::TokenizeGNUCommandLine; - if (MarkEOLs && Args.size() > 1 && StringRef(Args[1]).startswith("-cc1")) + if (MarkEOLs && Args.size() > 1 && StringRef(Args[1]).starts_with("-cc1")) MarkEOLs = false; llvm::cl::ExpansionContext ECtx(Alloc, Tokenizer); @@ -6620,7 +6620,7 @@ llvm::Error driver::expandResponseFiles(SmallVectorImpl<const char *> &Args, // If -cc1 came from a response file, remove the EOL sentinels. auto FirstArg = llvm::find_if(llvm::drop_begin(Args), [](const char *A) { return A != nullptr; }); - if (FirstArg != Args.end() && StringRef(*FirstArg).startswith("-cc1")) { + if (FirstArg != Args.end() && StringRef(*FirstArg).starts_with("-cc1")) { // If -cc1 came from a response file, remove the EOL sentinels. if (MarkEOLs) { auto newEnd = std::remove(Args.begin(), Args.end(), nullptr); diff --git a/clang/lib/Driver/Job.cpp b/clang/lib/Driver/Job.cpp index 203400440f9f..a6c1581be796 100644 --- a/clang/lib/Driver/Job.cpp +++ b/clang/lib/Driver/Job.cpp @@ -95,10 +95,10 @@ static bool skipArgs(const char *Flag, bool HaveCrashVFS, int &SkipNum, // These flags are treated as a single argument (e.g., -F<Dir>). StringRef FlagRef(Flag); - IsInclude = FlagRef.startswith("-F") || FlagRef.startswith("-I"); + IsInclude = FlagRef.starts_with("-F") || FlagRef.starts_with("-I"); if (IsInclude) return !HaveCrashVFS; - if (FlagRef.startswith("-fmodules-cache-path=")) + if (FlagRef.starts_with("-fmodules-cache-path=")) return true; SkipNum = 0; @@ -185,8 +185,8 @@ rewriteIncludes(const llvm::ArrayRef<const char *> &Args, size_t Idx, SmallString<128> NewInc; if (NumArgs == 1) { StringRef FlagRef(Args[Idx + NumArgs - 1]); - assert((FlagRef.startswith("-F") || FlagRef.startswith("-I")) && - "Expecting -I or -F"); + assert((FlagRef.starts_with("-F") || FlagRef.starts_with("-I")) && + "Expecting -I or -F"); StringRef Inc = FlagRef.slice(2, StringRef::npos); if (getAbsPath(Inc, NewInc)) { SmallString<128> NewArg(FlagRef.slice(0, 2)); diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp index ab19166f18c2..96a57927339a 100644 --- a/clang/lib/Driver/ToolChain.cpp +++ b/clang/lib/Driver/ToolChain.cpp @@ -315,7 +315,7 @@ static const DriverSuffix *FindDriverSuffix(StringRef ProgName, size_t &Pos) { for (const auto &DS : DriverSuffixes) { StringRef Suffix(DS.Suffix); - if (ProgName.endswith(Suffix)) { + if (ProgName.ends_with(Suffix)) { Pos = ProgName.size() - Suffix.size(); return &DS; } @@ -345,7 +345,7 @@ static const DriverSuffix *parseDriverSuffix(StringRef ProgName, size_t &Pos) { // added via -target as implicit first argument. const DriverSuffix *DS = FindDriverSuffix(ProgName, Pos); - if (!DS && ProgName.endswith(".exe")) { + if (!DS && ProgName.ends_with(".exe")) { // Try again after stripping the executable suffix: // clang++.exe -> clang++ ProgName = ProgName.drop_back(StringRef(".exe").size()); diff --git a/clang/lib/Driver/ToolChains/AIX.cpp b/clang/lib/Driver/ToolChains/AIX.cpp index aed8734b2bab..f9670ea6f251 100644 --- a/clang/lib/Driver/ToolChains/AIX.cpp +++ b/clang/lib/Driver/ToolChains/AIX.cpp @@ -88,7 +88,7 @@ static bool hasExportListLinkerOpts(const ArgStringList &CmdArgs) { for (size_t i = 0, Size = CmdArgs.size(); i < Size; ++i) { llvm::StringRef ArgString(CmdArgs[i]); - if (ArgString.startswith("-bE:") || ArgString.startswith("-bexport:") || + if (ArgString.starts_with("-bE:") || ArgString.starts_with("-bexport:") || ArgString == "-bexpall" || ArgString == "-bexpfull") return true; @@ -96,8 +96,8 @@ static bool hasExportListLinkerOpts(const ArgStringList &CmdArgs) { if (ArgString == "-b" && i + 1 < Size) { ++i; llvm::StringRef ArgNextString(CmdArgs[i]); - if (ArgNextString.startswith("E:") || - ArgNextString.startswith("export:") || ArgNextString == "expall" || + if (ArgNextString.starts_with("E:") || + ArgNextString.starts_with("export:") || ArgNextString == "expall" || ArgNextString == "expfull") return true; } diff --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp b/clang/lib/Driver/ToolChains/AMDGPU.cpp index cad206ea4df1..56f06fc5fccb 100644 --- a/clang/lib/Driver/ToolChains/AMDGPU.cpp +++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp @@ -49,7 +49,7 @@ RocmInstallationDetector::findSPACKPackage(const Candidate &Cand, FileEnd; File != FileEnd && !EC; File.increment(EC)) { llvm::StringRef FileName = llvm::sys::path::filename(File->path()); - if (FileName.startswith(Prefix)) { + if (FileName.starts_with(Prefix)) { SubDirs.push_back(FileName); if (SubDirs.size() > 1) break; @@ -84,13 +84,13 @@ void RocmInstallationDetector::scanLibDevicePath(llvm::StringRef Path) { !EC && LI != LE; LI = LI.increment(EC)) { StringRef FilePath = LI->path(); StringRef FileName = llvm::sys::path::filename(FilePath); - if (!FileName.endswith(Suffix)) + if (!FileName.ends_with(Suffix)) continue; StringRef BaseName; - if (FileName.endswith(Suffix2)) + if (FileName.ends_with(Suffix2)) BaseName = FileName.drop_back(Suffix2.size()); - else if (FileName.endswith(Suffix)) + else if (FileName.ends_with(Suffix)) BaseName = FileName.drop_back(Suffix.size()); const StringRef ABIVersionPrefix = "oclc_abi_version_"; @@ -124,7 +124,7 @@ void RocmInstallationDetector::scanLibDevicePath(llvm::StringRef Path) { WavefrontSize64.On = FilePath; } else if (BaseName == "oclc_wavefrontsize64_off") { WavefrontSize64.Off = FilePath; - } else if (BaseName.startswith(ABIVersionPrefix)) { + } else if (BaseName.starts_with(ABIVersionPrefix)) { unsigned ABIVersionNumber; if (BaseName.drop_front(ABIVersionPrefix.size()) .getAsInteger(/*Redex=*/0, ABIVersionNumber)) @@ -134,7 +134,7 @@ void RocmInstallationDetector::scanLibDevicePath(llvm::StringRef Path) { // Process all bitcode filenames that look like // ocl_isa_version_XXX.amdgcn.bc const StringRef DeviceLibPrefix = "oclc_isa_version_"; - if (!BaseName.startswith(DeviceLibPrefix)) + if (!BaseName.starts_with(DeviceLibPrefix)) continue; StringRef IsaVersionNumber = @@ -230,7 +230,7 @@ RocmInstallationDetector::getInstallationPathCandidates() { // <rocm_root>/llvm-amdgpu-<rocm_release_string>-<hash>/bin directory. // We only consider the parent directory of llvm-amdgpu package as ROCm // installation candidate for SPACK. - if (ParentName.startswith("llvm-amdgpu-")) { + if (ParentName.starts_with("llvm-amdgpu-")) { auto SPACKPostfix = ParentName.drop_front(strlen("llvm-amdgpu-")).split('-'); auto SPACKReleaseStr = SPACKPostfix.first; @@ -243,7 +243,7 @@ RocmInstallationDetector::getInstallationPathCandidates() { // Some versions of the rocm llvm package install to /opt/rocm/llvm/bin // Some versions of the aomp package install to /opt/rocm/aomp/bin - if (ParentName == "llvm" || ParentName.startswith("aomp")) + if (ParentName == "llvm" || ParentName.starts_with("aomp")) ParentDir = llvm::sys::path::parent_path(ParentDir); return Candidate(ParentDir.str(), /*StrictChecking=*/true); @@ -292,7 +292,7 @@ RocmInstallationDetector::getInstallationPathCandidates() { FileEnd; File != FileEnd && !EC; File.increment(EC)) { llvm::StringRef FileName = llvm::sys::path::filename(File->path()); - if (!FileName.startswith("rocm-")) + if (!FileName.starts_with("rocm-")) continue; if (LatestROCm.empty()) { LatestROCm = FileName.str(); diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp index 097258b16924..912df79417ae 100644 --- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp +++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp @@ -228,7 +228,7 @@ getAArch64MicroArchFeaturesFromMtune(const Driver &D, StringRef Mtune, if (MtuneLowerCase == "native") MtuneLowerCase = std::string(llvm::sys::getHostCPUName()); if (MtuneLowerCase == "cyclone" || - StringRef(MtuneLowerCase).startswith("apple")) { + StringRef(MtuneLowerCase).starts_with("apple")) { Features.push_back("+zcm"); Features.push_back("+zcz"); } @@ -262,7 +262,7 @@ void aarch64::getAArch64TargetFeatures(const Driver &D, for (const auto *A : Args.filtered(options::OPT_Wa_COMMA, options::OPT_Xassembler)) for (StringRef Value : A->getValues()) - if (Value.startswith("-march=")) + if (Value.starts_with("-march=")) WaMArch = Value.substr(7); // Call getAArch64ArchFeaturesFromMarch only if "-Wa,-march=" or // "-Xassembler -march" is detected. Otherwise it may return false diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp b/clang/lib/Driver/ToolChains/Arch/ARM.cpp index f1d7aeb555f8..25470db2b6ce 100644 --- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp +++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp @@ -67,9 +67,9 @@ void arm::getARMArchCPUFromArgs(const ArgList &Args, llvm::StringRef &Arch, // Use getValues because -Wa can have multiple arguments // e.g. -Wa,-mcpu=foo,-mcpu=bar for (StringRef Value : A->getValues()) { - if (Value.startswith("-mcpu=")) + if (Value.starts_with("-mcpu=")) CPU = Value.substr(6); - if (Value.startswith("-march=")) + if (Value.starts_with("-march=")) Arch = Value.substr(7); } } @@ -285,9 +285,9 @@ void arm::setArchNameInTriple(const Driver &D, const ArgList &Args, // There is no assembler equivalent of -mno-thumb, -marm, or -mno-arm. if (Value == "-mthumb") IsThumb = true; - else if (Value.startswith("-march=")) + else if (Value.starts_with("-march=")) WaMArch = Value.substr(7); - else if (Value.startswith("-mcpu=")) + else if (Value.starts_with("-mcpu=")) WaMCPU = Value.substr(6); } } @@ -528,13 +528,13 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver &D, // We use getValues here because you can have many options per -Wa // We will keep the last one we find for each of these for (StringRef Value : A->getValues()) { - if (Value.startswith("-mfpu=")) { + if (Value.starts_with("-mfpu=")) { WaFPU = std::make_pair(A, Value.substr(6)); - } else if (Value.startswith("-mcpu=")) { + } else if (Value.starts_with("-mcpu=")) { WaCPU = std::make_pair(A, Value.substr(6)); - } else if (Value.startswith("-mhwdiv=")) { + } else if (Value.starts_with("-mhwdiv=")) { WaHDiv = std::make_pair(A, Value.substr(8)); - } else if (Value.startswith("-march=")) { + } else if (Value.starts_with("-march=")) { WaArch = std::make_pair(A, Value.substr(7)); } } @@ -796,7 +796,7 @@ fp16_fml_fallthrough: // Propagate frame-chain model selection if (Arg *A = Args.getLastArg(options::OPT_mframe_chain)) { StringRef FrameChainOption = A->getValue(); - if (FrameChainOption.startswith("aapcs")) + if (FrameChainOption.starts_with("aapcs")) Features.push_back("+aapcs-frame-chain"); if (FrameChainOption == "aapcs+leaf") Features.push_back("+aapcs-frame-chain-leaf"); diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp b/clang/lib/Driver/ToolChains/Arch/X86.cpp index 3e51b2b5ce86..fef0522aaf45 100644 --- a/clang/lib/Driver/ToolChains/Arch/X86.cpp +++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp @@ -234,15 +234,15 @@ void x86::getX86TargetFeatures(const Driver &D, const llvm::Triple &Triple, A->claim(); // Skip over "-m". - assert(Name.startswith("m") && "Invalid feature name."); + assert(Name.starts_with("m") && "Invalid feature name."); Name = Name.substr(1); - bool IsNegative = Name.startswith("no-"); + bool IsNegative = Name.starts_with("no-"); if (IsNegative) Name = Name.substr(3); #ifndef NDEBUG - assert(Name.startswith("avx10.") && "Invalid AVX10 feature name."); + assert(Name.starts_with("avx10.") && "Invalid AVX10 feature name."); StringRef Version, Width; std::tie(Version, Width) = Name.substr(6).split('-'); assert(Version == "1" && "Invalid AVX10 feature name."); @@ -260,7 +260,7 @@ void x86::getX86TargetFeatures(const Driver &D, const llvm::Triple &Triple, A->claim(); // Skip over "-m". - assert(Name.startswith("m") && "Invalid feature name."); + assert(Name.starts_with("m") && "Invalid feature name."); Name = Name.substr(1); // Replace -mgeneral-regs-only with -x87, -mmx, -sse @@ -269,7 +269,7 @@ void x86::getX86TargetFeatures(const Driver &D, const llvm::Triple &Triple, continue; } - bool IsNegative = Name.startswith("no-"); + bool IsNegative = Name.starts_with("no-"); if (A->getOption().matches(options::OPT_mapx_features_EQ) || A->getOption().matches(options::OPT_mno_apx_features_EQ)) { diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index f95f3227aba7..de9fd5eaa1e0 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -223,7 +223,7 @@ static void ParseMRecip(const Driver &D, const ArgList &Args, for (unsigned i = 0; i != NumOptions; ++i) { StringRef Val = A->getValue(i); - bool IsDisabled = Val.startswith(DisabledPrefixIn); + bool IsDisabled = Val.starts_with(DisabledPrefixIn); // Ignore the disablement token for string matching. if (IsDisabled) Val = Val.substr(1); @@ -433,7 +433,7 @@ static void addDebugObjectName(const ArgList &Args, ArgStringList &CmdArgs, const char *OutputFileName) { // No need to generate a value for -object-file-name if it was provided. for (auto *Arg : Args.filtered(options::OPT_Xclang)) - if (StringRef(Arg->getValue()).startswith("-object-file-name")) + if (StringRef(Arg->getValue()).starts_with("-object-file-name")) return; if (Args.hasArg(options::OPT_object_file_name_EQ)) @@ -940,7 +940,7 @@ static void handleAMDGPUCodeObjectVersionOptions(const Driver &D, static bool hasClangPchSignature(const Driver &D, StringRef Path) { if (llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> MemBuf = D.getVFS().getBufferForFile(Path)) - return (*MemBuf)->getBuffer().startswith("CPCH"); + return (*MemBuf)->getBuffer().starts_with("CPCH"); return false; } @@ -1715,7 +1715,7 @@ void Clang::AddAArch64TargetArgs(const ArgList &Args, Val.equals("256+") || Val.equals("512+") || Val.equals("1024+") || Val.equals("2048+")) { unsigned Bits = 0; - if (Val.endswith("+")) + if (Val.ends_with("+")) Val = Val.substr(0, Val.size() - 1); else { bool Invalid = Val.getAsInteger(10, Bits); (void)Invalid; @@ -2503,7 +2503,7 @@ static void CollectArgsForIntegratedAssembler(Compilation &C, case llvm::Triple::thumbeb: case llvm::Triple::arm: case llvm::Triple::armeb: - if (Value.startswith("-mimplicit-it=")) { + if (Value.starts_with("-mimplicit-it=")) { // Only store the value; the last value set takes effect. ImplicitIt = Value.split("=").second; if (CheckARMImplicitITArg(ImplicitIt)) @@ -2528,12 +2528,12 @@ static void CollectArgsForIntegratedAssembler(Compilation &C, CmdArgs.push_back("-use-tcc-in-div"); continue; } - if (Value.startswith("-msoft-float")) { + if (Value.starts_with("-msoft-float")) { CmdArgs.push_back("-target-feature"); CmdArgs.push_back("+soft-float"); continue; } - if (Value.startswith("-mhard-float")) { + if (Value.starts_with("-mhard-float")) { CmdArgs.push_back("-target-feature"); CmdArgs.push_back("-soft-float"); continue; @@ -2570,8 +2570,8 @@ static void CollectArgsForIntegratedAssembler(Compilation &C, CmdArgs.push_back("-massembler-no-warn"); } else if (Value == "--noexecstack") { UseNoExecStack = true; - } else if (Value.startswith("-compress-debug-sections") || - Value.startswith("--compress-debug-sections") || + } else if (Value.starts_with("-compress-debug-sections") || + Value.starts_with("--compress-debug-sections") || Value == "-nocompress-debug-sections" || Value == "--nocompress-debug-sections") { CmdArgs.push_back(Value.data()); @@ -2581,13 +2581,13 @@ static void CollectArgsForIntegratedAssembler(Compilation &C, } else if (Value == "-mrelax-relocations=no" || Value == "--mrelax-relocations=no") { UseRelaxRelocations = false; - } else if (Value.startswith("-I")) { + } else if (Value.starts_with("-I")) { CmdArgs.push_back(Value.data()); // We need to consume the next argument if the current arg is a plain // -I. The next arg will be the include directory. if (Value == "-I") TakeNextArg = true; - } else if (Value.startswith("-gdwarf-")) { + } else if (Value.starts_with("-gdwarf-")) { // "-gdwarf-N" options are not cc1as options. unsigned DwarfVersion = DwarfVersionNum(Value); if (DwarfVersion == 0) { // Send it onward, and let cc1as complain. @@ -2597,30 +2597,30 @@ static void CollectArgsForIntegratedAssembler(Compilation &C, llvm::codegenoptions::DebugInfoConstructor, DwarfVersion, llvm::DebuggerKind::Default); } - } else if (Value.startswith("-mcpu") || Value.startswith("-mfpu") || - Value.startswith("-mhwdiv") || Value.startswith("-march")) { + } else if (Value.starts_with("-mcpu") || Value.starts_with("-mfpu") || + Value.starts_with("-mhwdiv") || Value.starts_with("-march")) { // Do nothing, we'll validate it later. } else if (Value == "-defsym") { - if (A->getNumValues() != 2) { - D.Diag(diag::err_drv_defsym_invalid_format) << Value; - break; - } - const char *S = A->getValue(1); - auto Pair = StringRef(S).split('='); - auto Sym = Pair.first; - auto SVal = Pair.second; - - if (Sym.empty() || SVal.empty()) { - D.Diag(diag::err_drv_defsym_invalid_format) << S; - break; - } - int64_t IVal; - if (SVal.getAsInteger(0, IVal)) { - D.Diag(diag::err_drv_defsym_invalid_symval) << SVal; - break; - } - CmdArgs.push_back(Value.data()); - TakeNextArg = true; + if (A->getNumValues() != 2) { + D.Diag(diag::err_drv_defsym_invalid_format) << Value; + break; + } + const char *S = A->getValue(1); + auto Pair = StringRef(S).split('='); + auto Sym = Pair.first; + auto SVal = Pair.second; + + if (Sym.empty() || SVal.empty()) { + D.Diag(diag::err_drv_defsym_invalid_format) << S; + break; + } + int64_t IVal; + if (SVal.getAsInteger(0, IVal)) { + D.Diag(diag::err_drv_defsym_invalid_symval) << SVal; + break; + } + CmdArgs.push_back(Value.data()); + TakeNextArg = true; } else if (Value == "-fdebug-compilation-dir") { CmdArgs.push_back("-fdebug-compilation-dir"); TakeNextArg = true; @@ -3331,7 +3331,7 @@ static void RenderSSPOptions(const Driver &D, const ToolChain &TC, // --param ssp-buffer-size= for (const Arg *A : Args.filtered(options::OPT__param)) { StringRef Str(A->getValue()); - if (Str.startswith("ssp-buffer-size=")) { + if (Str.starts_with("ssp-buffer-size=")) { if (StackProtectorLevel) { CmdArgs.push_back("-stack-protector-buffer-size"); // FIXME: Verify the argument is a valid integer. @@ -5615,6 +5615,10 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, options::OPT_fno_auto_import); } + if (Args.hasFlag(options::OPT_fms_volatile, options::OPT_fno_ms_volatile, + Triple.isX86() && D.IsCLMode())) + CmdArgs.push_back("-fms-volatile"); + // Non-PIC code defaults to -fdirect-access-external-data while PIC code // defaults to -fno-direct-access-external-data. Pass the option if different // from the default. @@ -5882,7 +5886,7 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, StringRef Val = A->getValue(); if (Triple.isX86() && Triple.isOSBinFormatELF()) { if (Val != "all" && Val != "labels" && Val != "none" && - !Val.startswith("list=")) + !Val.starts_with("list=")) D.Diag(diag::err_drv_invalid_value) << A->getAsString(Args) << A->getValue(); else @@ -7947,18 +7951,6 @@ void Clang::AddClangCLArgs(const ArgList &Args, types::ID InputType, CmdArgs.push_back("-P"); } - unsigned VolatileOptionID; - if (getToolChain().getTriple().isX86()) - VolatileOptionID = options::OPT__SLASH_volatile_ms; - else - VolatileOptionID = options::OPT__SLASH_volatile_iso; - - if (Arg *A = Args.getLastArg(options::OPT__SLASH_volatile_Group)) - VolatileOptionID = A->getOption().getID(); - - if (VolatileOptionID == options::OPT__SLASH_volatile_ms) - CmdArgs.push_back("-fms-volatile"); - if (Args.hasFlag(options::OPT__SLASH_Zc_dllexportInlines_, options::OPT__SLASH_Zc_dllexportInlines, false)) { @@ -8390,14 +8382,14 @@ void ClangAs::ConstructJob(Compilation &C, const JobAction &JA, continue; auto &JArgs = J.getArguments(); for (unsigned I = 0; I < JArgs.size(); ++I) { - if (StringRef(JArgs[I]).startswith("-object-file-name=") && + if (StringRef(JArgs[I]).starts_with("-object-file-name=") && Output.isFilename()) { - ArgStringList NewArgs(JArgs.begin(), JArgs.begin() + I); - addDebugObjectName(Args, NewArgs, DebugCompilationDir, - Output.getFilename()); - NewArgs.append(JArgs.begin() + I + 1, JArgs.end()); - J.replaceArguments(NewArgs); - break; + ArgStringList NewArgs(JArgs.begin(), JArgs.begin() + I); + addDebugObjectName(Args, NewArgs, DebugCompilationDir, + Output.getFilename()); + NewArgs.append(JArgs.begin() + I + 1, JArgs.end()); + J.replaceArguments(NewArgs); + break; } } } @@ -8661,7 +8653,7 @@ void OffloadPackager::ConstructJob(Compilation &C, const JobAction &JA, getTargetFeatures(TC->getDriver(), TC->getTriple(), TCArgs, Features, false); llvm::copy_if(Features, std::back_inserter(FeatureArgs), - [](StringRef Arg) { return !Arg.startswith("-target"); }); + [](StringRef Arg) { return !Arg.starts_with("-target"); }); if (TC->getTriple().isAMDGPU()) { for (StringRef Feature : llvm::split(Arch.split(':').second, ':')) { diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 31e7d68161ff..01fb0718b407 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -303,7 +303,7 @@ void tools::handleTargetFeaturesGroup(const Driver &D, A->claim(); // Skip over "-m". - assert(Name.startswith("m") && "Invalid feature name."); + assert(Name.starts_with("m") && "Invalid feature name."); Name = Name.substr(1); auto Proc = getCPUName(D, Args, Triple); @@ -317,7 +317,7 @@ void tools::handleTargetFeaturesGroup(const Driver &D, continue; } - bool IsNegative = Name.startswith("no-"); + bool IsNegative = Name.starts_with("no-"); if (IsNegative) Name = Name.substr(3); @@ -2336,20 +2336,20 @@ static void GetSDLFromOffloadArchive( llvm::Triple Triple(D.getTargetTriple()); bool IsMSVC = Triple.isWindowsMSVCEnvironment(); auto Ext = IsMSVC ? ".lib" : ".a"; - if (!Lib.startswith(":") && !Lib.startswith("-l")) { + if (!Lib.starts_with(":") && !Lib.starts_with("-l")) { if (llvm::sys::fs::exists(Lib)) { ArchiveOfBundles = Lib; FoundAOB = true; } } else { - if (Lib.startswith("-l")) + if (Lib.starts_with("-l")) Lib = Lib.drop_front(2); for (auto LPath : LibraryPaths) { ArchiveOfBundles.clear(); - auto LibFile = - (Lib.startswith(":") ? Lib.drop_front() - : IsMSVC ? Lib + Ext : "lib" + Lib + Ext) - .str(); + auto LibFile = (Lib.starts_with(":") ? Lib.drop_front() + : IsMSVC ? Lib + Ext + : "lib" + Lib + Ext) + .str(); for (auto Prefix : {"/libdevice/", "/"}) { auto AOB = Twine(LPath + Prefix + LibFile).str(); if (llvm::sys::fs::exists(AOB)) { diff --git a/clang/lib/Driver/ToolChains/Cuda.cpp b/clang/lib/Driver/ToolChains/Cuda.cpp index ef1e77974c1e..f7a208575cb0 100644 --- a/clang/lib/Driver/ToolChains/Cuda.cpp +++ b/clang/lib/Driver/ToolChains/Cuda.cpp @@ -238,7 +238,7 @@ CudaInstallationDetector::CudaInstallationDetector( // Process all bitcode filenames that look like // libdevice.compute_XX.YY.bc const StringRef LibDeviceName = "libdevice."; - if (!(FileName.startswith(LibDeviceName) && FileName.endswith(".bc"))) + if (!(FileName.starts_with(LibDeviceName) && FileName.ends_with(".bc"))) continue; StringRef GpuArch = FileName.slice( LibDeviceName.size(), FileName.find('.', LibDeviceName.size())); diff --git a/clang/lib/Driver/ToolChains/Darwin.cpp b/clang/lib/Driver/ToolChains/Darwin.cpp index 692b3a3f285d..65846cace461 100644 --- a/clang/lib/Driver/ToolChains/Darwin.cpp +++ b/clang/lib/Driver/ToolChains/Darwin.cpp @@ -1010,13 +1010,13 @@ static const char *ArmMachOArchNameCPU(StringRef CPU) { // FIXME: Make sure this MachO triple mangling is really necessary. // ARMv5* normalises to ARMv5. - if (Arch.startswith("armv5")) + if (Arch.starts_with("armv5")) Arch = Arch.substr(0, 5); // ARMv6*, except ARMv6M, normalises to ARMv6. - else if (Arch.startswith("armv6") && !Arch.endswith("6m")) + else if (Arch.starts_with("armv6") && !Arch.ends_with("6m")) Arch = Arch.substr(0, 5); // ARMv7A normalises to ARMv7. - else if (Arch.endswith("v7a")) + else if (Arch.ends_with("v7a")) Arch = Arch.substr(0, 5); return Arch.data(); } @@ -1319,8 +1319,8 @@ StringRef Darwin::getSDKName(StringRef isysroot) { auto EndSDK = llvm::sys::path::rend(isysroot); for (auto IT = BeginSDK; IT != EndSDK; ++IT) { StringRef SDK = *IT; - if (SDK.endswith(".sdk")) - return SDK.slice(0, SDK.size() - 4); + if (SDK.ends_with(".sdk")) + return SDK.slice(0, SDK.size() - 4); } return ""; } @@ -1959,22 +1959,23 @@ inferDeploymentTargetFromSDK(DerivedArgList &Args, auto CreatePlatformFromSDKName = [&](StringRef SDK) -> std::optional<DarwinPlatform> { - if (SDK.startswith("iPhoneOS") || SDK.startswith("iPhoneSimulator")) + if (SDK.starts_with("iPhoneOS") || SDK.starts_with("iPhoneSimulator")) return DarwinPlatform::createFromSDK( Darwin::IPhoneOS, Version, - /*IsSimulator=*/SDK.startswith("iPhoneSimulator")); - else if (SDK.startswith("MacOSX")) + /*IsSimulator=*/SDK.starts_with("iPhoneSimulator")); + else if (SDK.starts_with("MacOSX")) return DarwinPlatform::createFromSDK(Darwin::MacOS, getSystemOrSDKMacOSVersion(Version)); - else if (SDK.startswith("WatchOS") || SDK.startswith("WatchSimulator")) + else if (SDK.starts_with("WatchOS") || SDK.starts_with("WatchSimulator")) return DarwinPlatform::createFromSDK( Darwin::WatchOS, Version, - /*IsSimulator=*/SDK.startswith("WatchSimulator")); - else if (SDK.startswith("AppleTVOS") || SDK.startswith("AppleTVSimulator")) + /*IsSimulator=*/SDK.starts_with("WatchSimulator")); + else if (SDK.starts_with("AppleTVOS") || + SDK.starts_with("AppleTVSimulator")) return DarwinPlatform::createFromSDK( Darwin::TvOS, Version, - /*IsSimulator=*/SDK.startswith("AppleTVSimulator")); - else if (SDK.startswith("DriverKit")) + /*IsSimulator=*/SDK.starts_with("AppleTVSimulator")); + else if (SDK.starts_with("DriverKit")) return DarwinPlatform::createFromSDK(Darwin::DriverKit, Version); return std::nullopt; }; @@ -2339,8 +2340,8 @@ void Darwin::AddDeploymentTarget(DerivedArgList &Args) const { if (SDK.size() > 0) { size_t StartVer = SDK.find_first_of("0123456789"); StringRef SDKName = SDK.slice(0, StartVer); - if (!SDKName.startswith(getPlatformFamily()) && - !dropSDKNamePrefix(SDKName).startswith(getPlatformFamily())) + if (!SDKName.starts_with(getPlatformFamily()) && + !dropSDKNamePrefix(SDKName).starts_with(getPlatformFamily())) getDriver().Diag(diag::warn_incompatible_sysroot) << SDKName << getPlatformFamily(); } diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index 502b9f17a06c..41eaad3bbad0 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -182,7 +182,7 @@ void Flang::AddAArch64TargetArgs(const ArgList &Args, Val.equals("256+") || Val.equals("512+") || Val.equals("1024+") || Val.equals("2048+")) { unsigned Bits = 0; - if (Val.endswith("+")) + if (Val.ends_with("+")) Val = Val.substr(0, Val.size() - 1); else { [[maybe_unused]] bool Invalid = Val.getAsInteger(10, Bits); diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index b875991844ff..835215a83c40 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -1084,7 +1084,7 @@ static bool findMipsCsMultilibs(const Multilib::flags_list &Flags, .FilterOut(NonExistent) .setIncludeDirsCallback([](const Multilib &M) { std::vector<std::string> Dirs({"/include"}); - if (StringRef(M.includeSuffix()).startswith("/uclibc")) + if (StringRef(M.includeSuffix()).starts_with("/uclibc")) Dirs.push_back( "/../../../../mips-linux-gnu/libc/uclibc/usr/include"); else @@ -1288,7 +1288,7 @@ static bool findMipsMtiMultilibs(const Multilib::flags_list &Flags, .FilterOut(NonExistent) .setIncludeDirsCallback([](const Multilib &M) { std::vector<std::string> Dirs({"/include"}); - if (StringRef(M.includeSuffix()).startswith("/uclibc")) + if (StringRef(M.includeSuffix()).starts_with("/uclibc")) Dirs.push_back("/../../../../sysroot/uclibc/usr/include"); else Dirs.push_back("/../../../../sysroot/usr/include"); @@ -3055,7 +3055,7 @@ void Generic_GCC::AddMultilibPaths(const Driver &D, // the cross. Note that GCC does include some of these directories in some // configurations but this seems somewhere between questionable and simply // a bug. - if (StringRef(LibPath).startswith(SysRoot)) + if (StringRef(LibPath).starts_with(SysRoot)) addPathIfExists(D, LibPath + "/../" + OSLibDir, Paths); } } diff --git a/clang/lib/Driver/ToolChains/Hexagon.cpp b/clang/lib/Driver/ToolChains/Hexagon.cpp index d0ff7d0c1310..6a2a105bee32 100644 --- a/clang/lib/Driver/ToolChains/Hexagon.cpp +++ b/clang/lib/Driver/ToolChains/Hexagon.cpp @@ -54,11 +54,11 @@ static void handleHVXTargetFeatures(const Driver &D, const ArgList &Args, auto makeFeature = [&Args](Twine T, bool Enable) -> StringRef { const std::string &S = T.str(); StringRef Opt(S); - if (Opt.endswith("=")) + if (Opt.ends_with("=")) Opt = Opt.drop_back(1); - if (Opt.startswith("mno-")) + if (Opt.starts_with("mno-")) Opt = Opt.drop_front(4); - else if (Opt.startswith("m")) + else if (Opt.starts_with("m")) Opt = Opt.drop_front(1); return Args.MakeArgString(Twine(Enable ? "+" : "-") + Twine(Opt)); }; @@ -801,7 +801,7 @@ StringRef HexagonToolChain::GetTargetCPUVersion(const ArgList &Args) { CpuArg = A; StringRef CPU = CpuArg ? CpuArg->getValue() : GetDefaultCPU(); - if (CPU.startswith("hexagon")) + if (CPU.starts_with("hexagon")) return CPU.substr(sizeof("hexagon") - 1); return CPU; } diff --git a/clang/lib/Driver/ToolChains/Hurd.cpp b/clang/lib/Driver/ToolChains/Hurd.cpp index 2dfc90ef37f7..7a4c2bb7ede1 100644 --- a/clang/lib/Driver/ToolChains/Hurd.cpp +++ b/clang/lib/Driver/ToolChains/Hurd.cpp @@ -92,7 +92,7 @@ Hurd::Hurd(const Driver &D, const llvm::Triple &Triple, const ArgList &Args) // those searched. // FIXME: It's not clear whether we should use the driver's installed // directory ('Dir' below) or the ResourceDir. - if (StringRef(D.Dir).startswith(SysRoot)) { + if (StringRef(D.Dir).starts_with(SysRoot)) { addPathIfExists(D, D.Dir + "/../lib/" + MultiarchTriple, Paths); addPathIfExists(D, D.Dir + "/../" + OSLibDir, Paths); } @@ -110,7 +110,7 @@ Hurd::Hurd(const Driver &D, const llvm::Triple &Triple, const ArgList &Args) // searched. // FIXME: It's not clear whether we should use the driver's installed // directory ('Dir' below) or the ResourceDir. - if (StringRef(D.Dir).startswith(SysRoot)) + if (StringRef(D.Dir).starts_with(SysRoot)) addPathIfExists(D, D.Dir + "/../lib", Paths); addPathIfExists(D, SysRoot + "/lib", Paths); diff --git a/clang/lib/Driver/ToolChains/MSP430.cpp b/clang/lib/Driver/ToolChains/MSP430.cpp index b28d5e45706c..8dc23521f400 100644 --- a/clang/lib/Driver/ToolChains/MSP430.cpp +++ b/clang/lib/Driver/ToolChains/MSP430.cpp @@ -166,7 +166,7 @@ void MSP430ToolChain::addClangTargetOptions(const ArgList &DriverArgs, return; const StringRef MCU = MCUArg->getValue(); - if (MCU.startswith("msp430i")) { + if (MCU.starts_with("msp430i")) { // 'i' should be in lower case as it's defined in TI MSP430-GCC headers CC1Args.push_back(DriverArgs.MakeArgString( "-D__MSP430i" + MCU.drop_front(7).upper() + "__")); diff --git a/clang/lib/Driver/ToolChains/MSVC.cpp b/clang/lib/Driver/ToolChains/MSVC.cpp index 6d925555b7bb..8e1e95173836 100644 --- a/clang/lib/Driver/ToolChains/MSVC.cpp +++ b/clang/lib/Driver/ToolChains/MSVC.cpp @@ -302,7 +302,7 @@ void visualstudio::Linker::ConstructJob(Compilation &C, const JobAction &JA, if (A.getOption().matches(options::OPT_l)) { StringRef Lib = A.getValue(); const char *LinkLibArg; - if (Lib.endswith(".lib")) + if (Lib.ends_with(".lib")) LinkLibArg = Args.MakeArgString(Lib); else LinkLibArg = Args.MakeArgString(Lib + ".lib"); diff --git a/clang/lib/Driver/ToolChains/MinGW.cpp b/clang/lib/Driver/ToolChains/MinGW.cpp index 5d7f8675daf8..65512f16357d 100644 --- a/clang/lib/Driver/ToolChains/MinGW.cpp +++ b/clang/lib/Driver/ToolChains/MinGW.cpp @@ -86,9 +86,9 @@ void tools::MinGW::Linker::AddLibGCC(const ArgList &Args, CmdArgs.push_back("-lmoldname"); CmdArgs.push_back("-lmingwex"); for (auto Lib : Args.getAllArgValues(options::OPT_l)) - if (StringRef(Lib).startswith("msvcr") || - StringRef(Lib).startswith("ucrt") || - StringRef(Lib).startswith("crtdll")) + if (StringRef(Lib).starts_with("msvcr") || + StringRef(Lib).starts_with("ucrt") || + StringRef(Lib).starts_with("crtdll")) return; CmdArgs.push_back("-lmsvcrt"); } diff --git a/clang/lib/Driver/ToolChains/PPCLinux.cpp b/clang/lib/Driver/ToolChains/PPCLinux.cpp index bdbecaef6040..0ed0f91ad166 100644 --- a/clang/lib/Driver/ToolChains/PPCLinux.cpp +++ b/clang/lib/Driver/ToolChains/PPCLinux.cpp @@ -31,10 +31,10 @@ static bool GlibcSupportsFloat128(const std::string &Linker) { // Since glibc 2.34, the installed .so file is not symlink anymore. But we can // still safely assume it's newer than 2.32. - if (LinkerName.startswith("ld64.so")) + if (LinkerName.starts_with("ld64.so")) return true; - if (!LinkerName.startswith("ld-2.")) + if (!LinkerName.starts_with("ld-2.")) return false; unsigned Minor = (LinkerName[5] - '0') * 10 + (LinkerName[6] - '0'); if (Minor < 32) diff --git a/clang/lib/Driver/ToolChains/Solaris.cpp b/clang/lib/Driver/ToolChains/Solaris.cpp index 485730da7df1..9a9792d019d5 100644 --- a/clang/lib/Driver/ToolChains/Solaris.cpp +++ b/clang/lib/Driver/ToolChains/Solaris.cpp @@ -328,7 +328,7 @@ Solaris::Solaris(const Driver &D, const llvm::Triple &Triple, // If we are currently running Clang inside of the requested system root, // add its parent library path to those searched. - if (StringRef(D.Dir).startswith(D.SysRoot)) + if (StringRef(D.Dir).starts_with(D.SysRoot)) addPathIfExists(D, D.Dir + "/../lib", Paths); addPathIfExists(D, D.SysRoot + "/usr/lib" + LibSuffix, Paths); diff --git a/clang/lib/Driver/ToolChains/WebAssembly.cpp b/clang/lib/Driver/ToolChains/WebAssembly.cpp index f131b6cf3baf..57f4600727ec 100644 --- a/clang/lib/Driver/ToolChains/WebAssembly.cpp +++ b/clang/lib/Driver/ToolChains/WebAssembly.cpp @@ -328,7 +328,7 @@ void WebAssembly::addClangTargetOptions(const ArgList &DriverArgs, for (const Arg *A : DriverArgs.filtered(options::OPT_mllvm)) { StringRef Opt = A->getValue(0); - if (Opt.startswith("-emscripten-cxx-exceptions-allowed")) { + if (Opt.starts_with("-emscripten-cxx-exceptions-allowed")) { // '-mllvm -emscripten-cxx-exceptions-allowed' should be used with // '-mllvm -enable-emscripten-cxx-exceptions' bool EmEHArgExists = false; @@ -355,7 +355,7 @@ void WebAssembly::addClangTargetOptions(const ArgList &DriverArgs, } } - if (Opt.startswith("-wasm-enable-sjlj")) { + if (Opt.starts_with("-wasm-enable-sjlj")) { // '-mllvm -wasm-enable-sjlj' is not compatible with // '-mno-exception-handling' if (DriverArgs.hasFlag(options::OPT_mno_exception_handing, diff --git a/clang/lib/Edit/Commit.cpp b/clang/lib/Edit/Commit.cpp index 7c5aea6e5069..6e785e866666 100644 --- a/clang/lib/Edit/Commit.cpp +++ b/clang/lib/Edit/Commit.cpp @@ -334,7 +334,7 @@ bool Commit::canReplaceText(SourceLocation loc, StringRef text, return false; Len = text.size(); - return file.substr(Offs.getOffset()).startswith(text); + return file.substr(Offs.getOffset()).starts_with(text); } bool Commit::isAtStartOfMacroExpansion(SourceLocation loc, diff --git a/clang/lib/Edit/RewriteObjCFoundationAPI.cpp b/clang/lib/Edit/RewriteObjCFoundationAPI.cpp index adb34eba4970..d5bf553e2412 100644 --- a/clang/lib/Edit/RewriteObjCFoundationAPI.cpp +++ b/clang/lib/Edit/RewriteObjCFoundationAPI.cpp @@ -697,7 +697,7 @@ static bool getLiteralInfo(SourceRange literalRange, struct Suff { static bool has(StringRef suff, StringRef &text) { - if (text.endswith(suff)) { + if (text.ends_with(suff)) { text = text.substr(0, text.size()-suff.size()); return true; } @@ -739,9 +739,9 @@ static bool getLiteralInfo(SourceRange literalRange, Info.F = UpperF ? "F" : "f"; Info.Hex = Info.Octal = false; - if (text.startswith("0x")) + if (text.starts_with("0x")) Info.Hex = true; - else if (!isFloat && !isIntZero && text.startswith("0")) + else if (!isFloat && !isIntZero && text.starts_with("0")) Info.Octal = true; SourceLocation B = literalRange.getBegin(); diff --git a/clang/lib/ExtractAPI/ExtractAPIConsumer.cpp b/clang/lib/ExtractAPI/ExtractAPIConsumer.cpp index fe282dfb19e8..fd62d841197d 100644 --- a/clang/lib/ExtractAPI/ExtractAPIConsumer.cpp +++ b/clang/lib/ExtractAPI/ExtractAPIConsumer.cpp @@ -105,10 +105,10 @@ std::optional<std::string> getRelativeIncludeName(const CompilerInstance &CI, // Special case Apple .sdk folders since the search path is typically a // symlink like `iPhoneSimulator14.5.sdk` while the file is instead // located in `iPhoneSimulator.sdk` (the real folder). - if (NI->endswith(".sdk") && DI->endswith(".sdk")) { + if (NI->ends_with(".sdk") && DI->ends_with(".sdk")) { StringRef NBasename = path::stem(*NI); StringRef DBasename = path::stem(*DI); - if (DBasename.startswith(NBasename)) + if (DBasename.starts_with(NBasename)) continue; } diff --git a/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp b/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp index d9675b0c94de..53b22297ee0e 100644 --- a/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp +++ b/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp @@ -743,7 +743,7 @@ bool SymbolGraphSerializer::shouldSkip(const APIRecord &Record) const { // Filter out symbols prefixed with an underscored as they are understood to // be symbols clients should not use. - if (Record.Name.startswith("_")) + if (Record.Name.starts_with("_")) return true; return false; diff --git a/clang/lib/Format/BreakableToken.cpp b/clang/lib/Format/BreakableToken.cpp index 954eeb9a6f24..473908e8fee3 100644 --- a/clang/lib/Format/BreakableToken.cpp +++ b/clang/lib/Format/BreakableToken.cpp @@ -55,7 +55,7 @@ static StringRef getLineCommentIndentPrefix(StringRef Comment, })); for (StringRef KnownPrefix : KnownPrefixes) { - if (Comment.startswith(KnownPrefix)) { + if (Comment.starts_with(KnownPrefix)) { const auto PrefixLength = Comment.find_first_not_of(' ', KnownPrefix.size()); return Comment.substr(0, PrefixLength); @@ -220,8 +220,8 @@ bool switchesFormatting(const FormatToken &Token) { assert((Token.is(TT_BlockComment) || Token.is(TT_LineComment)) && "formatting regions are switched by comment tokens"); StringRef Content = Token.TokenText.substr(2).ltrim(); - return Content.startswith("clang-format on") || - Content.startswith("clang-format off"); + return Content.starts_with("clang-format on") || + Content.starts_with("clang-format off"); } unsigned @@ -271,7 +271,7 @@ BreakableStringLiteral::BreakableStringLiteral( : BreakableToken(Tok, InPPDirective, Encoding, Style), StartColumn(StartColumn), Prefix(Prefix), Postfix(Postfix), UnbreakableTailLength(UnbreakableTailLength) { - assert(Tok.TokenText.startswith(Prefix) && Tok.TokenText.endswith(Postfix)); + assert(Tok.TokenText.starts_with(Prefix) && Tok.TokenText.ends_with(Postfix)); Line = Tok.TokenText.substr( Prefix.size(), Tok.TokenText.size() - Prefix.size() - Postfix.size()); } @@ -454,7 +454,7 @@ static bool mayReflowContent(StringRef Content) { bool hasSpecialMeaningPrefix = false; for (StringRef Prefix : {"@", "TODO", "FIXME", "XXX", "-# ", "- ", "+ ", "* "}) { - if (Content.startswith(Prefix)) { + if (Content.starts_with(Prefix)) { hasSpecialMeaningPrefix = true; break; } @@ -471,7 +471,7 @@ static bool mayReflowContent(StringRef Content) { // characters and either the first or second character must be // non-punctuation. return Content.size() >= 2 && !hasSpecialMeaningPrefix && - !Content.endswith("\\") && + !Content.ends_with("\\") && // Note that this is UTF-8 safe, since if isPunctuation(Content[0]) is // true, then the first code point must be 1 byte long. (!isPunctuation(Content[0]) || !isPunctuation(Content[1])); @@ -488,7 +488,7 @@ BreakableBlockComment::BreakableBlockComment( "block comment section must start with a block comment"); StringRef TokenText(Tok.TokenText); - assert(TokenText.startswith("/*") && TokenText.endswith("*/")); + assert(TokenText.starts_with("/*") && TokenText.ends_with("*/")); TokenText.substr(2, TokenText.size() - 4) .split(Lines, UseCRLF ? "\r\n" : "\n"); @@ -511,7 +511,7 @@ BreakableBlockComment::BreakableBlockComment( // /* // ** blah blah blah // */ - if (Lines.size() >= 2 && Content[1].startswith("**") && + if (Lines.size() >= 2 && Content[1].starts_with("**") && static_cast<unsigned>(ContentColumn[1]) == StartColumn) { DecorationColumn = StartColumn; } @@ -531,10 +531,10 @@ BreakableBlockComment::BreakableBlockComment( // If the last line is empty, the closing "*/" will have a star. if (Text.empty()) break; - } else if (!Text.empty() && Decoration.startswith(Text)) { + } else if (!Text.empty() && Decoration.starts_with(Text)) { continue; } - while (!Text.startswith(Decoration)) + while (!Text.starts_with(Decoration)) Decoration = Decoration.drop_back(1); } @@ -562,13 +562,13 @@ BreakableBlockComment::BreakableBlockComment( // The last line excludes the star if LastLineNeedsDecoration is false. // For all other lines, adjust the line to exclude the star and // (optionally) the first whitespace. - unsigned DecorationSize = Decoration.startswith(Content[i]) + unsigned DecorationSize = Decoration.starts_with(Content[i]) ? Content[i].size() : Decoration.size(); if (DecorationSize) ContentColumn[i] = DecorationColumn + DecorationSize; Content[i] = Content[i].substr(DecorationSize); - if (!Decoration.startswith(Content[i])) { + if (!Decoration.starts_with(Content[i])) { IndentAtLineBreak = std::min<int>(IndentAtLineBreak, std::max(0, ContentColumn[i])); } @@ -577,10 +577,10 @@ BreakableBlockComment::BreakableBlockComment( // Detect a multiline jsdoc comment and set DelimitersOnNewline in that case. if (Style.isJavaScript() || Style.Language == FormatStyle::LK_Java) { - if ((Lines[0] == "*" || Lines[0].startswith("* ")) && Lines.size() > 1) { + if ((Lines[0] == "*" || Lines[0].starts_with("* ")) && Lines.size() > 1) { // This is a multiline jsdoc comment. DelimitersOnNewline = true; - } else if (Lines[0].startswith("* ") && Lines.size() == 1) { + } else if (Lines[0].starts_with("* ") && Lines.size() == 1) { // Detect a long single-line comment, like: // /** long long long */ // Below, '2' is the width of '*/'. @@ -612,7 +612,7 @@ BreakableToken::Split BreakableBlockComment::getSplit( return Split(StringRef::npos, 0); return getCommentSplit(Content[LineIndex].substr(TailOffset), ContentStartColumn, ColumnLimit, Style.TabWidth, - Encoding, Style, Decoration.endswith("*")); + Encoding, Style, Decoration.ends_with("*")); } void BreakableBlockComment::adjustWhitespace(unsigned LineIndex, @@ -623,7 +623,7 @@ void BreakableBlockComment::adjustWhitespace(unsigned LineIndex, // trimming the trailing whitespace. The backslash will be re-added later when // inserting a line break. size_t EndOfPreviousLine = Lines[LineIndex - 1].size(); - if (InPPDirective && Lines[LineIndex - 1].endswith("\\")) + if (InPPDirective && Lines[LineIndex - 1].ends_with("\\")) --EndOfPreviousLine; // Calculate the end of the non-whitespace text in the previous line. @@ -672,7 +672,7 @@ unsigned BreakableBlockComment::getRemainingLength(unsigned LineIndex, // We never need a decoration when breaking just the trailing "*/" postfix. bool HasRemainingText = Offset < Content[LineIndex].size(); if (!HasRemainingText) { - bool HasDecoration = Lines[LineIndex].ltrim().startswith(Decoration); + bool HasDecoration = Lines[LineIndex].ltrim().starts_with(Decoration); if (HasDecoration) LineLength -= Decoration.size(); } @@ -700,7 +700,7 @@ unsigned BreakableBlockComment::getContentIndent(unsigned LineIndex) const { // /** line 0 */ // is "* line 0", so we need to skip over the decoration in that case. StringRef ContentWithNoDecoration = Content[LineIndex]; - if (LineIndex == 0 && ContentWithNoDecoration.startswith("*")) + if (LineIndex == 0 && ContentWithNoDecoration.starts_with("*")) ContentWithNoDecoration = ContentWithNoDecoration.substr(1).ltrim(Blanks); StringRef FirstWord = ContentWithNoDecoration.substr( 0, ContentWithNoDecoration.find_first_of(Blanks)); @@ -853,7 +853,7 @@ bool BreakableBlockComment::mayReflow( // Content[LineIndex] may exclude the indent after the '*' decoration. In that // case, we compute the start of the comment pragma manually. StringRef IndentContent = Content[LineIndex]; - if (Lines[LineIndex].ltrim(Blanks).startswith("*")) + if (Lines[LineIndex].ltrim(Blanks).starts_with("*")) IndentContent = Lines[LineIndex].ltrim(Blanks).substr(1); return LineIndex > 0 && !CommentPragmasRegex.match(IndentContent) && mayReflowContent(Content[LineIndex]) && !Tok.Finalized && @@ -876,7 +876,7 @@ BreakableLineCommentSection::BreakableLineCommentSection( CurrentTok = CurrentTok->Next) { LastLineTok = LineTok; StringRef TokenText(CurrentTok->TokenText); - assert((TokenText.startswith("//") || TokenText.startswith("#")) && + assert((TokenText.starts_with("//") || TokenText.starts_with("#")) && "unsupported line comment prefix, '//' and '#' are supported"); size_t FirstLineIndex = Lines.size(); TokenText.split(Lines, "\n"); @@ -913,7 +913,7 @@ BreakableLineCommentSection::BreakableLineCommentSection( // ######### // # section // ######### - if (FirstCommentChar == '#' && !TokenText.startswith("#")) + if (FirstCommentChar == '#' && !TokenText.starts_with("#")) return false; return FirstCommentChar == '\\' || isPunctuation(FirstCommentChar) || isHorizontalWhitespace(FirstCommentChar); @@ -1152,7 +1152,7 @@ bool BreakableLineCommentSection::mayReflow( // Line comments have the indent as part of the prefix, so we need to // recompute the start of the line. StringRef IndentContent = Content[LineIndex]; - if (Lines[LineIndex].startswith("//")) + if (Lines[LineIndex].starts_with("//")) IndentContent = Lines[LineIndex].substr(2); // FIXME: Decide whether we want to reflow non-regular indents: // Currently, we only reflow when the OriginalPrefix[LineIndex] matches the diff --git a/clang/lib/Format/ContinuationIndenter.cpp b/clang/lib/Format/ContinuationIndenter.cpp index 9e4e939503df..bd319f21b05f 100644 --- a/clang/lib/Format/ContinuationIndenter.cpp +++ b/clang/lib/Format/ContinuationIndenter.cpp @@ -161,7 +161,7 @@ static bool opensProtoMessageField(const FormatToken &LessTok, // string. For example, the delimiter of R"deli(cont)deli" is deli. static std::optional<StringRef> getRawStringDelimiter(StringRef TokenText) { if (TokenText.size() < 5 // The smallest raw string possible is 'R"()"'. - || !TokenText.startswith("R\"") || !TokenText.endswith("\"")) { + || !TokenText.starts_with("R\"") || !TokenText.ends_with("\"")) { return std::nullopt; } @@ -177,7 +177,7 @@ static std::optional<StringRef> getRawStringDelimiter(StringRef TokenText) { size_t RParenPos = TokenText.size() - Delimiter.size() - 2; if (TokenText[RParenPos] != ')') return std::nullopt; - if (!TokenText.substr(RParenPos + 1).startswith(Delimiter)) + if (!TokenText.substr(RParenPos + 1).starts_with(Delimiter)) return std::nullopt; return Delimiter; } @@ -608,7 +608,7 @@ bool ContinuationIndenter::mustBreak(const LineState &State) { if (Current.is(tok::lessless) && ((Previous.is(tok::identifier) && Previous.TokenText == "endl") || - (Previous.Tok.isLiteral() && (Previous.TokenText.endswith("\\n\"") || + (Previous.Tok.isLiteral() && (Previous.TokenText.ends_with("\\n\"") || Previous.TokenText == "\'\\n\'")))) { return true; } @@ -2293,12 +2293,13 @@ ContinuationIndenter::createBreakableToken(const FormatToken &Current, if (Style.isVerilog() || Style.Language == FormatStyle::LK_Java || Style.isJavaScript() || Style.isCSharp()) { BreakableStringLiteralUsingOperators::QuoteStyleType QuoteStyle; - if (Style.isJavaScript() && Text.startswith("'") && Text.endswith("'")) { + if (Style.isJavaScript() && Text.starts_with("'") && + Text.ends_with("'")) { QuoteStyle = BreakableStringLiteralUsingOperators::SingleQuotes; - } else if (Style.isCSharp() && Text.startswith("@\"") && - Text.endswith("\"")) { + } else if (Style.isCSharp() && Text.starts_with("@\"") && + Text.ends_with("\"")) { QuoteStyle = BreakableStringLiteralUsingOperators::AtDoubleQuotes; - } else if (Text.startswith("\"") && Text.endswith("\"")) { + } else if (Text.starts_with("\"") && Text.ends_with("\"")) { QuoteStyle = BreakableStringLiteralUsingOperators::DoubleQuotes; } else { return nullptr; @@ -2315,12 +2316,14 @@ ContinuationIndenter::createBreakableToken(const FormatToken &Current, // FIXME: Store Prefix and Suffix (or PrefixLength and SuffixLength to // reduce the overhead) for each FormatToken, which is a string, so that we // don't run multiple checks here on the hot path. - if ((Text.endswith(Postfix = "\"") && - (Text.startswith(Prefix = "@\"") || Text.startswith(Prefix = "\"") || - Text.startswith(Prefix = "u\"") || Text.startswith(Prefix = "U\"") || - Text.startswith(Prefix = "u8\"") || - Text.startswith(Prefix = "L\""))) || - (Text.startswith(Prefix = "_T(\"") && Text.endswith(Postfix = "\")"))) { + if ((Text.ends_with(Postfix = "\"") && + (Text.starts_with(Prefix = "@\"") || Text.starts_with(Prefix = "\"") || + Text.starts_with(Prefix = "u\"") || + Text.starts_with(Prefix = "U\"") || + Text.starts_with(Prefix = "u8\"") || + Text.starts_with(Prefix = "L\""))) || + (Text.starts_with(Prefix = "_T(\"") && + Text.ends_with(Postfix = "\")"))) { return std::make_unique<BreakableStringLiteral>( Current, StartColumn, Prefix, Postfix, UnbreakableTailLength, State.Line->InPPDirective, Encoding, Style); @@ -2342,7 +2345,7 @@ ContinuationIndenter::createBreakableToken(const FormatToken &Current, bool RegularComments = [&]() { for (const FormatToken *T = &Current; T && T->is(TT_LineComment); T = T->Next) { - if (!(T->TokenText.startswith("//") || T->TokenText.startswith("#"))) + if (!(T->TokenText.starts_with("//") || T->TokenText.starts_with("#"))) return false; } return true; @@ -2754,7 +2757,7 @@ bool ContinuationIndenter::nextIsMultilineString(const LineState &State) { // We never consider raw string literals "multiline" for the purpose of // AlwaysBreakBeforeMultilineStrings implementation as they are special-cased // (see TokenAnnotator::mustBreakBefore(). - if (Current.TokenText.startswith("R\"")) + if (Current.TokenText.starts_with("R\"")) return false; if (Current.IsMultiline) return true; diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp index 8feee7457fc3..668e959a9416 100644 --- a/clang/lib/Format/Format.cpp +++ b/clang/lib/Format/Format.cpp @@ -2346,9 +2346,9 @@ private: // NB: testing for not starting with a double quote to avoid // breaking `template strings`. (Style.JavaScriptQuotes == FormatStyle::JSQS_Single && - !Input.startswith("\"")) || + !Input.starts_with("\"")) || (Style.JavaScriptQuotes == FormatStyle::JSQS_Double && - !Input.startswith("\'"))) { + !Input.starts_with("\'"))) { continue; } @@ -2932,7 +2932,7 @@ private: }; for (auto *Line : AnnotatedLines) { - if (Line->First && (Line->First->TokenText.startswith("#") || + if (Line->First && (Line->First->TokenText.starts_with("#") || Line->First->TokenText == "__pragma" || Line->First->TokenText == "_Pragma")) { continue; @@ -3217,7 +3217,7 @@ tooling::Replacements sortCppIncludes(const FormatStyle &Style, StringRef Code, Style.IncludeStyle.IncludeBlocks == tooling::IncludeStyle::IBS_Regroup); - bool MergeWithNextLine = Trimmed.endswith("\\"); + bool MergeWithNextLine = Trimmed.ends_with("\\"); if (!FormattingOff && !MergeWithNextLine) { if (tooling::HeaderIncludes::IncludeRegex.match(Line, &Matches)) { StringRef IncludeName = Matches[2]; @@ -3243,7 +3243,7 @@ tooling::Replacements sortCppIncludes(const FormatStyle &Style, StringRef Code, sortCppIncludes(Style, IncludesInBlock, Ranges, FileName, Code, Replaces, Cursor); IncludesInBlock.clear(); - if (Trimmed.startswith("#pragma hdrstop")) // Precompiled headers. + if (Trimmed.starts_with("#pragma hdrstop")) // Precompiled headers. FirstIncludeBlock = true; else FirstIncludeBlock = false; @@ -3271,7 +3271,7 @@ static unsigned findJavaImportGroup(const FormatStyle &Style, unsigned LongestMatchLength = 0; for (unsigned I = 0; I < Style.JavaImportGroups.size(); I++) { const std::string &GroupPrefix = Style.JavaImportGroups[I]; - if (ImportIdentifier.startswith(GroupPrefix) && + if (ImportIdentifier.starts_with(GroupPrefix) && GroupPrefix.length() > LongestMatchLength) { LongestMatchIndex = I; LongestMatchLength = GroupPrefix.length(); @@ -3426,7 +3426,7 @@ bool isMpegTS(StringRef Code) { return Code.size() > 188 && Code[0] == 0x47 && Code[188] == 0x47; } -bool isLikelyXml(StringRef Code) { return Code.ltrim().startswith("<"); } +bool isLikelyXml(StringRef Code) { return Code.ltrim().starts_with("<"); } tooling::Replacements sortIncludes(const FormatStyle &Style, StringRef Code, ArrayRef<tooling::Range> Ranges, @@ -3538,7 +3538,7 @@ fixCppIncludeInsertions(StringRef Code, const tooling::Replacements &Replaces, for (const auto &Header : HeadersToDelete) { tooling::Replacements Replaces = - Includes.remove(Header.trim("\"<>"), Header.startswith("<")); + Includes.remove(Header.trim("\"<>"), Header.starts_with("<")); for (const auto &R : Replaces) { auto Err = Result.add(R); if (Err) { @@ -3560,7 +3560,7 @@ fixCppIncludeInsertions(StringRef Code, const tooling::Replacements &Replaces, (void)Matched; auto IncludeName = Matches[2]; auto Replace = - Includes.insert(IncludeName.trim("\"<>"), IncludeName.startswith("<"), + Includes.insert(IncludeName.trim("\"<>"), IncludeName.starts_with("<"), tooling::IncludeDirective::Include); if (Replace) { auto Err = Result.add(*Replace); @@ -3882,14 +3882,14 @@ const char *StyleOptionHelpDescription = " --style=\"{BasedOnStyle: llvm, IndentWidth: 8}\""; static FormatStyle::LanguageKind getLanguageByFileName(StringRef FileName) { - if (FileName.endswith(".java")) + if (FileName.ends_with(".java")) return FormatStyle::LK_Java; if (FileName.ends_with_insensitive(".js") || FileName.ends_with_insensitive(".mjs") || FileName.ends_with_insensitive(".ts")) { return FormatStyle::LK_JavaScript; // (module) JavaScript or TypeScript. } - if (FileName.endswith(".m") || FileName.endswith(".mm")) + if (FileName.ends_with(".m") || FileName.ends_with(".mm")) return FormatStyle::LK_ObjC; if (FileName.ends_with_insensitive(".proto") || FileName.ends_with_insensitive(".protodevel")) { @@ -3963,7 +3963,7 @@ llvm::Expected<FormatStyle> getStyle(StringRef StyleName, StringRef FileName, llvm::SmallVector<std::unique_ptr<llvm::MemoryBuffer>, 1> ChildFormatTextToApply; - if (StyleName.startswith("{")) { + if (StyleName.starts_with("{")) { // Parse YAML/JSON style from the command line. StringRef Source = "<command-line>"; if (std::error_code ec = @@ -4123,7 +4123,7 @@ static bool isClangFormatOnOff(StringRef Comment, bool On) { static const char ClangFormatOff[] = "// clang-format off"; const unsigned Size = (On ? sizeof ClangFormatOn : sizeof ClangFormatOff) - 1; - return Comment.startswith(On ? ClangFormatOn : ClangFormatOff) && + return Comment.starts_with(On ? ClangFormatOn : ClangFormatOff) && (Comment.size() == Size || Comment[Size] == ':'); } diff --git a/clang/lib/Format/FormatToken.h b/clang/lib/Format/FormatToken.h index 14a3c21ba44e..3f9664f8f78a 100644 --- a/clang/lib/Format/FormatToken.h +++ b/clang/lib/Format/FormatToken.h @@ -667,7 +667,7 @@ public: /// Returns whether \p Tok is ([{ or an opening < of a template or in /// protos. bool opensScope() const { - if (is(TT_TemplateString) && TokenText.endswith("${")) + if (is(TT_TemplateString) && TokenText.ends_with("${")) return true; if (is(TT_DictLiteral) && is(tok::less)) return true; @@ -677,7 +677,7 @@ public: /// Returns whether \p Tok is )]} or a closing > of a template or in /// protos. bool closesScope() const { - if (is(TT_TemplateString) && TokenText.startswith("}")) + if (is(TT_TemplateString) && TokenText.starts_with("}")) return true; if (is(TT_DictLiteral) && is(tok::greater)) return true; @@ -743,9 +743,9 @@ public: if (isNot(tok::string_literal)) return false; StringRef Content = TokenText; - if (Content.startswith("\"") || Content.startswith("'")) + if (Content.starts_with("\"") || Content.starts_with("'")) Content = Content.drop_front(1); - if (Content.endswith("\"") || Content.endswith("'")) + if (Content.ends_with("\"") || Content.ends_with("'")) Content = Content.drop_back(1); Content = Content.trim(); return Content.size() > 1 && @@ -1823,7 +1823,7 @@ private: }; inline bool isLineComment(const FormatToken &FormatTok) { - return FormatTok.is(tok::comment) && !FormatTok.TokenText.startswith("/*"); + return FormatTok.is(tok::comment) && !FormatTok.TokenText.starts_with("/*"); } // Checks if \p FormatTok is a line comment that continues the line comment diff --git a/clang/lib/Format/FormatTokenLexer.cpp b/clang/lib/Format/FormatTokenLexer.cpp index e4e32e2671df..61430282c6f8 100644 --- a/clang/lib/Format/FormatTokenLexer.cpp +++ b/clang/lib/Format/FormatTokenLexer.cpp @@ -711,12 +711,12 @@ void FormatTokenLexer::handleCSharpVerbatimAndInterpolatedStrings() { bool Verbatim = false; bool Interpolated = false; - if (TokenText.startswith(R"($@")") || TokenText.startswith(R"(@$")")) { + if (TokenText.starts_with(R"($@")") || TokenText.starts_with(R"(@$")")) { Verbatim = true; Interpolated = true; - } else if (TokenText.startswith(R"(@")")) { + } else if (TokenText.starts_with(R"(@")")) { Verbatim = true; - } else if (TokenText.startswith(R"($")")) { + } else if (TokenText.starts_with(R"($")")) { Interpolated = true; } @@ -1110,7 +1110,7 @@ FormatToken *FormatTokenLexer::getNextToken() { // the comment token at the backslash, and resets the lexer to restart behind // the backslash. if ((Style.isJavaScript() || Style.Language == FormatStyle::LK_Java) && - FormatTok->is(tok::comment) && FormatTok->TokenText.startswith("//")) { + FormatTok->is(tok::comment) && FormatTok->TokenText.starts_with("//")) { size_t BackslashPos = FormatTok->TokenText.find('\\'); while (BackslashPos != StringRef::npos) { if (BackslashPos + 1 < FormatTok->TokenText.size() && diff --git a/clang/lib/Format/SortJavaScriptImports.cpp b/clang/lib/Format/SortJavaScriptImports.cpp index 8c6722e91534..1a6a1b19e702 100644 --- a/clang/lib/Format/SortJavaScriptImports.cpp +++ b/clang/lib/Format/SortJavaScriptImports.cpp @@ -468,10 +468,10 @@ private: // URL = TokenText without the quotes. Reference.URL = Current->TokenText.substr(1, Current->TokenText.size() - 2); - if (Reference.URL.startswith("..")) { + if (Reference.URL.starts_with("..")) { Reference.Category = JsModuleReference::ReferenceCategory::RELATIVE_PARENT; - } else if (Reference.URL.startswith(".")) { + } else if (Reference.URL.starts_with(".")) { Reference.Category = JsModuleReference::ReferenceCategory::RELATIVE; } else { Reference.Category = JsModuleReference::ReferenceCategory::ABSOLUTE; diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index eaccb5881ca3..febd6830eca1 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -1307,7 +1307,7 @@ private: if (Previous->isOneOf(TT_BinaryOperator, TT_UnaryOperator, tok::comma, tok::star, tok::arrow, tok::amp, tok::ampamp) || // User defined literal. - Previous->TokenText.startswith("\"\"")) { + Previous->TokenText.starts_with("\"\"")) { Previous->setType(TT_OverloadedOperator); if (CurrentToken->isOneOf(tok::less, tok::greater)) break; @@ -1466,7 +1466,7 @@ private: // Mark tokens up to the trailing line comments as implicit string // literals. if (CurrentToken->isNot(tok::comment) && - !CurrentToken->TokenText.startswith("//")) { + !CurrentToken->TokenText.starts_with("//")) { CurrentToken->setType(TT_ImplicitStringLiteral); } next(); @@ -2077,8 +2077,8 @@ private: } Current.setType(TT_BinaryOperator); } else if (Current.is(tok::comment)) { - if (Current.TokenText.startswith("/*")) { - if (Current.TokenText.endswith("*/")) { + if (Current.TokenText.starts_with("/*")) { + if (Current.TokenText.ends_with("*/")) { Current.setType(TT_BlockComment); } else { // The lexer has for some reason determined a comment here. But we @@ -3724,8 +3724,8 @@ unsigned TokenAnnotator::splitPenalty(const AnnotatedLine &Line, return 100; if (Left.is(TT_JsTypeColon)) return 35; - if ((Left.is(TT_TemplateString) && Left.TokenText.endswith("${")) || - (Right.is(TT_TemplateString) && Right.TokenText.startswith("}"))) { + if ((Left.is(TT_TemplateString) && Left.TokenText.ends_with("${")) || + (Right.is(TT_TemplateString) && Right.TokenText.starts_with("}"))) { return 100; } // Prefer breaking call chains (".foo") over empty "{}", "[]" or "()". @@ -4224,7 +4224,7 @@ bool TokenAnnotator::spaceRequiredBetween(const AnnotatedLine &Line, } if (Left.is(TT_BlockComment)) { // No whitespace in x(/*foo=*/1), except for JavaScript. - return Style.isJavaScript() || !Left.TokenText.endswith("=*/"); + return Style.isJavaScript() || !Left.TokenText.ends_with("=*/"); } // Space between template and attribute. @@ -4572,8 +4572,8 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line, if (Next && Next->is(TT_FatArrow)) return true; } - if ((Left.is(TT_TemplateString) && Left.TokenText.endswith("${")) || - (Right.is(TT_TemplateString) && Right.TokenText.startswith("}"))) { + if ((Left.is(TT_TemplateString) && Left.TokenText.ends_with("${")) || + (Right.is(TT_TemplateString) && Right.TokenText.starts_with("}"))) { return false; } // In tagged template literals ("html`bar baz`"), there is no space between @@ -5212,7 +5212,7 @@ bool TokenAnnotator::mustBreakBefore(const AnnotatedLine &Line, Left.is(TT_InheritanceComma)) { return true; } - if (Right.is(tok::string_literal) && Right.TokenText.startswith("R\"")) { + if (Right.is(tok::string_literal) && Right.TokenText.starts_with("R\"")) { // Multiline raw string literals are special wrt. line breaks. The author // has made a deliberate choice and might have aligned the contents of the // string literal accordingly. Thus, we try keep existing line breaks. diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index 57126b8dfeac..c38b4c884070 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -1333,7 +1333,7 @@ bool UnwrappedLineParser::parseModuleImport() { // Mark tokens up to the trailing line comments as implicit string // literals. if (FormatTok->isNot(tok::comment) && - !FormatTok->TokenText.startswith("//")) { + !FormatTok->TokenText.starts_with("//")) { FormatTok->setFinalizedType(TT_ImplicitStringLiteral); } nextToken(); @@ -1371,7 +1371,7 @@ void UnwrappedLineParser::readTokenWithJavaScriptASI() { bool PreviousMustBeValue = mustBeJSIdentOrValue(Keywords, Previous); bool PreviousStartsTemplateExpr = - Previous->is(TT_TemplateString) && Previous->TokenText.endswith("${"); + Previous->is(TT_TemplateString) && Previous->TokenText.ends_with("${"); if (PreviousMustBeValue || Previous->is(tok::r_paren)) { // If the line contains an '@' sign, the previous token might be an // annotation, which can precede another identifier/value. @@ -1385,7 +1385,7 @@ void UnwrappedLineParser::readTokenWithJavaScriptASI() { return addUnwrappedLine(); bool NextMustBeValue = mustBeJSIdentOrValue(Keywords, Next); bool NextEndsTemplateExpr = - Next->is(TT_TemplateString) && Next->TokenText.startswith("}"); + Next->is(TT_TemplateString) && Next->TokenText.starts_with("}"); if (NextMustBeValue && !NextEndsTemplateExpr && !PreviousStartsTemplateExpr && (PreviousMustBeValue || Previous->isOneOf(tok::r_square, tok::r_paren, tok::plusplus, @@ -4459,8 +4459,8 @@ continuesLineCommentSection(const FormatToken &FormatTok, return false; StringRef IndentContent = FormatTok.TokenText; - if (FormatTok.TokenText.startswith("//") || - FormatTok.TokenText.startswith("/*")) { + if (FormatTok.TokenText.starts_with("//") || + FormatTok.TokenText.starts_with("/*")) { IndentContent = FormatTok.TokenText.substr(2); } if (CommentPragmasRegex.match(IndentContent)) diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index b33bdad2ad81..11f3f2c2d642 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -2829,7 +2829,7 @@ static bool ParseFrontendArgs(FrontendOptions &Opts, ArgList &Args, "-interface-stub-version=ifs-v1" << ErrorMessage; ProgramAction = frontend::ParseSyntaxOnly; - } else if (!ArgStr.startswith("ifs-")) { + } else if (!ArgStr.starts_with("ifs-")) { std::string ErrorMessage = "Invalid interface stub format: " + ArgStr.str() + "."; Diags.Report(diag::err_drv_invalid_value) @@ -4106,13 +4106,13 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args, // Check the version number is valid: either 3.x (0 <= x <= 9) or // y or y.0 (4 <= y <= current version). - if (!VerParts.first.startswith("0") && - !VerParts.first.getAsInteger(10, Major) && - 3 <= Major && Major <= CLANG_VERSION_MAJOR && - (Major == 3 ? VerParts.second.size() == 1 && - !VerParts.second.getAsInteger(10, Minor) - : VerParts.first.size() == Ver.size() || - VerParts.second == "0")) { + if (!VerParts.first.starts_with("0") && + !VerParts.first.getAsInteger(10, Major) && 3 <= Major && + Major <= CLANG_VERSION_MAJOR && + (Major == 3 + ? VerParts.second.size() == 1 && + !VerParts.second.getAsInteger(10, Minor) + : VerParts.first.size() == Ver.size() || VerParts.second == "0")) { // Got a valid version number. if (Major == 3 && Minor <= 8) Opts.setClangABICompat(LangOptions::ClangABI::Ver3_8); diff --git a/clang/lib/Frontend/DependencyGraph.cpp b/clang/lib/Frontend/DependencyGraph.cpp index 6aad04370f6e..e96669f856bb 100644 --- a/clang/lib/Frontend/DependencyGraph.cpp +++ b/clang/lib/Frontend/DependencyGraph.cpp @@ -110,7 +110,7 @@ void DependencyGraphCallback::OutputGraphFile() { writeNodeReference(OS, AllFiles[I]); OS << " [ shape=\"box\", label=\""; StringRef FileName = AllFiles[I].getName(); - if (FileName.startswith(SysRoot)) + if (FileName.starts_with(SysRoot)) FileName = FileName.substr(SysRoot.size()); OS << DOT::EscapeString(std::string(FileName)) << "\"];\n"; diff --git a/clang/lib/Frontend/Rewrite/InclusionRewriter.cpp b/clang/lib/Frontend/Rewrite/InclusionRewriter.cpp index 2c3a253a67d5..b6b37461089e 100644 --- a/clang/lib/Frontend/Rewrite/InclusionRewriter.cpp +++ b/clang/lib/Frontend/Rewrite/InclusionRewriter.cpp @@ -307,7 +307,7 @@ void InclusionRewriter::OutputContentUpTo(const MemoryBufferRef &FromFile, Rest = Rest.substr(Idx); } } - if (EnsureNewline && !TextToWrite.endswith(LocalEOL)) + if (EnsureNewline && !TextToWrite.ends_with(LocalEOL)) OS << MainEOL; WriteFrom = WriteTo; diff --git a/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp b/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp index ab8174f4f4db..09c1460d54e1 100644 --- a/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp +++ b/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp @@ -226,10 +226,10 @@ public: P = C; while (P < End) { StringRef S(P, End - P); - if (S.startswith(OpenBrace)) { + if (S.starts_with(OpenBrace)) { ++Depth; P += OpenBrace.size(); - } else if (S.startswith(CloseBrace)) { + } else if (S.starts_with(CloseBrace)) { --Depth; if (Depth == 0) { PEnd = P + CloseBrace.size(); @@ -445,7 +445,7 @@ static bool ParseDirective(StringRef S, ExpectedData *ED, SourceManager &SM, // others. // Regex in initial directive token: -re - if (DToken.endswith("-re")) { + if (DToken.ends_with("-re")) { D.RegexKind = true; KindStr = "regex"; DToken = DToken.substr(0, DToken.size()-3); @@ -454,20 +454,19 @@ static bool ParseDirective(StringRef S, ExpectedData *ED, SourceManager &SM, // Type in initial directive token: -{error|warning|note|no-diagnostics} bool NoDiag = false; StringRef DType; - if (DToken.endswith(DType="-error")) + if (DToken.ends_with(DType = "-error")) D.DL = ED ? &ED->Errors : nullptr; - else if (DToken.endswith(DType="-warning")) + else if (DToken.ends_with(DType = "-warning")) D.DL = ED ? &ED->Warnings : nullptr; - else if (DToken.endswith(DType="-remark")) + else if (DToken.ends_with(DType = "-remark")) D.DL = ED ? &ED->Remarks : nullptr; - else if (DToken.endswith(DType="-note")) + else if (DToken.ends_with(DType = "-note")) D.DL = ED ? &ED->Notes : nullptr; - else if (DToken.endswith(DType="-no-diagnostics")) { + else if (DToken.ends_with(DType = "-no-diagnostics")) { NoDiag = true; if (D.RegexKind) continue; - } - else + } else continue; DToken = DToken.substr(0, DToken.size()-DType.size()); @@ -1145,7 +1144,7 @@ std::unique_ptr<Directive> Directive::create(bool RegexKind, std::string RegexStr; StringRef S = Text; while (!S.empty()) { - if (S.startswith("{{")) { + if (S.starts_with("{{")) { S = S.drop_front(2); size_t RegexMatchLength = S.find("}}"); assert(RegexMatchLength != StringRef::npos); diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt index fdd54c05eedf..f8fdd402777e 100644 --- a/clang/lib/Headers/CMakeLists.txt +++ b/clang/lib/Headers/CMakeLists.txt @@ -387,6 +387,8 @@ if(ARM IN_LIST LLVM_TARGETS_TO_BUILD OR AArch64 IN_LIST LLVM_TARGETS_TO_BUILD) clang_generate_header(-gen-arm-mve-header arm_mve.td arm_mve.h) # Generate arm_cde.h clang_generate_header(-gen-arm-cde-header arm_cde.td arm_cde.h) + # Generate arm_vector_types.h + clang_generate_header(-gen-arm-vector-type arm_neon.td arm_vector_types.h) # Add headers to target specific lists list(APPEND arm_common_generated_files @@ -403,6 +405,7 @@ if(ARM IN_LIST LLVM_TARGETS_TO_BUILD OR AArch64 IN_LIST LLVM_TARGETS_TO_BUILD) "${CMAKE_CURRENT_BINARY_DIR}/arm_sve.h" "${CMAKE_CURRENT_BINARY_DIR}/arm_sme_draft_spec_subject_to_change.h" "${CMAKE_CURRENT_BINARY_DIR}/arm_bf16.h" + "${CMAKE_CURRENT_BINARY_DIR}/arm_vector_types.h" ) endif() if(RISCV IN_LIST LLVM_TARGETS_TO_BUILD) diff --git a/clang/lib/Index/IndexSymbol.cpp b/clang/lib/Index/IndexSymbol.cpp index c67810ad126b..0f79694d1faa 100644 --- a/clang/lib/Index/IndexSymbol.cpp +++ b/clang/lib/Index/IndexSymbol.cpp @@ -36,7 +36,7 @@ static bool isUnitTest(const ObjCMethodDecl *D) { return false; if (!D->getReturnType()->isVoidType()) return false; - if (!D->getSelector().getNameForSlot(0).startswith("test")) + if (!D->getSelector().getNameForSlot(0).starts_with("test")) return false; return isUnitTestCase(D->getClassInterface()); } diff --git a/clang/lib/IndexSerialization/SerializablePathCollection.cpp b/clang/lib/IndexSerialization/SerializablePathCollection.cpp index bd5f861bf482..74ed18a4f612 100644 --- a/clang/lib/IndexSerialization/SerializablePathCollection.cpp +++ b/clang/lib/IndexSerialization/SerializablePathCollection.cpp @@ -70,11 +70,11 @@ PathPool::DirPath SerializablePathCollection::tryStoreDirPath(StringRef Dir) { const std::string OrigDir = Dir.str(); PathPool::RootDirKind Root = PathPool::RootDirKind::Regular; - if (!SysRoot.empty() && Dir.startswith(SysRoot) && + if (!SysRoot.empty() && Dir.starts_with(SysRoot) && llvm::sys::path::is_separator(Dir[SysRoot.size()])) { Root = PathPool::RootDirKind::SysRoot; Dir = Dir.drop_front(SysRoot.size()); - } else if (!WorkDir.empty() && Dir.startswith(WorkDir) && + } else if (!WorkDir.empty() && Dir.starts_with(WorkDir) && llvm::sys::path::is_separator(Dir[WorkDir.size()])) { Root = PathPool::RootDirKind::CurrentWorkDir; Dir = Dir.drop_front(WorkDir.size()); diff --git a/clang/lib/Lex/HeaderMap.cpp b/clang/lib/Lex/HeaderMap.cpp index 22a1532c2d93..00bf880726ee 100644 --- a/clang/lib/Lex/HeaderMap.cpp +++ b/clang/lib/Lex/HeaderMap.cpp @@ -11,16 +11,17 @@ //===----------------------------------------------------------------------===// #include "clang/Lex/HeaderMap.h" -#include "clang/Lex/HeaderMapTypes.h" #include "clang/Basic/CharInfo.h" #include "clang/Basic/FileManager.h" +#include "clang/Lex/HeaderMapTypes.h" #include "llvm/ADT/SmallString.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/DataTypes.h" +#include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SwapByteOrder.h" -#include "llvm/Support/Debug.h" +#include "llvm/Support/SystemZ/zOSSupport.h" #include <cstring> #include <memory> #include <optional> diff --git a/clang/lib/Lex/HeaderSearch.cpp b/clang/lib/Lex/HeaderSearch.cpp index c03cf19688d9..f24013d68795 100644 --- a/clang/lib/Lex/HeaderSearch.cpp +++ b/clang/lib/Lex/HeaderSearch.cpp @@ -796,7 +796,7 @@ static bool isFrameworkStylePath(StringRef Path, bool &IsPrivateHeader, } else if (*I == "PrivateHeaders") { ++FoundComp; IsPrivateHeader = true; - } else if (I->endswith(".framework")) { + } else if (I->ends_with(".framework")) { StringRef Name = I->drop_back(10); // Drop .framework // Need to reset the strings and counter to support nested frameworks. FrameworkName.clear(); @@ -1085,7 +1085,7 @@ OptionalFileEntryRef HeaderSearch::LookupFile( // If the filename matches a known system header prefix, override // whether the file is a system header. for (unsigned j = SystemHeaderPrefixes.size(); j; --j) { - if (Filename.startswith(SystemHeaderPrefixes[j-1].first)) { + if (Filename.starts_with(SystemHeaderPrefixes[j - 1].first)) { HFI.DirInfo = SystemHeaderPrefixes[j-1].second ? SrcMgr::C_System : SrcMgr::C_User; break; @@ -1694,7 +1694,7 @@ bool HeaderSearch::loadModuleMapFile(FileEntryRef File, bool IsSystem, StringRef DirName(Dir->getName()); if (llvm::sys::path::filename(DirName) == "Modules") { DirName = llvm::sys::path::parent_path(DirName); - if (DirName.endswith(".framework")) + if (DirName.ends_with(".framework")) if (auto MaybeDir = FileMgr.getOptionalDirectoryRef(DirName)) Dir = *MaybeDir; // FIXME: This assert can fail if there's a race between the above check @@ -1965,10 +1965,10 @@ std::string HeaderSearch::suggestPathToFileForDiagnostics( // Special case Apple .sdk folders since the search path is typically a // symlink like `iPhoneSimulator14.5.sdk` while the file is instead // located in `iPhoneSimulator.sdk` (the real folder). - if (NI->endswith(".sdk") && DI->endswith(".sdk")) { + if (NI->ends_with(".sdk") && DI->ends_with(".sdk")) { StringRef NBasename = path::stem(*NI); StringRef DBasename = path::stem(*DI); - if (DBasename.startswith(NBasename)) + if (DBasename.starts_with(NBasename)) continue; } diff --git a/clang/lib/Lex/InitHeaderSearch.cpp b/clang/lib/Lex/InitHeaderSearch.cpp index 5b1b7c859c85..2218db15013d 100644 --- a/clang/lib/Lex/InitHeaderSearch.cpp +++ b/clang/lib/Lex/InitHeaderSearch.cpp @@ -141,8 +141,8 @@ bool InitHeaderSearch::AddUnmappedPath(const Twine &Path, IncludeDirGroup Group, StringRef MappedPathStr = Path.toStringRef(MappedPathStorage); // If use system headers while cross-compiling, emit the warning. - if (HasSysroot && (MappedPathStr.startswith("/usr/include") || - MappedPathStr.startswith("/usr/local/include"))) { + if (HasSysroot && (MappedPathStr.starts_with("/usr/include") || + MappedPathStr.starts_with("/usr/local/include"))) { Headers.getDiags().Report(diag::warn_poison_system_directories) << MappedPathStr; } diff --git a/clang/lib/Lex/Lexer.cpp b/clang/lib/Lex/Lexer.cpp index f4f1daab857f..50b56265f6e1 100644 --- a/clang/lib/Lex/Lexer.cpp +++ b/clang/lib/Lex/Lexer.cpp @@ -3212,8 +3212,8 @@ bool Lexer::IsStartOfConflictMarker(const char *CurPtr) { return false; // Check to see if we have <<<<<<< or >>>>. - if (!StringRef(CurPtr, BufferEnd - CurPtr).startswith("<<<<<<<") && - !StringRef(CurPtr, BufferEnd - CurPtr).startswith(">>>> ")) + if (!StringRef(CurPtr, BufferEnd - CurPtr).starts_with("<<<<<<<") && + !StringRef(CurPtr, BufferEnd - CurPtr).starts_with(">>>> ")) return false; // If we have a situation where we don't care about conflict markers, ignore diff --git a/clang/lib/Lex/ModuleMap.cpp b/clang/lib/Lex/ModuleMap.cpp index d35c282543c5..ea5d13deb114 100644 --- a/clang/lib/Lex/ModuleMap.cpp +++ b/clang/lib/Lex/ModuleMap.cpp @@ -235,7 +235,7 @@ OptionalFileEntryRef ModuleMap::findHeader( llvm::sys::path::append(FullPathName, RelativePathName); auto NormalHdrFile = GetFile(FullPathName); - if (!NormalHdrFile && Directory->getName().endswith(".framework")) { + if (!NormalHdrFile && Directory->getName().ends_with(".framework")) { // The lack of 'framework' keyword in a module declaration it's a simple // mistake we can diagnose when the header exists within the proper // framework style path. @@ -1034,7 +1034,7 @@ Module *ModuleMap::inferFrameworkModule(DirectoryEntryRef FrameworkDir, if (inferred == InferredDirectories.end()) { // We haven't looked here before. Load a module map, if there is // one. - bool IsFrameworkDir = Parent.endswith(".framework"); + bool IsFrameworkDir = Parent.ends_with(".framework"); if (OptionalFileEntryRef ModMapFile = HeaderInfo.lookupModuleMapFile(*ParentDir, IsFrameworkDir)) { parseModuleMapFile(*ModMapFile, Attrs.IsSystem, *ParentDir); @@ -1125,7 +1125,7 @@ Module *ModuleMap::inferFrameworkModule(DirectoryEntryRef FrameworkDir, Dir = FS.dir_begin(SubframeworksDirName, EC), DirEnd; Dir != DirEnd && !EC; Dir.increment(EC)) { - if (!StringRef(Dir->path()).endswith(".framework")) + if (!StringRef(Dir->path()).ends_with(".framework")) continue; if (auto SubframeworkDir = FileMgr.getOptionalDirectoryRef(Dir->path())) { @@ -1337,7 +1337,7 @@ ModuleMap::canonicalizeModuleMapPath(SmallVectorImpl<char> &Path) { // Modules/ not Versions/A/Modules. if (llvm::sys::path::filename(Dir) == "Modules") { StringRef Parent = llvm::sys::path::parent_path(Dir); - if (Parent.endswith(".framework")) + if (Parent.ends_with(".framework")) Dir = Parent; } @@ -2119,8 +2119,8 @@ void ModuleMapParser::parseModuleDecl() { ActiveModule->Directory = Directory; StringRef MapFileName(ModuleMapFile.getName()); - if (MapFileName.endswith("module.private.modulemap") || - MapFileName.endswith("module_private.map")) { + if (MapFileName.ends_with("module.private.modulemap") || + MapFileName.ends_with("module_private.map")) { ActiveModule->ModuleMapIsPrivate = true; } diff --git a/clang/lib/Lex/PPDirectives.cpp b/clang/lib/Lex/PPDirectives.cpp index 14003480d7fa..112bc8dc572c 100644 --- a/clang/lib/Lex/PPDirectives.cpp +++ b/clang/lib/Lex/PPDirectives.cpp @@ -164,13 +164,13 @@ static bool isLanguageDefinedBuiltin(const SourceManager &SourceMgr, return false; // C defines macros starting with __STDC, and C++ defines macros starting with // __STDCPP - if (MacroName.startswith("__STDC")) + if (MacroName.starts_with("__STDC")) return true; // C++ defines the __cplusplus macro if (MacroName == "__cplusplus") return true; // C++ defines various feature-test macros starting with __cpp - if (MacroName.startswith("__cpp")) + if (MacroName.starts_with("__cpp")) return true; // Anything else isn't language-defined return false; @@ -646,7 +646,7 @@ void Preprocessor::SkipExcludedConditionalBlock(SourceLocation HashTokenLoc, Directive = StringRef(DirectiveBuf, IdLen); } - if (Directive.startswith("if")) { + if (Directive.starts_with("if")) { StringRef Sub = Directive.substr(2); if (Sub.empty() || // "if" Sub == "def" || // "ifdef" @@ -2788,14 +2788,14 @@ static bool isConfigurationPattern(Token &MacroName, MacroInfo *MI, return false; StringRef ValueText = II->getName(); StringRef TrimmedValue = ValueText; - if (!ValueText.startswith("__")) { - if (ValueText.startswith("_")) + if (!ValueText.starts_with("__")) { + if (ValueText.starts_with("_")) TrimmedValue = TrimmedValue.drop_front(1); else return false; } else { TrimmedValue = TrimmedValue.drop_front(2); - if (TrimmedValue.endswith("__")) + if (TrimmedValue.ends_with("__")) TrimmedValue = TrimmedValue.drop_back(2); } return TrimmedValue.equals(MacroText); diff --git a/clang/lib/Lex/PPExpressions.cpp b/clang/lib/Lex/PPExpressions.cpp index 269984aae07b..1feb0eb18d71 100644 --- a/clang/lib/Lex/PPExpressions.cpp +++ b/clang/lib/Lex/PPExpressions.cpp @@ -267,7 +267,7 @@ static bool EvaluateValue(PPValue &Result, Token &PeekTok, DefinedTracker &DT, const StringRef IdentifierName = II->getName(); if (llvm::any_of(UndefPrefixes, [&IdentifierName](const std::string &Prefix) { - return IdentifierName.startswith(Prefix); + return IdentifierName.starts_with(Prefix); })) PP.Diag(PeekTok, diag::warn_pp_undef_prefix) << AddFlagValue{llvm::join(UndefPrefixes, ",")} << II; diff --git a/clang/lib/Lex/PPMacroExpansion.cpp b/clang/lib/Lex/PPMacroExpansion.cpp index 30c4abdbad8a..ad02f31209b0 100644 --- a/clang/lib/Lex/PPMacroExpansion.cpp +++ b/clang/lib/Lex/PPMacroExpansion.cpp @@ -1136,7 +1136,8 @@ static bool HasFeature(const Preprocessor &PP, StringRef Feature) { const LangOptions &LangOpts = PP.getLangOpts(); // Normalize the feature name, __foo__ becomes foo. - if (Feature.startswith("__") && Feature.endswith("__") && Feature.size() >= 4) + if (Feature.starts_with("__") && Feature.ends_with("__") && + Feature.size() >= 4) Feature = Feature.substr(2, Feature.size() - 4); #define FEATURE(Name, Predicate) .Case(#Name, Predicate) @@ -1162,7 +1163,7 @@ static bool HasExtension(const Preprocessor &PP, StringRef Extension) { const LangOptions &LangOpts = PP.getLangOpts(); // Normalize the extension name, __foo__ becomes foo. - if (Extension.startswith("__") && Extension.endswith("__") && + if (Extension.starts_with("__") && Extension.ends_with("__") && Extension.size() >= 4) Extension = Extension.substr(2, Extension.size() - 4); @@ -1691,9 +1692,9 @@ void Preprocessor::ExpandBuiltinMacro(Token &Tok) { // as being "builtin functions", even if the syntax isn't a valid // function call (for example, because the builtin takes a type // argument). - if (II->getName().startswith("__builtin_") || - II->getName().startswith("__is_") || - II->getName().startswith("__has_")) + if (II->getName().starts_with("__builtin_") || + II->getName().starts_with("__is_") || + II->getName().starts_with("__has_")) return true; return llvm::StringSwitch<bool>(II->getName()) .Case("__array_rank", true) diff --git a/clang/lib/Parse/ParseDecl.cpp b/clang/lib/Parse/ParseDecl.cpp index ece3698967e2..ed006f9d67de 100644 --- a/clang/lib/Parse/ParseDecl.cpp +++ b/clang/lib/Parse/ParseDecl.cpp @@ -84,7 +84,7 @@ TypeResult Parser::ParseTypeName(SourceRange *Range, DeclaratorContext Context, /// Normalizes an attribute name by dropping prefixed and suffixed __. static StringRef normalizeAttrName(StringRef Name) { - if (Name.size() >= 4 && Name.startswith("__") && Name.endswith("__")) + if (Name.size() >= 4 && Name.starts_with("__") && Name.ends_with("__")) return Name.drop_front(2).drop_back(2); return Name; } @@ -7854,7 +7854,7 @@ void Parser::ParseTypeofSpecifier(DeclSpec &DS) { bool IsUnqual = Tok.is(tok::kw_typeof_unqual); const IdentifierInfo *II = Tok.getIdentifierInfo(); - if (getLangOpts().C23 && !II->getName().startswith("__")) + if (getLangOpts().C23 && !II->getName().starts_with("__")) Diag(Tok.getLocation(), diag::warn_c23_compat_keyword) << Tok.getName(); Token OpTok = Tok; diff --git a/clang/lib/Parse/Parser.cpp b/clang/lib/Parse/Parser.cpp index ec67faf7dcaf..b703c2d9b8e0 100644 --- a/clang/lib/Parse/Parser.cpp +++ b/clang/lib/Parse/Parser.cpp @@ -2645,7 +2645,7 @@ Decl *Parser::ParseModuleImport(SourceLocation AtLoc, auto &SrcMgr = PP.getSourceManager(); auto FE = SrcMgr.getFileEntryRefForID(SrcMgr.getFileID(AtLoc)); if (FE && llvm::sys::path::parent_path(FE->getDir().getName()) - .endswith(".framework")) + .ends_with(".framework")) Diags.Report(AtLoc, diag::warn_atimport_in_framework_header); } diff --git a/clang/lib/Rewrite/Rewriter.cpp b/clang/lib/Rewrite/Rewriter.cpp index 0896221dd0bd..0e6ae3650644 100644 --- a/clang/lib/Rewrite/Rewriter.cpp +++ b/clang/lib/Rewrite/Rewriter.cpp @@ -386,7 +386,7 @@ bool Rewriter::IncreaseIndentation(CharSourceRange range, } if (parentSpace.size() >= startSpace.size()) return true; - if (!startSpace.startswith(parentSpace)) + if (!startSpace.starts_with(parentSpace)) return true; StringRef indent = startSpace.substr(parentSpace.size()); @@ -399,7 +399,7 @@ bool Rewriter::IncreaseIndentation(CharSourceRange range, while (isWhitespaceExceptNL(MB[i])) ++i; StringRef origIndent = MB.substr(offs, i-offs); - if (origIndent.startswith(startSpace)) + if (origIndent.starts_with(startSpace)) RB.InsertText(offs, indent, /*InsertAfter=*/false); } diff --git a/clang/lib/Sema/CodeCompleteConsumer.cpp b/clang/lib/Sema/CodeCompleteConsumer.cpp index 9caa1a8431e9..350bd78b5710 100644 --- a/clang/lib/Sema/CodeCompleteConsumer.cpp +++ b/clang/lib/Sema/CodeCompleteConsumer.cpp @@ -630,15 +630,16 @@ bool PrintingCodeCompleteConsumer::isResultFilteredOut( StringRef Filter, CodeCompletionResult Result) { switch (Result.Kind) { case CodeCompletionResult::RK_Declaration: - return !(Result.Declaration->getIdentifier() && - Result.Declaration->getIdentifier()->getName().startswith(Filter)); + return !( + Result.Declaration->getIdentifier() && + Result.Declaration->getIdentifier()->getName().starts_with(Filter)); case CodeCompletionResult::RK_Keyword: - return !StringRef(Result.Keyword).startswith(Filter); + return !StringRef(Result.Keyword).starts_with(Filter); case CodeCompletionResult::RK_Macro: - return !Result.Macro->getName().startswith(Filter); + return !Result.Macro->getName().starts_with(Filter); case CodeCompletionResult::RK_Pattern: return !(Result.Pattern->getTypedText() && - StringRef(Result.Pattern->getTypedText()).startswith(Filter)); + StringRef(Result.Pattern->getTypedText()).starts_with(Filter)); } llvm_unreachable("Unknown code completion result Kind."); } diff --git a/clang/lib/Sema/SemaCXXScopeSpec.cpp b/clang/lib/Sema/SemaCXXScopeSpec.cpp index 44a40215b90d..b3b19b7ed7ff 100644 --- a/clang/lib/Sema/SemaCXXScopeSpec.cpp +++ b/clang/lib/Sema/SemaCXXScopeSpec.cpp @@ -30,6 +30,20 @@ static CXXRecordDecl *getCurrentInstantiationOf(QualType T, return nullptr; const Type *Ty = T->getCanonicalTypeInternal().getTypePtr(); + if (isa<TemplateSpecializationType>(Ty)) { + if (auto *Record = dyn_cast<CXXRecordDecl>(CurContext)) { + if (isa<ClassTemplatePartialSpecializationDecl>(Record) || + Record->getDescribedClassTemplate()) { + const Type *ICNT = Record->getTypeForDecl(); + QualType Injected = + cast<InjectedClassNameType>(ICNT)->getInjectedSpecializationType(); + + if (Ty == Injected->getCanonicalTypeInternal().getTypePtr()) + return Record; + } + } + } + if (const RecordType *RecordTy = dyn_cast<RecordType>(Ty)) { CXXRecordDecl *Record = cast<CXXRecordDecl>(RecordTy->getDecl()); if (!Record->isDependentContext() || @@ -37,10 +51,12 @@ static CXXRecordDecl *getCurrentInstantiationOf(QualType T, return Record; return nullptr; - } else if (isa<InjectedClassNameType>(Ty)) - return cast<InjectedClassNameType>(Ty)->getDecl(); - else - return nullptr; + } + + if (auto *ICNT = dyn_cast<InjectedClassNameType>(Ty)) + return ICNT->getDecl(); + + return nullptr; } /// Compute the DeclContext that is associated with the given type. diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index cdb6e9584e95..254c272b8093 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -1219,7 +1219,7 @@ void Sema::checkFortifiedBuiltinMemoryFunction(FunctionDecl *FD, if (IsChkVariant) { FunctionName = FunctionName.drop_front(std::strlen("__builtin___")); FunctionName = FunctionName.drop_back(std::strlen("_chk")); - } else if (FunctionName.startswith("__builtin_")) { + } else if (FunctionName.starts_with("__builtin_")) { FunctionName = FunctionName.drop_front(std::strlen("__builtin_")); } return FunctionName; @@ -18270,15 +18270,14 @@ static bool isSetterLikeSelector(Selector sel) { StringRef str = sel.getNameForSlot(0); while (!str.empty() && str.front() == '_') str = str.substr(1); - if (str.startswith("set")) + if (str.starts_with("set")) str = str.substr(3); - else if (str.startswith("add")) { + else if (str.starts_with("add")) { // Specially allow 'addOperationWithBlock:'. - if (sel.getNumArgs() == 1 && str.startswith("addOperationWithBlock")) + if (sel.getNumArgs() == 1 && str.starts_with("addOperationWithBlock")) return false; str = str.substr(3); - } - else + } else return false; if (str.empty()) return true; diff --git a/clang/lib/Sema/SemaCodeComplete.cpp b/clang/lib/Sema/SemaCodeComplete.cpp index 143968b4ab04..c44be0df9b0a 100644 --- a/clang/lib/Sema/SemaCodeComplete.cpp +++ b/clang/lib/Sema/SemaCodeComplete.cpp @@ -9798,7 +9798,7 @@ void Sema::CodeCompleteObjCMethodDeclSelector( Results.ExitScope(); if (!AtParameterName && !SelIdents.empty() && - SelIdents.front()->getName().startswith("init")) { + SelIdents.front()->getName().starts_with("init")) { for (const auto &M : PP.macros()) { if (M.first->getName() != "NS_DESIGNATED_INITIALIZER") continue; @@ -10110,7 +10110,7 @@ void Sema::CodeCompleteIncludedFile(llvm::StringRef Dir, bool Angled) { } const StringRef &Dirname = llvm::sys::path::filename(Dir); - const bool isQt = Dirname.startswith("Qt") || Dirname == "ActiveQt"; + const bool isQt = Dirname.starts_with("Qt") || Dirname == "ActiveQt"; const bool ExtensionlessHeaders = IsSystem || isQt || Dir.ends_with(".framework/Headers"); std::error_code EC; diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index 19d972ed8ab2..be6a136ef37b 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -15800,7 +15800,7 @@ Decl *Sema::ActOnSkippedFunctionBody(Decl *Decl) { } Decl *Sema::ActOnFinishFunctionBody(Decl *D, Stmt *BodyArg) { - return ActOnFinishFunctionBody(D, BodyArg, false); + return ActOnFinishFunctionBody(D, BodyArg, /*IsInstantiation=*/false); } /// RAII object that pops an ExpressionEvaluationContext when exiting a function @@ -16005,7 +16005,7 @@ Decl *Sema::ActOnFinishFunctionBody(Decl *dcl, Stmt *Body, return StartTok.consume_front("const") && (StartTok.empty() || isWhitespace(StartTok[0]) || - StartTok.startswith("/*") || StartTok.startswith("//")); + StartTok.starts_with("/*") || StartTok.starts_with("//")); }; auto findBeginLoc = [&]() { @@ -16359,7 +16359,7 @@ NamedDecl *Sema::ImplicitlyDefineFunction(SourceLocation Loc, // Extension in C99 (defaults to error). Legal in C89, but warn about it. unsigned diag_id; - if (II.getName().startswith("__builtin_")) + if (II.getName().starts_with("__builtin_")) diag_id = diag::warn_builtin_unknown; // OpenCL v2.0 s6.9.u - Implicit function declaration is not supported. else if (getLangOpts().C99) diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 59e456fd9f72..22f291ee1133 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -1809,8 +1809,8 @@ static void handleAssumumptionAttr(Sema &S, Decl *D, const ParsedAttr &AL) { /// Normalize the attribute, __foo__ becomes foo. /// Returns true if normalization was applied. static bool normalizeName(StringRef &AttrName) { - if (AttrName.size() > 4 && AttrName.startswith("__") && - AttrName.endswith("__")) { + if (AttrName.size() > 4 && AttrName.starts_with("__") && + AttrName.ends_with("__")) { AttrName = AttrName.drop_front(2).drop_back(2); return true; } @@ -3605,7 +3605,7 @@ bool Sema::checkTargetClonesAttrString( } } else { // Other targets ( currently X86 ) - if (Cur.startswith("arch=")) { + if (Cur.starts_with("arch=")) { if (!Context.getTargetInfo().isValidCPUName( Cur.drop_front(sizeof("arch=") - 1))) return Diag(CurLoc, diag::warn_unsupported_target_attribute) @@ -3623,7 +3623,7 @@ bool Sema::checkTargetClonesAttrString( StringsBuffer.push_back(Cur); } } - if (Str.rtrim().endswith(",")) + if (Str.rtrim().ends_with(",")) return Diag(LiteralLoc, diag::warn_unsupported_target_attribute) << Unsupported << None << "" << TargetClones; return false; @@ -5819,7 +5819,7 @@ struct IntrinToName { static bool ArmBuiltinAliasValid(unsigned BuiltinID, StringRef AliasName, ArrayRef<IntrinToName> Map, const char *IntrinNames) { - if (AliasName.startswith("__arm_")) + if (AliasName.starts_with("__arm_")) AliasName = AliasName.substr(6); const IntrinToName *It = llvm::lower_bound(Map, BuiltinID, [](const IntrinToName &L, unsigned Id) { @@ -6663,10 +6663,10 @@ validateSwiftFunctionName(Sema &S, const ParsedAttr &AL, SourceLocation Loc, // Check whether this will be mapped to a getter or setter of a property. bool IsGetter = false, IsSetter = false; - if (Name.startswith("getter:")) { + if (Name.starts_with("getter:")) { IsGetter = true; Name = Name.substr(7); - } else if (Name.startswith("setter:")) { + } else if (Name.starts_with("setter:")) { IsSetter = true; Name = Name.substr(7); } @@ -7292,7 +7292,7 @@ static void handleHLSLResourceBindingAttr(Sema &S, Decl *D, } } - if (!Space.startswith("space")) { + if (!Space.starts_with("space")) { S.Diag(SpaceArgLoc, diag::err_hlsl_expected_space) << Space; return; } diff --git a/clang/lib/Sema/SemaDeclObjC.cpp b/clang/lib/Sema/SemaDeclObjC.cpp index cdfa6ad3f281..c3b95e168a60 100644 --- a/clang/lib/Sema/SemaDeclObjC.cpp +++ b/clang/lib/Sema/SemaDeclObjC.cpp @@ -296,7 +296,7 @@ static void DiagnoseObjCImplementedDeprecations(Sema &S, const NamedDecl *ND, RealizedPlatform = S.Context.getTargetInfo().getPlatformName(); // Warn about implementing unavailable methods, unless the unavailable // is for an app extension. - if (RealizedPlatform.endswith("_app_extension")) + if (RealizedPlatform.ends_with("_app_extension")) return; S.Diag(ImplLoc, diag::warn_unavailable_def); S.Diag(ND->getLocation(), diag::note_method_declared_at) diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index d629be083d8c..c7185d56cc99 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -13808,12 +13808,12 @@ static void diagnoseXorMisusedAsPow(Sema &S, const ExprResult &XorLHS, StringRef RHSStrRef = RHSStr; // Do not diagnose literals with digit separators, binary, hexadecimal, octal // literals. - if (LHSStrRef.startswith("0b") || LHSStrRef.startswith("0B") || - RHSStrRef.startswith("0b") || RHSStrRef.startswith("0B") || - LHSStrRef.startswith("0x") || LHSStrRef.startswith("0X") || - RHSStrRef.startswith("0x") || RHSStrRef.startswith("0X") || - (LHSStrRef.size() > 1 && LHSStrRef.startswith("0")) || - (RHSStrRef.size() > 1 && RHSStrRef.startswith("0")) || + if (LHSStrRef.starts_with("0b") || LHSStrRef.starts_with("0B") || + RHSStrRef.starts_with("0b") || RHSStrRef.starts_with("0B") || + LHSStrRef.starts_with("0x") || LHSStrRef.starts_with("0X") || + RHSStrRef.starts_with("0x") || RHSStrRef.starts_with("0X") || + (LHSStrRef.size() > 1 && LHSStrRef.starts_with("0")) || + (RHSStrRef.size() > 1 && RHSStrRef.starts_with("0")) || LHSStrRef.contains('\'') || RHSStrRef.contains('\'')) return; @@ -15508,7 +15508,7 @@ static void checkObjCPointerIntrospection(Sema &S, ExprResult &L, ExprResult &R, if (const ObjCMessageExpr *ME = dyn_cast<ObjCMessageExpr>(Ex)) { Selector S = ME->getSelector(); StringRef SelArg0 = S.getNameForSlot(0); - if (SelArg0.startswith("performSelector")) + if (SelArg0.starts_with("performSelector")) Diag = diag::warn_objc_pointer_masking_performSelector; } diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp index 5ca6b232df66..4028b2d642b2 100644 --- a/clang/lib/Sema/SemaInit.cpp +++ b/clang/lib/Sema/SemaInit.cpp @@ -465,7 +465,8 @@ class InitListChecker { void FillInEmptyInitForField(unsigned Init, FieldDecl *Field, const InitializedEntity &ParentEntity, InitListExpr *ILE, bool &RequiresSecondPass, - bool FillWithNoInit = false); + bool FillWithNoInit = false, + bool WarnIfMissing = false); void FillInEmptyInitializations(const InitializedEntity &Entity, InitListExpr *ILE, bool &RequiresSecondPass, InitListExpr *OuterILE, unsigned OuterIndex, @@ -654,11 +655,16 @@ void InitListChecker::FillInEmptyInitForBase( } } -void InitListChecker::FillInEmptyInitForField(unsigned Init, FieldDecl *Field, - const InitializedEntity &ParentEntity, - InitListExpr *ILE, - bool &RequiresSecondPass, - bool FillWithNoInit) { +static bool hasAnyDesignatedInits(const InitListExpr *IL) { + return llvm::any_of(*IL, [=](const Stmt *Init) { + return isa_and_nonnull<DesignatedInitExpr>(Init); + }); +} + +void InitListChecker::FillInEmptyInitForField( + unsigned Init, FieldDecl *Field, const InitializedEntity &ParentEntity, + InitListExpr *ILE, bool &RequiresSecondPass, bool FillWithNoInit, + bool WarnIfMissing) { SourceLocation Loc = ILE->getEndLoc(); unsigned NumInits = ILE->getNumInits(); InitializedEntity MemberEntity @@ -726,15 +732,52 @@ void InitListChecker::FillInEmptyInitForField(unsigned Init, FieldDecl *Field, if (hadError || VerifyOnly) { // Do nothing - } else if (Init < NumInits) { - ILE->setInit(Init, MemberInit.getAs<Expr>()); - } else if (!isa<ImplicitValueInitExpr>(MemberInit.get())) { - // Empty initialization requires a constructor call, so - // extend the initializer list to include the constructor - // call and make a note that we'll need to take another pass - // through the initializer list. - ILE->updateInit(SemaRef.Context, Init, MemberInit.getAs<Expr>()); - RequiresSecondPass = true; + } else { + if (WarnIfMissing) { + auto CheckAnonMember = [&](const FieldDecl *FD, + auto &&CheckAnonMember) -> FieldDecl * { + FieldDecl *Uninitialized = nullptr; + RecordDecl *RD = FD->getType()->getAsRecordDecl(); + assert(RD && "Not anonymous member checked?"); + for (auto *F : RD->fields()) { + FieldDecl *UninitializedFieldInF = nullptr; + if (F->isAnonymousStructOrUnion()) + UninitializedFieldInF = CheckAnonMember(F, CheckAnonMember); + else if (!F->isUnnamedBitfield() && + !F->getType()->isIncompleteArrayType() && + !F->hasInClassInitializer()) + UninitializedFieldInF = F; + + if (RD->isUnion() && !UninitializedFieldInF) + return nullptr; + if (!Uninitialized) + Uninitialized = UninitializedFieldInF; + } + return Uninitialized; + }; + + FieldDecl *FieldToDiagnose = nullptr; + if (Field->isAnonymousStructOrUnion()) + FieldToDiagnose = CheckAnonMember(Field, CheckAnonMember); + else if (!Field->isUnnamedBitfield() && + !Field->getType()->isIncompleteArrayType()) + FieldToDiagnose = Field; + + if (FieldToDiagnose) + SemaRef.Diag(Loc, diag::warn_missing_field_initializers) + << FieldToDiagnose; + } + + if (Init < NumInits) { + ILE->setInit(Init, MemberInit.getAs<Expr>()); + } else if (!isa<ImplicitValueInitExpr>(MemberInit.get())) { + // Empty initialization requires a constructor call, so + // extend the initializer list to include the constructor + // call and make a note that we'll need to take another pass + // through the initializer list. + ILE->updateInit(SemaRef.Context, Init, MemberInit.getAs<Expr>()); + RequiresSecondPass = true; + } } } else if (InitListExpr *InnerILE = dyn_cast<InitListExpr>(ILE->getInit(Init))) { @@ -802,9 +845,25 @@ InitListChecker::FillInEmptyInitializations(const InitializedEntity &Entity, } } } else { + InitListExpr *SForm = + ILE->isSyntacticForm() ? ILE : ILE->getSyntacticForm(); // The fields beyond ILE->getNumInits() are default initialized, so in // order to leave them uninitialized, the ILE is expanded and the extra // fields are then filled with NoInitExpr. + + // Some checks that are required for missing fields warning are bound to + // how many elements the initializer list originally was provided; perform + // them before the list is expanded. + bool WarnIfMissingField = + !SForm->isIdiomaticZeroInitializer(SemaRef.getLangOpts()) && + ILE->getNumInits(); + + // Disable check for missing fields when designators are used in C to + // match gcc behaviour. + // FIXME: Should we emulate possible gcc warning bug? + WarnIfMissingField &= + SemaRef.getLangOpts().CPlusPlus || !hasAnyDesignatedInits(SForm); + unsigned NumElems = numStructUnionElements(ILE->getType()); if (!RDecl->isUnion() && RDecl->hasFlexibleArrayMember()) ++NumElems; @@ -832,7 +891,7 @@ InitListChecker::FillInEmptyInitializations(const InitializedEntity &Entity, return; FillInEmptyInitForField(Init, Field, Entity, ILE, RequiresSecondPass, - FillWithNoInit); + FillWithNoInit, WarnIfMissingField); if (hadError) return; @@ -947,13 +1006,6 @@ InitListChecker::FillInEmptyInitializations(const InitializedEntity &Entity, } } -static bool hasAnyDesignatedInits(const InitListExpr *IL) { - for (const Stmt *Init : *IL) - if (isa_and_nonnull<DesignatedInitExpr>(Init)) - return true; - return false; -} - InitListChecker::InitListChecker( Sema &S, const InitializedEntity &Entity, InitListExpr *IL, QualType &T, bool VerifyOnly, bool TreatUnavailableAsInvalid, bool InOverloadResolution, @@ -2225,12 +2277,8 @@ void InitListChecker::CheckStructUnionTypes( size_t NumRecordDecls = llvm::count_if(RD->decls(), [&](const Decl *D) { return isa<FieldDecl>(D) || isa<RecordDecl>(D); }); - bool CheckForMissingFields = - !IList->isIdiomaticZeroInitializer(SemaRef.getLangOpts()); bool HasDesignatedInit = false; - llvm::SmallPtrSet<FieldDecl *, 4> InitializedFields; - while (Index < IList->getNumInits()) { Expr *Init = IList->getInit(Index); SourceLocation InitLoc = Init->getBeginLoc(); @@ -2254,24 +2302,17 @@ void InitListChecker::CheckStructUnionTypes( // Find the field named by the designated initializer. DesignatedInitExpr::Designator *D = DIE->getDesignator(0); - if (!VerifyOnly && D->isFieldDesignator()) { + if (!VerifyOnly && D->isFieldDesignator() && !DesignatedInitFailed) { FieldDecl *F = D->getFieldDecl(); - InitializedFields.insert(F); - if (!DesignatedInitFailed) { - QualType ET = SemaRef.Context.getBaseElementType(F->getType()); - if (checkDestructorReference(ET, InitLoc, SemaRef)) { - hadError = true; - return; - } + QualType ET = SemaRef.Context.getBaseElementType(F->getType()); + if (checkDestructorReference(ET, InitLoc, SemaRef)) { + hadError = true; + return; } } InitializedSomething = true; - // Disable check for missing fields when designators are used. - // This matches gcc behaviour. - if (!SemaRef.getLangOpts().CPlusPlus) - CheckForMissingFields = false; continue; } @@ -2350,7 +2391,6 @@ void InitListChecker::CheckStructUnionTypes( CheckSubElementType(MemberEntity, IList, Field->getType(), Index, StructuredList, StructuredIndex); InitializedSomething = true; - InitializedFields.insert(*Field); if (RD->isUnion() && StructuredList) { // Initialize the first field within the union. @@ -2360,28 +2400,6 @@ void InitListChecker::CheckStructUnionTypes( ++Field; } - // Emit warnings for missing struct field initializers. - if (!VerifyOnly && InitializedSomething && CheckForMissingFields && - !RD->isUnion()) { - // It is possible we have one or more unnamed bitfields remaining. - // Find first (if any) named field and emit warning. - for (RecordDecl::field_iterator it = HasDesignatedInit ? RD->field_begin() - : Field, - end = RD->field_end(); - it != end; ++it) { - if (HasDesignatedInit && InitializedFields.count(*it)) - continue; - - if (!it->isUnnamedBitfield() && !it->hasInClassInitializer() && - !it->getType()->isIncompleteArrayType()) { - SemaRef.Diag(IList->getSourceRange().getEnd(), - diag::warn_missing_field_initializers) - << *it; - break; - } - } - } - // Check that any remaining fields can be value-initialized if we're not // building a structured list. (If we are, we'll check this later.) if (!StructuredList && Field != FieldEnd && !RD->isUnion() && diff --git a/clang/lib/Sema/SemaModule.cpp b/clang/lib/Sema/SemaModule.cpp index 9282ceb8dee0..db0cbd5ec6d6 100644 --- a/clang/lib/Sema/SemaModule.cpp +++ b/clang/lib/Sema/SemaModule.cpp @@ -268,7 +268,7 @@ Sema::ActOnModuleDecl(SourceLocation StartLoc, SourceLocation ModuleLoc, StringRef FirstComponentName = Path[0].first->getName(); if (!getSourceManager().isInSystemHeader(Path[0].second) && (FirstComponentName == "std" || - (FirstComponentName.startswith("std") && + (FirstComponentName.starts_with("std") && llvm::all_of(FirstComponentName.drop_front(3), &llvm::isDigit)))) Diag(Path[0].second, diag::warn_reserved_module_name) << Path[0].first; diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index f10abeaba0d4..cca7d6130615 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -39,6 +39,7 @@ #include "llvm/ADT/SmallBitVector.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/Support/SaveAndRestore.h" #include <iterator> #include <optional> @@ -3990,9 +3991,14 @@ QualType Sema::CheckTemplateIdType(TemplateName Name, if (Inst.isInvalid()) return QualType(); - CanonType = SubstType(Pattern->getUnderlyingType(), - TemplateArgLists, AliasTemplate->getLocation(), - AliasTemplate->getDeclName()); + { + Sema::ContextRAII SavedContext(*this, Pattern->getDeclContext()); + if (RebuildingTypesInCurrentInstantiation) + SavedContext.pop(); + CanonType = + SubstType(Pattern->getUnderlyingType(), TemplateArgLists, + AliasTemplate->getLocation(), AliasTemplate->getDeclName()); + } if (CanonType.isNull()) { // If this was enable_if and we failed to find the nested type // within enable_if in a SFINAE context, dig out the specific @@ -11392,6 +11398,8 @@ TypeSourceInfo *Sema::RebuildTypeInCurrentInstantiation(TypeSourceInfo *T, if (!T || !T->getType()->isInstantiationDependentType()) return T; + llvm::SaveAndRestore DisableContextSwitchForTypeAliases( + RebuildingTypesInCurrentInstantiation, true); CurrentInstantiationRebuilder Rebuilder(*this, Loc, Name); return Rebuilder.TransformType(T); } diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp index 83610503ed9b..a376f20fa4f4 100644 --- a/clang/lib/Sema/SemaType.cpp +++ b/clang/lib/Sema/SemaType.cpp @@ -5371,7 +5371,7 @@ static TypeSourceInfo *GetFullTypeForDeclarator(TypeProcessingState &state, !(D.getIdentifier() && ((D.getIdentifier()->getName() == "printf" && LangOpts.getOpenCLCompatibleVersion() >= 120) || - D.getIdentifier()->getName().startswith("__")))) { + D.getIdentifier()->getName().starts_with("__")))) { S.Diag(D.getIdentifierLoc(), diag::err_opencl_variadic_function); D.setInvalidType(true); } @@ -8360,12 +8360,25 @@ static void HandleNeonVectorTypeAttr(QualType &CurType, const ParsedAttr &Attr, // not to need a separate attribute) if (!(S.Context.getTargetInfo().hasFeature("neon") || S.Context.getTargetInfo().hasFeature("mve") || - IsTargetCUDAAndHostARM)) { + S.Context.getTargetInfo().hasFeature("sve") || + S.Context.getTargetInfo().hasFeature("sme") || + IsTargetCUDAAndHostARM) && + VecKind == VectorKind::Neon) { + S.Diag(Attr.getLoc(), diag::err_attribute_unsupported) + << Attr << "'neon', 'mve', 'sve' or 'sme'"; + Attr.setInvalid(); + return; + } + if (!(S.Context.getTargetInfo().hasFeature("neon") || + S.Context.getTargetInfo().hasFeature("mve") || + IsTargetCUDAAndHostARM) && + VecKind == VectorKind::NeonPoly) { S.Diag(Attr.getLoc(), diag::err_attribute_unsupported) << Attr << "'neon' or 'mve'"; Attr.setInvalid(); return; } + // Check the attribute arguments. if (Attr.getNumArgs() != 1) { S.Diag(Attr.getLoc(), diag::err_attribute_wrong_number_arguments) diff --git a/clang/lib/StaticAnalyzer/Checkers/CheckObjCDealloc.cpp b/clang/lib/StaticAnalyzer/Checkers/CheckObjCDealloc.cpp index bd6655cc1e3f..fedc6db3723a 100644 --- a/clang/lib/StaticAnalyzer/Checkers/CheckObjCDealloc.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/CheckObjCDealloc.cpp @@ -1045,8 +1045,8 @@ bool ObjCDeallocChecker::isReleasedByCIFilterDealloc( StringRef IvarName = PropImpl->getPropertyIvarDecl()->getName(); const char *ReleasePrefix = "input"; - if (!(PropName.startswith(ReleasePrefix) || - IvarName.startswith(ReleasePrefix))) { + if (!(PropName.starts_with(ReleasePrefix) || + IvarName.starts_with(ReleasePrefix))) { return false; } diff --git a/clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp b/clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp index dbba12bb4355..afc5e6b48008 100644 --- a/clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp @@ -140,7 +140,7 @@ void WalkAST::VisitCallExpr(CallExpr *CE) { if (!II) // if no identifier, not a simple C function return; StringRef Name = II->getName(); - if (Name.startswith("__builtin_")) + if (Name.starts_with("__builtin_")) Name = Name.substr(10); // Set the evaluation function by switching on the callee name. @@ -763,7 +763,7 @@ void WalkAST::checkDeprecatedOrUnsafeBufferHandling(const CallExpr *CE, enum { DEPR_ONLY = -1, UNKNOWN_CALL = -2 }; StringRef Name = FD->getIdentifier()->getName(); - if (Name.startswith("__builtin_")) + if (Name.starts_with("__builtin_")) Name = Name.substr(10); int ArgIndex = diff --git a/clang/lib/StaticAnalyzer/Checkers/DeadStoresChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/DeadStoresChecker.cpp index 5f44c9476928..86f446fc411c 100644 --- a/clang/lib/StaticAnalyzer/Checkers/DeadStoresChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/DeadStoresChecker.cpp @@ -183,7 +183,7 @@ public: // Files autogenerated by DriverKit IIG contain some dead stores that // we don't want to report. - if (Data.startswith("/* iig")) + if (Data.starts_with("/* iig")) return true; return false; diff --git a/clang/lib/StaticAnalyzer/Checkers/GCDAntipatternChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/GCDAntipatternChecker.cpp index 8e02ef74c668..5637941a58f0 100644 --- a/clang/lib/StaticAnalyzer/Checkers/GCDAntipatternChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/GCDAntipatternChecker.cpp @@ -73,7 +73,7 @@ decltype(auto) bindAssignmentToDecl(const char *DeclName) { static bool isTest(const Decl *D) { if (const auto* ND = dyn_cast<NamedDecl>(D)) { std::string DeclName = ND->getNameAsString(); - if (StringRef(DeclName).startswith("test")) + if (StringRef(DeclName).starts_with("test")) return true; } if (const auto *OD = dyn_cast<ObjCMethodDecl>(D)) { diff --git a/clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp index b77e9bf09a33..70f911fc66ab 100644 --- a/clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp @@ -817,9 +817,9 @@ void NonLocalizedStringChecker::checkPreObjCMessage(const ObjCMethodCall &msg, // Handle the case where the receiver is an NSString // These special NSString methods draw to the screen - if (!(SelectorName.startswith("drawAtPoint") || - SelectorName.startswith("drawInRect") || - SelectorName.startswith("drawWithRect"))) + if (!(SelectorName.starts_with("drawAtPoint") || + SelectorName.starts_with("drawInRect") || + SelectorName.starts_with("drawWithRect"))) return; SVal svTitle = msg.getReceiverSVal(); diff --git a/clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp index c5e4add50188..79ab05f2c786 100644 --- a/clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/MallocChecker.cpp @@ -3150,16 +3150,16 @@ bool MallocChecker::mayFreeAnyEscapedMemoryOrIsModeledExplicitly( // transferred. Again, though, we can't be sure that the object will use // free() to deallocate the memory, so we can't model it explicitly. StringRef FirstSlot = Msg->getSelector().getNameForSlot(0); - if (FirstSlot.endswith("NoCopy")) + if (FirstSlot.ends_with("NoCopy")) return true; // If the first selector starts with addPointer, insertPointer, // or replacePointer, assume we are dealing with NSPointerArray or similar. // This is similar to C++ containers (vector); we still might want to check // that the pointers get freed by following the container itself. - if (FirstSlot.startswith("addPointer") || - FirstSlot.startswith("insertPointer") || - FirstSlot.startswith("replacePointer") || + if (FirstSlot.starts_with("addPointer") || + FirstSlot.starts_with("insertPointer") || + FirstSlot.starts_with("replacePointer") || FirstSlot.equals("valueWithPointer")) { return true; } @@ -3199,7 +3199,7 @@ bool MallocChecker::mayFreeAnyEscapedMemoryOrIsModeledExplicitly( // White list the 'XXXNoCopy' CoreFoundation functions. // We specifically check these before - if (FName.endswith("NoCopy")) { + if (FName.ends_with("NoCopy")) { // Look for the deallocator argument. We know that the memory ownership // is not transferred only if the deallocator argument is // 'kCFAllocatorNull'. diff --git a/clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp index 627b51af6bd4..06f1ad00eaf2 100644 --- a/clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp @@ -890,7 +890,7 @@ void NullabilityChecker::checkPostCall(const CallEvent &Call, // of CG calls. const SourceManager &SM = C.getSourceManager(); StringRef FilePath = SM.getFilename(SM.getSpellingLoc(Decl->getBeginLoc())); - if (llvm::sys::path::filename(FilePath).startswith("CG")) { + if (llvm::sys::path::filename(FilePath).starts_with("CG")) { State = State->set<NullabilityMap>(Region, Nullability::Contradicted); C.addTransition(State); return; @@ -992,7 +992,7 @@ void NullabilityChecker::checkPostObjCMessage(const ObjCMethodCall &M, // In order to reduce the noise in the diagnostics generated by this checker, // some framework and programming style based heuristics are used. These // heuristics are for Cocoa APIs which have NS prefix. - if (Name.startswith("NS")) { + if (Name.starts_with("NS")) { // Developers rely on dynamic invariants such as an item should be available // in a collection, or a collection is not empty often. Those invariants can // not be inferred by any static analysis tool. To not to bother the users diff --git a/clang/lib/StaticAnalyzer/Checkers/ObjCPropertyChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/ObjCPropertyChecker.cpp index 4636fd160511..08ad6877cbe6 100644 --- a/clang/lib/StaticAnalyzer/Checkers/ObjCPropertyChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/ObjCPropertyChecker.cpp @@ -50,7 +50,7 @@ void ObjCPropertyChecker::checkCopyMutable(const ObjCPropertyDecl *D, const std::string &PropTypeName(T->getPointeeType().getCanonicalType() .getUnqualifiedType() .getAsString()); - if (!StringRef(PropTypeName).startswith("NSMutable")) + if (!StringRef(PropTypeName).starts_with("NSMutable")) return; const ObjCImplDecl *ImplD = nullptr; diff --git a/clang/lib/StaticAnalyzer/Core/BugReporter.cpp b/clang/lib/StaticAnalyzer/Core/BugReporter.cpp index 9532254e3c45..a253f2b637f5 100644 --- a/clang/lib/StaticAnalyzer/Core/BugReporter.cpp +++ b/clang/lib/StaticAnalyzer/Core/BugReporter.cpp @@ -2139,15 +2139,14 @@ PathSensitiveBugReport::PathSensitiveBugReport( "checkers to emit warnings, because checkers should depend on " "*modeling*, not *diagnostics*."); - assert( - (bt.getCheckerName().startswith("debug") || - !isHidden(ErrorNode->getState() - ->getAnalysisManager() - .getCheckerManager() - ->getCheckerRegistryData(), - bt.getCheckerName())) && - "Hidden checkers musn't emit diagnostics as they are by definition " - "non-user facing!"); + assert((bt.getCheckerName().starts_with("debug") || + !isHidden(ErrorNode->getState() + ->getAnalysisManager() + .getCheckerManager() + ->getCheckerRegistryData(), + bt.getCheckerName())) && + "Hidden checkers musn't emit diagnostics as they are by definition " + "non-user facing!"); } void PathSensitiveBugReport::addVisitor( @@ -3064,8 +3063,7 @@ void BugReporter::FlushReport(BugReportEquivClass& EQ) { // See whether we need to silence the checker/package. for (const std::string &CheckerOrPackage : getAnalyzerOptions().SilencedCheckersAndPackages) { - if (report->getBugType().getCheckerName().startswith( - CheckerOrPackage)) + if (report->getBugType().getCheckerName().starts_with(CheckerOrPackage)) return; } diff --git a/clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp b/clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp index 4a9d130c240a..2f9965036b9e 100644 --- a/clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp +++ b/clang/lib/StaticAnalyzer/Core/BugReporterVisitors.cpp @@ -3372,7 +3372,7 @@ void LikelyFalsePositiveSuppressionBRVisitor::finalizeVisitor( FullSourceLoc Loc = BR.getLocation().asLocation(); while (Loc.isMacroID()) { Loc = Loc.getSpellingLoc(); - if (SM.getFilename(Loc).endswith("sys/queue.h")) { + if (SM.getFilename(Loc).ends_with("sys/queue.h")) { BR.markInvalid(getTag(), nullptr); return; } diff --git a/clang/lib/StaticAnalyzer/Core/CallEvent.cpp b/clang/lib/StaticAnalyzer/Core/CallEvent.cpp index d004c12bf2c1..0ac1d91b79be 100644 --- a/clang/lib/StaticAnalyzer/Core/CallEvent.cpp +++ b/clang/lib/StaticAnalyzer/Core/CallEvent.cpp @@ -659,17 +659,17 @@ bool AnyFunctionCall::argumentsMayEscape() const { // - CoreFoundation functions that end with "NoCopy" can free a passed-in // buffer even if it is const. - if (FName.endswith("NoCopy")) + if (FName.ends_with("NoCopy")) return true; // - NSXXInsertXX, for example NSMapInsertIfAbsent, since they can // be deallocated by NSMapRemove. - if (FName.startswith("NS") && FName.contains("Insert")) + if (FName.starts_with("NS") && FName.contains("Insert")) return true; // - Many CF containers allow objects to escape through custom // allocators/deallocators upon container construction. (PR12101) - if (FName.startswith("CF") || FName.startswith("CG")) { + if (FName.starts_with("CF") || FName.starts_with("CG")) { return StrInStrNoCase(FName, "InsertValue") != StringRef::npos || StrInStrNoCase(FName, "AddValue") != StringRef::npos || StrInStrNoCase(FName, "SetValue") != StringRef::npos || diff --git a/clang/lib/StaticAnalyzer/Core/CheckerContext.cpp b/clang/lib/StaticAnalyzer/Core/CheckerContext.cpp index c25165cce128..d6d4cec9dd3d 100644 --- a/clang/lib/StaticAnalyzer/Core/CheckerContext.cpp +++ b/clang/lib/StaticAnalyzer/Core/CheckerContext.cpp @@ -105,10 +105,11 @@ bool CheckerContext::isCLibraryFunction(const FunctionDecl *FD, if (FName.equals(Name)) return true; - if (FName.startswith("__inline") && FName.contains(Name)) + if (FName.starts_with("__inline") && FName.contains(Name)) return true; - if (FName.startswith("__") && FName.endswith("_chk") && FName.contains(Name)) + if (FName.starts_with("__") && FName.ends_with("_chk") && + FName.contains(Name)) return true; return false; diff --git a/clang/lib/StaticAnalyzer/Core/CheckerRegistryData.cpp b/clang/lib/StaticAnalyzer/Core/CheckerRegistryData.cpp index 1b3e8b11549d..b9c6278991f4 100644 --- a/clang/lib/StaticAnalyzer/Core/CheckerRegistryData.cpp +++ b/clang/lib/StaticAnalyzer/Core/CheckerRegistryData.cpp @@ -82,7 +82,7 @@ static constexpr char PackageSeparator = '.'; static bool isInPackage(const CheckerInfo &Checker, StringRef PackageName) { // Does the checker's full name have the package as a prefix? - if (!Checker.FullName.startswith(PackageName)) + if (!Checker.FullName.starts_with(PackageName)) return false; // Is the package actually just the name of a specific checker? @@ -158,7 +158,7 @@ void CheckerRegistryData::printCheckerWithDescList( continue; } - if (Checker.FullName.startswith("alpha")) { + if (Checker.FullName.starts_with("alpha")) { if (AnOpts.ShowCheckerHelpAlpha) Print(Out, Checker, ("(Enable only for development!) " + Checker.Desc).str()); @@ -228,7 +228,7 @@ void CheckerRegistryData::printCheckerOptionList(const AnalyzerOptions &AnOpts, } if (Option.DevelopmentStatus == "alpha" || - Entry.first.startswith("alpha")) { + Entry.first.starts_with("alpha")) { if (AnOpts.ShowCheckerOptionAlphaList) Print(Out, FullOption, llvm::Twine("(Enable only for development!) " + Desc).str()); diff --git a/clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp b/clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp index 142acab7cd08..b6ef40595e3c 100644 --- a/clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp +++ b/clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp @@ -308,7 +308,7 @@ public: bool VisitFunctionDecl(FunctionDecl *FD) { IdentifierInfo *II = FD->getIdentifier(); - if (II && II->getName().startswith("__inline")) + if (II && II->getName().starts_with("__inline")) return true; // We skip function template definitions, as their semantics is diff --git a/clang/lib/StaticAnalyzer/Frontend/CheckerRegistry.cpp b/clang/lib/StaticAnalyzer/Frontend/CheckerRegistry.cpp index f0d3f43c414c..317df90a7781 100644 --- a/clang/lib/StaticAnalyzer/Frontend/CheckerRegistry.cpp +++ b/clang/lib/StaticAnalyzer/Frontend/CheckerRegistry.cpp @@ -310,8 +310,8 @@ template <bool IsWeak> void CheckerRegistry::resolveDependencies() { "Failed to find the dependency of a checker!"); // We do allow diagnostics from unit test/example dependency checkers. - assert((DependencyIt->FullName.startswith("test") || - DependencyIt->FullName.startswith("example") || IsWeak || + assert((DependencyIt->FullName.starts_with("test") || + DependencyIt->FullName.starts_with("example") || IsWeak || DependencyIt->IsHidden) && "Strong dependencies are modeling checkers, and as such " "non-user facing! Mark them hidden in Checkers.td!"); diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp b/clang/lib/Support/RISCVVIntrinsicUtils.cpp index a04694e628de..bb9f7dc7e7e3 100644 --- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp +++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp @@ -464,7 +464,7 @@ PrototypeDescriptor::parsePrototypeDescriptor( PrototypeDescriptorStr = PrototypeDescriptorStr.drop_back(); // Compute the vector type transformers, it can only appear one time. - if (PrototypeDescriptorStr.startswith("(")) { + if (PrototypeDescriptorStr.starts_with("(")) { assert(VTM == VectorTypeModifier::NoModifier && "VectorTypeModifier should only have one modifier"); size_t Idx = PrototypeDescriptorStr.find(')'); diff --git a/clang/lib/Tooling/ASTDiff/ASTDiff.cpp b/clang/lib/Tooling/ASTDiff/ASTDiff.cpp index 52e57976ac09..356b4bd5a1b8 100644 --- a/clang/lib/Tooling/ASTDiff/ASTDiff.cpp +++ b/clang/lib/Tooling/ASTDiff/ASTDiff.cpp @@ -371,7 +371,7 @@ SyntaxTree::Impl::getRelativeName(const NamedDecl *ND, // Strip the qualifier, if Val refers to something in the current scope. // But leave one leading ':' in place, so that we know that this is a // relative path. - if (!ContextPrefix.empty() && StringRef(Val).startswith(ContextPrefix)) + if (!ContextPrefix.empty() && StringRef(Val).starts_with(ContextPrefix)) Val = Val.substr(ContextPrefix.size() + 1); return Val; } diff --git a/clang/lib/Tooling/ArgumentsAdjusters.cpp b/clang/lib/Tooling/ArgumentsAdjusters.cpp index e40df6257378..df4c74205b08 100644 --- a/clang/lib/Tooling/ArgumentsAdjusters.cpp +++ b/clang/lib/Tooling/ArgumentsAdjusters.cpp @@ -45,12 +45,12 @@ ArgumentsAdjuster getClangSyntaxOnlyAdjuster() { StringRef Arg = Args[i]; // Skip output commands. if (llvm::any_of(OutputCommands, [&Arg](llvm::StringRef OutputCommand) { - return Arg.startswith(OutputCommand); + return Arg.starts_with(OutputCommand); })) continue; - if (!Arg.startswith("-fcolor-diagnostics") && - !Arg.startswith("-fdiagnostics-color")) + if (!Arg.starts_with("-fcolor-diagnostics") && + !Arg.starts_with("-fdiagnostics-color")) AdjustedArgs.push_back(Args[i]); // If we strip a color option, make sure we strip any preceeding `-Xclang` // option as well. @@ -73,7 +73,7 @@ ArgumentsAdjuster getClangStripOutputAdjuster() { CommandLineArguments AdjustedArgs; for (size_t i = 0, e = Args.size(); i < e; ++i) { StringRef Arg = Args[i]; - if (!Arg.startswith("-o")) + if (!Arg.starts_with("-o")) AdjustedArgs.push_back(Args[i]); if (Arg == "-o") { @@ -102,11 +102,11 @@ ArgumentsAdjuster getClangStripDependencyFileAdjuster() { // When not using the cl driver mode, dependency file generation options // begin with -M. These include -MM, -MF, -MG, -MP, -MT, -MQ, -MD, and // -MMD. - if (!UsingClDriver && Arg.startswith("-M")) + if (!UsingClDriver && Arg.starts_with("-M")) continue; // Under MSVC's cl driver mode, dependency file generation is controlled // using /showIncludes - if (Arg.startswith("/showIncludes") || Arg.startswith("-showIncludes")) + if (Arg.starts_with("/showIncludes") || Arg.starts_with("-showIncludes")) continue; AdjustedArgs.push_back(Args[i]); @@ -159,7 +159,7 @@ ArgumentsAdjuster getStripPluginsAdjuster() { // -Xclang <arbitrary-argument> if (I + 4 < E && Args[I] == "-Xclang" && (Args[I + 1] == "-load" || Args[I + 1] == "-plugin" || - llvm::StringRef(Args[I + 1]).startswith("-plugin-arg-") || + llvm::StringRef(Args[I + 1]).starts_with("-plugin-arg-") || Args[I + 1] == "-add-plugin") && Args[I + 2] == "-Xclang") { I += 3; diff --git a/clang/lib/Tooling/CompilationDatabase.cpp b/clang/lib/Tooling/CompilationDatabase.cpp index fdf6015508d9..87ad8f25a1ab 100644 --- a/clang/lib/Tooling/CompilationDatabase.cpp +++ b/clang/lib/Tooling/CompilationDatabase.cpp @@ -204,7 +204,7 @@ public: // which don't support these options. struct FilterUnusedFlags { bool operator() (StringRef S) { - return (S == "-no-integrated-as") || S.startswith("-Wa,"); + return (S == "-no-integrated-as") || S.starts_with("-Wa,"); } }; diff --git a/clang/lib/Tooling/DependencyScanning/DependencyScanningFilesystem.cpp b/clang/lib/Tooling/DependencyScanning/DependencyScanningFilesystem.cpp index 3e53c8fc5740..6f71650a3982 100644 --- a/clang/lib/Tooling/DependencyScanning/DependencyScanningFilesystem.cpp +++ b/clang/lib/Tooling/DependencyScanning/DependencyScanningFilesystem.cpp @@ -290,7 +290,7 @@ DependencyScanningWorkerFilesystem::status(const Twine &Path) { SmallString<256> OwnedFilename; StringRef Filename = Path.toStringRef(OwnedFilename); - if (Filename.endswith(".pcm")) + if (Filename.ends_with(".pcm")) return getUnderlyingFS().status(Path); llvm::ErrorOr<EntryRef> Result = getOrCreateFileSystemEntry(Filename); @@ -350,7 +350,7 @@ DependencyScanningWorkerFilesystem::openFileForRead(const Twine &Path) { SmallString<256> OwnedFilename; StringRef Filename = Path.toStringRef(OwnedFilename); - if (Filename.endswith(".pcm")) + if (Filename.ends_with(".pcm")) return getUnderlyingFS().openFileForRead(Path); llvm::ErrorOr<EntryRef> Result = getOrCreateFileSystemEntry(Filename); diff --git a/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp b/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp index f65da413bb87..4a3cd054f23d 100644 --- a/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp +++ b/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp @@ -530,7 +530,7 @@ ModuleDepCollectorPP::handleTopLevelModule(const Module *M) { // this file in the proper directory and relies on the rest of Clang to // handle it like normal. With explicitly built modules we don't need // to play VFS tricks, so replace it with the correct module map. - if (StringRef(IFI.Filename).endswith("__inferred_module.map")) { + if (StringRef(IFI.Filename).ends_with("__inferred_module.map")) { MDC.addFileDep(MD, ModuleMap->getName()); return; } @@ -548,7 +548,7 @@ ModuleDepCollectorPP::handleTopLevelModule(const Module *M) { if (!(IFI.TopLevel && IFI.ModuleMap)) return; if (StringRef(IFI.FilenameAsRequested) - .endswith("__inferred_module.map")) + .ends_with("__inferred_module.map")) return; MD.ModuleMapFileDeps.emplace_back(IFI.FilenameAsRequested); }); diff --git a/clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp b/clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp index 0b3c4de08ab8..52b634e2e1af 100644 --- a/clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp +++ b/clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp @@ -21,7 +21,7 @@ bool isIf(llvm::StringRef Line) { if (!Line.consume_front("#")) return false; Line = Line.ltrim(); - return Line.startswith("if"); + return Line.starts_with("if"); } // Is Line an #error directive mentioning includes? @@ -30,7 +30,7 @@ bool isErrorAboutInclude(llvm::StringRef Line) { if (!Line.consume_front("#")) return false; Line = Line.ltrim(); - if (!Line.startswith("error")) + if (!Line.starts_with("error")) return false; return Line.contains_insensitive( "includ"); // Matches "include" or "including". @@ -54,7 +54,7 @@ bool isImportLine(llvm::StringRef Line) { if (!Line.consume_front("#")) return false; Line = Line.ltrim(); - return Line.startswith("import"); + return Line.starts_with("import"); } llvm::StringRef getFileContents(FileEntryRef FE, const SourceManager &SM) { diff --git a/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp b/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp index 15a2024c4788..d275222ac6b5 100644 --- a/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp +++ b/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp @@ -196,10 +196,10 @@ IncludeCategoryManager::IncludeCategoryManager(const IncludeStyle &Style, ? llvm::Regex::NoFlags : llvm::Regex::IgnoreCase); } - IsMainFile = FileName.endswith(".c") || FileName.endswith(".cc") || - FileName.endswith(".cpp") || FileName.endswith(".c++") || - FileName.endswith(".cxx") || FileName.endswith(".m") || - FileName.endswith(".mm"); + IsMainFile = FileName.ends_with(".c") || FileName.ends_with(".cc") || + FileName.ends_with(".cpp") || FileName.ends_with(".c++") || + FileName.ends_with(".cxx") || FileName.ends_with(".m") || + FileName.ends_with(".mm"); if (!Style.IncludeIsMainSourceRegex.empty()) { llvm::Regex MainFileRegex(Style.IncludeIsMainSourceRegex); IsMainFile |= MainFileRegex.match(FileName); @@ -234,7 +234,7 @@ int IncludeCategoryManager::getSortIncludePriority(StringRef IncludeName, return Ret; } bool IncludeCategoryManager::isMainHeader(StringRef IncludeName) const { - if (!IncludeName.startswith("\"")) + if (!IncludeName.starts_with("\"")) return false; IncludeName = @@ -357,8 +357,8 @@ HeaderIncludes::insert(llvm::StringRef IncludeName, bool IsAngled, if (It != ExistingIncludes.end()) { for (const auto &Inc : It->second) if (Inc.Directive == Directive && - ((IsAngled && StringRef(Inc.Name).startswith("<")) || - (!IsAngled && StringRef(Inc.Name).startswith("\"")))) + ((IsAngled && StringRef(Inc.Name).starts_with("<")) || + (!IsAngled && StringRef(Inc.Name).starts_with("\"")))) return std::nullopt; } std::string Quoted = @@ -400,8 +400,8 @@ tooling::Replacements HeaderIncludes::remove(llvm::StringRef IncludeName, if (Iter == ExistingIncludes.end()) return Result; for (const auto &Inc : Iter->second) { - if ((IsAngled && StringRef(Inc.Name).startswith("\"")) || - (!IsAngled && StringRef(Inc.Name).startswith("<"))) + if ((IsAngled && StringRef(Inc.Name).starts_with("\"")) || + (!IsAngled && StringRef(Inc.Name).starts_with("<"))) continue; llvm::Error Err = Result.add(tooling::Replacement( FileName, Inc.R.getOffset(), Inc.R.getLength(), "")); diff --git a/clang/lib/Tooling/Refactoring/AtomicChange.cpp b/clang/lib/Tooling/Refactoring/AtomicChange.cpp index 7237393f00e5..3d5ae2fed014 100644 --- a/clang/lib/Tooling/Refactoring/AtomicChange.cpp +++ b/clang/lib/Tooling/Refactoring/AtomicChange.cpp @@ -150,7 +150,7 @@ createReplacementsForHeaders(llvm::StringRef FilePath, llvm::StringRef Code, for (const auto &Change : Changes) { for (llvm::StringRef Header : Change.getInsertedHeaders()) { std::string EscapedHeader = - Header.startswith("<") || Header.startswith("\"") + Header.starts_with("<") || Header.starts_with("\"") ? Header.str() : ("\"" + Header + "\"").str(); std::string ReplacementText = "#include " + EscapedHeader; diff --git a/clang/lib/Tooling/Refactoring/Lookup.cpp b/clang/lib/Tooling/Refactoring/Lookup.cpp index 9468d4d032a7..52799f16fab2 100644 --- a/clang/lib/Tooling/Refactoring/Lookup.cpp +++ b/clang/lib/Tooling/Refactoring/Lookup.cpp @@ -98,7 +98,7 @@ static StringRef getBestNamespaceSubstr(const DeclContext *DeclA, // from NewName if it has an identical prefix. std::string NS = "::" + cast<NamespaceDecl>(DeclA)->getQualifiedNameAsString() + "::"; - if (NewName.startswith(NS)) + if (NewName.starts_with(NS)) return NewName.substr(NS.size()); // No match yet. Strip of a namespace from the end of the chain and try @@ -128,9 +128,9 @@ static std::string disambiguateSpellingInScope(StringRef Spelling, StringRef QName, const DeclContext &UseContext, SourceLocation UseLoc) { - assert(QName.startswith("::")); - assert(QName.endswith(Spelling)); - if (Spelling.startswith("::")) + assert(QName.starts_with("::")); + assert(QName.ends_with(Spelling)); + if (Spelling.starts_with("::")) return std::string(Spelling); auto UnspelledSpecifier = QName.drop_back(Spelling.size()); @@ -146,7 +146,7 @@ static std::string disambiguateSpellingInScope(StringRef Spelling, UseLoc = SM.getSpellingLoc(UseLoc); auto IsAmbiguousSpelling = [&](const llvm::StringRef CurSpelling) { - if (CurSpelling.startswith("::")) + if (CurSpelling.starts_with("::")) return false; // Lookup the first component of Spelling in all enclosing namespaces // and check if there is any existing symbols with the same name but in @@ -160,7 +160,7 @@ static std::string disambiguateSpellingInScope(StringRef Spelling, // ambiguous. For example, a reference in a header file should not be // affected by a potentially ambiguous name in some file that includes // the header. - if (!TrimmedQName.startswith(Res->getQualifiedNameAsString()) && + if (!TrimmedQName.starts_with(Res->getQualifiedNameAsString()) && SM.isBeforeInTranslationUnit( SM.getSpellingLoc(Res->getLocation()), UseLoc)) return true; @@ -187,7 +187,7 @@ std::string tooling::replaceNestedName(const NestedNameSpecifier *Use, const DeclContext *UseContext, const NamedDecl *FromDecl, StringRef ReplacementString) { - assert(ReplacementString.startswith("::") && + assert(ReplacementString.starts_with("::") && "Expected fully-qualified name!"); // We can do a raw name replacement when we are not inside the namespace for diff --git a/clang/lib/Tooling/Refactoring/Rename/USRLocFinder.cpp b/clang/lib/Tooling/Refactoring/Rename/USRLocFinder.cpp index 9cdeeec0574b..c18f9290471f 100644 --- a/clang/lib/Tooling/Refactoring/Rename/USRLocFinder.cpp +++ b/clang/lib/Tooling/Refactoring/Rename/USRLocFinder.cpp @@ -562,8 +562,8 @@ createRenameAtomicChanges(llvm::ArrayRef<std::string> USRs, ReplacedName = tooling::replaceNestedName( RenameInfo.Specifier, RenameInfo.Begin, RenameInfo.Context->getDeclContext(), RenameInfo.FromDecl, - NewName.startswith("::") ? NewName.str() - : ("::" + NewName).str()); + NewName.starts_with("::") ? NewName.str() + : ("::" + NewName).str()); } else { // This fixes the case where type `T` is a parameter inside a function // type (e.g. `std::function<void(T)>`) and the DeclContext of `T` @@ -578,13 +578,13 @@ createRenameAtomicChanges(llvm::ArrayRef<std::string> USRs, SM, TranslationUnitDecl->getASTContext().getLangOpts()); // Add the leading "::" back if the name written in the code contains // it. - if (ActualName.startswith("::") && !NewName.startswith("::")) { + if (ActualName.starts_with("::") && !NewName.starts_with("::")) { ReplacedName = "::" + NewName.str(); } } } // If the NewName contains leading "::", add it back. - if (NewName.startswith("::") && NewName.substr(2) == ReplacedName) + if (NewName.starts_with("::") && NewName.substr(2) == ReplacedName) ReplacedName = NewName.str(); } Replace(RenameInfo.Begin, RenameInfo.End, ReplacedName); diff --git a/clang/lib/Tooling/Tooling.cpp b/clang/lib/Tooling/Tooling.cpp index e292fa724d2b..33bfa8d3d81f 100644 --- a/clang/lib/Tooling/Tooling.cpp +++ b/clang/lib/Tooling/Tooling.cpp @@ -255,7 +255,7 @@ llvm::Expected<std::string> getAbsolutePath(llvm::vfs::FileSystem &FS, StringRef File) { StringRef RelativePath(File); // FIXME: Should '.\\' be accepted on Win32? - if (RelativePath.startswith("./")) { + if (RelativePath.starts_with("./")) { RelativePath = RelativePath.substr(strlen("./")); } @@ -294,9 +294,9 @@ void addTargetAndModeForProgramName(std::vector<std::string> &CommandLine, for (auto Token = ++CommandLine.begin(); Token != CommandLine.end(); ++Token) { StringRef TokenRef(*Token); - ShouldAddTarget = ShouldAddTarget && !TokenRef.startswith(TargetOPT) && + ShouldAddTarget = ShouldAddTarget && !TokenRef.starts_with(TargetOPT) && !TokenRef.equals(TargetOPTLegacy); - ShouldAddMode = ShouldAddMode && !TokenRef.startswith(DriverModeOPT); + ShouldAddMode = ShouldAddMode && !TokenRef.starts_with(DriverModeOPT); } if (ShouldAddMode) { CommandLine.insert(++CommandLine.begin(), TargetMode.DriverMode); @@ -507,7 +507,7 @@ static void injectResourceDir(CommandLineArguments &Args, const char *Argv0, void *MainAddr) { // Allow users to override the resource dir. for (StringRef Arg : Args) - if (Arg.startswith("-resource-dir")) + if (Arg.starts_with("-resource-dir")) return; // If there's no override in place add our resource dir. diff --git a/clang/lib/Tooling/Transformer/SourceCode.cpp b/clang/lib/Tooling/Transformer/SourceCode.cpp index 30009537b592..6aae834b0db5 100644 --- a/clang/lib/Tooling/Transformer/SourceCode.cpp +++ b/clang/lib/Tooling/Transformer/SourceCode.cpp @@ -425,7 +425,7 @@ CharSourceRange tooling::getAssociatedRange(const Decl &Decl, for (llvm::StringRef Prefix : {"[[", "__attribute__(("}) { // Handle whitespace between attribute prefix and attribute value. - if (BeforeAttrStripped.endswith(Prefix)) { + if (BeforeAttrStripped.ends_with(Prefix)) { // Move start to start position of prefix, which is // length(BeforeAttr) - length(BeforeAttrStripped) + length(Prefix) // positions to the left. diff --git a/clang/test/AST/Interp/functions.cpp b/clang/test/AST/Interp/functions.cpp index ab562e70606b..179a195098b1 100644 --- a/clang/test/AST/Interp/functions.cpp +++ b/clang/test/AST/Interp/functions.cpp @@ -267,6 +267,17 @@ namespace InvalidCall { // ref-error {{must be initialized by a constant expression}} \ // ref-note {{in call to 'SS()'}} + + /// This should not emit a diagnostic. + constexpr int f(); + constexpr int a() { + return f(); + } + constexpr int f() { + return 5; + } + static_assert(a() == 5, ""); + } namespace CallWithArgs { diff --git a/clang/test/CXX/temp/temp.decls/temp.alias/p3.cpp b/clang/test/CXX/temp/temp.decls/temp.alias/p3.cpp index 2d46502e1d9b..2b33a4ef566d 100644 --- a/clang/test/CXX/temp/temp.decls/temp.alias/p3.cpp +++ b/clang/test/CXX/temp/temp.decls/temp.alias/p3.cpp @@ -2,11 +2,12 @@ // The example given in the standard (this is rejected for other reasons anyway). template<class T> struct A; -template<class T> using B = typename A<T>::U; // expected-error {{no type named 'U' in 'A<T>'}} +template<class T> using B = typename A<T>::U; // expected-error {{no type named 'U' in 'A<short>'}} + // expected-note@-1 {{in instantiation of template class 'A<short>' requested here}} template<class T> struct A { typedef B<T> U; // expected-note {{in instantiation of template type alias 'B' requested here}} }; -B<short> b; +B<short> b; // expected-note {{in instantiation of template type alias 'B' requested here}} template<typename T> using U = int; diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fp_reduce.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fp_reduce.c new file mode 100644 index 000000000000..e58cf4e49a37 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fp_reduce.c @@ -0,0 +1,285 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: aarch64-registered-target +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +#include <arm_neon.h> +#include <arm_sve.h> + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 +#endif + +// FADDQV + +// CHECK-LABEL: @test_svaddqv_f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.addqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) +// CHECK-NEXT: ret <8 x half> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svaddqv_f16u10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.addqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]] +// +float16x8_t test_svaddqv_f16(svbool_t pg, svfloat16_t op) +{ + return SVE_ACLE_FUNC(svaddqv,,_f16,)(pg, op); +} + +// CHECK-LABEL: @test_svaddqv_f32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.addqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CHECK-NEXT: ret <4 x float> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svaddqv_f32u10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.addqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]] +// +float32x4_t test_svaddqv_f32(svbool_t pg, svfloat32_t op) +{ + return SVE_ACLE_FUNC(svaddqv,,_f32,)(pg, op); +} + +// CHECK-LABEL: @test_svaddqv_f64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.addqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CHECK-NEXT: ret <2 x double> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svaddqv_f64u10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.addqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]] +// +float64x2_t test_svaddqv_f64(svbool_t pg, svfloat64_t op) +{ + return SVE_ACLE_FUNC(svaddqv,,_f64,)(pg, op); +} + + +// FMAXQV + +// CHECK-LABEL: @test_svmaxqv_f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fmaxqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) +// CHECK-NEXT: ret <8 x half> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svmaxqv_f16u10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fmaxqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]] +// +float16x8_t test_svmaxqv_f16(svbool_t pg, svfloat16_t op) +{ + return SVE_ACLE_FUNC(svmaxqv,,_f16,)(pg, op); +} + +// CHECK-LABEL: @test_svmaxqv_f32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fmaxqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CHECK-NEXT: ret <4 x float> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svmaxqv_f32u10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fmaxqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]] +// +float32x4_t test_svmaxqv_f32(svbool_t pg, svfloat32_t op) +{ + return SVE_ACLE_FUNC(svmaxqv,,_f32,)(pg, op); +} + +// CHECK-LABEL: @test_svmaxqv_f64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fmaxqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CHECK-NEXT: ret <2 x double> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svmaxqv_f64u10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fmaxqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]] +// +float64x2_t test_svmaxqv_f64(svbool_t pg, svfloat64_t op) +{ + return SVE_ACLE_FUNC(svmaxqv,,_f64,)(pg, op); +} + + +// FMINQV + +// CHECK-LABEL: @test_svminqv_f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fminqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) +// CHECK-NEXT: ret <8 x half> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svminqv_f16u10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fminqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]] +// +float16x8_t test_svminqv_f16(svbool_t pg, svfloat16_t op) +{ + return SVE_ACLE_FUNC(svminqv,,_f16,)(pg, op); +} + +// CHECK-LABEL: @test_svminqv_f32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fminqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CHECK-NEXT: ret <4 x float> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svminqv_f32u10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fminqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]] +// +float32x4_t test_svminqv_f32(svbool_t pg, svfloat32_t op) +{ + return SVE_ACLE_FUNC(svminqv,,_f32,)(pg, op); +} + +// CHECK-LABEL: @test_svminqv_f64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fminqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CHECK-NEXT: ret <2 x double> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svminqv_f64u10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fminqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]] +// +float64x2_t test_svminqv_f64(svbool_t pg, svfloat64_t op) +{ + return SVE_ACLE_FUNC(svminqv,,_f64,)(pg, op); +} + + +// FMAXNMQV + +// CHECK-LABEL: @test_svmaxnmqv_f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fmaxnmqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) +// CHECK-NEXT: ret <8 x half> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z18test_svmaxnmqv_f16u10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fmaxnmqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]] +// +float16x8_t test_svmaxnmqv_f16(svbool_t pg, svfloat16_t op) +{ + return SVE_ACLE_FUNC(svmaxnmqv,,_f16,)(pg, op); +} + +// CHECK-LABEL: @test_svmaxnmqv_f32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fmaxnmqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CHECK-NEXT: ret <4 x float> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z18test_svmaxnmqv_f32u10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fmaxnmqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]] +// +float32x4_t test_svmaxnmqv_f32(svbool_t pg, svfloat32_t op) +{ + return SVE_ACLE_FUNC(svmaxnmqv,,_f32,)(pg, op); +} + +// CHECK-LABEL: @test_svmaxnmqv_f64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fmaxnmqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CHECK-NEXT: ret <2 x double> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z18test_svmaxnmqv_f64u10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fmaxnmqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]] +// +float64x2_t test_svmaxnmqv_f64(svbool_t pg, svfloat64_t op) +{ + return SVE_ACLE_FUNC(svmaxnmqv,,_f64,)(pg, op); +} + + +// FMINNMQV + +// CHECK-LABEL: @test_svminnmqv_f16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fminnmqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) +// CHECK-NEXT: ret <8 x half> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z18test_svminnmqv_f16u10__SVBool_tu13__SVFloat16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.fminnmqv.v8f16.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <8 x half> [[TMP1]] +// +float16x8_t test_svminnmqv_f16(svbool_t pg, svfloat16_t op) +{ + return SVE_ACLE_FUNC(svminnmqv,,_f16,)(pg, op); +} + +// CHECK-LABEL: @test_svminnmqv_f32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fminnmqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CHECK-NEXT: ret <4 x float> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z18test_svminnmqv_f32u10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.fminnmqv.v4f32.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <4 x float> [[TMP1]] +// +float32x4_t test_svminnmqv_f32(svbool_t pg, svfloat32_t op) +{ + return SVE_ACLE_FUNC(svminnmqv,,_f32,)(pg, op); +} + +// CHECK-LABEL: @test_svminnmqv_f64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fminnmqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CHECK-NEXT: ret <2 x double> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z18test_svminnmqv_f64u10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.fminnmqv.v2f64.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <2 x double> [[TMP1]] +// +float64x2_t test_svminnmqv_f64(svbool_t pg, svfloat64_t op) +{ + return SVE_ACLE_FUNC(svminnmqv,,_f64,)(pg, op); +} diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_int_reduce.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_int_reduce.c new file mode 100644 index 000000000000..b395b4d1323e --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_int_reduce.c @@ -0,0 +1,783 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: aarch64-registered-target +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +#include <arm_sve.h> + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 +#endif + + +// ADDQV + +// CHECK-LABEL: @test_svaddqv_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.addqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z15test_svaddqv_s8u10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.addqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_svaddqv_s8(svbool_t pg, svint8_t op1) { + return SVE_ACLE_FUNC(svaddqv,_s8,,)(pg, op1); +} + +// CHECK-LABEL: @test_svaddqv_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.addqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svaddqv_s16u10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.addqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +int16x8_t test_svaddqv_s16(svbool_t pg, svint16_t op1) { + return SVE_ACLE_FUNC(svaddqv,_s16,,)(pg, op1); +} + +// CHECK-LABEL: @test_svaddqv_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.addqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svaddqv_s32u10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.addqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int32x4_t test_svaddqv_s32(svbool_t pg, svint32_t op1) { + return SVE_ACLE_FUNC(svaddqv,_s32,,)(pg, op1); +} + +// CHECK-LABEL: @test_svaddqv_s64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.addqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svaddqv_s64u10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.addqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +int64x2_t test_svaddqv_s64(svbool_t pg, svint64_t op1) { + return SVE_ACLE_FUNC(svaddqv,_s64,,)(pg, op1); +} + +// CHECK-LABEL: @test_svaddqv_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.addqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z15test_svaddqv_u8u10__SVBool_tu11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.addqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_svaddqv_u8(svbool_t pg, svuint8_t op1) { + return SVE_ACLE_FUNC(svaddqv,_u8,,)(pg, op1); +} + +// CHECK-LABEL: @test_svaddqv_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.addqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svaddqv_u16u10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.addqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +uint16x8_t test_svaddqv_u16(svbool_t pg, svuint16_t op1) { + return SVE_ACLE_FUNC(svaddqv,_u16,,)(pg, op1); +} + +// CHECK-LABEL: @test_svaddqv_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.addqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svaddqv_u32u10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.addqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +uint32x4_t test_svaddqv_u32(svbool_t pg, svuint32_t op1) { + return SVE_ACLE_FUNC(svaddqv,_u32,,)(pg, op1); +} + +// CHECK-LABEL: @test_svaddqv_u64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.addqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svaddqv_u64u10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.addqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +uint64x2_t test_svaddqv_u64(svbool_t pg, svuint64_t op1) { + return SVE_ACLE_FUNC(svaddqv,_u64,,)(pg, op1); +} + + +// ANDQV + +// CHECK-LABEL: @test_svandqv_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.andqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z15test_svandqv_s8u10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.andqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_svandqv_s8(svbool_t pg, svint8_t op1) { + return SVE_ACLE_FUNC(svandqv,_s8,,)(pg, op1); +} + +// CHECK-LABEL: @test_svandqv_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.andqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svandqv_s16u10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.andqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +int16x8_t test_svandqv_s16(svbool_t pg, svint16_t op1) { + return SVE_ACLE_FUNC(svandqv,_s16,,)(pg, op1); +} + +// CHECK-LABEL: @test_svandqv_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.andqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svandqv_s32u10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.andqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int32x4_t test_svandqv_s32(svbool_t pg, svint32_t op1) { + return SVE_ACLE_FUNC(svandqv,_s32,,)(pg, op1); +} + +// CHECK-LABEL: @test_svandqv_s64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.andqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svandqv_s64u10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.andqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +int64x2_t test_svandqv_s64(svbool_t pg, svint64_t op1) { + return SVE_ACLE_FUNC(svandqv,_s64,,)(pg, op1); +} + +// CHECK-LABEL: @test_svandqv_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.andqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z15test_svandqv_u8u10__SVBool_tu11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.andqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_svandqv_u8(svbool_t pg, svuint8_t op1) { + return SVE_ACLE_FUNC(svandqv,_u8,,)(pg, op1); +} + +// CHECK-LABEL: @test_svandqv_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.andqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svandqv_u16u10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.andqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +uint16x8_t test_svandqv_u16(svbool_t pg, svuint16_t op1) { + return SVE_ACLE_FUNC(svandqv,_u16,,)(pg, op1); +} + +// CHECK-LABEL: @test_svandqv_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.andqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svandqv_u32u10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.andqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +uint32x4_t test_svandqv_u32(svbool_t pg, svuint32_t op1) { + return SVE_ACLE_FUNC(svandqv,_u32,,)(pg, op1); +} + +// CHECK-LABEL: @test_svandqv_u64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.andqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svandqv_u64u10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.andqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +uint64x2_t test_svandqv_u64(svbool_t pg, svuint64_t op1) { + return SVE_ACLE_FUNC(svandqv,_u64,,)(pg, op1); +} + + +// EORQV + +// CHECK-LABEL: @test_sveorqv_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.eorqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z15test_sveorqv_s8u10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.eorqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_sveorqv_s8(svbool_t pg, svint8_t op1) { + return SVE_ACLE_FUNC(sveorqv,_s8,,)(pg, op1); +} + +// CHECK-LABEL: @test_sveorqv_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.eorqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_sveorqv_s16u10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.eorqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +int16x8_t test_sveorqv_s16(svbool_t pg, svint16_t op1) { + return SVE_ACLE_FUNC(sveorqv,_s16,,)(pg, op1); +} + +// CHECK-LABEL: @test_sveorqv_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.eorqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_sveorqv_s32u10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.eorqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int32x4_t test_sveorqv_s32(svbool_t pg, svint32_t op1) { + return SVE_ACLE_FUNC(sveorqv,_s32,,)(pg, op1); +} + +// CHECK-LABEL: @test_sveorqv_s64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.eorqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_sveorqv_s64u10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.eorqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +int64x2_t test_sveorqv_s64(svbool_t pg, svint64_t op1) { + return SVE_ACLE_FUNC(sveorqv,_s64,,)(pg, op1); +} + +// CHECK-LABEL: @test_sveorqv_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.eorqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z15test_sveorqv_u8u10__SVBool_tu11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.eorqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_sveorqv_u8(svbool_t pg, svuint8_t op1) { + return SVE_ACLE_FUNC(sveorqv,_u8,,)(pg, op1); +} + +// CHECK-LABEL: @test_sveorqv_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.eorqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_sveorqv_u16u10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.eorqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +uint16x8_t test_sveorqv_u16(svbool_t pg, svuint16_t op1) { + return SVE_ACLE_FUNC(sveorqv,_u16,,)(pg, op1); +} + +// CHECK-LABEL: @test_sveorqv_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.eorqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_sveorqv_u32u10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.eorqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +uint32x4_t test_sveorqv_u32(svbool_t pg, svuint32_t op1) { + return SVE_ACLE_FUNC(sveorqv,_u32,,)(pg, op1); +} + +// CHECK-LABEL: @test_sveorqv_u64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.eorqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_sveorqv_u64u10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.eorqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +uint64x2_t test_sveorqv_u64(svbool_t pg, svuint64_t op1) { + return SVE_ACLE_FUNC(sveorqv,_u64,,)(pg, op1); +} + + +// ORQV + +// CHECK-LABEL: @test_svorqv_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.orqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z14test_svorqv_s8u10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.orqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_svorqv_s8(svbool_t pg, svint8_t op1) { + return SVE_ACLE_FUNC(svorqv,_s8,,)(pg, op1); +} + +// CHECK-LABEL: @test_svorqv_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.orqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z15test_svorqv_s16u10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.orqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +int16x8_t test_svorqv_s16(svbool_t pg, svint16_t op1) { + return SVE_ACLE_FUNC(svorqv,_s16,,)(pg, op1); +} + +// CHECK-LABEL: @test_svorqv_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.orqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z15test_svorqv_s32u10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.orqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int32x4_t test_svorqv_s32(svbool_t pg, svint32_t op1) { + return SVE_ACLE_FUNC(svorqv,_s32,,)(pg, op1); +} + +// CHECK-LABEL: @test_svorqv_s64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.orqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z15test_svorqv_s64u10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.orqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +int64x2_t test_svorqv_s64(svbool_t pg, svint64_t op1) { + return SVE_ACLE_FUNC(svorqv,_s64,,)(pg, op1); +} + +// CHECK-LABEL: @test_svorqv_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.orqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z14test_svorqv_u8u10__SVBool_tu11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.orqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_svorqv_u8(svbool_t pg, svuint8_t op1) { + return SVE_ACLE_FUNC(svorqv,_u8,,)(pg, op1); +} + +// CHECK-LABEL: @test_svorqv_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.orqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z15test_svorqv_u16u10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.orqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +uint16x8_t test_svorqv_u16(svbool_t pg, svuint16_t op1) { + return SVE_ACLE_FUNC(svorqv,_u16,,)(pg, op1); +} + +// CHECK-LABEL: @test_svorqv_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.orqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z15test_svorqv_u32u10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.orqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +uint32x4_t test_svorqv_u32(svbool_t pg, svuint32_t op1) { + return SVE_ACLE_FUNC(svorqv,_u32,,)(pg, op1); +} + +// CHECK-LABEL: @test_svorqv_u64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.orqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z15test_svorqv_u64u10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.orqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +uint64x2_t test_svorqv_u64(svbool_t pg, svuint64_t op1) { + return SVE_ACLE_FUNC(svorqv,_u64,,)(pg, op1); +} + + +// SMAXQV + +// CHECK-LABEL: @test_svmaxqv_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.smaxqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z15test_svmaxqv_s8u10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.smaxqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_svmaxqv_s8(svbool_t pg, svint8_t op1) { + return SVE_ACLE_FUNC(svmaxqv,_s8,,)(pg, op1); +} + +// CHECK-LABEL: @test_svmaxqv_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.smaxqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svmaxqv_s16u10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.smaxqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +int16x8_t test_svmaxqv_s16(svbool_t pg, svint16_t op1) { + return SVE_ACLE_FUNC(svmaxqv,_s16,,)(pg, op1); +} + +// CHECK-LABEL: @test_svmaxqv_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.smaxqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svmaxqv_s32u10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.smaxqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int32x4_t test_svmaxqv_s32(svbool_t pg, svint32_t op1) { + return SVE_ACLE_FUNC(svmaxqv,_s32,,)(pg, op1); +} + +// CHECK-LABEL: @test_svmaxqv_s64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.smaxqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svmaxqv_s64u10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.smaxqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +int64x2_t test_svmaxqv_s64(svbool_t pg, svint64_t op1) { + return SVE_ACLE_FUNC(svmaxqv,_s64,,)(pg, op1); +} + + +// UMAXQV + +// CHECK-LABEL: @test_svmaxqv_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.umaxqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z15test_svmaxqv_u8u10__SVBool_tu11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.umaxqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_svmaxqv_u8(svbool_t pg, svuint8_t op1) { + return SVE_ACLE_FUNC(svmaxqv,_u8,,)(pg, op1); +} + +// CHECK-LABEL: @test_svmaxqv_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.umaxqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svmaxqv_u16u10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.umaxqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +uint16x8_t test_svmaxqv_u16(svbool_t pg, svuint16_t op1) { + return SVE_ACLE_FUNC(svmaxqv,_u16,,)(pg, op1); +} + +// CHECK-LABEL: @test_svmaxqv_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.umaxqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svmaxqv_u32u10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.umaxqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +uint32x4_t test_svmaxqv_u32(svbool_t pg, svuint32_t op1) { + return SVE_ACLE_FUNC(svmaxqv,_u32,,)(pg, op1); +} + +// CHECK-LABEL: @test_svmaxqv_u64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.umaxqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svmaxqv_u64u10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.umaxqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +uint64x2_t test_svmaxqv_u64(svbool_t pg, svuint64_t op1) { + return SVE_ACLE_FUNC(svmaxqv,_u64,,)(pg, op1); +} + + +// SMINQV + +// CHECK-LABEL: @test_svminqv_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.sminqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z15test_svminqv_s8u10__SVBool_tu10__SVInt8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.sminqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_svminqv_s8(svbool_t pg, svint8_t op1) { + return SVE_ACLE_FUNC(svminqv,_s8,,)(pg, op1); +} + +// CHECK-LABEL: @test_svminqv_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.sminqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svminqv_s16u10__SVBool_tu11__SVInt16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.sminqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +int16x8_t test_svminqv_s16(svbool_t pg, svint16_t op1) { + return SVE_ACLE_FUNC(svminqv,_s16,,)(pg, op1); +} + +// CHECK-LABEL: @test_svminqv_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.sminqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svminqv_s32u10__SVBool_tu11__SVInt32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.sminqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +int32x4_t test_svminqv_s32(svbool_t pg, svint32_t op1) { + return SVE_ACLE_FUNC(svminqv,_s32,,)(pg, op1); +} + +// CHECK-LABEL: @test_svminqv_s64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.sminqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svminqv_s64u10__SVBool_tu11__SVInt64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.sminqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +int64x2_t test_svminqv_s64(svbool_t pg, svint64_t op1) { + return SVE_ACLE_FUNC(svminqv,_s64,,)(pg, op1); +} + + +// UMINQV + +// CHECK-LABEL: @test_svminqv_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.uminqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z15test_svminqv_u8u10__SVBool_tu11__SVUint8_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <16 x i8> @llvm.aarch64.sve.uminqv.v16i8.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_svminqv_u8(svbool_t pg, svuint8_t op1) { + return SVE_ACLE_FUNC(svminqv,_u8,,)(pg, op1); +} + +// CHECK-LABEL: @test_svminqv_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.uminqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svminqv_u16u10__SVBool_tu12__SVUint16_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i16> @llvm.aarch64.sve.uminqv.v8i16.nxv8i16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <8 x i16> [[TMP1]] +// +uint16x8_t test_svminqv_u16(svbool_t pg, svuint16_t op1) { + return SVE_ACLE_FUNC(svminqv,_u16,,)(pg, op1); +} + +// CHECK-LABEL: @test_svminqv_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.uminqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svminqv_u32u10__SVBool_tu12__SVUint32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.aarch64.sve.uminqv.v4i32.nxv4i32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <4 x i32> [[TMP1]] +// +uint32x4_t test_svminqv_u32(svbool_t pg, svuint32_t op1) { + return SVE_ACLE_FUNC(svminqv,_u32,,)(pg, op1); +} + +// CHECK-LABEL: @test_svminqv_u64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.uminqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z16test_svminqv_u64u10__SVBool_tu12__SVUint64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.aarch64.sve.uminqv.v2i64.nxv2i64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP1:%.*]]) +// CPP-CHECK-NEXT: ret <2 x i64> [[TMP1]] +// +uint64x2_t test_svminqv_u64(svbool_t pg, svuint64_t op1) { + return SVE_ACLE_FUNC(svminqv,_u64,,)(pg, op1); +} diff --git a/clang/test/CodeGen/arm-vector_type-params-returns.c b/clang/test/CodeGen/arm-vector_type-params-returns.c new file mode 100644 index 000000000000..14c3512ab81a --- /dev/null +++ b/clang/test/CodeGen/arm-vector_type-params-returns.c @@ -0,0 +1,136 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 + +// RUN: %clang_cc1 -DSVE_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1 -DSVE_HEADER -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o - /dev/null %s + +// RUN: %clang_cc1 -DNEON_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1 -DNEON_HEADER -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o - /dev/null %s + +// RUN: %clang_cc1 -DSVE_HEADER -DNEON_HEADER -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1 -DSVE_HEADER -DNEON_HEADER -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o - /dev/null %s + +// RUN: %clang_cc1 -DNEON_HEADER -DSVE_HEADER2 -triple aarch64 -target-feature +sve -emit-llvm -O2 -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1 -DNEON_HEADER -DSVE_HEADER2 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -o - /dev/null %s + +// REQUIRES: aarch64-registered-target + +#ifdef SVE_HEADER + #include <arm_sve.h> +#endif + +#ifdef NEON_HEADER + #include <arm_neon.h> +#endif + +#ifdef SVE_HEADER_2 + #include <arm_sve.h> +#endif + +// function return types +// CHECK-LABEL: define dso_local <8 x half> @test_ret_v8f16( +// CHECK-SAME: <8 x half> noundef returned [[V:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret <8 x half> [[V]] +// +float16x8_t test_ret_v8f16(float16x8_t v) { + return v; +} + +// CHECK-LABEL: define dso_local <4 x float> @test_ret_v4f32( +// CHECK-SAME: <4 x float> noundef returned [[V:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret <4 x float> [[V]] +// +float32x4_t test_ret_v4f32(float32x4_t v) { + return v; +} + +// CHECK-LABEL: define dso_local <2 x double> @test_ret_v2f64( +// CHECK-SAME: <2 x double> noundef returned [[V:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret <2 x double> [[V]] +// +float64x2_t test_ret_v2f64(float64x2_t v) { + return v; +} + +// CHECK-LABEL: define dso_local <8 x bfloat> @test_ret_v8bf16( +// CHECK-SAME: <8 x bfloat> noundef returned [[V:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret <8 x bfloat> [[V]] +// +bfloat16x8_t test_ret_v8bf16(bfloat16x8_t v) { + return v; +} + +// CHECK-LABEL: define dso_local <16 x i8> @test_ret_v16s8( +// CHECK-SAME: <16 x i8> noundef returned [[V:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret <16 x i8> [[V]] +// +int8x16_t test_ret_v16s8(int8x16_t v) { + return v; +} + +// CHECK-LABEL: define dso_local <8 x i16> @test_ret_v8s16( +// CHECK-SAME: <8 x i16> noundef returned [[V:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret <8 x i16> [[V]] +// +int16x8_t test_ret_v8s16(int16x8_t v) { + return v; +} + +// CHECK-LABEL: define dso_local <4 x i32> @test_ret_v32s4( +// CHECK-SAME: <4 x i32> noundef returned [[V:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret <4 x i32> [[V]] +// +int32x4_t test_ret_v32s4(int32x4_t v) { + return v; +} + +// CHECK-LABEL: define dso_local <2 x i64> @test_ret_v64s2( +// CHECK-SAME: <2 x i64> noundef returned [[V:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret <2 x i64> [[V]] +// +int64x2_t test_ret_v64s2(int64x2_t v) { + return v; +} + +// CHECK-LABEL: define dso_local <16 x i8> @test_ret_v16u8( +// CHECK-SAME: <16 x i8> noundef returned [[V:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret <16 x i8> [[V]] +// +uint8x16_t test_ret_v16u8(uint8x16_t v) { + return v; +} + +// CHECK-LABEL: define dso_local <8 x i16> @test_ret_v8u16( +// CHECK-SAME: <8 x i16> noundef returned [[V:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret <8 x i16> [[V]] +// +uint16x8_t test_ret_v8u16(uint16x8_t v) { + return v; +} + +// CHECK-LABEL: define dso_local <4 x i32> @test_ret_v32u4( +// CHECK-SAME: <4 x i32> noundef returned [[V:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret <4 x i32> [[V]] +// +uint32x4_t test_ret_v32u4(uint32x4_t v) { + return v; +} + +// CHECK-LABEL: define dso_local <2 x i64> @test_ret_v64u2( +// CHECK-SAME: <2 x i64> noundef returned [[V:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: ret <2 x i64> [[V]] +// +uint64x2_t test_ret_v64u2(uint64x2_t v) { + return v; +} diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-err.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-err.cl new file mode 100644 index 000000000000..5e0153c42825 --- /dev/null +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-err.cl @@ -0,0 +1,24 @@ +// REQUIRES: amdgpu-registered-target + +// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx1200 -verify -S -emit-llvm -o - %s + +kernel void builtins_amdgcn_s_barrier_signal_err(global int* in, global int* out, int barrier) { + + __builtin_amdgcn_s_barrier_signal(barrier); // expected-error {{'__builtin_amdgcn_s_barrier_signal' must be a constant integer}} + __builtin_amdgcn_s_barrier_wait(-1); + *out = *in; +} + +kernel void builtins_amdgcn_s_barrier_wait_err(global int* in, global int* out, int barrier) { + + __builtin_amdgcn_s_barrier_signal(-1); + __builtin_amdgcn_s_barrier_wait(barrier); // expected-error {{'__builtin_amdgcn_s_barrier_wait' must be a constant integer}} + *out = *in; +} + +kernel void builtins_amdgcn_s_barrier_signal_isfirst_err(global int* in, global int* out, int barrier) { + + __builtin_amdgcn_s_barrier_signal_isfirst(barrier); // expected-error {{'__builtin_amdgcn_s_barrier_signal_isfirst' must be a constant integer}} + __builtin_amdgcn_s_barrier_wait(-1); + *out = *in; +} diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl new file mode 100644 index 000000000000..b8d281531e21 --- /dev/null +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl @@ -0,0 +1,174 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown -target-cpu gfx1200 -S -emit-llvm -o - %s | FileCheck %s + +// CHECK-LABEL: @test_s_barrier_signal( +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -1) +// CHECK-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1) +// CHECK-NEXT: ret void +// +void test_s_barrier_signal() +{ + __builtin_amdgcn_s_barrier_signal(-1); + __builtin_amdgcn_s_barrier_wait(-1); +} + +// CHECK-LABEL: @test_s_barrier_signal_var( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 [[A:%.*]], ptr addrspace(5) [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(5) [[A_ADDR]], align 4 +// CHECK-NEXT: call void @llvm.amdgcn.s.barrier.signal.var(i32 [[TMP0]]) +// CHECK-NEXT: ret void +// +void test_s_barrier_signal_var(int a) +{ + __builtin_amdgcn_s_barrier_signal_var(a); +} + +// CHECK-LABEL: @test_s_barrier_signal_isfirst( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: store ptr [[A:%.*]], ptr addrspace(5) [[A_ADDR]], align 8 +// CHECK-NEXT: store ptr [[B:%.*]], ptr addrspace(5) [[B_ADDR]], align 8 +// CHECK-NEXT: store ptr [[C:%.*]], ptr addrspace(5) [[C_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 1) +// CHECK-NEXT: br i1 [[TMP0]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +// CHECK: if.then: +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr addrspace(5) [[B_ADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr addrspace(5) [[A_ADDR]], align 8 +// CHECK-NEXT: br label [[IF_END:%.*]] +// CHECK: if.else: +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr addrspace(5) [[C_ADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr addrspace(5) [[A_ADDR]], align 8 +// CHECK-NEXT: br label [[IF_END]] +// CHECK: if.end: +// CHECK-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 1) +// CHECK-NEXT: ret void +// +void test_s_barrier_signal_isfirst(int* a, int* b, int *c) +{ + if(__builtin_amdgcn_s_barrier_signal_isfirst(1)) + a = b; + else + a = c; + + __builtin_amdgcn_s_barrier_wait(1); +} + +// CHECK-LABEL: @test_s_barrier_isfirst_var( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[D_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store ptr [[A:%.*]], ptr addrspace(5) [[A_ADDR]], align 8 +// CHECK-NEXT: store ptr [[B:%.*]], ptr addrspace(5) [[B_ADDR]], align 8 +// CHECK-NEXT: store ptr [[C:%.*]], ptr addrspace(5) [[C_ADDR]], align 8 +// CHECK-NEXT: store i32 [[D:%.*]], ptr addrspace(5) [[D_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(5) [[D_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst.var(i32 [[TMP0]]) +// CHECK-NEXT: br i1 [[TMP1]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +// CHECK: if.then: +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr addrspace(5) [[B_ADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr addrspace(5) [[A_ADDR]], align 8 +// CHECK-NEXT: br label [[IF_END:%.*]] +// CHECK: if.else: +// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr addrspace(5) [[C_ADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP3]], ptr addrspace(5) [[A_ADDR]], align 8 +// CHECK-NEXT: br label [[IF_END]] +// CHECK: if.end: +// CHECK-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 1) +// CHECK-NEXT: ret void +// +void test_s_barrier_isfirst_var(int* a, int* b, int *c, int d) +{ + if ( __builtin_amdgcn_s_barrier_signal_isfirst_var(d)) + a = b; + else + a = c; + + __builtin_amdgcn_s_barrier_wait(1); + +} + +// CHECK-LABEL: @test_s_barrier_init( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 [[A:%.*]], ptr addrspace(5) [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(5) [[A_ADDR]], align 4 +// CHECK-NEXT: call void @llvm.amdgcn.s.barrier.init(i32 1, i32 [[TMP0]]) +// CHECK-NEXT: ret void +// +void test_s_barrier_init(int a) +{ + __builtin_amdgcn_s_barrier_init(1, a); +} + +// CHECK-LABEL: @test_s_barrier_join( +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @llvm.amdgcn.s.barrier.join(i32 1) +// CHECK-NEXT: ret void +// +void test_s_barrier_join() +{ + __builtin_amdgcn_s_barrier_join(1); +} + +// CHECK-LABEL: @test_s_wakeup_barrier( +// CHECK-NEXT: entry: +// CHECK-NEXT: call void @llvm.amdgcn.s.barrier.join(i32 1) +// CHECK-NEXT: ret void +// +void test_s_wakeup_barrier() +{ + __builtin_amdgcn_s_barrier_join(1); +} + +// CHECK-LABEL: @test_s_barrier_leave( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// CHECK-NEXT: store ptr [[A:%.*]], ptr addrspace(5) [[A_ADDR]], align 8 +// CHECK-NEXT: store ptr [[B:%.*]], ptr addrspace(5) [[B_ADDR]], align 8 +// CHECK-NEXT: store ptr [[C:%.*]], ptr addrspace(5) [[C_ADDR]], align 8 +// CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.s.barrier.leave() +// CHECK-NEXT: br i1 [[TMP0]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +// CHECK: if.then: +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr addrspace(5) [[B_ADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP1]], ptr addrspace(5) [[A_ADDR]], align 8 +// CHECK-NEXT: br label [[IF_END:%.*]] +// CHECK: if.else: +// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr addrspace(5) [[C_ADDR]], align 8 +// CHECK-NEXT: store ptr [[TMP2]], ptr addrspace(5) [[A_ADDR]], align 8 +// CHECK-NEXT: br label [[IF_END]] +// CHECK: if.end: +// CHECK-NEXT: ret void +// +void test_s_barrier_leave(int* a, int* b, int *c) +{ + if (__builtin_amdgcn_s_barrier_leave()) + a = b; + else + a = c; +} + +// CHECK-LABEL: @test_s_get_barrier_state( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: [[STATE:%.*]] = alloca i32, align 4, addrspace(5) +// CHECK-NEXT: store i32 [[A:%.*]], ptr addrspace(5) [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(5) [[A_ADDR]], align 4 +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.s.get.barrier.state(i32 [[TMP0]]) +// CHECK-NEXT: store i32 [[TMP1]], ptr addrspace(5) [[STATE]], align 4 +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(5) [[STATE]], align 4 +// CHECK-NEXT: ret i32 [[TMP2]] +// +unsigned test_s_get_barrier_state(int a) +{ + unsigned State = __builtin_amdgcn_s_get_barrier_state(a); + return State; +} diff --git a/clang/test/Driver/cl-options.c b/clang/test/Driver/cl-options.c index 81d1b907eced..5b6dfe308a76 100644 --- a/clang/test/Driver/cl-options.c +++ b/clang/test/Driver/cl-options.c @@ -272,10 +272,12 @@ // RUN: not %clang_cl /vmg /vmm /vms -### -- %s 2>&1 | FileCheck -check-prefix=VMX %s // VMX: '/vms' not allowed with '/vmm' -// RUN: %clang_cl /volatile:iso -### -- %s 2>&1 | FileCheck -check-prefix=VOLATILE-ISO %s +// RUN: %clang_cl --target=i686-pc-win32 /volatile:iso -### -- %s 2>&1 | FileCheck -check-prefix=VOLATILE-ISO %s +// RUN: %clang_cl --target=aarch64-pc-win32 -### -- %s 2>&1 | FileCheck -check-prefix=VOLATILE-ISO %s // VOLATILE-ISO-NOT: "-fms-volatile" -// RUN: %clang_cl /volatile:ms -### -- %s 2>&1 | FileCheck -check-prefix=VOLATILE-MS %s +// RUN: %clang_cl --target=aarch64-pc-win32 /volatile:ms -### -- %s 2>&1 | FileCheck -check-prefix=VOLATILE-MS %s +// RUN: %clang_cl --target=i686-pc-win32 -### -- %s 2>&1 | FileCheck -check-prefix=VOLATILE-MS %s // VOLATILE-MS: "-fms-volatile" // RUN: %clang_cl /W0 -### -- %s 2>&1 | FileCheck -check-prefix=W0 %s diff --git a/clang/test/Driver/clang_f_opts.c b/clang/test/Driver/clang_f_opts.c index ebe8a0520bf0..c8b44e056e58 100644 --- a/clang/test/Driver/clang_f_opts.c +++ b/clang/test/Driver/clang_f_opts.c @@ -611,3 +611,9 @@ // CHECK-INT-OBJEMITTER-NOT: unsupported option '-fintegrated-objemitter' for target // RUN: not %clang -### -fno-integrated-objemitter --target=x86_64 %s 2>&1 | FileCheck -check-prefix=CHECK-NOINT-OBJEMITTER %s // CHECK-NOINT-OBJEMITTER: unsupported option '-fno-integrated-objemitter' for target + +// RUN: %clang -### --target=aarch64-windows-msvc %s 2>&1 | FileCheck -check-prefix=CHECK-NO-MS-VOLATILE %s +// RUN: %clang -### --target=aarch64-windows-msvc -fms-volatile %s 2>&1 | FileCheck -check-prefix=CHECK-MS-VOLATILE %s +// RUN: %clang -### --target=aarch64-windows-msvc -fno-ms-volatile %s 2>&1 | FileCheck -check-prefix=CHECK-NO-MS-VOLATILE %s +// CHECK-MS-VOLATILE: -fms-volatile +// CHECK-NO-MS-VOLATILE-NOT: -fms-volatile diff --git a/clang/test/Driver/darwin-builtin-modules.c b/clang/test/Driver/darwin-builtin-modules.c index 215f2b8d2c14..1c56e13bfb92 100644 --- a/clang/test/Driver/darwin-builtin-modules.c +++ b/clang/test/Driver/darwin-builtin-modules.c @@ -9,19 +9,3 @@ // RUN: %clang -isysroot %S/Inputs/MacOSX99.0.sdk -target x86_64-apple-macos98.0 -### %s 2>&1 | FileCheck --check-prefix=CHECK_FUTURE %s // RUN: %clang -isysroot %S/Inputs/MacOSX99.0.sdk -target x86_64-apple-macos99.0 -### %s 2>&1 | FileCheck --check-prefix=CHECK_FUTURE %s // CHECK_FUTURE-NOT: -fbuiltin-headers-in-system-modules - - -// Check that builtin_headers_in_system_modules is only set if -fbuiltin-headers-in-system-modules and -fmodules are both set. - -// RUN: %clang -isysroot %S/Inputs/iPhoneOS13.0.sdk -target arm64-apple-ios13.0 -fsyntax-only %s -Xclang -verify=no-feature -// RUN: %clang -isysroot %S/Inputs/iPhoneOS13.0.sdk -target arm64-apple-ios13.0 -fsyntax-only %s -fmodules -Xclang -verify=yes-feature -// RUN: %clang -isysroot %S/Inputs/MacOSX99.0.sdk -target x86_64-apple-macos99.0 -fsyntax-only %s -Xclang -verify=no-feature -// RUN: %clang -isysroot %S/Inputs/MacOSX99.0.sdk -target x86_64-apple-macos99.0 -fsyntax-only %s -fmodules -Xclang -verify=no-feature - -#if __has_feature(builtin_headers_in_system_modules) -#error "has builtin_headers_in_system_modules" -// yes-feature-error@-1 {{}} -#else -#error "no builtin_headers_in_system_modules" -// no-feature-error@-1 {{}} -#endif diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 6fc921a8c6ee..35208b2eae8f 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1056,12 +1056,12 @@ // CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 8000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zicfilp0p2 -x c -E -dM %s \ +// RUN: -march=rv32i_zicfilp0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s // RUN: %clang --target=riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zicfilp0p2 -x c -E -dM %s \ +// RUN: -march=rv64i_zicfilp0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s -// CHECK-ZICFILP-EXT: __riscv_zicfilp 2000{{$}} +// CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \ diff --git a/clang/test/Sema/aarch64-sve-intrinsics/acle_sve_target.cpp b/clang/test/Sema/aarch64-sve-intrinsics/acle_sve_target.cpp index f41030c18e93..2f771ca170e7 100644 --- a/clang/test/Sema/aarch64-sve-intrinsics/acle_sve_target.cpp +++ b/clang/test/Sema/aarch64-sve-intrinsics/acle_sve_target.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -fsyntax-only -verify -emit-llvm -o - -ferror-limit 100 %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -fsyntax-only -verify -emit-llvm -o - -ferror-limit 100 %s // REQUIRES: aarch64-registered-target // Test that functions with the correct target attributes can use the correct SVE intrinsics. @@ -29,4 +29,5 @@ void __attribute__((target("sve2-sha3"))) test_sve2_sha3() void __attribute__((target("sve2"))) test_f16(svbool_t pg) { svlogb_f16_z(pg, svundef_f16()); -}
\ No newline at end of file +} + diff --git a/clang/test/Sema/arm-vector-types-support.c b/clang/test/Sema/arm-vector-types-support.c index fa101afa3122..83a83ddfe780 100644 --- a/clang/test/Sema/arm-vector-types-support.c +++ b/clang/test/Sema/arm-vector-types-support.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 %s -triple armv7 -fsyntax-only -verify -typedef __attribute__((neon_vector_type(2))) int int32x2_t; // expected-error{{'neon_vector_type' attribute is not supported on targets missing 'neon' or 'mve'; specify an appropriate -march= or -mcpu=}} +typedef __attribute__((neon_vector_type(2))) int int32x2_t; // expected-error{{'neon_vector_type' attribute is not supported on targets missing 'neon', 'mve', 'sve' or 'sme'; specify an appropriate -march= or -mcpu=}} typedef __attribute__((neon_polyvector_type(16))) short poly8x16_t; // expected-error{{'neon_polyvector_type' attribute is not supported on targets missing 'neon' or 'mve'; specify an appropriate -march= or -mcpu=}} typedef __attribute__((arm_sve_vector_bits(256))) void nosveflag; // expected-error{{'arm_sve_vector_bits' attribute is not supported on targets missing 'sve'; specify an appropriate -march= or -mcpu=}} diff --git a/clang/test/Sema/missing-field-initializers.c b/clang/test/Sema/missing-field-initializers.c index 1e65b2d62e1a..8653591ff118 100644 --- a/clang/test/Sema/missing-field-initializers.c +++ b/clang/test/Sema/missing-field-initializers.c @@ -18,7 +18,7 @@ struct Foo bar1[] = { 1, 2, 1, 2, 1 -}; // expected-warning {{missing field 'b' initializer}} +}; // expected-warning@-1 {{missing field 'b' initializer}} struct Foo bar2[] = { {}, {}, {} }; diff --git a/clang/test/SemaCUDA/neon-attrs.cu b/clang/test/SemaCUDA/neon-attrs.cu index a72b03f3bbbd..129056741ac9 100644 --- a/clang/test/SemaCUDA/neon-attrs.cu +++ b/clang/test/SemaCUDA/neon-attrs.cu @@ -15,7 +15,8 @@ // quiet-no-diagnostics typedef __attribute__((neon_vector_type(4))) float float32x4_t; -// expected-error@-1 {{'neon_vector_type' attribute is not supported on targets missing 'neon' or 'mve'}} +// expected-error@-1 {{'neon_vector_type' attribute is not supported on targets missing 'neon', 'mve', 'sve' or 'sme'}} +// expect typedef unsigned char poly8_t; typedef __attribute__((neon_polyvector_type(8))) poly8_t poly8x8_t; // expected-error@-1 {{'neon_polyvector_type' attribute is not supported on targets missing 'neon' or 'mve'}} diff --git a/clang/test/SemaCXX/alias-template.cpp b/clang/test/SemaCXX/alias-template.cpp index 5189405e23db..dca63e15f5bb 100644 --- a/clang/test/SemaCXX/alias-template.cpp +++ b/clang/test/SemaCXX/alias-template.cpp @@ -192,3 +192,68 @@ int g = sfinae_me<int>(); // expected-error{{no matching function for call to 's namespace NullExceptionDecl { template<int... I> auto get = []() { try { } catch(...) {}; return I; }; // expected-error{{initializer contains unexpanded parameter pack 'I'}} } + +namespace GH41693 { +// No errors when a type alias defined in a class or a friend of a class +// accesses private members of the same class. +struct S { +private: + template <typename> static constexpr void Impl() {} + +public: + template <typename X> using U = decltype(Impl<X>()); +}; + +using X = S::U<void>; +struct Y { +private: + static constexpr int x=0; + + template <typename> + static constexpr int y=0; + + template <typename> + static constexpr int foo(); + +public: + template <typename U> + using bar1 = decltype(foo<U>()); + using bar2 = decltype(x); + template <typename U> + using bar3 = decltype(y<U>); +}; + + +using type1 = Y::bar1<float>; +using type2 = Y::bar2; +using type3 = Y::bar3<float>; + +struct theFriend{ + template<class T> + using theAlias = decltype(&T::i); +}; + +class theC{ + int i; + public: + friend struct theFriend; +}; + +int foo(){ + (void)sizeof(theFriend::theAlias<theC>); +} + +// Test case that regressed with the first iteration of the fix for GH41693. +template <typename T> class SP { + T* data; +}; + +template <typename T> class A { + static SP<A> foo(); +}; + +template<typename T> using TRet = SP<A<T>>; + +template<typename T> TRet<T> A<T>::foo() { return TRet<T>{};}; + +} diff --git a/clang/test/SemaCXX/cxx2a-initializer-aggregates.cpp b/clang/test/SemaCXX/cxx2a-initializer-aggregates.cpp index 510ace58c35a..0d977e07ed03 100644 --- a/clang/test/SemaCXX/cxx2a-initializer-aggregates.cpp +++ b/clang/test/SemaCXX/cxx2a-initializer-aggregates.cpp @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -std=c++20 %s -verify=cxx20,expected,pedantic,override,reorder -pedantic-errors // RUN: %clang_cc1 -std=c++17 %s -verify=expected,pedantic,override,reorder -Wno-c++20-designator -pedantic-errors -// RUN: %clang_cc1 -std=c++20 %s -verify=cxx20,expected,pedantic -Werror=c99-designator -Wno-reorder-init-list -Wno-initializer-overrides +// RUN: %clang_cc1 -std=c++20 %s -verify=cxx20,expected,pedantic -Werror=c99-designator -Wno-reorder-init-list -Wno-initializer-overrides -Werror=nested-anon-types -Werror=gnu-anonymous-struct // RUN: %clang_cc1 -std=c++20 %s -verify=cxx20,expected,reorder -Wno-c99-designator -Werror=reorder-init-list -Wno-initializer-overrides // RUN: %clang_cc1 -std=c++20 %s -verify=cxx20,expected,override -Wno-c99-designator -Wno-reorder-init-list -Werror=initializer-overrides // RUN: %clang_cc1 -std=c++20 %s -verify=cxx20,expected -Wno-c99-designator -Wno-reorder-init-list -Wno-initializer-overrides @@ -39,6 +39,7 @@ A a1 = { }; int arr[3] = {[1] = 5}; // pedantic-error {{array designators are a C99 extension}} B b = {.a.x = 0}; // pedantic-error {{nested designators are a C99 extension}} + // wmissing-warning@-1 {{missing field 'y' initializer}} A a2 = { .x = 1, // pedantic-error {{mixture of designated and non-designated initializers in the same initializer list is a C99 extension}} 2 // pedantic-note {{first non-designated initializer is here}} @@ -60,7 +61,6 @@ B b2 = {.a = 1}; // pedantic-error {{brace elision for designated initializer is B b3 = {.a = 1, 2}; // pedantic-error {{mixture of designated and non-designated}} pedantic-note {{first non-designated}} pedantic-error {{brace elision}} B b4 = {.a = 1, 2, 3}; // pedantic-error {{mixture of designated and non-designated}} pedantic-note {{first non-designated}} pedantic-error {{brace elision}} expected-error {{excess elements}} B b5 = {.a = nullptr}; // expected-error {{cannot initialize}} - // wmissing-warning@-1 {{missing field 'y' initializer}} struct C { int :0, x, :0, y, :0; }; C c = { .x = 1, // override-note {{previous}} @@ -247,3 +247,87 @@ void foo() { // } } + +namespace GH70384 { + +struct A { + int m; + union { int a; float n = 0; }; +}; + +struct B { + int m; + int b; + union { int a ; }; +}; + +union CU { + int a = 1; + double b; +}; + +struct C { + int a; + union { int b; CU c;}; +}; + +struct CC { + int a; + CU c; +}; + +void foo() { + A a = A{.m = 0}; + A aa = {0}; + A aaa = {.a = 7}; // wmissing-warning {{missing field 'm' initializer}} + B b = {.m = 1, .b = 3 }; //wmissing-warning {{missing field 'a' initializer}} + B bb = {1}; // wmissing-warning {{missing field 'b' initializer}} + // wmissing-warning@-1 {{missing field 'a' initializer}} + C c = {.a = 1}; // wmissing-warning {{missing field 'b' initializer}} + CC cc = {.a = 1}; // wmissing-warning {{missing field 'c' initializer}} +} + +struct C1 { + int m; + union { float b; union {int n = 1; }; }; + // pedantic-error@-1 {{anonymous types declared in an anonymous union are an extension}} +}; + +struct C2 { + int m; + struct { float b; int n = 1; }; // pedantic-error {{anonymous structs are a GNU extension}} +}; + +struct C3 { + int m; + struct { float b = 1; union {int a;}; int n = 1; }; + // pedantic-error@-1 {{anonymous structs are a GNU extension}} + // pedantic-error@-2 {{anonymous types declared in an anonymous struct are an extension}} +}; + +C1 c = C1{.m = 1}; +C1 cc = C1{.b = 1}; // wmissing-warning {{missing field 'm' initializer}} +C2 c1 = C2{.m = 1}; // wmissing-warning {{missing field 'b' initializer}} +C2 c22 = C2{.m = 1, .b = 1}; +C3 c2 = C3{.b = 1}; // wmissing-warning {{missing field 'a' initializer}} + // wmissing-warning@-1 {{missing field 'm' initializer}} + +struct C4 { + union { + struct { int n; }; // pedantic-error {{anonymous structs are a GNU extension}} + // pedantic-error@-1 {{anonymous types declared in an anonymous union are an extension}} + int m = 0; }; + int z; +}; +C4 a = {.z = 1}; + +struct C5 { + int a; + struct { // pedantic-error {{anonymous structs are a GNU extension}} + int x; + struct { int y = 0; }; // pedantic-error {{anonymous types declared in an anonymous struct are an extension}} + // pedantic-error@-1 {{anonymous structs are a GNU extension}} + }; +}; +C5 c5 = C5{.a = 0}; //wmissing-warning {{missing field 'x' initializer}} +} diff --git a/clang/tools/arcmt-test/arcmt-test.cpp b/clang/tools/arcmt-test/arcmt-test.cpp index 53229ac570bc..b61f38e9905d 100644 --- a/clang/tools/arcmt-test/arcmt-test.cpp +++ b/clang/tools/arcmt-test/arcmt-test.cpp @@ -230,7 +230,7 @@ static bool verifyTransformedFiles(ArrayRef<std::string> resultFiles) { for (ArrayRef<std::string>::iterator I = resultFiles.begin(), E = resultFiles.end(); I != E; ++I) { StringRef fname(*I); - if (!fname.endswith(".result")) { + if (!fname.ends_with(".result")) { errs() << "error: filename '" << fname << "' does not have '.result' extension\n"; return true; diff --git a/clang/tools/c-arcmt-test/c-arcmt-test.c b/clang/tools/c-arcmt-test/c-arcmt-test.c index 3bbb2d5d6a85..00999f188c7d 100644 --- a/clang/tools/c-arcmt-test/c-arcmt-test.c +++ b/clang/tools/c-arcmt-test/c-arcmt-test.c @@ -1,8 +1,9 @@ /* c-arcmt-test.c */ #include "clang-c/Index.h" -#include <stdlib.h> +#include "llvm/Support/AutoConvert.h" #include <stdio.h> +#include <stdlib.h> #include <string.h> #if defined(_WIN32) #include <io.h> @@ -107,6 +108,14 @@ static void flush_atexit(void) { } int main(int argc, const char **argv) { +#ifdef __MVS__ + if (enableAutoConversion(fileno(stdout)) == -1) + fprintf(stderr, "Setting conversion on stdout failed\n"); + + if (enableAutoConversion(fileno(stderr)) == -1) + fprintf(stderr, "Setting conversion on stderr failed\n"); +#endif + thread_info client_data; atexit(flush_atexit); diff --git a/clang/tools/c-index-test/c-index-test.c b/clang/tools/c-index-test/c-index-test.c index 2c0c9cb8eb5e..6fa400a0675b 100644 --- a/clang/tools/c-index-test/c-index-test.c +++ b/clang/tools/c-index-test/c-index-test.c @@ -8,6 +8,7 @@ #include "clang-c/Documentation.h" #include "clang-c/Index.h" #include "clang/Config/config.h" +#include "llvm/Support/AutoConvert.h" #include <assert.h> #include <ctype.h> #include <stdio.h> @@ -5150,6 +5151,14 @@ static void flush_atexit(void) { int main(int argc, const char **argv) { thread_info client_data; +#ifdef __MVS__ + if (enableAutoConversion(fileno(stdout)) == -1) + fprintf(stderr, "Setting conversion on stdout failed\n"); + + if (enableAutoConversion(fileno(stderr)) == -1) + fprintf(stderr, "Setting conversion on stderr failed\n"); +#endif + atexit(flush_atexit); #ifdef CLANG_HAVE_LIBXML diff --git a/clang/tools/clang-extdef-mapping/ClangExtDefMapGen.cpp b/clang/tools/clang-extdef-mapping/ClangExtDefMapGen.cpp index 769727eedec7..c048f335f91c 100644 --- a/clang/tools/clang-extdef-mapping/ClangExtDefMapGen.cpp +++ b/clang/tools/clang-extdef-mapping/ClangExtDefMapGen.cpp @@ -181,7 +181,7 @@ static int HandleFiles(ArrayRef<std::string> SourceFiles, // process them directly in HandleAST, otherwise put them // on a list for ClangTool to handle. for (StringRef Src : SourceFiles) { - if (Src.endswith(".ast")) { + if (Src.ends_with(".ast")) { if (!HandleAST(Src)) { return 1; } diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index 5d2fe98fe560..bd2fd02c6a3e 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -1151,7 +1151,7 @@ linkAndWrapDeviceFiles(SmallVectorImpl<OffloadFile> &LinkerInputFiles, std::optional<std::string> findFile(StringRef Dir, StringRef Root, const Twine &Name) { SmallString<128> Path; - if (Dir.startswith("=")) + if (Dir.starts_with("=")) sys::path::append(Path, Root, Dir.substr(1), Name); else sys::path::append(Path, Dir, Name); @@ -1188,7 +1188,7 @@ searchLibraryBaseName(StringRef Name, StringRef Root, /// `-lfoo` or `-l:libfoo.a`. std::optional<std::string> searchLibrary(StringRef Input, StringRef Root, ArrayRef<StringRef> SearchPaths) { - if (Input.startswith(":") || Input.ends_with(".lib")) + if (Input.starts_with(":") || Input.ends_with(".lib")) return findFromSearchPaths(Input.drop_front(), Root, SearchPaths); return searchLibraryBaseName(Input, Root, SearchPaths); } diff --git a/clang/tools/clang-refactor/ClangRefactor.cpp b/clang/tools/clang-refactor/ClangRefactor.cpp index d362eecf06d8..175a2b8234e9 100644 --- a/clang/tools/clang-refactor/ClangRefactor.cpp +++ b/clang/tools/clang-refactor/ClangRefactor.cpp @@ -146,7 +146,7 @@ private: std::unique_ptr<SourceSelectionArgument> SourceSelectionArgument::fromString(StringRef Value) { - if (Value.startswith("test:")) { + if (Value.starts_with("test:")) { StringRef Filename = Value.drop_front(strlen("test:")); std::optional<TestSelectionRangesInFile> ParsedTestSelection = findTestSelectionRanges(Filename); diff --git a/clang/tools/clang-repl/ClangRepl.cpp b/clang/tools/clang-repl/ClangRepl.cpp index 5663c2c5a6c9..b9b287127015 100644 --- a/clang/tools/clang-repl/ClangRepl.cpp +++ b/clang/tools/clang-repl/ClangRepl.cpp @@ -234,7 +234,7 @@ int main(int argc, const char **argv) { while (std::optional<std::string> Line = LE.readLine()) { llvm::StringRef L = *Line; L = L.trim(); - if (L.endswith("\\")) { + if (L.ends_with("\\")) { // FIXME: Support #ifdef X \ ... Input += L.drop_back(1); LE.setPrompt("clang-repl... "); diff --git a/clang/tools/clang-scan-deps/ClangScanDeps.cpp b/clang/tools/clang-scan-deps/ClangScanDeps.cpp index f11c933d9576..75aa4ae97c61 100644 --- a/clang/tools/clang-scan-deps/ClangScanDeps.cpp +++ b/clang/tools/clang-scan-deps/ClangScanDeps.cpp @@ -830,9 +830,9 @@ int clang_scan_deps_main(int argc, char **argv, const llvm::ToolContext &) { // Also, clang-cl adds ".obj" extension if none is found. if ((Arg == "-o" || Arg == "/o") && I != R) LastO = I[-1]; // Next argument (reverse iterator) - else if (Arg.startswith("/Fo") || Arg.startswith("-Fo")) + else if (Arg.starts_with("/Fo") || Arg.starts_with("-Fo")) LastO = Arg.drop_front(3).str(); - else if (Arg.startswith("/o") || Arg.startswith("-o")) + else if (Arg.starts_with("/o") || Arg.starts_with("-o")) LastO = Arg.drop_front(2).str(); if (!LastO.empty() && !llvm::sys::path::has_extension(LastO)) diff --git a/clang/tools/diagtool/TreeView.cpp b/clang/tools/diagtool/TreeView.cpp index 4f5d3fd3ef0a..eae16243d3d5 100644 --- a/clang/tools/diagtool/TreeView.cpp +++ b/clang/tools/diagtool/TreeView.cpp @@ -160,7 +160,7 @@ int TreeView::run(unsigned int argc, char **argv, llvm::raw_ostream &out) { break; case 1: RootGroup = argv[0]; - if (RootGroup.startswith("-W")) + if (RootGroup.starts_with("-W")) RootGroup = RootGroup.substr(2); if (RootGroup == "everything") ShowAll = true; diff --git a/clang/tools/driver/driver.cpp b/clang/tools/driver/driver.cpp index 531b5b4a61c1..4adc7f7ad0da 100644 --- a/clang/tools/driver/driver.cpp +++ b/clang/tools/driver/driver.cpp @@ -122,7 +122,7 @@ static void ApplyOneQAOverride(raw_ostream &OS, GetStableCStr(SavedStrings, Edit.substr(1)); OS << "### Adding argument " << Str << " at end\n"; Args.push_back(Str); - } else if (Edit[0] == 's' && Edit[1] == '/' && Edit.endswith("/") && + } else if (Edit[0] == 's' && Edit[1] == '/' && Edit.ends_with("/") && Edit.slice(2, Edit.size() - 1).contains('/')) { StringRef MatchPattern = Edit.substr(2).split('/').first; StringRef ReplPattern = Edit.substr(2).split('/').second; @@ -403,7 +403,7 @@ int clang_main(int Argc, char **Argv, const llvm::ToolContext &ToolContext) { } // Handle -cc1 integrated tools. - if (Args.size() >= 2 && StringRef(Args[1]).startswith("-cc1")) + if (Args.size() >= 2 && StringRef(Args[1]).starts_with("-cc1")) return ExecuteCC1Tool(Args, ToolContext); // Handle options that need handling before the real command line parsing in diff --git a/clang/tools/libclang/CIndexUSRs.cpp b/clang/tools/libclang/CIndexUSRs.cpp index 75bb3b01299f..be7c670cca01 100644 --- a/clang/tools/libclang/CIndexUSRs.cpp +++ b/clang/tools/libclang/CIndexUSRs.cpp @@ -28,7 +28,7 @@ using namespace clang::index; //===----------------------------------------------------------------------===// static inline StringRef extractUSRSuffix(StringRef s) { - return s.startswith("c:") ? s.substr(2) : ""; + return s.starts_with("c:") ? s.substr(2) : ""; } bool cxcursor::getDeclCursorUSR(const Decl *D, SmallVectorImpl<char> &Buf) { diff --git a/clang/unittests/Analysis/CloneDetectionTest.cpp b/clang/unittests/Analysis/CloneDetectionTest.cpp index fe65fab98c5e..738f6efd2018 100644 --- a/clang/unittests/Analysis/CloneDetectionTest.cpp +++ b/clang/unittests/Analysis/CloneDetectionTest.cpp @@ -42,7 +42,7 @@ public: for (const StmtSequence &Arg : {A, B}) { if (const auto *D = dyn_cast<const FunctionDecl>(Arg.getContainingDecl())) { - if (D->getName().startswith("bar")) + if (D->getName().starts_with("bar")) return false; } } diff --git a/clang/unittests/Driver/ModuleCacheTest.cpp b/clang/unittests/Driver/ModuleCacheTest.cpp index 6a0f68f26a67..48744415647e 100644 --- a/clang/unittests/Driver/ModuleCacheTest.cpp +++ b/clang/unittests/Driver/ModuleCacheTest.cpp @@ -22,6 +22,6 @@ TEST(ModuleCacheTest, GetTargetAndMode) { Driver::getDefaultModuleCachePath(Buf); StringRef Path = Buf; EXPECT_TRUE(Path.find("clang") != Path.npos); - EXPECT_TRUE(Path.endswith("ModuleCache")); + EXPECT_TRUE(Path.ends_with("ModuleCache")); } } // end anonymous namespace. diff --git a/clang/unittests/Driver/MultilibBuilderTest.cpp b/clang/unittests/Driver/MultilibBuilderTest.cpp index 60fe10ac3ba5..e23fe7e2441d 100644 --- a/clang/unittests/Driver/MultilibBuilderTest.cpp +++ b/clang/unittests/Driver/MultilibBuilderTest.cpp @@ -144,7 +144,7 @@ TEST(MultilibBuilderTest, SetFilterObject) { << "Size before filter was incorrect. Contents:\n" << MS; MS.FilterOut([](const Multilib &M) { - return StringRef(M.gccSuffix()).startswith("/p"); + return StringRef(M.gccSuffix()).starts_with("/p"); }); ASSERT_EQ((int)MS.size(), 1 /* Default */ + 1 /* orange */ + 1 /* orange/pear */ + 1 /* orange/plum */ + @@ -152,7 +152,7 @@ TEST(MultilibBuilderTest, SetFilterObject) { << "Size after filter was incorrect. Contents:\n" << MS; for (MultilibSet::const_iterator I = MS.begin(), E = MS.end(); I != E; ++I) { - ASSERT_FALSE(StringRef(I->gccSuffix()).startswith("/p")) + ASSERT_FALSE(StringRef(I->gccSuffix()).starts_with("/p")) << "The filter should have removed " << *I; } } diff --git a/clang/unittests/Driver/ToolChainTest.cpp b/clang/unittests/Driver/ToolChainTest.cpp index acbbb87390d5..a9b5f3c70031 100644 --- a/clang/unittests/Driver/ToolChainTest.cpp +++ b/clang/unittests/Driver/ToolChainTest.cpp @@ -531,7 +531,7 @@ TEST(ToolChainTest, CommandOutput) { const auto &InFile = CmdCompile->getInputInfos().front().getFilename(); EXPECT_STREQ(InFile, "foo.cpp"); auto ObjFile = CmdCompile->getOutputFilenames().front(); - EXPECT_TRUE(StringRef(ObjFile).endswith(".o")); + EXPECT_TRUE(StringRef(ObjFile).ends_with(".o")); const auto &CmdLink = Jobs.getJobs().back(); const auto LinkInFile = CmdLink->getInputInfos().front().getFilename(); diff --git a/clang/unittests/Frontend/OutputStreamTest.cpp b/clang/unittests/Frontend/OutputStreamTest.cpp index 9cb101ecff8a..7d360f661daa 100644 --- a/clang/unittests/Frontend/OutputStreamTest.cpp +++ b/clang/unittests/Frontend/OutputStreamTest.cpp @@ -42,7 +42,7 @@ TEST(FrontendOutputTests, TestOutputStream) { bool Success = ExecuteCompilerInvocation(&Compiler); EXPECT_TRUE(Success); EXPECT_TRUE(!IRBuffer.empty()); - EXPECT_TRUE(StringRef(IRBuffer.data()).startswith("BC")); + EXPECT_TRUE(StringRef(IRBuffer.data()).starts_with("BC")); } TEST(FrontendOutputTests, TestVerboseOutputStreamShared) { diff --git a/clang/unittests/Interpreter/IncrementalProcessingTest.cpp b/clang/unittests/Interpreter/IncrementalProcessingTest.cpp index f43b3ddac68f..accdf6828963 100644 --- a/clang/unittests/Interpreter/IncrementalProcessingTest.cpp +++ b/clang/unittests/Interpreter/IncrementalProcessingTest.cpp @@ -44,7 +44,7 @@ const char TestProgram2[] = "extern \"C\" int funcForProg2() { return 42; }\n" const Function *getGlobalInit(llvm::Module *M) { for (const auto &Func : *M) - if (Func.hasName() && Func.getName().startswith("_GLOBAL__sub_I_")) + if (Func.hasName() && Func.getName().starts_with("_GLOBAL__sub_I_")) return &Func; return nullptr; diff --git a/clang/unittests/StaticAnalyzer/AnalyzerOptionsTest.cpp b/clang/unittests/StaticAnalyzer/AnalyzerOptionsTest.cpp index cd78014eae9d..aace4b991b5e 100644 --- a/clang/unittests/StaticAnalyzer/AnalyzerOptionsTest.cpp +++ b/clang/unittests/StaticAnalyzer/AnalyzerOptionsTest.cpp @@ -15,10 +15,10 @@ namespace ento { TEST(StaticAnalyzerOptions, getRegisteredCheckers) { auto IsDebugChecker = [](StringRef CheckerName) { - return CheckerName.startswith("debug"); + return CheckerName.starts_with("debug"); }; auto IsAlphaChecker = [](StringRef CheckerName) { - return CheckerName.startswith("alpha"); + return CheckerName.starts_with("alpha"); }; const auto &AllCheckers = AnalyzerOptions::getRegisteredCheckers(/*IncludeExperimental=*/true); diff --git a/clang/unittests/Tooling/HeaderIncludesTest.cpp b/clang/unittests/Tooling/HeaderIncludesTest.cpp index 256aa825554c..929156a11d0d 100644 --- a/clang/unittests/Tooling/HeaderIncludesTest.cpp +++ b/clang/unittests/Tooling/HeaderIncludesTest.cpp @@ -23,9 +23,9 @@ protected: std::string insert(llvm::StringRef Code, llvm::StringRef Header, IncludeDirective Directive = IncludeDirective::Include) { HeaderIncludes Includes(FileName, Code, Style); - assert(Header.startswith("\"") || Header.startswith("<")); - auto R = - Includes.insert(Header.trim("\"<>"), Header.startswith("<"), Directive); + assert(Header.starts_with("\"") || Header.starts_with("<")); + auto R = Includes.insert(Header.trim("\"<>"), Header.starts_with("<"), + Directive); if (!R) return std::string(Code); auto Result = applyAllReplacements(Code, Replacements(*R)); @@ -35,8 +35,9 @@ protected: std::string remove(llvm::StringRef Code, llvm::StringRef Header) { HeaderIncludes Includes(FileName, Code, Style); - assert(Header.startswith("\"") || Header.startswith("<")); - auto Replaces = Includes.remove(Header.trim("\"<>"), Header.startswith("<")); + assert(Header.starts_with("\"") || Header.starts_with("<")); + auto Replaces = + Includes.remove(Header.trim("\"<>"), Header.starts_with("<")); auto Result = applyAllReplacements(Code, Replaces); EXPECT_TRUE(static_cast<bool>(Result)); return *Result; diff --git a/clang/unittests/libclang/LibclangTest.cpp b/clang/unittests/libclang/LibclangTest.cpp index 60904bc3baf8..87075a46d751 100644 --- a/clang/unittests/libclang/LibclangTest.cpp +++ b/clang/unittests/libclang/LibclangTest.cpp @@ -451,8 +451,8 @@ public: const auto Filename = llvm::sys::path::filename(File->path()); EXPECT_EQ(Filename.size(), std::strlen("preamble-%%%%%%.pch")); - EXPECT_TRUE(Filename.startswith("preamble-")); - EXPECT_TRUE(Filename.endswith(".pch")); + EXPECT_TRUE(Filename.starts_with("preamble-")); + EXPECT_TRUE(Filename.ends_with(".pch")); const auto Status = File->status(); ASSERT_TRUE(Status); @@ -659,7 +659,7 @@ TEST_F(LibclangReparseTest, FileName) { clang_disposeString(cxname); cxname = clang_File_tryGetRealPathName(cxf); - ASSERT_TRUE(llvm::StringRef(clang_getCString(cxname)).endswith("main.cpp")); + ASSERT_TRUE(llvm::StringRef(clang_getCString(cxname)).ends_with("main.cpp")); clang_disposeString(cxname); } diff --git a/clang/utils/TableGen/ASTTableGen.cpp b/clang/utils/TableGen/ASTTableGen.cpp index 60f563d9a1ff..54288ff6a03b 100644 --- a/clang/utils/TableGen/ASTTableGen.cpp +++ b/clang/utils/TableGen/ASTTableGen.cpp @@ -33,7 +33,7 @@ llvm::StringRef clang::tblgen::HasProperties::getName() const { static StringRef removeExpectedNodeNameSuffix(Record *node, StringRef suffix) { StringRef nodeName = node->getName(); - if (!nodeName.endswith(suffix)) { + if (!nodeName.ends_with(suffix)) { PrintFatalError(node->getLoc(), Twine("name of node doesn't end in ") + suffix); } diff --git a/clang/utils/TableGen/MveEmitter.cpp b/clang/utils/TableGen/MveEmitter.cpp index fae889d68346..f0bd0865c1c8 100644 --- a/clang/utils/TableGen/MveEmitter.cpp +++ b/clang/utils/TableGen/MveEmitter.cpp @@ -882,7 +882,7 @@ public: } else if (V->varnameUsed()) { std::string Type = V->typeName(); OS << V->typeName(); - if (!StringRef(Type).endswith("*")) + if (!StringRef(Type).ends_with("*")) OS << " "; OS << V->varname() << " = "; } @@ -1680,7 +1680,7 @@ void EmitterBase::EmitBuiltinCG(raw_ostream &OS) { for (size_t i = 0, e = MG.ParamTypes.size(); i < e; ++i) { StringRef Type = MG.ParamTypes[i]; OS << " " << Type; - if (!Type.endswith("*")) + if (!Type.ends_with("*")) OS << " "; OS << " Param" << utostr(i) << ";\n"; } @@ -1833,7 +1833,7 @@ void MveEmitter::EmitHeader(raw_ostream &OS) { // prototype. std::string RetTypeName = Int.returnType()->cName(); - if (!StringRef(RetTypeName).endswith("*")) + if (!StringRef(RetTypeName).ends_with("*")) RetTypeName += " "; std::vector<std::string> ArgTypeNames; @@ -2078,7 +2078,7 @@ void CdeEmitter::EmitHeader(raw_ostream &OS) { // Make strings for the types involved in the function's // prototype. std::string RetTypeName = Int.returnType()->cName(); - if (!StringRef(RetTypeName).endswith("*")) + if (!StringRef(RetTypeName).ends_with("*")) RetTypeName += " "; std::vector<std::string> ArgTypeNames; diff --git a/clang/utils/TableGen/NeonEmitter.cpp b/clang/utils/TableGen/NeonEmitter.cpp index 4b112972a1ec..e5f79ba99c5c 100644 --- a/clang/utils/TableGen/NeonEmitter.cpp +++ b/clang/utils/TableGen/NeonEmitter.cpp @@ -593,6 +593,8 @@ public: // Emit arm_bf16.h.inc void runBF16(raw_ostream &o); + void runVectorTypes(raw_ostream &o); + // Emit all the __builtin prototypes used in arm_neon.h, arm_fp16.h and // arm_bf16.h void runHeader(raw_ostream &o); @@ -2355,13 +2357,7 @@ void NeonEmitter::run(raw_ostream &OS) { OS << "#include <arm_bf16.h>\n"; - // Emit NEON-specific scalar typedefs. - OS << "typedef float float32_t;\n"; - OS << "typedef __fp16 float16_t;\n"; - - OS << "#ifdef __aarch64__\n"; - OS << "typedef double float64_t;\n"; - OS << "#endif\n\n"; + OS << "#include <arm_vector_types.h>\n"; // For now, signedness of polynomial types depends on target OS << "#ifdef __aarch64__\n"; @@ -2374,10 +2370,7 @@ void NeonEmitter::run(raw_ostream &OS) { OS << "typedef int16_t poly16_t;\n"; OS << "typedef int64_t poly64_t;\n"; OS << "#endif\n"; - - emitNeonTypeDefs("cQcsQsiQilQlUcQUcUsQUsUiQUiUlQUlhQhfQfdQdPcQPcPsQPsPlQPl", OS); - - emitNeonTypeDefs("bQb", OS); + emitNeonTypeDefs("PcQPcPsQPsPlQPl", OS); OS << "#define __ai static __inline__ __attribute__((__always_inline__, " "__nodebug__))\n\n"; @@ -2546,6 +2539,38 @@ void NeonEmitter::runFP16(raw_ostream &OS) { OS << "#endif /* __ARM_FP16_H */\n"; } +void NeonEmitter::runVectorTypes(raw_ostream &OS) { + OS << "/*===---- arm_vector_types - ARM vector type " + "------===\n" + " *\n" + " *\n" + " * Part of the LLVM Project, under the Apache License v2.0 with LLVM " + "Exceptions.\n" + " * See https://llvm.org/LICENSE.txt for license information.\n" + " * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception\n" + " *\n" + " *===-----------------------------------------------------------------" + "------===\n" + " */\n\n"; + OS << "#if !defined(__ARM_NEON_H) && !defined(__ARM_SVE_H)\n"; + OS << "#error \"This file should not be used standalone. Please include" + " arm_neon.h or arm_sve.h instead\"\n\n"; + OS << "#endif\n"; + OS << "#ifndef __ARM_NEON_TYPES_H\n"; + OS << "#define __ARM_NEON_TYPES_H\n"; + OS << "typedef float float32_t;\n"; + OS << "typedef __fp16 float16_t;\n"; + + OS << "#ifdef __aarch64__\n"; + OS << "typedef double float64_t;\n"; + OS << "#endif\n\n"; + + emitNeonTypeDefs("cQcsQsiQilQlUcQUcUsQUsUiQUiUlQUlhQhfQfdQd", OS); + + emitNeonTypeDefs("bQb", OS); + OS << "#endif // __ARM_NEON_TYPES_H\n"; +} + void NeonEmitter::runBF16(raw_ostream &OS) { OS << "/*===---- arm_bf16.h - ARM BF16 intrinsics " "-----------------------------------===\n" @@ -2640,6 +2665,10 @@ void clang::EmitNeonSema(RecordKeeper &Records, raw_ostream &OS) { NeonEmitter(Records).runHeader(OS); } +void clang::EmitVectorTypes(RecordKeeper &Records, raw_ostream &OS) { + NeonEmitter(Records).runVectorTypes(OS); +} + void clang::EmitNeonTest(RecordKeeper &Records, raw_ostream &OS) { llvm_unreachable("Neon test generation no longer implemented!"); } diff --git a/clang/utils/TableGen/SveEmitter.cpp b/clang/utils/TableGen/SveEmitter.cpp index b8a1fb4bab0f..9361b9950637 100644 --- a/clang/utils/TableGen/SveEmitter.cpp +++ b/clang/utils/TableGen/SveEmitter.cpp @@ -97,6 +97,7 @@ public: bool isScalar() const { return NumVectors == 0; } bool isVector() const { return NumVectors > 0; } bool isScalableVector() const { return isVector() && IsScalable; } + bool isFixedLengthVector() const { return isVector() && !IsScalable; } bool isChar() const { return ElementBitwidth == 8; } bool isVoid() const { return Void & !Pointer; } bool isDefault() const { return DefaultType; } @@ -466,7 +467,8 @@ std::string SVEType::builtin_str() const { return S; } - assert(isScalableVector() && "Unsupported type"); + if (isFixedLengthVector()) + return "V" + utostr(getNumElements() * NumVectors) + S; return "q" + utostr(getNumElements() * NumVectors) + S; } @@ -499,7 +501,7 @@ std::string SVEType::str() const { if (!isScalarPredicate() && !isPredicateVector() && !isSvcount()) S += utostr(ElementBitwidth); - if (!isScalableVector() && isVector()) + if (isFixedLengthVector()) S += "x" + utostr(getNumElements()); if (NumVectors > 1) S += "x" + utostr(NumVectors); @@ -610,6 +612,11 @@ void SVEType::applyModifier(char Mod) { Bitwidth = 16; ElementBitwidth = 1; break; + case '{': + IsScalable = false; + Bitwidth = 128; + NumVectors = 1; + break; case 's': case 'a': Bitwidth = ElementBitwidth; @@ -1286,6 +1293,7 @@ void SVEEmitter::createHeader(raw_ostream &OS) { OS << "typedef __SVBfloat16_t svbfloat16_t;\n"; OS << "#include <arm_bf16.h>\n"; + OS << "#include <arm_vector_types.h>\n"; OS << "typedef __SVFloat32_t svfloat32_t;\n"; OS << "typedef __SVFloat64_t svfloat64_t;\n"; @@ -1730,4 +1738,5 @@ void EmitSmeBuiltinCG(RecordKeeper &Records, raw_ostream &OS) { void EmitSmeRangeChecks(RecordKeeper &Records, raw_ostream &OS) { SVEEmitter(Records).createSMERangeChecks(OS); } + } // End namespace clang diff --git a/clang/utils/TableGen/TableGen.cpp b/clang/utils/TableGen/TableGen.cpp index 7efb6c731d3e..3ad46b95984e 100644 --- a/clang/utils/TableGen/TableGen.cpp +++ b/clang/utils/TableGen/TableGen.cpp @@ -73,6 +73,7 @@ enum ActionType { GenArmNeon, GenArmFP16, GenArmBF16, + GenArmVectorType, GenArmNeonSema, GenArmNeonTest, GenArmMveHeader, @@ -229,6 +230,8 @@ cl::opt<ActionType> Action( clEnumValN(GenArmNeon, "gen-arm-neon", "Generate arm_neon.h for clang"), clEnumValN(GenArmFP16, "gen-arm-fp16", "Generate arm_fp16.h for clang"), clEnumValN(GenArmBF16, "gen-arm-bf16", "Generate arm_bf16.h for clang"), + clEnumValN(GenArmVectorType, "gen-arm-vector-type", + "Generate arm_vector_types.h for clang"), clEnumValN(GenArmNeonSema, "gen-arm-neon-sema", "Generate ARM NEON sema support for clang"), clEnumValN(GenArmNeonTest, "gen-arm-neon-test", @@ -449,6 +452,9 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper &Records) { case GenArmFP16: EmitFP16(Records, OS); break; + case GenArmVectorType: + EmitVectorTypes(Records, OS); + break; case GenArmBF16: EmitBF16(Records, OS); break; diff --git a/clang/utils/TableGen/TableGenBackends.h b/clang/utils/TableGen/TableGenBackends.h index d8f447069376..ef255612f4b8 100644 --- a/clang/utils/TableGen/TableGenBackends.h +++ b/clang/utils/TableGen/TableGenBackends.h @@ -97,6 +97,7 @@ void EmitNeon(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitFP16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitBF16(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitNeonSema(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); +void EmitVectorTypes(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitNeonTest(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitSveHeader(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); diff --git a/compiler-rt/test/sanitizer_common/TestCases/Posix/fork_threaded.c b/compiler-rt/test/sanitizer_common/TestCases/Posix/fork_threaded.c index cbdf9ee00cff..eaa1a0482e90 100644 --- a/compiler-rt/test/sanitizer_common/TestCases/Posix/fork_threaded.c +++ b/compiler-rt/test/sanitizer_common/TestCases/Posix/fork_threaded.c @@ -2,6 +2,9 @@ // UNSUPPORTED: asan, lsan, hwasan +// The test uses pthread barriers which are not available on Darwin. +// UNSUPPORTED: darwin + // Forking in multithread environment is unsupported. However we already have // some workarounds, and will add more, so this is the test. // The test try to check two things: @@ -58,6 +61,10 @@ NOSAN static void *inchild(void *arg) { } int main(void) { +#if __has_feature(hwaddress_sanitizer) + __hwasan_enable_allocator_tagging(); +#endif + pid_t pid; pthread_barrier_init(&bar, NULL, 2); diff --git a/compiler-rt/test/sanitizer_common/sanitizer_specific.h b/compiler-rt/test/sanitizer_common/sanitizer_specific.h index 541af18a7497..898899f00e37 100644 --- a/compiler-rt/test/sanitizer_common/sanitizer_specific.h +++ b/compiler-rt/test/sanitizer_common/sanitizer_specific.h @@ -31,19 +31,6 @@ static void make_mem_good(void *p, size_t s) { static void make_mem_bad(void *p, size_t s) { __asan_poison_memory_region(p, s); } -#elif __has_feature(hwaddress_sanitizer) -# include <sanitizer/hwasan_interface.h> -# include <stdlib.h> -static void check_mem_is_good(void *p, size_t s) { - if (__hwasan_test_shadow(p, s) != -1) - abort(); -} -static void make_mem_good(void *p, size_t s) { - __hwasan_tag_memory(p, __hwasan_get_tag_from_pointer(p), s); -} -static void make_mem_bad(void *p, size_t s) { - __hwasan_tag_memory(p, ~__hwasan_get_tag_from_pointer(p), s); -} #else static void check_mem_is_good(void *p, size_t s) {} static void make_mem_good(void *p, size_t s) {} diff --git a/flang/lib/Lower/IO.cpp b/flang/lib/Lower/IO.cpp index 4186d6158fb1..a60ca92a8733 100644 --- a/flang/lib/Lower/IO.cpp +++ b/flang/lib/Lower/IO.cpp @@ -641,7 +641,8 @@ static void genNamelistIO(Fortran::lower::AbstractConverter &converter, mlir::Location loc = converter.getCurrentLocation(); makeNextConditionalOn(builder, loc, checkResult, ok); mlir::Type argType = funcOp.getFunctionType().getInput(1); - mlir::Value groupAddr = getNamelistGroup(converter, symbol, stmtCtx); + mlir::Value groupAddr = + getNamelistGroup(converter, symbol.GetUltimate(), stmtCtx); groupAddr = builder.createConvert(loc, argType, groupAddr); llvm::SmallVector<mlir::Value> args = {cookie, groupAddr}; ok = builder.create<fir::CallOp>(loc, funcOp, args).getResult(0); diff --git a/flang/test/Lower/namelist.f90 b/flang/test/Lower/namelist.f90 index bba7a0ea1977..9fdd8a2c8f61 100644 --- a/flang/test/Lower/namelist.f90 +++ b/flang/test/Lower/namelist.f90 @@ -1,88 +1,144 @@ -! RUN: bbc -emit-fir -hlfir=false -o - %s | FileCheck %s +! RUN: bbc -emit-fir -o - %s | FileCheck %s -! CHECK-LABEL: func @_QQmain +! CHECK-LABEL: c.func @_QQmain program p - ! CHECK-DAG: [[ccc:%[0-9]+]] = fir.alloca !fir.array<4x!fir.char<1,3>> {bindc_name = "ccc", uniq_name = "_QFEccc"} - ! CHECK-DAG: [[jjj:%[0-9]+]] = fir.alloca i32 {bindc_name = "jjj", uniq_name = "_QFEjjj"} + ! CHECK: %[[V_1:[0-9]+]] = fir.alloca !fir.box<!fir.ptr<!fir.array<4x!fir.char<1,3>>>> + ! CHECK: %[[V_2:[0-9]+]] = fir.alloca !fir.box<!fir.ptr<i32>> + ! CHECK: %[[V_3:[0-9]+]] = fir.alloca !fir.box<!fir.ptr<!fir.array<4x!fir.char<1,3>>>> + ! CHECK: %[[V_4:[0-9]+]] = fir.alloca !fir.box<!fir.ptr<i32>> + ! CHECK: %[[V_5:[0-9]+]] = fir.alloca !fir.array<4x!fir.char<1,3>> {bindc_name = "ccc", uniq_name = "_QFEccc"} + ! CHECK: %[[V_6:[0-9]+]] = fir.shape %c4{{.*}} : (index) -> !fir.shape<1> + ! CHECK: %[[V_7:[0-9]+]] = fir.declare %[[V_5]](%[[V_6]]) typeparams %c3{{.*}} {uniq_name = "_QFEccc"} : (!fir.ref<!fir.array<4x!fir.char<1,3>>>, !fir.shape<1>, index) -> !fir.ref<!fir.array<4x!fir.char<1,3>>> + ! CHECK: %[[V_8:[0-9]+]] = fir.alloca i32 {bindc_name = "jjj", uniq_name = "_QFEjjj"} + ! CHECK: %[[V_9:[0-9]+]] = fir.declare %[[V_8]] {uniq_name = "_QFEjjj"} : (!fir.ref<i32>) -> !fir.ref<i32> + ! CHECK: fir.store %c17{{.*}} to %[[V_9]] : !fir.ref<i32> character*3 ccc(4) namelist /nnn/ jjj, ccc jjj = 17 ccc = ["aa ", "bb ", "cc ", "dd "] - ! CHECK: [[cookie:%[0-9]+]] = fir.call @_FortranAioBeginExternalListOutput - ! CHECK: fir.alloca !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> - ! CHECK: fir.undefined - ! CHECK: fir.address_of - ! CHECK: fir.insert_value - ! CHECK: fir.embox [[jjj]] - ! CHECK: fir.insert_value - ! CHECK: fir.address_of - ! CHECK: fir.insert_value - ! CHECK: fir.embox [[ccc]] - ! CHECK: fir.insert_value - ! CHECK: fir.alloca tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> - ! CHECK: fir.address_of - ! CHECK-COUNT-4: fir.insert_value - ! CHECK: fir.call @_FortranAioOutputNamelist([[cookie]] - ! CHECK: fir.call @_FortranAioEndIoStatement([[cookie]] + + ! CHECK: %[[V_23:[0-9]+]] = fir.call @_FortranAioBeginExternalListOutput + ! CHECK: %[[V_24:[0-9]+]] = fir.alloca !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: %[[V_25:[0-9]+]] = fir.undefined !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: %[[V_26:[0-9]+]] = fir.address_of(@_QQclX6A6A6A00) : !fir.ref<!fir.char<1,4>> + ! CHECK: %[[V_27:[0-9]+]] = fir.convert %[[V_26]] : (!fir.ref<!fir.char<1,4>>) -> !fir.ref<i8> + ! CHECK: %[[V_28:[0-9]+]] = fir.insert_value %[[V_25]], %[[V_27]], [0 : index, 0 : index] : (!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>, !fir.ref<i8>) -> !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: %[[V_29:[0-9]+]] = fir.embox %[[V_9]] : (!fir.ref<i32>) -> !fir.box<!fir.ptr<i32>> + ! CHECK: fir.store %[[V_29]] to %[[V_4]] : !fir.ref<!fir.box<!fir.ptr<i32>>> + ! CHECK: %[[V_30:[0-9]+]] = fir.convert %[[V_4]] : (!fir.ref<!fir.box<!fir.ptr<i32>>>) -> !fir.ref<!fir.box<none>> + ! CHECK: %[[V_31:[0-9]+]] = fir.insert_value %[[V_28]], %[[V_30]], [0 : index, 1 : index] : (!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>, !fir.ref<!fir.box<none>>) -> !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: %[[V_32:[0-9]+]] = fir.address_of(@_QQclX63636300) : !fir.ref<!fir.char<1,4>> + ! CHECK: %[[V_33:[0-9]+]] = fir.convert %[[V_32]] : (!fir.ref<!fir.char<1,4>>) -> !fir.ref<i8> + ! CHECK: %[[V_34:[0-9]+]] = fir.insert_value %[[V_31]], %[[V_33]], [1 : index, 0 : index] : (!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>, !fir.ref<i8>) -> !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: %[[V_35:[0-9]+]] = fir.embox %[[V_7]](%[[V_6]]) : (!fir.ref<!fir.array<4x!fir.char<1,3>>>, !fir.shape<1>) -> !fir.box<!fir.ptr<!fir.array<4x!fir.char<1,3>>>> + ! CHECK: fir.store %[[V_35]] to %[[V_3]] : !fir.ref<!fir.box<!fir.ptr<!fir.array<4x!fir.char<1,3>>>>> + ! CHECK: %[[V_36:[0-9]+]] = fir.convert %[[V_3]] : (!fir.ref<!fir.box<!fir.ptr<!fir.array<4x!fir.char<1,3>>>>>) -> !fir.ref<!fir.box<none>> + ! CHECK: %[[V_37:[0-9]+]] = fir.insert_value %[[V_34]], %[[V_36]], [1 : index, 1 : index] : (!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>, !fir.ref<!fir.box<none>>) -> !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: fir.store %[[V_37]] to %[[V_24]] : !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>> + ! CHECK: %[[V_38:[0-9]+]] = fir.alloca tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: %[[V_39:[0-9]+]] = fir.undefined tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: %[[V_40:[0-9]+]] = fir.address_of(@_QQclX6E6E6E00) : !fir.ref<!fir.char<1,4>> + ! CHECK: %[[V_41:[0-9]+]] = fir.convert %[[V_40]] : (!fir.ref<!fir.char<1,4>>) -> !fir.ref<i8> + ! CHECK: %[[V_42:[0-9]+]] = fir.insert_value %[[V_39]], %[[V_41]], [0 : index] : (tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>, !fir.ref<i8>) -> tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: %[[V_43:[0-9]+]] = fir.insert_value %[[V_42]], %c2{{.*}}, [1 : index] : (tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>, i64) -> tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: %[[V_44:[0-9]+]] = fir.insert_value %[[V_43]], %[[V_24]], [2 : index] : (tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>) -> tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: %[[V_45:[0-9]+]] = fir.address_of(@default.nonTbpDefinedIoTable) : !fir.ref<tuple<i64, !fir.ref<!fir.array<0xtuple<!fir.ref<none>, !fir.ref<none>, i32, i1>>>, i1>> + ! CHECK: %[[V_46:[0-9]+]] = fir.convert %[[V_45]] : (!fir.ref<tuple<i64, !fir.ref<!fir.array<0xtuple<!fir.ref<none>, !fir.ref<none>, i32, i1>>>, i1>>) -> !fir.ref<none> + ! CHECK: %[[V_47:[0-9]+]] = fir.insert_value %[[V_44]], %[[V_46]], [3 : index] : (tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>, !fir.ref<none>) -> tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: fir.store %[[V_47]] to %[[V_38]] : !fir.ref<tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>> + ! CHECK: %[[V_48:[0-9]+]] = fir.convert %[[V_38]] : (!fir.ref<tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>>) -> !fir.ref<tuple<>> + ! CHECK: %[[V_49:[0-9]+]] = fir.call @_FortranAioOutputNamelist(%[[V_23]], %[[V_48]]) fastmath<contract> : (!fir.ref<i8>, !fir.ref<tuple<>>) -> i1 + ! CHECK: %[[V_50:[0-9]+]] = fir.call @_FortranAioEndIoStatement(%[[V_23]]) fastmath<contract> : (!fir.ref<i8>) -> i32 write(*, nnn) jjj = 27 - ! CHECK: fir.coordinate_of ccc(4) = "zz " - ! CHECK: [[cookie:%[0-9]+]] = fir.call @_FortranAioBeginExternalListOutput - ! CHECK: fir.alloca !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> - ! CHECK: fir.undefined - ! CHECK: fir.address_of - ! CHECK: fir.insert_value - ! CHECK: fir.embox [[jjj]] - ! CHECK: fir.insert_value - ! CHECK: fir.address_of - ! CHECK: fir.insert_value - ! CHECK: fir.embox [[ccc]] - ! CHECK: fir.insert_value - ! CHECK: fir.alloca tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> - ! CHECK: fir.address_of - ! CHECK-COUNT-4: fir.insert_value - ! CHECK: fir.call @_FortranAioOutputNamelist([[cookie]] - ! CHECK: fir.call @_FortranAioEndIoStatement([[cookie]] + ! CHECK: %[[V_58:[0-9]+]] = fir.call @_FortranAioBeginExternalListOutput + ! CHECK: %[[V_59:[0-9]+]] = fir.alloca !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: fir.store %[[V_29]] to %[[V_2]] : !fir.ref<!fir.box<!fir.ptr<i32>>> + ! CHECK: %[[V_60:[0-9]+]] = fir.convert %[[V_2]] : (!fir.ref<!fir.box<!fir.ptr<i32>>>) -> !fir.ref<!fir.box<none>> + ! CHECK: %[[V_61:[0-9]+]] = fir.insert_value %[[V_28]], %[[V_60]], [0 : index, 1 : index] : (!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>, !fir.ref<!fir.box<none>>) -> !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: %[[V_62:[0-9]+]] = fir.insert_value %[[V_61]], %[[V_33]], [1 : index, 0 : index] : (!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>, !fir.ref<i8>) -> !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: fir.store %[[V_35]] to %[[V_1]] : !fir.ref<!fir.box<!fir.ptr<!fir.array<4x!fir.char<1,3>>>>> + ! CHECK: %[[V_63:[0-9]+]] = fir.convert %[[V_1]] : (!fir.ref<!fir.box<!fir.ptr<!fir.array<4x!fir.char<1,3>>>>>) -> !fir.ref<!fir.box<none>> + ! CHECK: %[[V_64:[0-9]+]] = fir.insert_value %[[V_62]], %[[V_63]], [1 : index, 1 : index] : (!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>, !fir.ref<!fir.box<none>>) -> !fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: fir.store %[[V_64]] to %[[V_59]] : !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>> + ! CHECK: %[[V_65:[0-9]+]] = fir.alloca tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: %[[V_66:[0-9]+]] = fir.insert_value %[[V_43]], %[[V_59]], [2 : index] : (tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>) -> tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: %[[V_67:[0-9]+]] = fir.insert_value %[[V_66]], %[[V_46]], [3 : index] : (tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>, !fir.ref<none>) -> tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: fir.store %[[V_67]] to %[[V_65]] : !fir.ref<tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>> + ! CHECK: %[[V_68:[0-9]+]] = fir.convert %[[V_65]] : (!fir.ref<tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<2xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>>) -> !fir.ref<tuple<>> + ! CHECK: %[[V_69:[0-9]+]] = fir.call @_FortranAioOutputNamelist(%[[V_58]], %[[V_68]]) fastmath<contract> : (!fir.ref<i8>, !fir.ref<tuple<>>) -> i1 + ! CHECK: %[[V_70:[0-9]+]] = fir.call @_FortranAioEndIoStatement(%[[V_58]]) fastmath<contract> : (!fir.ref<i8>) -> i32 write(*, nnn) + + call rename end -! CHECK-LABEL: sss +! CHECK-LABEL: c.func @_QPsss subroutine sss + ! CHECK: %[[V_0:[0-9]+]] = fir.alloca !fir.box<!fir.ptr<!fir.array<3xi32>>> + ! CHECK: %[[V_1:[0-9]+]] = fir.alloca !fir.array<3xi32> {bindc_name = "xxx", uniq_name = "_QFsssExxx"} + ! CHECK: %[[V_2:[0-9]+]] = fir.shape_shift %c11{{.*}}, %c3{{.*}} : (index, index) -> !fir.shapeshift<1> + ! CHECK: %[[V_3:[0-9]+]] = fir.declare %[[V_1]](%[[V_2]]) {uniq_name = "_QFsssExxx"} : (!fir.ref<!fir.array<3xi32>>, !fir.shapeshift<1>) -> !fir.ref<!fir.array<3xi32>> integer xxx(11:13) + + ! CHECK: %[[V_7:[0-9]+]] = fir.call @_FortranAioBeginExternalListInput + ! CHECK: %[[V_8:[0-9]+]] = fir.alloca !fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: %[[V_9:[0-9]+]] = fir.undefined !fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: %[[V_10:[0-9]+]] = fir.address_of(@_QQclX78787800) : !fir.ref<!fir.char<1,4>> + ! CHECK: %[[V_11:[0-9]+]] = fir.convert %[[V_10]] : (!fir.ref<!fir.char<1,4>>) -> !fir.ref<i8> + ! CHECK: %[[V_12:[0-9]+]] = fir.insert_value %[[V_9]], %[[V_11]], [0 : index, 0 : index] : (!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>, !fir.ref<i8>) -> !fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: %[[V_13:[0-9]+]] = fir.embox %[[V_3]](%[[V_2]]) : (!fir.ref<!fir.array<3xi32>>, !fir.shapeshift<1>) -> !fir.box<!fir.ptr<!fir.array<3xi32>>> + ! CHECK: fir.store %[[V_13]] to %[[V_0]] : !fir.ref<!fir.box<!fir.ptr<!fir.array<3xi32>>>> + ! CHECK: %[[V_14:[0-9]+]] = fir.convert %[[V_0]] : (!fir.ref<!fir.box<!fir.ptr<!fir.array<3xi32>>>>) -> !fir.ref<!fir.box<none>> + ! CHECK: %[[V_15:[0-9]+]] = fir.insert_value %[[V_12]], %[[V_14]], [0 : index, 1 : index] : (!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>, !fir.ref<!fir.box<none>>) -> !fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>> + ! CHECK: fir.store %[[V_15]] to %[[V_8]] : !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>> + ! CHECK: %[[V_16:[0-9]+]] = fir.alloca tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: %[[V_17:[0-9]+]] = fir.undefined tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: %[[V_18:[0-9]+]] = fir.address_of(@_QQclX72727200) : !fir.ref<!fir.char<1,4>> + ! CHECK: %[[V_19:[0-9]+]] = fir.convert %[[V_18]] : (!fir.ref<!fir.char<1,4>>) -> !fir.ref<i8> + ! CHECK: %[[V_20:[0-9]+]] = fir.insert_value %[[V_17]], %[[V_19]], [0 : index] : (tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>, !fir.ref<i8>) -> tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: %[[V_21:[0-9]+]] = fir.insert_value %[[V_20]], %c1{{.*}}, [1 : index] : (tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>, i64) -> tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: %[[V_22:[0-9]+]] = fir.insert_value %[[V_21]], %[[V_8]], [2 : index] : (tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>) -> tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: %[[V_23:[0-9]+]] = fir.address_of(@default.nonTbpDefinedIoTable) : !fir.ref<tuple<i64, !fir.ref<!fir.array<0xtuple<!fir.ref<none>, !fir.ref<none>, i32, i1>>>, i1>> + ! CHECK: %[[V_24:[0-9]+]] = fir.convert %[[V_23]] : (!fir.ref<tuple<i64, !fir.ref<!fir.array<0xtuple<!fir.ref<none>, !fir.ref<none>, i32, i1>>>, i1>>) -> !fir.ref<none> + ! CHECK: %[[V_25:[0-9]+]] = fir.insert_value %[[V_22]], %[[V_24]], [3 : index] : (tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>, !fir.ref<none>) -> tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>> + ! CHECK: fir.store %[[V_25]] to %[[V_16]] : !fir.ref<tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>> + ! CHECK: %[[V_26:[0-9]+]] = fir.convert %[[V_16]] : (!fir.ref<tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>>) -> !fir.ref<tuple<>> + ! CHECK: %[[V_27:[0-9]+]] = fir.call @_FortranAioInputNamelist(%[[V_7]], %[[V_26]]) fastmath<contract> : (!fir.ref<i8>, !fir.ref<tuple<>>) -> i1 + ! CHECK: %[[V_28:[0-9]+]] = fir.call @_FortranAioEndIoStatement(%[[V_7]]) fastmath<contract> : (!fir.ref<i8>) -> i32 namelist /rrr/ xxx - ! CHECK: [[xxx:%[0-9]+]] = fir.alloca {{.*}} = "xxx" - ! CHECK: [[cookie:%[0-9]+]] = fir.call @_FortranAioBeginExternalListInput - ! CHECK: alloca - ! CHECK: undefined - ! CHECK: fir.address_of{{.*}}787878 - ! CHECK: fir.insert_value - ! CHECK: fir.shape_shift %c11 - ! CHECK: fir.embox [[xxx]] - ! CHECK: fir.insert_value - ! CHECK: fir.alloca - ! CHECK: fir.undefined - ! CHECK: fir.address_of{{.*}}727272 - ! CHECK-COUNT-3: fir.insert_value - ! CHECK: fir.call @_FortranAioInputNamelist([[cookie]] - ! CHECK: fir.call @_FortranAioEndIoStatement([[cookie]] read(*, rrr) end -! CHECK-LABEL: global_pointer +! CHECK-LABEL: c.func @_QPglobal_pointer subroutine global_pointer real,pointer,save::ptrarray(:) - ! CHECK: %[[a0:.*]] = fir.address_of + ! CHECK: %[[V_4:[0-9]+]] = fir.call @_FortranAioBeginExternalListOutput + ! CHECK: %[[V_5:[0-9]+]] = fir.address_of(@_QFglobal_pointerNmygroup) : !fir.ref<tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>> + ! CHECK: %[[V_6:[0-9]+]] = fir.convert %[[V_5]] : (!fir.ref<tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>>) -> !fir.ref<tuple<>> + ! CHECK: %[[V_7:[0-9]+]] = fir.call @_FortranAioOutputNamelist(%[[V_4]], %[[V_6]]) fastmath<contract> : (!fir.ref<i8>, !fir.ref<tuple<>>) -> i1 + ! CHECK: %[[V_8:[0-9]+]] = fir.call @_FortranAioEndIoStatement(%[[V_4]]) fastmath<contract> : (!fir.ref<i8>) -> i32 namelist/mygroup/ptrarray - ! CHECK: %[[a1:.*]] = fir.convert %[[a0]] - ! CHECK: %[[a2:.*]] = fir.call @_FortranAioBeginExternalListOutput({{.*}}, %[[a1]], {{.*}}) {{.*}}: (i32, !fir.ref<i8>, i32) -> !fir.ref<i8> - ! CHECK: %[[a3:.*]] = fir.address_of - ! CHECK: %[[a4:.*]] = fir.convert %[[a3]] - ! CHECK: %[[a5:.*]] = fir.call @_FortranAioOutputNamelist(%[[a2]], %[[a4]]) - ! CHECK: %[[a6:.*]] = fir.call @_FortranAioEndIoStatement(%[[a2]]) write(10, nml=mygroup) end - ! CHECK-DAG: fir.global linkonce @_QQclX6A6A6A00 constant : !fir.char<1,4> - ! CHECK-DAG: fir.global linkonce @_QQclX63636300 constant : !fir.char<1,4> - ! CHECK-DAG: fir.global linkonce @_QQclX6E6E6E00 constant : !fir.char<1,4> +module mmm + real rrr + namelist /aaa/ rrr +end + +! CHECK-LABEL: c.func @_QPrename +subroutine rename + use mmm, bbb => aaa + rrr = 3. + ! CHECK: %[[V_4:[0-9]+]] = fir.call @_FortranAioBeginExternalListOutput + ! CHECK: %[[V_5:[0-9]+]] = fir.address_of(@_QMmmmNaaa) : !fir.ref<tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>> + ! CHECK: %[[V_6:[0-9]+]] = fir.convert %[[V_5]] : (!fir.ref<tuple<!fir.ref<i8>, i64, !fir.ref<!fir.array<1xtuple<!fir.ref<i8>, !fir.ref<!fir.box<none>>>>>, !fir.ref<none>>>) -> !fir.ref<tuple<>> + ! CHECK: %[[V_7:[0-9]+]] = fir.call @_FortranAioOutputNamelist(%[[V_4]], %[[V_6]]) fastmath<contract> : (!fir.ref<i8>, !fir.ref<tuple<>>) -> i1 + ! CHECK: %[[V_8:[0-9]+]] = fir.call @_FortranAioEndIoStatement(%[[V_4]]) fastmath<contract> : (!fir.ref<i8>) -> i32 + write(*,bbb) +end + +! CHECK-NOT: bbb +! CHECK: fir.string_lit "aaa\00"(4) : !fir.char<1,4> diff --git a/libc/include/llvm-libc-macros/linux/fcntl-macros.h b/libc/include/llvm-libc-macros/linux/fcntl-macros.h index cdd1cf22d7b6..495c5ec780ed 100644 --- a/libc/include/llvm-libc-macros/linux/fcntl-macros.h +++ b/libc/include/llvm-libc-macros/linux/fcntl-macros.h @@ -46,31 +46,6 @@ #define O_RDWR 00000002 #define O_WRONLY 00000001 -// File mode flags -#define S_IRWXU 0700 -#define S_IRUSR 0400 -#define S_IWUSR 0200 -#define S_IXUSR 0100 -#define S_IRWXG 070 -#define S_IRGRP 040 -#define S_IWGRP 020 -#define S_IXGRP 010 -#define S_IRWXO 07 -#define S_IROTH 04 -#define S_IWOTH 02 -#define S_IXOTH 01 -#define S_ISUID 04000 -#define S_ISGID 02000 - -// File type flags -#define S_IFMT 0170000 -#define S_IFDIR 0040000 -#define S_IFCHR 0020000 -#define S_IFBLK 0060000 -#define S_IFREG 0100000 -#define S_FIFO 0010000 -#define S_IFLNK 0120000 - // Special directory FD to indicate that the path argument to // openat is relative to the current directory. #define AT_FDCWD -100 diff --git a/libc/include/llvm-libc-macros/linux/sys-stat-macros.h b/libc/include/llvm-libc-macros/linux/sys-stat-macros.h index 3be743328a26..48606cfa08ce 100644 --- a/libc/include/llvm-libc-macros/linux/sys-stat-macros.h +++ b/libc/include/llvm-libc-macros/linux/sys-stat-macros.h @@ -10,7 +10,7 @@ #define __LLVM_LIBC_MACROS_LINUX_SYS_STAT_MACROS_H // Definitions from linux/stat.h -#define S_IFMT 00170000 +#define S_IFMT 0170000 #define S_IFSOCK 0140000 #define S_IFLNK 0120000 #define S_IFREG 0100000 diff --git a/libc/src/__support/FPUtil/FPBits.h b/libc/src/__support/FPUtil/FPBits.h index 65c53921181a..bef166e14d72 100644 --- a/libc/src/__support/FPUtil/FPBits.h +++ b/libc/src/__support/FPUtil/FPBits.h @@ -36,71 +36,74 @@ template <typename T> struct ExponentWidth { // floating numbers. On x86 platforms however, the 'long double' type maps to // an x87 floating point format. This format is an IEEE 754 extension format. // It is handled as an explicit specialization of this class. -template <typename T> struct FPBits { +template <typename T> struct FPBits : private FloatProperties<T> { static_assert(cpp::is_floating_point_v<T>, "FPBits instantiated with invalid type."); + using typename FloatProperties<T>::UIntType; + using FloatProperties<T>::BIT_WIDTH; + using FloatProperties<T>::EXP_MANT_MASK; + using FloatProperties<T>::EXPONENT_MASK; + using FloatProperties<T>::EXPONENT_BIAS; + using FloatProperties<T>::EXPONENT_WIDTH; + using FloatProperties<T>::MANTISSA_MASK; + using FloatProperties<T>::MANTISSA_WIDTH; + using FloatProperties<T>::QUIET_NAN_MASK; + using FloatProperties<T>::SIGN_MASK; // Reinterpreting bits as an integer value and interpreting the bits of an // integer value as a floating point value is used in tests. So, a convenient // type is provided for such reinterpretations. - using FloatProp = FloatProperties<T>; - using UIntType = typename FloatProp::UIntType; - UIntType bits; LIBC_INLINE constexpr void set_mantissa(UIntType mantVal) { - mantVal &= (FloatProp::MANTISSA_MASK); - bits &= ~(FloatProp::MANTISSA_MASK); + mantVal &= MANTISSA_MASK; + bits &= ~MANTISSA_MASK; bits |= mantVal; } LIBC_INLINE constexpr UIntType get_mantissa() const { - return bits & FloatProp::MANTISSA_MASK; + return bits & MANTISSA_MASK; } LIBC_INLINE constexpr void set_biased_exponent(UIntType expVal) { - expVal = (expVal << (FloatProp::MANTISSA_WIDTH)) & FloatProp::EXPONENT_MASK; - bits &= ~(FloatProp::EXPONENT_MASK); + expVal = (expVal << MANTISSA_WIDTH) & EXPONENT_MASK; + bits &= ~EXPONENT_MASK; bits |= expVal; } LIBC_INLINE constexpr uint16_t get_biased_exponent() const { - return uint16_t((bits & FloatProp::EXPONENT_MASK) >> - (FloatProp::MANTISSA_WIDTH)); + return uint16_t((bits & EXPONENT_MASK) >> MANTISSA_WIDTH); } // The function return mantissa with the implicit bit set iff the current // value is a valid normal number. LIBC_INLINE constexpr UIntType get_explicit_mantissa() { return ((get_biased_exponent() > 0 && !is_inf_or_nan()) - ? (FloatProp::MANTISSA_MASK + 1) + ? (MANTISSA_MASK + 1) : 0) | - (FloatProp::MANTISSA_MASK & bits); + (MANTISSA_MASK & bits); } LIBC_INLINE constexpr void set_sign(bool signVal) { - bits |= FloatProp::SIGN_MASK; + bits |= SIGN_MASK; if (!signVal) - bits -= FloatProp::SIGN_MASK; + bits -= SIGN_MASK; } LIBC_INLINE constexpr bool get_sign() const { - return (bits & FloatProp::SIGN_MASK) != 0; + return (bits & SIGN_MASK) != 0; } static_assert(sizeof(T) == sizeof(UIntType), "Data type and integral representation have different sizes."); - static constexpr int EXPONENT_BIAS = (1 << (ExponentWidth<T>::VALUE - 1)) - 1; - static constexpr int MAX_EXPONENT = (1 << ExponentWidth<T>::VALUE) - 1; + static constexpr int MAX_EXPONENT = (1 << EXPONENT_WIDTH) - 1; static constexpr UIntType MIN_SUBNORMAL = UIntType(1); - static constexpr UIntType MAX_SUBNORMAL = - (UIntType(1) << MantissaWidth<T>::VALUE) - 1; - static constexpr UIntType MIN_NORMAL = - (UIntType(1) << MantissaWidth<T>::VALUE); + static constexpr UIntType MAX_SUBNORMAL = (UIntType(1) << MANTISSA_WIDTH) - 1; + static constexpr UIntType MIN_NORMAL = (UIntType(1) << MANTISSA_WIDTH); static constexpr UIntType MAX_NORMAL = - ((UIntType(MAX_EXPONENT) - 1) << MantissaWidth<T>::VALUE) | MAX_SUBNORMAL; + ((UIntType(MAX_EXPONENT) - 1) << MANTISSA_WIDTH) | MAX_SUBNORMAL; // We don't want accidental type promotions/conversions, so we require exact // type match. @@ -151,32 +154,29 @@ template <typename T> struct FPBits { } LIBC_INLINE constexpr bool is_inf() const { - return (bits & FloatProp::EXP_MANT_MASK) == FloatProp::EXPONENT_MASK; + return (bits & EXP_MANT_MASK) == EXPONENT_MASK; } LIBC_INLINE constexpr bool is_nan() const { - return (bits & FloatProp::EXP_MANT_MASK) > FloatProp::EXPONENT_MASK; + return (bits & EXP_MANT_MASK) > EXPONENT_MASK; } LIBC_INLINE constexpr bool is_quiet_nan() const { - return (bits & FloatProp::EXP_MANT_MASK) == - (FloatProp::EXPONENT_MASK | FloatProp::QUIET_NAN_MASK); + return (bits & EXP_MANT_MASK) == (EXPONENT_MASK | QUIET_NAN_MASK); } LIBC_INLINE constexpr bool is_inf_or_nan() const { - return (bits & FloatProp::EXPONENT_MASK) == FloatProp::EXPONENT_MASK; + return (bits & EXPONENT_MASK) == EXPONENT_MASK; } LIBC_INLINE static constexpr T zero(bool sign = false) { - return FPBits(sign ? FloatProp::SIGN_MASK : UIntType(0)).get_val(); + return FPBits(sign ? SIGN_MASK : UIntType(0)).get_val(); } LIBC_INLINE static constexpr T neg_zero() { return zero(true); } LIBC_INLINE static constexpr T inf(bool sign = false) { - return FPBits((sign ? FloatProp::SIGN_MASK : UIntType(0)) | - FloatProp::EXPONENT_MASK) - .get_val(); + return FPBits((sign ? SIGN_MASK : UIntType(0)) | EXPONENT_MASK).get_val(); } LIBC_INLINE static constexpr T neg_inf() { return inf(true); } @@ -204,7 +204,7 @@ template <typename T> struct FPBits { } LIBC_INLINE static constexpr T build_quiet_nan(UIntType v) { - return build_nan(FloatProp::QUIET_NAN_MASK | v); + return build_nan(QUIET_NAN_MASK | v); } // The function convert integer number and unbiased exponent to proper float @@ -220,7 +220,7 @@ template <typename T> struct FPBits { LIBC_INLINE static constexpr FPBits<T> make_value(UIntType number, int ep) { FPBits<T> result; // offset: +1 for sign, but -1 for implicit first bit - int lz = cpp::countl_zero(number) - FloatProp::EXPONENT_WIDTH; + int lz = cpp::countl_zero(number) - EXPONENT_WIDTH; number <<= lz; ep -= lz; diff --git a/libc/src/__support/FPUtil/generic/FMod.h b/libc/src/__support/FPUtil/generic/FMod.h index 7502660c88a1..f30586f9d7f3 100644 --- a/libc/src/__support/FPUtil/generic/FMod.h +++ b/libc/src/__support/FPUtil/generic/FMod.h @@ -167,11 +167,11 @@ template <typename T> struct FModFastMathWrapper { template <typename T> class FModDivisionSimpleHelper { private: - using intU_t = typename FPBits<T>::UIntType; + using UIntType = typename FPBits<T>::UIntType; public: - LIBC_INLINE constexpr static intU_t - execute(int exp_diff, int sides_zeroes_count, intU_t m_x, intU_t m_y) { + LIBC_INLINE constexpr static UIntType + execute(int exp_diff, int sides_zeroes_count, UIntType m_x, UIntType m_y) { while (exp_diff > sides_zeroes_count) { exp_diff -= sides_zeroes_count; m_x <<= sides_zeroes_count; @@ -186,23 +186,22 @@ public: template <typename T> class FModDivisionInvMultHelper { private: using FPB = FPBits<T>; - using intU_t = typename FPB::UIntType; + using UIntType = typename FPB::UIntType; public: - LIBC_INLINE constexpr static intU_t - execute(int exp_diff, int sides_zeroes_count, intU_t m_x, intU_t m_y) { + LIBC_INLINE constexpr static UIntType + execute(int exp_diff, int sides_zeroes_count, UIntType m_x, UIntType m_y) { if (exp_diff > sides_zeroes_count) { - intU_t inv_hy = (cpp::numeric_limits<intU_t>::max() / m_y); + UIntType inv_hy = (cpp::numeric_limits<UIntType>::max() / m_y); while (exp_diff > sides_zeroes_count) { exp_diff -= sides_zeroes_count; - intU_t hd = - (m_x * inv_hy) >> (FPB::FloatProp::BIT_WIDTH - sides_zeroes_count); + UIntType hd = (m_x * inv_hy) >> (FPB::BIT_WIDTH - sides_zeroes_count); m_x <<= sides_zeroes_count; m_x -= hd * m_y; while (LIBC_UNLIKELY(m_x > m_y)) m_x -= m_y; } - intU_t hd = (m_x * inv_hy) >> (FPB::FloatProp::BIT_WIDTH - exp_diff); + UIntType hd = (m_x * inv_hy) >> (FPB::BIT_WIDTH - exp_diff); m_x <<= exp_diff; m_x -= hd * m_y; while (LIBC_UNLIKELY(m_x > m_y)) @@ -223,7 +222,7 @@ class FMod { private: using FPB = FPBits<T>; - using intU_t = typename FPB::UIntType; + using UIntType = typename FPB::UIntType; LIBC_INLINE static constexpr FPB eval_internal(FPB sx, FPB sy) { @@ -237,11 +236,11 @@ private: int e_y = sy.get_biased_exponent(); // Most common case where |y| is "very normal" and |x/y| < 2^EXPONENT_WIDTH - if (LIBC_LIKELY(e_y > int(FPB::FloatProp::MANTISSA_WIDTH) && - e_x - e_y <= int(FPB::FloatProp::EXPONENT_WIDTH))) { - intU_t m_x = sx.get_explicit_mantissa(); - intU_t m_y = sy.get_explicit_mantissa(); - intU_t d = (e_x == e_y) ? (m_x - m_y) : (m_x << (e_x - e_y)) % m_y; + if (LIBC_LIKELY(e_y > int(FPB::MANTISSA_WIDTH) && + e_x - e_y <= int(FPB::EXPONENT_WIDTH))) { + UIntType m_x = sx.get_explicit_mantissa(); + UIntType m_y = sy.get_explicit_mantissa(); + UIntType d = (e_x == e_y) ? (m_x - m_y) : (m_x << (e_x - e_y)) % m_y; if (d == 0) return FPB(FPB::zero()); // iy - 1 because of "zero power" for number with power 1 @@ -255,11 +254,11 @@ private: } // Note that hx is not subnormal by conditions above. - intU_t m_x = sx.get_explicit_mantissa(); + UIntType m_x = sx.get_explicit_mantissa(); e_x--; - intU_t m_y = sy.get_explicit_mantissa(); - int lead_zeros_m_y = FPB::FloatProp::EXPONENT_WIDTH; + UIntType m_y = sy.get_explicit_mantissa(); + int lead_zeros_m_y = FPB::EXPONENT_WIDTH; if (LIBC_LIKELY(e_y > 0)) { e_y--; } else { @@ -282,9 +281,8 @@ private: { // Shift hx left until the end or n = 0 - int left_shift = exp_diff < int(FPB::FloatProp::EXPONENT_WIDTH) - ? exp_diff - : FPB::FloatProp::EXPONENT_WIDTH; + int left_shift = + exp_diff < int(FPB::EXPONENT_WIDTH) ? exp_diff : FPB::EXPONENT_WIDTH; m_x <<= left_shift; exp_diff -= left_shift; } diff --git a/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h b/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h index f1ef928f2308..f682f171bcab 100644 --- a/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h +++ b/libc/src/__support/FPUtil/x86_64/LongDoubleBits.h @@ -26,10 +26,18 @@ namespace LIBC_NAMESPACE { namespace fputil { -template <> struct FPBits<long double> { - using UIntType = UInt128; +template <> struct FPBits<long double> : private FloatProperties<long double> { + using typename FloatProperties<long double>::UIntType; + using FloatProperties<long double>::BIT_WIDTH; + using FloatProperties<long double>::EXP_MANT_MASK; + using FloatProperties<long double>::EXPONENT_MASK; + using FloatProperties<long double>::EXPONENT_BIAS; + using FloatProperties<long double>::EXPONENT_WIDTH; + using FloatProperties<long double>::MANTISSA_MASK; + using FloatProperties<long double>::MANTISSA_WIDTH; + using FloatProperties<long double>::QUIET_NAN_MASK; + using FloatProperties<long double>::SIGN_MASK; - static constexpr int EXPONENT_BIAS = 0x3FFF; static constexpr int MAX_EXPONENT = 0x7FFF; static constexpr UIntType MIN_SUBNORMAL = UIntType(1); // Subnormal numbers include the implicit bit in x86 long double formats. @@ -41,59 +49,52 @@ template <> struct FPBits<long double> { (UIntType(MAX_EXPONENT - 1) << (MantissaWidth<long double>::VALUE + 1)) | (UIntType(1) << MantissaWidth<long double>::VALUE) | MAX_SUBNORMAL; - using FloatProp = FloatProperties<long double>; - UIntType bits; LIBC_INLINE constexpr void set_mantissa(UIntType mantVal) { - mantVal &= (FloatProp::MANTISSA_MASK); - bits &= ~(FloatProp::MANTISSA_MASK); + mantVal &= MANTISSA_MASK; + bits &= ~MANTISSA_MASK; bits |= mantVal; } LIBC_INLINE constexpr UIntType get_mantissa() const { - return bits & FloatProp::MANTISSA_MASK; + return bits & MANTISSA_MASK; } LIBC_INLINE constexpr UIntType get_explicit_mantissa() const { // The x86 80 bit float represents the leading digit of the mantissa // explicitly. This is the mask for that bit. - constexpr UIntType EXPLICIT_BIT_MASK = - (UIntType(1) << FloatProp::MANTISSA_WIDTH); - return bits & (FloatProp::MANTISSA_MASK | EXPLICIT_BIT_MASK); + constexpr UIntType EXPLICIT_BIT_MASK = UIntType(1) << MANTISSA_WIDTH; + return bits & (MANTISSA_MASK | EXPLICIT_BIT_MASK); } LIBC_INLINE constexpr void set_biased_exponent(UIntType expVal) { - expVal = - (expVal << (FloatProp::BIT_WIDTH - 1 - FloatProp::EXPONENT_WIDTH)) & - FloatProp::EXPONENT_MASK; - bits &= ~(FloatProp::EXPONENT_MASK); + expVal = (expVal << (BIT_WIDTH - 1 - EXPONENT_WIDTH)) & EXPONENT_MASK; + bits &= ~EXPONENT_MASK; bits |= expVal; } LIBC_INLINE constexpr uint16_t get_biased_exponent() const { - return uint16_t((bits & FloatProp::EXPONENT_MASK) >> - (FloatProp::BIT_WIDTH - 1 - FloatProp::EXPONENT_WIDTH)); + return uint16_t((bits & EXPONENT_MASK) >> (BIT_WIDTH - 1 - EXPONENT_WIDTH)); } LIBC_INLINE constexpr void set_implicit_bit(bool implicitVal) { - bits &= ~(UIntType(1) << FloatProp::MANTISSA_WIDTH); - bits |= (UIntType(implicitVal) << FloatProp::MANTISSA_WIDTH); + bits &= ~(UIntType(1) << MANTISSA_WIDTH); + bits |= (UIntType(implicitVal) << MANTISSA_WIDTH); } LIBC_INLINE constexpr bool get_implicit_bit() const { - return bool((bits & (UIntType(1) << FloatProp::MANTISSA_WIDTH)) >> - FloatProp::MANTISSA_WIDTH); + return bool((bits & (UIntType(1) << MANTISSA_WIDTH)) >> MANTISSA_WIDTH); } LIBC_INLINE constexpr void set_sign(bool signVal) { - bits &= ~(FloatProp::SIGN_MASK); - UIntType sign1 = UIntType(signVal) << (FloatProp::BIT_WIDTH - 1); + bits &= ~SIGN_MASK; + UIntType sign1 = UIntType(signVal) << (BIT_WIDTH - 1); bits |= sign1; } LIBC_INLINE constexpr bool get_sign() const { - return bool((bits & FloatProp::SIGN_MASK) >> (FloatProp::BIT_WIDTH - 1)); + return bool((bits & SIGN_MASK) >> (BIT_WIDTH - 1)); } LIBC_INLINE constexpr FPBits() : bits(0) {} @@ -117,7 +118,7 @@ template <> struct FPBits<long double> { LIBC_INLINE constexpr UIntType uintval() { // We zero the padding bits as they can contain garbage. - return bits & FloatProp::FP_MASK; + return bits & FP_MASK; } LIBC_INLINE constexpr long double get_val() const { @@ -196,7 +197,7 @@ template <> struct FPBits<long double> { } LIBC_INLINE static constexpr long double build_quiet_nan(UIntType v) { - return build_nan(FloatProp::QUIET_NAN_MASK | v); + return build_nan(QUIET_NAN_MASK | v); } LIBC_INLINE static constexpr long double min_normal() { diff --git a/libc/src/__support/File/linux/file.cpp b/libc/src/__support/File/linux/file.cpp index 2d4cea5b53c5..b84da64cbe63 100644 --- a/libc/src/__support/File/linux/file.cpp +++ b/libc/src/__support/File/linux/file.cpp @@ -17,6 +17,7 @@ #include <fcntl.h> // For mode_t and other flags to the open syscall #include <stdio.h> +#include <sys/stat.h> // For S_IS*, S_IF*, and S_IR* flags. #include <sys/syscall.h> // For syscall numbers namespace LIBC_NAMESPACE { diff --git a/libc/src/__support/str_to_float.h b/libc/src/__support/str_to_float.h index 2a6f15c018f1..3807d3ff5721 100644 --- a/libc/src/__support/str_to_float.h +++ b/libc/src/__support/str_to_float.h @@ -71,7 +71,7 @@ LIBC_INLINE cpp::optional<ExpandedFloat<T>> eisel_lemire(ExpandedFloat<T> init_num, RoundDirection round = RoundDirection::Nearest) { using FPBits = typename fputil::FPBits<T>; - using FloatProp = typename FPBits::FloatProp; + using FloatProp = typename fputil::FloatProperties<T>; using UIntType = typename FPBits::UIntType; UIntType mantissa = init_num.mantissa; @@ -184,7 +184,7 @@ LIBC_INLINE cpp::optional<ExpandedFloat<long double>> eisel_lemire<long double>(ExpandedFloat<long double> init_num, RoundDirection round) { using FPBits = typename fputil::FPBits<long double>; - using FloatProp = typename FPBits::FloatProp; + using FloatProp = typename fputil::FloatProperties<long double>; using UIntType = typename FPBits::UIntType; UIntType mantissa = init_num.mantissa; @@ -322,7 +322,7 @@ LIBC_INLINE FloatConvertReturn<T> simple_decimal_conversion(const char *__restrict numStart, RoundDirection round = RoundDirection::Nearest) { using FPBits = typename fputil::FPBits<T>; - using FloatProp = typename FPBits::FloatProp; + using FloatProp = typename fputil::FloatProperties<T>; using UIntType = typename FPBits::UIntType; int32_t exp2 = 0; @@ -516,7 +516,7 @@ LIBC_INLINE cpp::optional<ExpandedFloat<T>> clinger_fast_path(ExpandedFloat<T> init_num, RoundDirection round = RoundDirection::Nearest) { using FPBits = typename fputil::FPBits<T>; - using FloatProp = typename FPBits::FloatProp; + using FloatProp = typename fputil::FloatProperties<T>; using UIntType = typename FPBits::UIntType; UIntType mantissa = init_num.mantissa; @@ -724,7 +724,7 @@ LIBC_INLINE FloatConvertReturn<T> binary_exp_to_float(ExpandedFloat<T> init_num, bool truncated, RoundDirection round) { using FPBits = typename fputil::FPBits<T>; - using FloatProp = typename FPBits::FloatProp; + using FloatProp = typename fputil::FloatProperties<T>; using UIntType = typename FPBits::UIntType; UIntType mantissa = init_num.mantissa; diff --git a/libc/src/math/generic/acoshf.cpp b/libc/src/math/generic/acoshf.cpp index 9438be1bee74..142c17795d08 100644 --- a/libc/src/math/generic/acoshf.cpp +++ b/libc/src/math/generic/acoshf.cpp @@ -34,7 +34,7 @@ LLVM_LIBC_FUNCTION(float, acoshf, (float x)) { if (LIBC_UNLIKELY(x_u >= 0x4f8ffb03)) { // Check for exceptional values. - uint32_t x_abs = x_u & FPBits_t::FloatProp::EXP_MANT_MASK; + uint32_t x_abs = x_u & FPBits_t::EXP_MANT_MASK; if (LIBC_UNLIKELY(x_abs >= 0x7f80'0000U)) { // x is +inf or NaN. return x; diff --git a/libc/src/math/generic/asinhf.cpp b/libc/src/math/generic/asinhf.cpp index 6bde08d42a42..5b2f63d3fe14 100644 --- a/libc/src/math/generic/asinhf.cpp +++ b/libc/src/math/generic/asinhf.cpp @@ -21,7 +21,7 @@ LLVM_LIBC_FUNCTION(float, asinhf, (float x)) { using FPBits_t = typename fputil::FPBits<float>; FPBits_t xbits(x); uint32_t x_u = xbits.uintval(); - uint32_t x_abs = x_u & FPBits_t::FloatProp::EXP_MANT_MASK; + uint32_t x_abs = x_u & FPBits_t::EXP_MANT_MASK; // |x| <= 2^-3 if (LIBC_UNLIKELY(x_abs <= 0x3e80'0000U)) { diff --git a/libc/src/math/generic/atanhf.cpp b/libc/src/math/generic/atanhf.cpp index 839ef5b076ac..dfec28e9a44a 100644 --- a/libc/src/math/generic/atanhf.cpp +++ b/libc/src/math/generic/atanhf.cpp @@ -17,7 +17,7 @@ LLVM_LIBC_FUNCTION(float, atanhf, (float x)) { using FPBits = typename fputil::FPBits<float>; FPBits xbits(x); bool sign = xbits.get_sign(); - uint32_t x_abs = xbits.uintval() & FPBits::FloatProp::EXP_MANT_MASK; + uint32_t x_abs = xbits.uintval() & FPBits::EXP_MANT_MASK; // |x| >= 1.0 if (LIBC_UNLIKELY(x_abs >= 0x3F80'0000U)) { diff --git a/libc/src/math/generic/erff.cpp b/libc/src/math/generic/erff.cpp index a7b0897c3b58..d63fb8e31384 100644 --- a/libc/src/math/generic/erff.cpp +++ b/libc/src/math/generic/erff.cpp @@ -154,7 +154,7 @@ LLVM_LIBC_FUNCTION(float, erff, (float x)) { double xd = static_cast<double>(x); double xsq = xd * xd; - const uint32_t EIGHT = 3 << FPBits::FloatProp::MANTISSA_WIDTH; + const uint32_t EIGHT = 3 << FPBits::MANTISSA_WIDTH; int idx = static_cast<int>(FPBits(x_abs + EIGHT).get_val()); double x4 = xsq * xsq; diff --git a/libc/src/math/generic/explogxf.h b/libc/src/math/generic/explogxf.h index 77ec9cb94e08..3dae5af068b4 100644 --- a/libc/src/math/generic/explogxf.h +++ b/libc/src/math/generic/explogxf.h @@ -280,12 +280,11 @@ LIBC_INLINE static double log2_eval(double x) { double result = 0; result += bs.get_exponent(); - int p1 = - (bs.get_mantissa() >> (FPB::FloatProp::MANTISSA_WIDTH - LOG_P1_BITS)) & - (LOG_P1_SIZE - 1); + int p1 = (bs.get_mantissa() >> (FPB::MANTISSA_WIDTH - LOG_P1_BITS)) & + (LOG_P1_SIZE - 1); - bs.bits &= FPB::FloatProp::MANTISSA_MASK >> LOG_P1_BITS; - bs.set_biased_exponent(FPB::FloatProp::EXPONENT_BIAS); + bs.bits &= FPB::MANTISSA_MASK >> LOG_P1_BITS; + bs.set_biased_exponent(FPB::EXPONENT_BIAS); double dx = (bs.get_val() - 1.0) * LOG_P1_1_OVER[p1]; // Taylor series for log(2,1+x) @@ -311,12 +310,11 @@ LIBC_INLINE static double log_eval(double x) { // p1 is the leading 7 bits of mx, i.e. // p1 * 2^(-7) <= m_x < (p1 + 1) * 2^(-7). - int p1 = static_cast<int>(bs.get_mantissa() >> - (FPB::FloatProp::MANTISSA_WIDTH - 7)); + int p1 = static_cast<int>(bs.get_mantissa() >> (FPB::MANTISSA_WIDTH - 7)); // Set bs to (1 + (mx - p1*2^(-7)) - bs.bits &= FPB::FloatProp::MANTISSA_MASK >> 7; - bs.set_biased_exponent(FPB::FloatProp::EXPONENT_BIAS); + bs.bits &= FPB::MANTISSA_MASK >> 7; + bs.set_biased_exponent(FPB::EXPONENT_BIAS); // dx = (mx - p1*2^(-7)) / (1 + p1*2^(-7)). double dx = (bs.get_val() - 1.0) * ONE_OVER_F[p1]; diff --git a/libc/src/math/generic/inv_trigf_utils.h b/libc/src/math/generic/inv_trigf_utils.h index c88ded20b5bf..2ecd033ecbed 100644 --- a/libc/src/math/generic/inv_trigf_utils.h +++ b/libc/src/math/generic/inv_trigf_utils.h @@ -51,7 +51,7 @@ LIBC_INLINE double atan_eval(double x) { FPB bs(x); bool sign = bs.get_sign(); - auto x_abs = bs.uintval() & FPB::FloatProp::EXP_MANT_MASK; + auto x_abs = bs.uintval() & FPB::EXP_MANT_MASK; if (x_abs <= umin) { double pe = LIBC_NAMESPACE::fputil::polyeval( @@ -64,7 +64,8 @@ LIBC_INLINE double atan_eval(double x) { double one_over_x2 = one_over_x_m * one_over_x_m; double pe = LIBC_NAMESPACE::fputil::polyeval( one_over_x2, ATAN_K[0], ATAN_K[1], ATAN_K[2], ATAN_K[3]); - return fputil::multiply_add(pe, one_over_x_m, sign ? (-M_MATH_PI_2) : (M_MATH_PI_2)); + return fputil::multiply_add(pe, one_over_x_m, + sign ? (-M_MATH_PI_2) : (M_MATH_PI_2)); } double pos_x = FPB(x_abs).get_val(); diff --git a/libc/src/math/generic/log1p.cpp b/libc/src/math/generic/log1p.cpp index c8b45fd57b42..757f2793cb9c 100644 --- a/libc/src/math/generic/log1p.cpp +++ b/libc/src/math/generic/log1p.cpp @@ -873,8 +873,8 @@ LIBC_INLINE double log1p_accurate(int e_x, int index, LLVM_LIBC_FUNCTION(double, log1p, (double x)) { using FPBits_t = typename fputil::FPBits<double>; constexpr int EXPONENT_BIAS = FPBits_t::EXPONENT_BIAS; - constexpr int MANTISSA_WIDTH = FPBits_t::FloatProp::MANTISSA_WIDTH; - constexpr uint64_t MANTISSA_MASK = FPBits_t::FloatProp::MANTISSA_MASK; + constexpr int MANTISSA_WIDTH = FPBits_t::MANTISSA_WIDTH; + constexpr uint64_t MANTISSA_MASK = FPBits_t::MANTISSA_MASK; FPBits_t xbits(x); uint64_t x_u = xbits.uintval(); @@ -969,7 +969,7 @@ LLVM_LIBC_FUNCTION(double, log1p, (double x)) { // Scaling factior = 2^(-xh_bits.get_exponent()) uint64_t s_u = (static_cast<uint64_t>(EXPONENT_BIAS) << (MANTISSA_WIDTH + 1)) - - (x_u & FPBits_t::FloatProp::EXPONENT_MASK); + (x_u & FPBits_t::EXPONENT_MASK); // When the exponent of x is 2^1023, its inverse, 2^(-1023), is subnormal. const double EXPONENT_CORRECTION[2] = {0.0, 0x1.0p-1023}; double scaling = FPBits_t(s_u).get_val() + EXPONENT_CORRECTION[s_u == 0]; diff --git a/libc/src/math/generic/sinhf.cpp b/libc/src/math/generic/sinhf.cpp index 2f48ddbc0f88..db6794620b06 100644 --- a/libc/src/math/generic/sinhf.cpp +++ b/libc/src/math/generic/sinhf.cpp @@ -17,7 +17,7 @@ namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(float, sinhf, (float x)) { using FPBits = typename fputil::FPBits<float>; FPBits xbits(x); - uint32_t x_abs = xbits.uintval() & FPBits::FloatProp::EXP_MANT_MASK; + uint32_t x_abs = xbits.uintval() & FPBits::EXP_MANT_MASK; // When |x| >= 90, or x is inf or nan if (LIBC_UNLIKELY(x_abs >= 0x42b4'0000U || x_abs <= 0x3da0'0000U)) { @@ -57,8 +57,7 @@ LLVM_LIBC_FUNCTION(float, sinhf, (float x)) { int rounding = fputil::quick_get_round(); if (sign) { if (LIBC_UNLIKELY(rounding == FE_UPWARD || rounding == FE_TOWARDZERO)) - return FPBits(FPBits::MAX_NORMAL | FPBits::FloatProp::SIGN_MASK) - .get_val(); + return FPBits(FPBits::MAX_NORMAL | FPBits::SIGN_MASK).get_val(); } else { if (LIBC_UNLIKELY(rounding == FE_DOWNWARD || rounding == FE_TOWARDZERO)) return FPBits(FPBits::MAX_NORMAL).get_val(); diff --git a/libc/src/math/generic/tanhf.cpp b/libc/src/math/generic/tanhf.cpp index 7d9f86cf9044..a0046d3dabc6 100644 --- a/libc/src/math/generic/tanhf.cpp +++ b/libc/src/math/generic/tanhf.cpp @@ -24,7 +24,7 @@ LLVM_LIBC_FUNCTION(float, tanhf, (float x)) { using FPBits = typename fputil::FPBits<float>; FPBits xbits(x); uint32_t x_u = xbits.uintval(); - uint32_t x_abs = x_u & FPBits::FloatProp::EXP_MANT_MASK; + uint32_t x_abs = x_u & FPBits::EXP_MANT_MASK; // When |x| >= 15, or x is inf or nan, or |x| <= 0.078125 if (LIBC_UNLIKELY((x_abs >= 0x4170'0000U) || (x_abs <= 0x3da0'0000U))) { diff --git a/libc/src/stdlib/CMakeLists.txt b/libc/src/stdlib/CMakeLists.txt index c54d32eb7afd..a4d51fb9a11e 100644 --- a/libc/src/stdlib/CMakeLists.txt +++ b/libc/src/stdlib/CMakeLists.txt @@ -268,18 +268,27 @@ if(LLVM_LIBC_INCLUDE_SCUDO) set(SCUDO_DEPS "") include(${LIBC_SOURCE_DIR}/../compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake) - if(NOT (LIBC_TARGET_ARCHITECTURE IN_LIST ALL_SCUDO_STANDALONE_SUPPORTED_ARCH)) - message(FATAL_ERROR "Architecture ${LIBC_TARGET_ARCHITECTURE} is not supported by SCUDO. + + # scudo distinguishes riscv32 and riscv64, so we need to translate the architecture + set(LIBC_TARGET_ARCHITECTURE_FOR_SCUDO ${LIBC_TARGET_ARCHITECTURE}) + if(LIBC_TARGET_ARCHITECTURE_IS_RISCV64) + set(LIBC_TARGET_ARCHITECTURE_FOR_SCUDO riscv64) + elseif(LIBC_TARGET_ARCHITECTURE_IS_RISCV32) + set(LIBC_TARGET_ARCHITECTURE_FOR_SCUDO riscv32) + endif() + + if(NOT (LIBC_TARGET_ARCHITECTURE_FOR_SCUDO IN_LIST ALL_SCUDO_STANDALONE_SUPPORTED_ARCH)) + message(FATAL_ERROR "Architecture ${LIBC_TARGET_ARCHITECTURE_FOR_SCUDO} is not supported by SCUDO. Either disable LLVM_LIBC_INCLUDE_SCUDO or change your target architecture.") endif() - list(APPEND SCUDO_DEPS RTScudoStandalone.${LIBC_TARGET_ARCHITECTURE} - RTScudoStandaloneCWrappers.${LIBC_TARGET_ARCHITECTURE}) + list(APPEND SCUDO_DEPS RTScudoStandalone.${LIBC_TARGET_ARCHITECTURE_FOR_SCUDO} + RTScudoStandaloneCWrappers.${LIBC_TARGET_ARCHITECTURE_FOR_SCUDO}) list(APPEND SCUDO_DEPS - RTGwpAsan.${LIBC_TARGET_ARCHITECTURE} - RTGwpAsanBacktraceLibc.${LIBC_TARGET_ARCHITECTURE} - RTGwpAsanSegvHandler.${LIBC_TARGET_ARCHITECTURE} + RTGwpAsan.${LIBC_TARGET_ARCHITECTURE_FOR_SCUDO} + RTGwpAsanBacktraceLibc.${LIBC_TARGET_ARCHITECTURE_FOR_SCUDO} + RTGwpAsanSegvHandler.${LIBC_TARGET_ARCHITECTURE_FOR_SCUDO} ) add_entrypoint_external( diff --git a/libc/test/src/fcntl/creat_test.cpp b/libc/test/src/fcntl/creat_test.cpp index ca926b30e62f..ef30d8862c45 100644 --- a/libc/test/src/fcntl/creat_test.cpp +++ b/libc/test/src/fcntl/creat_test.cpp @@ -13,6 +13,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + TEST(LlvmLibcCreatTest, CreatAndOpen) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *TEST_FILE = "testdata/creat.test"; diff --git a/libc/test/src/math/FDimTest.h b/libc/test/src/math/FDimTest.h index 3118c3661013..3fb82ed8bca2 100644 --- a/libc/test/src/math/FDimTest.h +++ b/libc/test/src/math/FDimTest.h @@ -74,9 +74,9 @@ public: private: // constexpr does not work on FPBits yet, so we cannot have these constants as // static. - const T nan = T(LIBC_NAMESPACE::fputil::FPBits<T>::build_quiet_nan(1)); - const T inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::inf()); - const T neg_inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_inf()); - const T zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::zero()); - const T neg_zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_zero()); + const T nan = T(FPBits::build_quiet_nan(1)); + const T inf = T(FPBits::inf()); + const T neg_inf = T(FPBits::neg_inf()); + const T zero = T(FPBits::zero()); + const T neg_zero = T(FPBits::neg_zero()); }; diff --git a/libc/test/src/math/FmaTest.h b/libc/test/src/math/FmaTest.h index c2573d037926..94412b7021df 100644 --- a/libc/test/src/math/FmaTest.h +++ b/libc/test/src/math/FmaTest.h @@ -23,11 +23,11 @@ private: using Func = T (*)(T, T, T); using FPBits = LIBC_NAMESPACE::fputil::FPBits<T>; using UIntType = typename FPBits::UIntType; - const T nan = T(LIBC_NAMESPACE::fputil::FPBits<T>::build_quiet_nan(1)); - const T inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::inf()); - const T neg_inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_inf()); - const T zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::zero()); - const T neg_zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_zero()); + const T nan = T(FPBits::build_quiet_nan(1)); + const T inf = T(FPBits::inf()); + const T neg_inf = T(FPBits::neg_inf()); + const T zero = T(FPBits::zero()); + const T neg_zero = T(FPBits::neg_zero()); UIntType get_random_bit_pattern() { UIntType bits{0}; diff --git a/libc/test/src/math/ILogbTest.h b/libc/test/src/math/ILogbTest.h index e51a5d7a2544..9e12b4515c28 100644 --- a/libc/test/src/math/ILogbTest.h +++ b/libc/test/src/math/ILogbTest.h @@ -24,15 +24,12 @@ public: template <typename T> void test_special_numbers(typename ILogbFunc<T>::Func func) { - EXPECT_EQ(FP_ILOGB0, func(T(LIBC_NAMESPACE::fputil::FPBits<T>::zero()))); - EXPECT_EQ(FP_ILOGB0, - func(T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_zero()))); - - EXPECT_EQ(FP_ILOGBNAN, - func(T(LIBC_NAMESPACE::fputil::FPBits<T>::build_quiet_nan(1)))); - - EXPECT_EQ(INT_MAX, func(T(LIBC_NAMESPACE::fputil::FPBits<T>::inf()))); - EXPECT_EQ(INT_MAX, func(T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_inf()))); + using FPBits = LIBC_NAMESPACE::fputil::FPBits<T>; + EXPECT_EQ(FP_ILOGB0, func(T(FPBits::zero()))); + EXPECT_EQ(FP_ILOGB0, func(T(FPBits::neg_zero()))); + EXPECT_EQ(FP_ILOGBNAN, func(T(FPBits::build_quiet_nan(1)))); + EXPECT_EQ(INT_MAX, func(T(FPBits::inf()))); + EXPECT_EQ(INT_MAX, func(T(FPBits::neg_inf()))); } template <typename T> diff --git a/libc/test/src/math/LdExpTest.h b/libc/test/src/math/LdExpTest.h index a75c8ef31a2c..ce0896ec2f4c 100644 --- a/libc/test/src/math/LdExpTest.h +++ b/libc/test/src/math/LdExpTest.h @@ -28,11 +28,11 @@ class LdExpTestTemplate : public LIBC_NAMESPACE::testing::Test { // A normalized mantissa to be used with tests. static constexpr UIntType MANTISSA = NormalFloat::ONE + 0x1234; - const T zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::zero()); - const T neg_zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_zero()); - const T inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::inf()); - const T neg_inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_inf()); - const T nan = T(LIBC_NAMESPACE::fputil::FPBits<T>::build_quiet_nan(1)); + const T zero = T(FPBits::zero()); + const T neg_zero = T(FPBits::neg_zero()); + const T inf = T(FPBits::inf()); + const T neg_inf = T(FPBits::neg_inf()); + const T nan = T(FPBits::build_quiet_nan(1)); public: typedef T (*LdExpFunc)(T, int); diff --git a/libc/test/src/math/RemQuoTest.h b/libc/test/src/math/RemQuoTest.h index 6da0756c3a1b..a345e8b72e78 100644 --- a/libc/test/src/math/RemQuoTest.h +++ b/libc/test/src/math/RemQuoTest.h @@ -23,11 +23,11 @@ class RemQuoTestTemplate : public LIBC_NAMESPACE::testing::Test { using FPBits = LIBC_NAMESPACE::fputil::FPBits<T>; using UIntType = typename FPBits::UIntType; - const T zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::zero()); - const T neg_zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_zero()); - const T inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::inf()); - const T neg_inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_inf()); - const T nan = T(LIBC_NAMESPACE::fputil::FPBits<T>::build_quiet_nan(1)); + const T zero = T(FPBits::zero()); + const T neg_zero = T(FPBits::neg_zero()); + const T inf = T(FPBits::inf()); + const T neg_inf = T(FPBits::neg_inf()); + const T nan = T(FPBits::build_quiet_nan(1)); public: typedef T (*RemQuoFunc)(T, T, int *); diff --git a/libc/test/src/math/smoke/FDimTest.h b/libc/test/src/math/smoke/FDimTest.h index 3118c3661013..3fb82ed8bca2 100644 --- a/libc/test/src/math/smoke/FDimTest.h +++ b/libc/test/src/math/smoke/FDimTest.h @@ -74,9 +74,9 @@ public: private: // constexpr does not work on FPBits yet, so we cannot have these constants as // static. - const T nan = T(LIBC_NAMESPACE::fputil::FPBits<T>::build_quiet_nan(1)); - const T inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::inf()); - const T neg_inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_inf()); - const T zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::zero()); - const T neg_zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_zero()); + const T nan = T(FPBits::build_quiet_nan(1)); + const T inf = T(FPBits::inf()); + const T neg_inf = T(FPBits::neg_inf()); + const T zero = T(FPBits::zero()); + const T neg_zero = T(FPBits::neg_zero()); }; diff --git a/libc/test/src/math/smoke/FmaTest.h b/libc/test/src/math/smoke/FmaTest.h index 3c1c120d77d4..1da9652bfee1 100644 --- a/libc/test/src/math/smoke/FmaTest.h +++ b/libc/test/src/math/smoke/FmaTest.h @@ -19,11 +19,11 @@ private: using Func = T (*)(T, T, T); using FPBits = LIBC_NAMESPACE::fputil::FPBits<T>; using UIntType = typename FPBits::UIntType; - const T nan = T(LIBC_NAMESPACE::fputil::FPBits<T>::build_quiet_nan(1)); - const T inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::inf()); - const T neg_inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_inf()); - const T zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::zero()); - const T neg_zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_zero()); + const T nan = T(FPBits::build_quiet_nan(1)); + const T inf = T(FPBits::inf()); + const T neg_inf = T(FPBits::neg_inf()); + const T zero = T(FPBits::zero()); + const T neg_zero = T(FPBits::neg_zero()); public: void test_special_numbers(Func func) { diff --git a/libc/test/src/math/smoke/ILogbTest.h b/libc/test/src/math/smoke/ILogbTest.h index e51a5d7a2544..9e12b4515c28 100644 --- a/libc/test/src/math/smoke/ILogbTest.h +++ b/libc/test/src/math/smoke/ILogbTest.h @@ -24,15 +24,12 @@ public: template <typename T> void test_special_numbers(typename ILogbFunc<T>::Func func) { - EXPECT_EQ(FP_ILOGB0, func(T(LIBC_NAMESPACE::fputil::FPBits<T>::zero()))); - EXPECT_EQ(FP_ILOGB0, - func(T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_zero()))); - - EXPECT_EQ(FP_ILOGBNAN, - func(T(LIBC_NAMESPACE::fputil::FPBits<T>::build_quiet_nan(1)))); - - EXPECT_EQ(INT_MAX, func(T(LIBC_NAMESPACE::fputil::FPBits<T>::inf()))); - EXPECT_EQ(INT_MAX, func(T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_inf()))); + using FPBits = LIBC_NAMESPACE::fputil::FPBits<T>; + EXPECT_EQ(FP_ILOGB0, func(T(FPBits::zero()))); + EXPECT_EQ(FP_ILOGB0, func(T(FPBits::neg_zero()))); + EXPECT_EQ(FP_ILOGBNAN, func(T(FPBits::build_quiet_nan(1)))); + EXPECT_EQ(INT_MAX, func(T(FPBits::inf()))); + EXPECT_EQ(INT_MAX, func(T(FPBits::neg_inf()))); } template <typename T> diff --git a/libc/test/src/math/smoke/LdExpTest.h b/libc/test/src/math/smoke/LdExpTest.h index a75c8ef31a2c..ce0896ec2f4c 100644 --- a/libc/test/src/math/smoke/LdExpTest.h +++ b/libc/test/src/math/smoke/LdExpTest.h @@ -28,11 +28,11 @@ class LdExpTestTemplate : public LIBC_NAMESPACE::testing::Test { // A normalized mantissa to be used with tests. static constexpr UIntType MANTISSA = NormalFloat::ONE + 0x1234; - const T zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::zero()); - const T neg_zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_zero()); - const T inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::inf()); - const T neg_inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_inf()); - const T nan = T(LIBC_NAMESPACE::fputil::FPBits<T>::build_quiet_nan(1)); + const T zero = T(FPBits::zero()); + const T neg_zero = T(FPBits::neg_zero()); + const T inf = T(FPBits::inf()); + const T neg_inf = T(FPBits::neg_inf()); + const T nan = T(FPBits::build_quiet_nan(1)); public: typedef T (*LdExpFunc)(T, int); diff --git a/libc/test/src/math/smoke/RemQuoTest.h b/libc/test/src/math/smoke/RemQuoTest.h index 5a5d14377750..514190b6b31c 100644 --- a/libc/test/src/math/smoke/RemQuoTest.h +++ b/libc/test/src/math/smoke/RemQuoTest.h @@ -20,11 +20,11 @@ class RemQuoTestTemplate : public LIBC_NAMESPACE::testing::Test { using FPBits = LIBC_NAMESPACE::fputil::FPBits<T>; using UIntType = typename FPBits::UIntType; - const T zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::zero()); - const T neg_zero = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_zero()); - const T inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::inf()); - const T neg_inf = T(LIBC_NAMESPACE::fputil::FPBits<T>::neg_inf()); - const T nan = T(LIBC_NAMESPACE::fputil::FPBits<T>::build_quiet_nan(1)); + const T zero = T(FPBits::zero()); + const T neg_zero = T(FPBits::neg_zero()); + const T inf = T(FPBits::inf()); + const T neg_inf = T(FPBits::neg_inf()); + const T nan = T(FPBits::build_quiet_nan(1)); public: typedef T (*RemQuoFunc)(T, T, int *); diff --git a/libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp b/libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp index 7e6bb0aaca92..0870deeeb5d8 100644 --- a/libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp +++ b/libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp @@ -17,6 +17,7 @@ #include "test/UnitTest/Test.h" #include <sys/resource.h> +#include <sys/stat.h> TEST(LlvmLibcResourceLimitsTest, SetNoFileLimit) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; diff --git a/libc/test/src/unistd/access_test.cpp b/libc/test/src/unistd/access_test.cpp index ed1fe96f4f4a..7d4b3be443fe 100644 --- a/libc/test/src/unistd/access_test.cpp +++ b/libc/test/src/unistd/access_test.cpp @@ -14,6 +14,7 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> #include <unistd.h> TEST(LlvmLibcAccessTest, CreateAndTest) { diff --git a/libc/test/src/unistd/dup2_test.cpp b/libc/test/src/unistd/dup2_test.cpp index ff870db0334c..d46c4b919ce7 100644 --- a/libc/test/src/unistd/dup2_test.cpp +++ b/libc/test/src/unistd/dup2_test.cpp @@ -16,6 +16,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + TEST(LlvmLibcdupTest, ReadAndWriteViaDup) { constexpr int DUPFD = 0xD0; libc_errno = 0; diff --git a/libc/test/src/unistd/dup3_test.cpp b/libc/test/src/unistd/dup3_test.cpp index 279cfbfea1b1..d2d544d5d9a1 100644 --- a/libc/test/src/unistd/dup3_test.cpp +++ b/libc/test/src/unistd/dup3_test.cpp @@ -16,6 +16,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + // The tests here are exactly the same as those of dup2. We only test the // plumbing of the dup3 syscall and not the dup3 functionality itself as it is // a simple syscall wrapper. Testing dup3 functionality is beyond the scope of diff --git a/libc/test/src/unistd/dup_test.cpp b/libc/test/src/unistd/dup_test.cpp index 38c439125db3..856b004fbe65 100644 --- a/libc/test/src/unistd/dup_test.cpp +++ b/libc/test/src/unistd/dup_test.cpp @@ -16,6 +16,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + TEST(LlvmLibcdupTest, ReadAndWriteViaDup) { libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; diff --git a/libc/test/src/unistd/ftruncate_test.cpp b/libc/test/src/unistd/ftruncate_test.cpp index ae743b385e22..fc68348e32ec 100644 --- a/libc/test/src/unistd/ftruncate_test.cpp +++ b/libc/test/src/unistd/ftruncate_test.cpp @@ -17,6 +17,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + namespace cpp = LIBC_NAMESPACE::cpp; TEST(LlvmLibcFtruncateTest, CreateAndTruncate) { diff --git a/libc/test/src/unistd/isatty_test.cpp b/libc/test/src/unistd/isatty_test.cpp index fce4a3e5f506..7bf8dd708bfa 100644 --- a/libc/test/src/unistd/isatty_test.cpp +++ b/libc/test/src/unistd/isatty_test.cpp @@ -13,6 +13,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; diff --git a/libc/test/src/unistd/link_test.cpp b/libc/test/src/unistd/link_test.cpp index b1b9383cb62e..2d5aa7588b08 100644 --- a/libc/test/src/unistd/link_test.cpp +++ b/libc/test/src/unistd/link_test.cpp @@ -14,6 +14,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + TEST(LlvmLibcLinkTest, CreateAndUnlink) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *TEST_FILE = "testdata/link.test"; diff --git a/libc/test/src/unistd/linkat_test.cpp b/libc/test/src/unistd/linkat_test.cpp index 2ef41cd4e75f..d1ffe37d63b4 100644 --- a/libc/test/src/unistd/linkat_test.cpp +++ b/libc/test/src/unistd/linkat_test.cpp @@ -14,6 +14,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + TEST(LlvmLibcLinkatTest, CreateAndUnlink) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *TEST_DIR = "testdata"; diff --git a/libc/test/src/unistd/pread_pwrite_test.cpp b/libc/test/src/unistd/pread_pwrite_test.cpp index 6819f559424f..f90d1341c201 100644 --- a/libc/test/src/unistd/pread_pwrite_test.cpp +++ b/libc/test/src/unistd/pread_pwrite_test.cpp @@ -17,6 +17,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + TEST(LlvmLibcUniStd, PWriteAndPReadBackTest) { // The strategy here is that we first create a file and write to it. Next, // we open that file again and write at an offset. Finally, we open the diff --git a/libc/test/src/unistd/read_write_test.cpp b/libc/test/src/unistd/read_write_test.cpp index 20b51bb8082b..3007d4c38711 100644 --- a/libc/test/src/unistd/read_write_test.cpp +++ b/libc/test/src/unistd/read_write_test.cpp @@ -15,6 +15,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + TEST(LlvmLibcUniStd, WriteAndReadBackTest) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *TEST_FILE = "__unistd_read_write.test"; diff --git a/libc/test/src/unistd/symlink_test.cpp b/libc/test/src/unistd/symlink_test.cpp index 84d963b7a207..b25cfa4f8576 100644 --- a/libc/test/src/unistd/symlink_test.cpp +++ b/libc/test/src/unistd/symlink_test.cpp @@ -14,6 +14,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + TEST(LlvmLibcSymlinkTest, CreateAndUnlink) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *TEST_FILE_BASE = "symlink.test"; diff --git a/libc/test/src/unistd/symlinkat_test.cpp b/libc/test/src/unistd/symlinkat_test.cpp index b0308787f205..8aba2daee8cf 100644 --- a/libc/test/src/unistd/symlinkat_test.cpp +++ b/libc/test/src/unistd/symlinkat_test.cpp @@ -14,6 +14,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + TEST(LlvmLibcSymlinkatTest, CreateAndUnlink) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *TEST_DIR = "testdata"; diff --git a/libc/test/src/unistd/syscall_test.cpp b/libc/test/src/unistd/syscall_test.cpp index 211b27c3188c..6a5ca47f8d49 100644 --- a/libc/test/src/unistd/syscall_test.cpp +++ b/libc/test/src/unistd/syscall_test.cpp @@ -12,6 +12,7 @@ #include "test/UnitTest/Test.h" #include <fcntl.h> +#include <sys/stat.h> // For S_* flags. #include <sys/syscall.h> // For syscall numbers. #include <unistd.h> diff --git a/libc/test/src/unistd/truncate_test.cpp b/libc/test/src/unistd/truncate_test.cpp index 15940321e5ad..6d8a3b8e53f7 100644 --- a/libc/test/src/unistd/truncate_test.cpp +++ b/libc/test/src/unistd/truncate_test.cpp @@ -17,6 +17,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + namespace cpp = LIBC_NAMESPACE::cpp; TEST(LlvmLibcTruncateTest, CreateAndTruncate) { diff --git a/libc/test/src/unistd/unlink_test.cpp b/libc/test/src/unistd/unlink_test.cpp index 8a64f88ee6f2..77f65b5ecc6a 100644 --- a/libc/test/src/unistd/unlink_test.cpp +++ b/libc/test/src/unistd/unlink_test.cpp @@ -13,6 +13,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + TEST(LlvmLibcUnlinkTest, CreateAndUnlink) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *TEST_FILE = "testdata/unlink.test"; diff --git a/libc/test/src/unistd/unlinkat_test.cpp b/libc/test/src/unistd/unlinkat_test.cpp index 5953085bf12b..22a20bc6ad07 100644 --- a/libc/test/src/unistd/unlinkat_test.cpp +++ b/libc/test/src/unistd/unlinkat_test.cpp @@ -14,6 +14,8 @@ #include "test/UnitTest/ErrnoSetterMatcher.h" #include "test/UnitTest/Test.h" +#include <sys/stat.h> + TEST(LlvmLibcUnlinkatTest, CreateAndDeleteTest) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *TEST_DIR = "testdata"; diff --git a/libcxx/CMakeLists.txt b/libcxx/CMakeLists.txt index 5970322505dd..75cb63222da3 100644 --- a/libcxx/CMakeLists.txt +++ b/libcxx/CMakeLists.txt @@ -677,15 +677,17 @@ function(cxx_link_system_libraries target) target_add_link_flags_if_supported(${target} PRIVATE "--unwindlib=none") endif() - if (LIBCXX_USE_COMPILER_RT) - find_compiler_rt_library(builtins LIBCXX_BUILTINS_LIBRARY) - if (LIBCXX_BUILTINS_LIBRARY) - target_link_libraries(${target} PRIVATE "${LIBCXX_BUILTINS_LIBRARY}") + if (MSVC) + if (LIBCXX_USE_COMPILER_RT) + find_compiler_rt_library(builtins LIBCXX_BUILTINS_LIBRARY) + if (LIBCXX_BUILTINS_LIBRARY) + target_link_libraries(${target} PRIVATE "${LIBCXX_BUILTINS_LIBRARY}") + endif() + elseif (LIBCXX_HAS_GCC_LIB) + target_link_libraries(${target} PRIVATE gcc) + elseif (LIBCXX_HAS_GCC_S_LIB) + target_link_libraries(${target} PRIVATE gcc_s) endif() - elseif (LIBCXX_HAS_GCC_LIB) - target_link_libraries(${target} PRIVATE gcc) - elseif (LIBCXX_HAS_GCC_S_LIB) - target_link_libraries(${target} PRIVATE gcc_s) endif() if (LIBCXX_HAS_ATOMIC_LIB) diff --git a/libcxx/cmake/config-ix.cmake b/libcxx/cmake/config-ix.cmake index a365517936e7..1e8c2f5ce463 100644 --- a/libcxx/cmake/config-ix.cmake +++ b/libcxx/cmake/config-ix.cmake @@ -45,7 +45,9 @@ else() endif() endif() -if (CXX_SUPPORTS_NOSTDLIBXX_FLAG OR C_SUPPORTS_NODEFAULTLIBS_FLAG) +# Only link against compiler-rt manually if we use -nodefaultlibs, since +# otherwise the compiler will do the right thing on its own. +if (NOT CXX_SUPPORTS_NOSTDLIBXX_FLAG AND C_SUPPORTS_NODEFAULTLIBS_FLAG) if (LIBCXX_USE_COMPILER_RT) include(HandleCompilerRT) find_compiler_rt_library(builtins LIBCXX_BUILTINS_LIBRARY @@ -73,6 +75,9 @@ if (CXX_SUPPORTS_NOSTDLIBXX_FLAG OR C_SUPPORTS_NODEFAULTLIBS_FLAG) moldname mingwex msvcrt) list(APPEND CMAKE_REQUIRED_LIBRARIES ${MINGW_LIBRARIES}) endif() +endif() + +if (CXX_SUPPORTS_NOSTDLIBXX_FLAG OR C_SUPPORTS_NODEFAULTLIBS_FLAG) if (CMAKE_C_FLAGS MATCHES -fsanitize OR CMAKE_CXX_FLAGS MATCHES -fsanitize) set(CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS} -fno-sanitize=all") endif () diff --git a/libcxx/docs/index.rst b/libcxx/docs/index.rst index c9ce3d426a2e..c7769bae6bb1 100644 --- a/libcxx/docs/index.rst +++ b/libcxx/docs/index.rst @@ -67,10 +67,6 @@ Getting Started with libc++ Current Status ============== -.. image:: https://github.com/llvm/llvm-project/actions/workflows/libcxx-build-and-test.yaml/badge.svg?branch=main&event=schedule - :target: https://github.com/llvm/llvm-project/actions/workflows/libcxx-build-and-test.yaml?query=event%3Aschedule - :alt: Build and Test libc++ - After its initial introduction, many people have asked "why start a new library instead of contributing to an existing library?" (like Apache's libstdcxx, GNU's libstdc++, STLport, etc). There are many contributing @@ -206,6 +202,10 @@ Design Documents Build Bots and Test Coverage ============================ +.. image:: https://github.com/llvm/llvm-project/actions/workflows/libcxx-build-and-test.yaml/badge.svg?branch=main&event=schedule + :target: https://github.com/llvm/llvm-project/actions/workflows/libcxx-build-and-test.yaml?query=event%3Aschedule + :alt: Build and Test libc++ + * `Github Actions CI pipeline <https://github.com/llvm/llvm-project/actions/workflows/libcxx-build-and-test.yaml>`_ * `Buildkite CI pipeline <https://buildkite.com/llvm-project/libcxx-ci>`_ * `LLVM Buildbot Builders <https://lab.llvm.org/buildbot>`_ diff --git a/libcxx/include/__chrono/day.h b/libcxx/include/__chrono/day.h index c907c036c146..d908453d5b08 100644 --- a/libcxx/include/__chrono/day.h +++ b/libcxx/include/__chrono/day.h @@ -46,7 +46,7 @@ _LIBCPP_HIDE_FROM_ABI inline constexpr bool operator==(const day& __lhs, const day& __rhs) noexcept { return static_cast<unsigned>(__lhs) == static_cast<unsigned>(__rhs); } -_LIBCPP_HIDE_FROM_ABI constexpr strong_ordering operator<=>(const day& __lhs, const day& __rhs) noexcept { +_LIBCPP_HIDE_FROM_ABI inline constexpr strong_ordering operator<=>(const day& __lhs, const day& __rhs) noexcept { return static_cast<unsigned>(__lhs) <=> static_cast<unsigned>(__rhs); } diff --git a/libcxx/include/__chrono/hh_mm_ss.h b/libcxx/include/__chrono/hh_mm_ss.h index 5bd452e57fa3..0adee2d60db8 100644 --- a/libcxx/include/__chrono/hh_mm_ss.h +++ b/libcxx/include/__chrono/hh_mm_ss.h @@ -87,17 +87,17 @@ private: }; _LIBCPP_CTAD_SUPPORTED_FOR_TYPE(hh_mm_ss); -_LIBCPP_HIDE_FROM_ABI constexpr bool is_am(const hours& __h) noexcept { return __h >= hours( 0) && __h < hours(12); } -_LIBCPP_HIDE_FROM_ABI constexpr bool is_pm(const hours& __h) noexcept { return __h >= hours(12) && __h < hours(24); } +_LIBCPP_HIDE_FROM_ABI inline constexpr bool is_am(const hours& __h) noexcept { return __h >= hours( 0) && __h < hours(12); } +_LIBCPP_HIDE_FROM_ABI inline constexpr bool is_pm(const hours& __h) noexcept { return __h >= hours(12) && __h < hours(24); } -_LIBCPP_HIDE_FROM_ABI constexpr hours make12(const hours& __h) noexcept +_LIBCPP_HIDE_FROM_ABI inline constexpr hours make12(const hours& __h) noexcept { if (__h == hours( 0)) return hours(12); else if (__h <= hours(12)) return __h; else return __h - hours(12); } -_LIBCPP_HIDE_FROM_ABI constexpr hours make24(const hours& __h, bool __is_pm) noexcept +_LIBCPP_HIDE_FROM_ABI inline constexpr hours make24(const hours& __h, bool __is_pm) noexcept { if (__is_pm) return __h == hours(12) ? __h : __h + hours(12); diff --git a/libcxx/include/__chrono/month.h b/libcxx/include/__chrono/month.h index 7566e4ed2998..2dee5d8c6c70 100644 --- a/libcxx/include/__chrono/month.h +++ b/libcxx/include/__chrono/month.h @@ -46,7 +46,7 @@ _LIBCPP_HIDE_FROM_ABI inline constexpr bool operator==(const month& __lhs, const month& __rhs) noexcept { return static_cast<unsigned>(__lhs) == static_cast<unsigned>(__rhs); } -_LIBCPP_HIDE_FROM_ABI constexpr strong_ordering operator<=>(const month& __lhs, const month& __rhs) noexcept { +_LIBCPP_HIDE_FROM_ABI inline constexpr strong_ordering operator<=>(const month& __lhs, const month& __rhs) noexcept { return static_cast<unsigned>(__lhs) <=> static_cast<unsigned>(__rhs); } diff --git a/libcxx/include/__chrono/monthday.h b/libcxx/include/__chrono/monthday.h index 03fd7503a6b4..8403d9ec4eeb 100644 --- a/libcxx/include/__chrono/monthday.h +++ b/libcxx/include/__chrono/monthday.h @@ -59,7 +59,7 @@ _LIBCPP_HIDE_FROM_ABI inline constexpr bool operator==(const month_day& __lhs, const month_day& __rhs) noexcept { return __lhs.month() == __rhs.month() && __lhs.day() == __rhs.day(); } -_LIBCPP_HIDE_FROM_ABI constexpr strong_ordering operator<=>(const month_day& __lhs, const month_day& __rhs) noexcept { +_LIBCPP_HIDE_FROM_ABI inline constexpr strong_ordering operator<=>(const month_day& __lhs, const month_day& __rhs) noexcept { if (auto __c = __lhs.month() <=> __rhs.month(); __c != 0) return __c; return __lhs.day() <=> __rhs.day(); @@ -69,7 +69,7 @@ _LIBCPP_HIDE_FROM_ABI inline constexpr month_day operator/(const month& __lhs, const day& __rhs) noexcept { return month_day{__lhs, __rhs}; } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr month_day operator/(const day& __lhs, const month& __rhs) noexcept { return __rhs / __lhs; } @@ -77,11 +77,11 @@ _LIBCPP_HIDE_FROM_ABI inline constexpr month_day operator/(const month& __lhs, int __rhs) noexcept { return __lhs / day(__rhs); } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr month_day operator/(int __lhs, const day& __rhs) noexcept { return month(__lhs) / __rhs; } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr month_day operator/(const day& __lhs, int __rhs) noexcept { return month(__rhs) / __lhs; } @@ -99,7 +99,7 @@ _LIBCPP_HIDE_FROM_ABI inline constexpr bool operator==(const month_day_last& __lhs, const month_day_last& __rhs) noexcept { return __lhs.month() == __rhs.month(); } -_LIBCPP_HIDE_FROM_ABI constexpr strong_ordering +_LIBCPP_HIDE_FROM_ABI inline constexpr strong_ordering operator<=>(const month_day_last& __lhs, const month_day_last& __rhs) noexcept { return __lhs.month() <=> __rhs.month(); } diff --git a/libcxx/include/__chrono/weekday.h b/libcxx/include/__chrono/weekday.h index 776d8ed3124c..292fcb40dc30 100644 --- a/libcxx/include/__chrono/weekday.h +++ b/libcxx/include/__chrono/weekday.h @@ -85,7 +85,7 @@ _LIBCPP_HIDE_FROM_ABI inline constexpr bool operator>=(const weekday& __lhs, const weekday& __rhs) noexcept { return !(__lhs < __rhs); } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr weekday operator+(const weekday& __lhs, const days& __rhs) noexcept { auto const __mu = static_cast<long long>(__lhs.c_encoding()) + __rhs.count(); @@ -93,15 +93,15 @@ weekday operator+(const weekday& __lhs, const days& __rhs) noexcept return weekday{static_cast<unsigned>(__mu - __yr * 7)}; } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr weekday operator+(const days& __lhs, const weekday& __rhs) noexcept { return __rhs + __lhs; } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr weekday operator-(const weekday& __lhs, const days& __rhs) noexcept { return __lhs + -__rhs; } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr days operator-(const weekday& __lhs, const weekday& __rhs) noexcept { const int __wdu = __lhs.c_encoding() - __rhs.c_encoding(); diff --git a/libcxx/include/__chrono/year_month.h b/libcxx/include/__chrono/year_month.h index d1657b61015b..320cf588ccd3 100644 --- a/libcxx/include/__chrono/year_month.h +++ b/libcxx/include/__chrono/year_month.h @@ -53,13 +53,13 @@ _LIBCPP_HIDE_FROM_ABI inline constexpr bool operator==(const year_month& __lhs, const year_month& __rhs) noexcept { return __lhs.year() == __rhs.year() && __lhs.month() == __rhs.month(); } -_LIBCPP_HIDE_FROM_ABI constexpr strong_ordering operator<=>(const year_month& __lhs, const year_month& __rhs) noexcept { +_LIBCPP_HIDE_FROM_ABI inline constexpr strong_ordering operator<=>(const year_month& __lhs, const year_month& __rhs) noexcept { if (auto __c = __lhs.year() <=> __rhs.year(); __c != 0) return __c; return __lhs.month() <=> __rhs.month(); } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr year_month operator+(const year_month& __lhs, const months& __rhs) noexcept { int __dmi = static_cast<int>(static_cast<unsigned>(__lhs.month())) - 1 + __rhs.count(); @@ -68,27 +68,27 @@ year_month operator+(const year_month& __lhs, const months& __rhs) noexcept return (__lhs.year() + years(__dy)) / month(static_cast<unsigned>(__dmi)); } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr year_month operator+(const months& __lhs, const year_month& __rhs) noexcept { return __rhs + __lhs; } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr year_month operator+(const year_month& __lhs, const years& __rhs) noexcept { return (__lhs.year() + __rhs) / __lhs.month(); } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr year_month operator+(const years& __lhs, const year_month& __rhs) noexcept { return __rhs + __lhs; } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr months operator-(const year_month& __lhs, const year_month& __rhs) noexcept { return (__lhs.year() - __rhs.year()) + months(static_cast<unsigned>(__lhs.month()) - static_cast<unsigned>(__rhs.month())); } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr year_month operator-(const year_month& __lhs, const months& __rhs) noexcept { return __lhs + -__rhs; } -_LIBCPP_HIDE_FROM_ABI constexpr +_LIBCPP_HIDE_FROM_ABI inline constexpr year_month operator-(const year_month& __lhs, const years& __rhs) noexcept { return __lhs + -__rhs; } diff --git a/libcxx/include/__chrono/year_month_day.h b/libcxx/include/__chrono/year_month_day.h index ed5903f7d3f6..e84d2f8a838b 100644 --- a/libcxx/include/__chrono/year_month_day.h +++ b/libcxx/include/__chrono/year_month_day.h @@ -110,7 +110,7 @@ _LIBCPP_HIDE_FROM_ABI inline constexpr bool operator==(const year_month_day& __lhs, const year_month_day& __rhs) noexcept { return __lhs.year() == __rhs.year() && __lhs.month() == __rhs.month() && __lhs.day() == __rhs.day(); } -_LIBCPP_HIDE_FROM_ABI constexpr strong_ordering +_LIBCPP_HIDE_FROM_ABI inline constexpr strong_ordering operator<=>(const year_month_day& __lhs, const year_month_day& __rhs) noexcept { if (auto __c = __lhs.year() <=> __rhs.year(); __c != 0) return __c; diff --git a/libcxx/include/__ranges/lazy_split_view.h b/libcxx/include/__ranges/lazy_split_view.h index 2c654bfd325a..8ed4bcfdeb56 100644 --- a/libcxx/include/__ranges/lazy_split_view.h +++ b/libcxx/include/__ranges/lazy_split_view.h @@ -437,7 +437,7 @@ lazy_split_view(_Range&&, range_value_t<_Range>) namespace views { namespace __lazy_split_view { -struct __fn : __range_adaptor_closure<__fn> { +struct __fn { template <class _Range, class _Pattern> [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr auto operator()(_Range&& __range, _Pattern&& __pattern) const diff --git a/libcxx/include/__ranges/split_view.h b/libcxx/include/__ranges/split_view.h index a27ac4ef7a19..7f03be3c346a 100644 --- a/libcxx/include/__ranges/split_view.h +++ b/libcxx/include/__ranges/split_view.h @@ -194,7 +194,7 @@ public: namespace views { namespace __split_view { -struct __fn : __range_adaptor_closure<__fn> { +struct __fn { // clang-format off template <class _Range, class _Pattern> _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI diff --git a/libcxx/include/__ranges/take_view.h b/libcxx/include/__ranges/take_view.h index 4204017d9249..518375d684ab 100644 --- a/libcxx/include/__ranges/take_view.h +++ b/libcxx/include/__ranges/take_view.h @@ -180,10 +180,9 @@ public: return __lhs.count() == 0 || __lhs.base() == __rhs.__end_; } - template<bool _OtherConst = !_Const> + template <bool _OtherConst = !_Const> requires sentinel_for<sentinel_t<_Base>, iterator_t<__maybe_const<_OtherConst, _View>>> - _LIBCPP_HIDE_FROM_ABI - friend constexpr bool operator==(const _Iter<_Const>& __lhs, const __sentinel& __rhs) { + _LIBCPP_HIDE_FROM_ABI friend constexpr bool operator==(const _Iter<_OtherConst>& __lhs, const __sentinel& __rhs) { return __lhs.count() == 0 || __lhs.base() == __rhs.__end_; } }; diff --git a/libcxx/include/__variant/monostate.h b/libcxx/include/__variant/monostate.h index 8fec34008f2d..2944e41ac704 100644 --- a/libcxx/include/__variant/monostate.h +++ b/libcxx/include/__variant/monostate.h @@ -25,25 +25,25 @@ _LIBCPP_BEGIN_NAMESPACE_STD struct _LIBCPP_TEMPLATE_VIS monostate {}; -_LIBCPP_HIDE_FROM_ABI constexpr bool operator==(monostate, monostate) noexcept { return true; } +_LIBCPP_HIDE_FROM_ABI inline constexpr bool operator==(monostate, monostate) noexcept { return true; } # if _LIBCPP_STD_VER >= 20 -_LIBCPP_HIDE_FROM_ABI constexpr strong_ordering operator<=>(monostate, monostate) noexcept { +_LIBCPP_HIDE_FROM_ABI inline constexpr strong_ordering operator<=>(monostate, monostate) noexcept { return strong_ordering::equal; } # else // _LIBCPP_STD_VER >= 20 -_LIBCPP_HIDE_FROM_ABI constexpr bool operator!=(monostate, monostate) noexcept { return false; } +_LIBCPP_HIDE_FROM_ABI inline constexpr bool operator!=(monostate, monostate) noexcept { return false; } -_LIBCPP_HIDE_FROM_ABI constexpr bool operator<(monostate, monostate) noexcept { return false; } +_LIBCPP_HIDE_FROM_ABI inline constexpr bool operator<(monostate, monostate) noexcept { return false; } -_LIBCPP_HIDE_FROM_ABI constexpr bool operator>(monostate, monostate) noexcept { return false; } +_LIBCPP_HIDE_FROM_ABI inline constexpr bool operator>(monostate, monostate) noexcept { return false; } -_LIBCPP_HIDE_FROM_ABI constexpr bool operator<=(monostate, monostate) noexcept { return true; } +_LIBCPP_HIDE_FROM_ABI inline constexpr bool operator<=(monostate, monostate) noexcept { return true; } -_LIBCPP_HIDE_FROM_ABI constexpr bool operator>=(monostate, monostate) noexcept { return true; } +_LIBCPP_HIDE_FROM_ABI inline constexpr bool operator>=(monostate, monostate) noexcept { return true; } # endif // _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/cmath b/libcxx/include/cmath index 37f3c63fcef8..e8a2acf078cd 100644 --- a/libcxx/include/cmath +++ b/libcxx/include/cmath @@ -798,13 +798,13 @@ _Fp __lerp(_Fp __a, _Fp __b, _Fp __t) noexcept { return __x < __b ? __x : __b; } -_LIBCPP_HIDE_FROM_ABI constexpr float +_LIBCPP_HIDE_FROM_ABI inline constexpr float lerp(float __a, float __b, float __t) _NOEXCEPT { return __lerp(__a, __b, __t); } -_LIBCPP_HIDE_FROM_ABI constexpr double +_LIBCPP_HIDE_FROM_ABI inline constexpr double lerp(double __a, double __b, double __t) _NOEXCEPT { return __lerp(__a, __b, __t); } -_LIBCPP_HIDE_FROM_ABI constexpr long double +_LIBCPP_HIDE_FROM_ABI inline constexpr long double lerp(long double __a, long double __b, long double __t) _NOEXCEPT { return __lerp(__a, __b, __t); } template <class _A1, class _A2, class _A3> diff --git a/libcxx/include/complex b/libcxx/include/complex index 7017f25e6c5e..44579b1ad528 100644 --- a/libcxx/include/complex +++ b/libcxx/include/complex @@ -1503,34 +1503,34 @@ inline namespace literals { inline namespace complex_literals { - _LIBCPP_HIDE_FROM_ABI constexpr complex<long double> operator""il(long double __im) + _LIBCPP_HIDE_FROM_ABI inline constexpr complex<long double> operator""il(long double __im) { return { 0.0l, __im }; } - _LIBCPP_HIDE_FROM_ABI constexpr complex<long double> operator""il(unsigned long long __im) + _LIBCPP_HIDE_FROM_ABI inline constexpr complex<long double> operator""il(unsigned long long __im) { return { 0.0l, static_cast<long double>(__im) }; } - _LIBCPP_HIDE_FROM_ABI constexpr complex<double> operator""i(long double __im) + _LIBCPP_HIDE_FROM_ABI inline constexpr complex<double> operator""i(long double __im) { return { 0.0, static_cast<double>(__im) }; } - _LIBCPP_HIDE_FROM_ABI constexpr complex<double> operator""i(unsigned long long __im) + _LIBCPP_HIDE_FROM_ABI inline constexpr complex<double> operator""i(unsigned long long __im) { return { 0.0, static_cast<double>(__im) }; } - _LIBCPP_HIDE_FROM_ABI constexpr complex<float> operator""if(long double __im) + _LIBCPP_HIDE_FROM_ABI inline constexpr complex<float> operator""if(long double __im) { return { 0.0f, static_cast<float>(__im) }; } - _LIBCPP_HIDE_FROM_ABI constexpr complex<float> operator""if(unsigned long long __im) + _LIBCPP_HIDE_FROM_ABI inline constexpr complex<float> operator""if(unsigned long long __im) { return { 0.0f, static_cast<float>(__im) }; } diff --git a/libcxx/include/cstddef b/libcxx/include/cstddef index 3844d4a37332..24be0fe78058 100644 --- a/libcxx/include/cstddef +++ b/libcxx/include/cstddef @@ -71,7 +71,7 @@ namespace std // purposefully not versioned { enum class byte : unsigned char {}; -_LIBCPP_HIDE_FROM_ABI constexpr byte operator| (byte __lhs, byte __rhs) noexcept +_LIBCPP_HIDE_FROM_ABI inline constexpr byte operator| (byte __lhs, byte __rhs) noexcept { return static_cast<byte>( static_cast<unsigned char>( @@ -79,10 +79,10 @@ _LIBCPP_HIDE_FROM_ABI constexpr byte operator| (byte __lhs, byte __rhs) noexce )); } -_LIBCPP_HIDE_FROM_ABI constexpr byte& operator|=(byte& __lhs, byte __rhs) noexcept +_LIBCPP_HIDE_FROM_ABI inline constexpr byte& operator|=(byte& __lhs, byte __rhs) noexcept { return __lhs = __lhs | __rhs; } -_LIBCPP_HIDE_FROM_ABI constexpr byte operator& (byte __lhs, byte __rhs) noexcept +_LIBCPP_HIDE_FROM_ABI inline constexpr byte operator& (byte __lhs, byte __rhs) noexcept { return static_cast<byte>( static_cast<unsigned char>( @@ -90,10 +90,10 @@ _LIBCPP_HIDE_FROM_ABI constexpr byte operator& (byte __lhs, byte __rhs) noexce )); } -_LIBCPP_HIDE_FROM_ABI constexpr byte& operator&=(byte& __lhs, byte __rhs) noexcept +_LIBCPP_HIDE_FROM_ABI inline constexpr byte& operator&=(byte& __lhs, byte __rhs) noexcept { return __lhs = __lhs & __rhs; } -_LIBCPP_HIDE_FROM_ABI constexpr byte operator^ (byte __lhs, byte __rhs) noexcept +_LIBCPP_HIDE_FROM_ABI inline constexpr byte operator^ (byte __lhs, byte __rhs) noexcept { return static_cast<byte>( static_cast<unsigned char>( @@ -101,10 +101,10 @@ _LIBCPP_HIDE_FROM_ABI constexpr byte operator^ (byte __lhs, byte __rhs) noexce )); } -_LIBCPP_HIDE_FROM_ABI constexpr byte& operator^=(byte& __lhs, byte __rhs) noexcept +_LIBCPP_HIDE_FROM_ABI inline constexpr byte& operator^=(byte& __lhs, byte __rhs) noexcept { return __lhs = __lhs ^ __rhs; } -_LIBCPP_HIDE_FROM_ABI constexpr byte operator~ (byte __b) noexcept +_LIBCPP_HIDE_FROM_ABI inline constexpr byte operator~ (byte __b) noexcept { return static_cast<byte>( static_cast<unsigned char>( diff --git a/libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/user_defined_char_type.pass.cpp b/libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/user_defined_char_type.pass.cpp index d7b4b816d975..9a4a2f0d5657 100644 --- a/libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/user_defined_char_type.pass.cpp +++ b/libcxx/test/std/localization/locale.categories/category.numeric/locale.num.get/user_defined_char_type.pass.cpp @@ -16,8 +16,6 @@ #include <locale> #include <string> -#include "test_macros.h" - struct Char { Char() = default; Char(char c) : underlying_(c) {} @@ -73,15 +71,53 @@ struct char_traits<Char> { static int_type eof() { return char_traits<char>::eof(); } }; +// This ctype specialization treats all characters as spaces template <> -class ctype<Char> : public locale::facet { +class ctype<Char> : public locale::facet, public ctype_base { public: + using char_type = Char; static locale::id id; - Char toupper(Char c) const { return Char(std::toupper(c.underlying_)); } - const char* widen(const char* first, const char* last, Char* dst) const { - for (; first != last;) - *dst++ = Char(*first++); - return last; + explicit ctype(std::size_t refs = 0) : locale::facet(refs) {} + + bool is(mask m, char_type) const { return m & ctype_base::space; } + const char_type* is(const char_type* low, const char_type* high, mask* vec) const { + for (; low != high; ++low) + *vec++ = ctype_base::space; + return high; + } + + const char_type* scan_is(mask m, const char_type* beg, const char_type* end) const { + for (; beg != end; ++beg) + if (this->is(m, *beg)) + return beg; + return end; + } + + const char_type* scan_not(mask m, const char_type* beg, const char_type* end) const { + for (; beg != end; ++beg) + if (!this->is(m, *beg)) + return beg; + return end; + } + + char_type toupper(char_type c) const { return c; } + const char_type* toupper(char_type*, const char_type* end) const { return end; } + + char_type tolower(char_type c) const { return c; } + const char_type* tolower(char_type*, const char_type* end) const { return end; } + + char_type widen(char c) const { return char_type(c); } + const char* widen(const char* beg, const char* end, char_type* dst) const { + for (; beg != end; ++beg, ++dst) + *dst = char_type(*beg); + return end; + } + + char narrow(char_type c, char /*dflt*/) const { return c.underlying_; } + const char_type* narrow(const char_type* beg, const char_type* end, char /*dflt*/, char* dst) const { + for (; beg != end; ++beg, ++dst) + *dst = beg->underlying_; + return end; } }; diff --git a/libcxx/test/std/ranges/range.adaptors/range.lazy.split/adaptor.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.lazy.split/adaptor.pass.cpp index da4bd9fbbe17..6bfa0ab487ba 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.lazy.split/adaptor.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.lazy.split/adaptor.pass.cpp @@ -40,10 +40,16 @@ static_assert(!std::is_invocable_v<decltype(std::views::lazy_split), SomeView, N static_assert(!std::is_invocable_v<decltype(std::views::lazy_split), NotAView, SomeView>); static_assert( std::is_invocable_v<decltype(std::views::lazy_split), SomeView, SomeView>); -static_assert( CanBePiped<SomeView&, decltype(std::views::lazy_split)>); -static_assert( CanBePiped<char(&)[10], decltype(std::views::lazy_split)>); -static_assert(!CanBePiped<char(&&)[10], decltype(std::views::lazy_split)>); -static_assert(!CanBePiped<NotAView, decltype(std::views::lazy_split)>); +// Regression test for #75002, views::lazy_split shouldn't be a range adaptor closure +static_assert(!CanBePiped<SomeView&, decltype(std::views::lazy_split)>); +static_assert(!CanBePiped<char (&)[10], decltype(std::views::lazy_split)>); +static_assert(!CanBePiped<char (&&)[10], decltype(std::views::lazy_split)>); +static_assert(!CanBePiped<NotAView, decltype(std::views::lazy_split)>); + +static_assert(CanBePiped<SomeView&, decltype(std::views::lazy_split('x'))>); +static_assert(CanBePiped<char (&)[10], decltype(std::views::lazy_split('x'))>); +static_assert(!CanBePiped<char (&&)[10], decltype(std::views::lazy_split('x'))>); +static_assert(!CanBePiped<NotAView, decltype(std::views::lazy_split('x'))>); static_assert(std::same_as<decltype(std::views::lazy_split), decltype(std::ranges::views::lazy_split)>); diff --git a/libcxx/test/std/ranges/range.adaptors/range.split/adaptor.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.split/adaptor.pass.cpp index cd12011daeab..85d13ac5c29d 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.split/adaptor.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.split/adaptor.pass.cpp @@ -39,10 +39,16 @@ static_assert(!std::is_invocable_v<decltype(std::views::split), SomeView, NotAVi static_assert(!std::is_invocable_v<decltype(std::views::split), NotAView, SomeView>); static_assert( std::is_invocable_v<decltype(std::views::split), SomeView, SomeView>); -static_assert( CanBePiped<SomeView&, decltype(std::views::split)>); -static_assert( CanBePiped<char(&)[10], decltype(std::views::split)>); -static_assert(!CanBePiped<char(&&)[10], decltype(std::views::split)>); -static_assert(!CanBePiped<NotAView, decltype(std::views::split)>); +// Regression test for #75002, views::split shouldn't be a range adaptor closure +static_assert(!CanBePiped<SomeView&, decltype(std::views::split)>); +static_assert(!CanBePiped<char (&)[10], decltype(std::views::split)>); +static_assert(!CanBePiped<char (&&)[10], decltype(std::views::split)>); +static_assert(!CanBePiped<NotAView, decltype(std::views::split)>); + +static_assert(CanBePiped<SomeView&, decltype(std::views::split('x'))>); +static_assert(CanBePiped<char (&)[10], decltype(std::views::split('x'))>); +static_assert(!CanBePiped<char (&&)[10], decltype(std::views::split('x'))>); +static_assert(!CanBePiped<NotAView, decltype(std::views::split('x'))>); static_assert(std::same_as<decltype(std::views::split), decltype(std::ranges::views::split)>); diff --git a/libcxx/test/std/ranges/range.adaptors/range.take/sentinel/base.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/base.pass.cpp index c949eb7cc084..15b2b5476e86 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.take/sentinel/base.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/base.pass.cpp @@ -8,10 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 -// sentinel() = default; -// constexpr explicit sentinel(sentinel_t<Base> end); -// constexpr sentinel(sentinel<!Const> s) -// requires Const && convertible_to<sentinel_t<V>, sentinel_t<Base>>; +// constexpr sentinel_t<Base> base() const; #include <ranges> #include <cassert> diff --git a/libcxx/test/std/ranges/range.adaptors/range.take/sentinel/ctor.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/ctor.pass.cpp index 9d1bdaa82d95..8928371939c8 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.take/sentinel/ctor.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/ctor.pass.cpp @@ -34,14 +34,14 @@ constexpr bool test() { { // Test the conversion from "sentinel" to "sentinel-to-const". - using TakeView = std::ranges::take_view<MoveOnlyView>; - using Sentinel = std::ranges::sentinel_t<TakeView>; + using TakeView = std::ranges::take_view<MoveOnlyView>; + using Sentinel = std::ranges::sentinel_t<TakeView>; using ConstSentinel = std::ranges::sentinel_t<const TakeView>; static_assert(std::is_convertible_v<Sentinel, ConstSentinel>); - TakeView tv = TakeView(MoveOnlyView(buffer), 4); - Sentinel s = tv.end(); + TakeView tv = TakeView(MoveOnlyView(buffer), 4); + Sentinel s = tv.end(); ConstSentinel cs = s; - cs = s; // test assignment also + cs = s; // test assignment also assert(tv.begin() + 4 == s); assert(tv.begin() + 4 == cs); assert(std::as_const(tv).begin() + 4 == s); @@ -50,12 +50,12 @@ constexpr bool test() { { // Test the constructor from "base-sentinel" to "sentinel". - using TakeView = std::ranges::take_view<MoveOnlyView>; - using Sentinel = std::ranges::sentinel_t<TakeView>; + using TakeView = std::ranges::take_view<MoveOnlyView>; + using Sentinel = std::ranges::sentinel_t<TakeView>; sentinel_wrapper<int*> sw1 = MoveOnlyView(buffer).end(); - static_assert( std::is_constructible_v<Sentinel, sentinel_wrapper<int*>>); + static_assert(std::is_constructible_v<Sentinel, sentinel_wrapper<int*>>); static_assert(!std::is_convertible_v<sentinel_wrapper<int*>, Sentinel>); - auto s = Sentinel(sw1); + auto s = Sentinel(sw1); std::same_as<sentinel_wrapper<int*>> auto sw2 = s.base(); assert(base(sw2) == base(sw1)); } diff --git a/libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/eq.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/eq.pass.cpp new file mode 100644 index 000000000000..e6f433e30f60 --- /dev/null +++ b/libcxx/test/std/ranges/range.adaptors/range.take/range.take.sentinel/eq.pass.cpp @@ -0,0 +1,150 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17 + +// friend constexpr bool operator==(const CI<Const>& y, const sentinel& x); +// template<bool OtherConst = !Const> +// requires sentinel_for<sentinel_t<Base>, iterator_t<maybe-const<OtherConst, V>>> +// friend constexpr bool operator==(const CI<OtherConst>& y, const sentinel& x); + +#include <cassert> +#include <cstddef> +#include <ranges> +#include <type_traits> +#include <utility> + +#include "test_comparisons.h" +#include "test_iterators.h" + +template <bool Const> +using MaybeConstIterator = cpp20_input_iterator<std::conditional_t<Const, const int*, int*>>; + +template <bool Const> +class CrossConstComparableSentinel { + using Base = std::conditional_t<Const, const int*, int*>; + Base base_; + +public: + CrossConstComparableSentinel() = default; + constexpr explicit CrossConstComparableSentinel(Base base) : base_(base) {} + + friend constexpr bool operator==(const MaybeConstIterator<Const>& it, const CrossConstComparableSentinel& se) { + return base(it) == se.base_; + } + + friend constexpr bool operator==(const MaybeConstIterator<!Const>& it, const CrossConstComparableSentinel& se) { + return base(it) == se.base_; + } +}; + +static_assert(std::sentinel_for<CrossConstComparableSentinel<true>, MaybeConstIterator<false>>); +static_assert(std::sentinel_for<CrossConstComparableSentinel<true>, MaybeConstIterator<true>>); +static_assert(std::sentinel_for<CrossConstComparableSentinel<false>, MaybeConstIterator<false>>); +static_assert(std::sentinel_for<CrossConstComparableSentinel<false>, MaybeConstIterator<true>>); + +struct CrossConstComparableView : std::ranges::view_base { + template <std::size_t N> + constexpr explicit CrossConstComparableView(int (&arr)[N]) : b_(arr), e_(arr + N) {} + + constexpr MaybeConstIterator<false> begin() { return MaybeConstIterator<false>{b_}; } + constexpr CrossConstComparableSentinel<false> end() { return CrossConstComparableSentinel<false>{e_}; } + + constexpr MaybeConstIterator<true> begin() const { return MaybeConstIterator<true>{b_}; } + constexpr CrossConstComparableSentinel<true> end() const { return CrossConstComparableSentinel<true>{e_}; } + +private: + int* b_; + int* e_; +}; + +static_assert(std::ranges::range<CrossConstComparableView>); +static_assert(std::ranges::range<const CrossConstComparableView>); + +struct NonCrossConstComparableView : std::ranges::view_base { + int* begin(); + sentinel_wrapper<int*> end(); + + long* begin() const; + sentinel_wrapper<long*> end() const; +}; + +static_assert(std::ranges::range<NonCrossConstComparableView>); +static_assert(std::ranges::range<const NonCrossConstComparableView>); + +template <class T, class U> +concept weakly_equality_comparable_with = requires(const T& t, const U& u) { + t == u; + t != u; + u == t; + u != t; +}; + +constexpr bool test() { + int buffer[8] = {1, 2, 3, 4, 5, 6, 7, 8}; + using CrossConstComparableTakeView = std::ranges::take_view<CrossConstComparableView>; + + { // Compare CI<Const> with sentinel<Const> + { // Const == true + AssertEqualityReturnBool<std::ranges::iterator_t<const CrossConstComparableTakeView>, + std::ranges::sentinel_t<const CrossConstComparableTakeView>>(); + const CrossConstComparableTakeView tv(CrossConstComparableView{buffer}, 4); + assert(testEquality(std::ranges::next(tv.begin(), 4), tv.end(), true)); + assert(testEquality(tv.begin(), tv.end(), false)); + } + + { // Const == false + AssertEqualityReturnBool<std::ranges::iterator_t<CrossConstComparableTakeView>, + std::ranges::sentinel_t<CrossConstComparableTakeView>>(); + CrossConstComparableTakeView tv(CrossConstComparableView{buffer}, 4); + assert(testEquality(std::ranges::next(tv.begin(), 4), tv.end(), true)); + assert(testEquality(std::ranges::next(tv.begin(), 1), tv.end(), false)); + } + } + + { // Compare CI<Const> with sentinel<!Const> + { // Const == true + AssertEqualityReturnBool<std::ranges::iterator_t<const CrossConstComparableTakeView>, + std::ranges::sentinel_t<CrossConstComparableTakeView>>(); + CrossConstComparableTakeView tv(CrossConstComparableView{buffer}, 4); + assert(testEquality(std::ranges::next(std::as_const(tv).begin(), 4), tv.end(), true)); + assert(testEquality(std::ranges::next(std::as_const(tv).begin(), 2), tv.end(), false)); + } + + { // Const == false + AssertEqualityReturnBool<std::ranges::iterator_t<CrossConstComparableTakeView>, + std::ranges::sentinel_t<const CrossConstComparableTakeView>>(); + CrossConstComparableTakeView tv(CrossConstComparableView{buffer}, 4); + assert(testEquality(std::ranges::next(tv.begin(), 4), std::as_const(tv).end(), true)); + assert(testEquality(std::ranges::next(tv.begin(), 3), std::as_const(tv).end(), false)); + } + } + + { // Check invalid comparisons between CI<Const> and sentinel<!Const> + using TakeView = std::ranges::take_view<NonCrossConstComparableView>; + static_assert( + !weakly_equality_comparable_with<std::ranges::iterator_t<const TakeView>, std::ranges::sentinel_t<TakeView>>); + static_assert( + !weakly_equality_comparable_with<std::ranges::iterator_t<TakeView>, std::ranges::sentinel_t<const TakeView>>); + + // Those should be valid + static_assert( + weakly_equality_comparable_with<std::ranges::iterator_t<TakeView>, std::ranges::sentinel_t<TakeView>>); + static_assert(weakly_equality_comparable_with<std::ranges::iterator_t<const TakeView>, + std::ranges::sentinel_t<const TakeView>>); + } + + return true; +} + +int main(int, char**) { + test(); + static_assert(test()); + + return 0; +} diff --git a/libcxx/test/std/ranges/range.adaptors/range.take/sentinel/eq.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.take/sentinel/eq.pass.cpp deleted file mode 100644 index eb265a7e0348..000000000000 --- a/libcxx/test/std/ranges/range.adaptors/range.take/sentinel/eq.pass.cpp +++ /dev/null @@ -1,55 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -// UNSUPPORTED: c++03, c++11, c++14, c++17 - -// sentinel() = default; -// constexpr explicit sentinel(sentinel_t<Base> end); -// constexpr sentinel(sentinel<!Const> s) -// requires Const && convertible_to<sentinel_t<V>, sentinel_t<Base>>; - -#include <ranges> -#include <cassert> - -#include "test_macros.h" -#include "test_iterators.h" -#include "../types.h" - -constexpr bool test() { - int buffer[8] = {1, 2, 3, 4, 5, 6, 7, 8}; - - { - { - const std::ranges::take_view<MoveOnlyView> tv(MoveOnlyView{buffer}, 4); - assert(tv.end() == std::ranges::next(tv.begin(), 4)); - assert(std::ranges::next(tv.begin(), 4) == tv.end()); - } - - { - std::ranges::take_view<MoveOnlyView> tv(MoveOnlyView{buffer}, 4); - assert(tv.end() == std::ranges::next(tv.begin(), 4)); - assert(std::ranges::next(tv.begin(), 4) == tv.end()); - } - } - - { - std::ranges::take_view<MoveOnlyView> tvNonConst(MoveOnlyView{buffer}, 4); - const std::ranges::take_view<MoveOnlyView> tvConst(MoveOnlyView{buffer}, 4); - assert(tvNonConst.end() == std::ranges::next(tvConst.begin(), 4)); - assert(std::ranges::next(tvConst.begin(), 4) == tvNonConst.end()); - } - - return true; -} - -int main(int, char**) { - test(); - static_assert(test()); - - return 0; -} diff --git a/libcxx/test/support/test_comparisons.h b/libcxx/test/support/test_comparisons.h index e006f69f8bf6..db6977a96a2f 100644 --- a/libcxx/test/support/test_comparisons.h +++ b/libcxx/test/support/test_comparisons.h @@ -213,13 +213,11 @@ void AssertEqualityAreNoexcept() } template <class T, class U = T> -void AssertEqualityReturnBool() -{ - ASSERT_SAME_TYPE(decltype(std::declval<const T&>() == std::declval<const U&>()), bool); - ASSERT_SAME_TYPE(decltype(std::declval<const T&>() != std::declval<const U&>()), bool); +TEST_CONSTEXPR_CXX14 void AssertEqualityReturnBool() { + ASSERT_SAME_TYPE(decltype(std::declval<const T&>() == std::declval<const U&>()), bool); + ASSERT_SAME_TYPE(decltype(std::declval<const T&>() != std::declval<const U&>()), bool); } - template <class T, class U = T> void AssertEqualityConvertibleToBool() { diff --git a/libcxxabi/cmake/config-ix.cmake b/libcxxabi/cmake/config-ix.cmake index 39b9284b780e..10f2087c68c5 100644 --- a/libcxxabi/cmake/config-ix.cmake +++ b/libcxxabi/cmake/config-ix.cmake @@ -33,7 +33,9 @@ else() endif() endif() -if (CXX_SUPPORTS_NOSTDLIBXX_FLAG OR C_SUPPORTS_NODEFAULTLIBS_FLAG) +# Only link against compiler-rt manually if we use -nodefaultlibs, since +# otherwise the compiler will do the right thing on its own. +if (NOT CXX_SUPPORTS_NOSTDLIBXX_FLAG AND C_SUPPORTS_NODEFAULTLIBS_FLAG) if (LIBCXXABI_HAS_C_LIB) list(APPEND CMAKE_REQUIRED_LIBRARIES c) endif () @@ -67,6 +69,9 @@ if (CXX_SUPPORTS_NOSTDLIBXX_FLAG OR C_SUPPORTS_NODEFAULTLIBS_FLAG) moldname mingwex msvcrt) list(APPEND CMAKE_REQUIRED_LIBRARIES ${MINGW_LIBRARIES}) endif() +endif() + +if (CXX_SUPPORTS_NOSTDLIBXX_FLAG OR C_SUPPORTS_NODEFAULTLIBS_FLAG) if (CMAKE_C_FLAGS MATCHES -fsanitize OR CMAKE_CXX_FLAGS MATCHES -fsanitize) set(CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS} -fno-sanitize=all") endif () diff --git a/libcxxabi/src/CMakeLists.txt b/libcxxabi/src/CMakeLists.txt index 02031b69fd91..4198827203fc 100644 --- a/libcxxabi/src/CMakeLists.txt +++ b/libcxxabi/src/CMakeLists.txt @@ -166,7 +166,10 @@ if (LIBCXXABI_USE_LLVM_UNWINDER) target_link_libraries(cxxabi_shared_objects PUBLIC unwind_shared) endif() endif() -target_link_libraries(cxxabi_shared_objects PRIVATE cxx-headers ${LIBCXXABI_BUILTINS_LIBRARY} ${LIBCXXABI_LIBRARIES}) +target_link_libraries(cxxabi_shared_objects PRIVATE cxx-headers ${LIBCXXABI_LIBRARIES}) +if (NOT CXX_SUPPORTS_NOSTDLIBXX_FLAG) + target_link_libraries(cxxabi_shared_objects PRIVATE ${LIBCXXABI_BUILTINS_LIBRARY}) +endif() target_link_libraries(cxxabi_shared_objects PUBLIC cxxabi-headers) set_target_properties(cxxabi_shared_objects PROPERTIES diff --git a/libcxxabi/test/native/x86_64/lpstart-zero.pass.sh.s b/libcxxabi/test/native/x86_64/lpstart-zero.pass.sh.s index ea9dd0104c08..e18134cf8863 100644 --- a/libcxxabi/test/native/x86_64/lpstart-zero.pass.sh.s +++ b/libcxxabi/test/native/x86_64/lpstart-zero.pass.sh.s @@ -1,7 +1,8 @@ # RUN: %{cxx} %{flags} %s %{link_flags} -no-pie -o %t.exe -# RUN: %t.exe +# RUN: %{exec} %t.exe # REQUIRES: linux && target={{x86_64-.+}} +# UNSUPPORTED: target={{.+-android.*}} # UNSUPPORTED: no-exceptions ## Check that libc++abi works correctly when LPStart address is explicitly set @@ -82,7 +83,7 @@ GCC_except_table0: .byte 155 # @TType Encoding = indirect pcrel sdata4 .uleb128 .Lttbase0-.Lttbaseref0 .Lttbaseref0: - .byte 11 # Call site Encoding = udata4 + .byte 11 # Call site Encoding = sdata4 .uleb128 .Lcst_end0-.Lcst_begin0 .Lcst_begin0: .long .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 << diff --git a/libunwind/cmake/config-ix.cmake b/libunwind/cmake/config-ix.cmake index 7df8974b0a92..126c872f0d48 100644 --- a/libunwind/cmake/config-ix.cmake +++ b/libunwind/cmake/config-ix.cmake @@ -45,7 +45,9 @@ else() endif() endif() -if (CXX_SUPPORTS_NOSTDLIBXX_FLAG OR C_SUPPORTS_NODEFAULTLIBS_FLAG) +# Only link against compiler-rt manually if we use -nodefaultlibs, since +# otherwise the compiler will do the right thing on its own. +if (NOT CXX_SUPPORTS_NOSTDLIBXX_FLAG AND C_SUPPORTS_NODEFAULTLIBS_FLAG) if (LIBUNWIND_HAS_C_LIB) list(APPEND CMAKE_REQUIRED_LIBRARIES c) endif () @@ -78,6 +80,9 @@ if (CXX_SUPPORTS_NOSTDLIBXX_FLAG OR C_SUPPORTS_NODEFAULTLIBS_FLAG) moldname mingwex msvcrt) list(APPEND CMAKE_REQUIRED_LIBRARIES ${MINGW_LIBRARIES}) endif() +endif() + +if (CXX_SUPPORTS_NOSTDLIBXX_FLAG OR C_SUPPORTS_NODEFAULTLIBS_FLAG) if (CMAKE_C_FLAGS MATCHES -fsanitize OR CMAKE_CXX_FLAGS MATCHES -fsanitize) set(CMAKE_REQUIRED_FLAGS "${CMAKE_REQUIRED_FLAGS} -fno-sanitize=all") endif () diff --git a/lld/COFF/Driver.cpp b/lld/COFF/Driver.cpp index 99c1a60735ad..d4a2f5767a2e 100644 --- a/lld/COFF/Driver.cpp +++ b/lld/COFF/Driver.cpp @@ -1940,6 +1940,7 @@ void LinkerDriver::linkerMain(ArrayRef<const char *> argsArr) { parseMerge(".didat=.rdata"); parseMerge(".edata=.rdata"); parseMerge(".xdata=.rdata"); + parseMerge(".00cfg=.rdata"); parseMerge(".bss=.data"); if (config->mingw) { diff --git a/lld/test/COFF/Inputs/loadconfig-arm64ec.s b/lld/test/COFF/Inputs/loadconfig-arm64ec.s index 8bb5ccfed8eb..a270d281095d 100644 --- a/lld/test/COFF/Inputs/loadconfig-arm64ec.s +++ b/lld/test/COFF/Inputs/loadconfig-arm64ec.s @@ -1,4 +1,4 @@ - .section .rdata,"dr" + .section .00cfg,"dr" .globl _load_config_used .p2align 3, 0 _load_config_used: diff --git a/lld/test/COFF/Inputs/loadconfig-cfg-x64.s b/lld/test/COFF/Inputs/loadconfig-cfg-x64.s index 1440b115f46a..349d8c5a8db3 100644 --- a/lld/test/COFF/Inputs/loadconfig-cfg-x64.s +++ b/lld/test/COFF/Inputs/loadconfig-cfg-x64.s @@ -1,6 +1,6 @@ # This is the _load_config_used definition needed for /guard:cf tests. - .section .rdata,"dr" + .section .00cfg,"dr" .globl _load_config_used _load_config_used: .long 256 diff --git a/lld/test/COFF/merge-00cfg.s b/lld/test/COFF/merge-00cfg.s new file mode 100644 index 000000000000..89a4c8f08342 --- /dev/null +++ b/lld/test/COFF/merge-00cfg.s @@ -0,0 +1,17 @@ +// REQUIRES: x86 + +// RUN: llvm-mc -filetype=obj -triple=x86_64-windows %s -o %t-x86_64.obj +// RUN: llvm-mc -filetype=obj -triple=i686-windows %s -o %t-x86.obj +// RUN: lld-link -machine:amd64 -out:%t-x86_64.dll %t-x86_64.obj -dll -noentry +// RUN: lld-link -machine:x86 -out:%t-x86.dll %t-x86.obj -dll -noentry -safeseh:no + +// RUN: llvm-readobj --hex-dump=.rdata %t-x86_64.dll | FileCheck %s -check-prefix=RDATA +// RUN: llvm-readobj --hex-dump=.rdata %t-x86.dll | FileCheck %s -check-prefix=RDATA +// RDATA: 78563412 + +// RUN: llvm-readobj --sections %t-x86_64.dll | FileCheck %s -check-prefix=SECTIONS +// RUN: llvm-readobj --sections %t-x86.dll | FileCheck %s -check-prefix=SECTIONS +// SECTIONS-NOT: .00cfg + + .section ".00cfg", "dr" + .long 0x12345678 diff --git a/lld/test/ELF/ppc32-reloc-addr.s b/lld/test/ELF/ppc32-reloc-addr.s index 78865b82ccbf..9b40bce77aec 100644 --- a/lld/test/ELF/ppc32-reloc-addr.s +++ b/lld/test/ELF/ppc32-reloc-addr.s @@ -22,7 +22,7 @@ .section .R_PPC_ADDR24,"ax",@progbits ba a # CHECK-LABEL: section .R_PPC_ADDR24: -# CHECK: ba 4660 +# CHECK: ba 0x1234 .section .R_PPC_ADDR32,"a",@progbits .long a diff --git a/lldb/test/API/lang/cpp/union-static-data-members/TestCppUnionStaticMembers.py b/lldb/test/API/lang/cpp/union-static-data-members/TestCppUnionStaticMembers.py index 1988e997499b..dff23da8662a 100644 --- a/lldb/test/API/lang/cpp/union-static-data-members/TestCppUnionStaticMembers.py +++ b/lldb/test/API/lang/cpp/union-static-data-members/TestCppUnionStaticMembers.py @@ -42,7 +42,7 @@ class CppUnionStaticMembersTestCase(TestBase): name="val", value="42" )]) - @expectedFailureAll + @expectedFailureWindows def test_union_in_anon_namespace(self): """Tests that frame variable and expr work for union static data members in anonymous diff --git a/lldb/test/API/python_api/global_module_cache/Makefile b/lldb/test/API/python_api/global_module_cache/Makefile deleted file mode 100644 index 22f1051530f8..000000000000 --- a/lldb/test/API/python_api/global_module_cache/Makefile +++ /dev/null @@ -1 +0,0 @@ -include Makefile.rules diff --git a/lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py b/lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py deleted file mode 100644 index 98ebdec0404e..000000000000 --- a/lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py +++ /dev/null @@ -1,169 +0,0 @@ -""" -Test the use of the global module cache in lldb -""" - -import lldb - -from lldbsuite.test.decorators import * -from lldbsuite.test.lldbtest import * -from lldbsuite.test import lldbutil -import os -import shutil -from pathlib import Path -import time - -class GlobalModuleCacheTestCase(TestBase): - # NO_DEBUG_INFO_TESTCASE = True - - def check_counter_var(self, thread, value): - frame = thread.frames[0] - var = frame.FindVariable("counter") - self.assertTrue(var.GetError().Success(), "Got counter variable") - self.assertEqual(var.GetValueAsUnsigned(), value, "This was one-print") - - def copy_to_main(self, src, dst): - # We are relying on the source file being newer than the .o file from - # a previous build, so sleep a bit here to ensure that the touch is later. - time.sleep(2) - try: - shutil.copy(src, dst) - except: - self.fail(f"Could not copy {src} to {dst}") - Path(dst).touch() - - # The rerun tests indicate rerunning on Windows doesn't really work, so - # this one won't either. - @skipIfWindows - def test_OneTargetOneDebugger(self): - self.do_test(True, True) - - # This behaves as implemented but that behavior is not desirable. - # This test tests for the desired behavior as an expected fail. - @skipIfWindows - @expectedFailureAll - def test_TwoTargetsOneDebugger(self): - self.do_test(False, True) - - @skipIfWindows - @expectedFailureAll - def test_OneTargetTwoDebuggers(self): - self.do_test(True, False) - - def do_test(self, one_target, one_debugger): - # Make sure that if we have one target, and we run, then - # change the binary and rerun, the binary (and any .o files - # if using dwarf in .o file debugging) get removed from the - # shared module cache. They are no longer reachable. - debug_style = self.getDebugInfo() - - # Before we do anything, clear the global module cache so we don't - # see objects from other runs: - lldb.SBDebugger.MemoryPressureDetected() - - # Set up the paths for our two versions of main.c: - main_c_path = os.path.join(self.getBuildDir(), "main.c") - one_print_path = os.path.join(self.getSourceDir(), "one-print.c") - two_print_path = os.path.join(self.getSourceDir(), "two-print.c") - main_filespec = lldb.SBFileSpec(main_c_path) - - # First copy the one-print.c to main.c in the build folder and - # build our a.out from there: - self.copy_to_main(one_print_path, main_c_path) - self.build(dictionary={"C_SOURCES": main_c_path, "EXE": "a.out"}) - - (target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint( - self, "return counter;", main_filespec - ) - - # Make sure we ran the version we intended here: - self.check_counter_var(thread, 1) - process.Kill() - - # Now copy two-print.c over main.c, rebuild, and rerun: - # os.unlink(target.GetExecutable().fullpath) - self.copy_to_main(two_print_path, main_c_path) - - self.build(dictionary={"C_SOURCES": main_c_path, "EXE": "a.out"}) - error = lldb.SBError() - if one_debugger: - if one_target: - (_, process, thread, _) = lldbutil.run_to_breakpoint_do_run( - self, target, bkpt - ) - else: - (target2, process2, thread, bkpt) = lldbutil.run_to_source_breakpoint( - self, "return counter;", main_filespec - ) - else: - if one_target: - new_debugger = lldb.SBDebugger().Create() - self.old_debugger = self.dbg - self.dbg = new_debugger - def cleanupDebugger(self): - lldb.SBDebugger.Destroy(self.dbg) - self.dbg = self.old_debugger - self.old_debugger = None - - self.addTearDownHook(cleanupDebugger) - (target2, process2, thread, bkpt) = lldbutil.run_to_source_breakpoint( - self, "return counter;", main_filespec - ) - - # In two-print.c counter will be 2: - self.check_counter_var(thread, 2) - - # If we made two targets, destroy the first one, that should free up the - # unreachable Modules: - if not one_target: - target.Clear() - - num_a_dot_out_entries = 1 - # For dSYM's there will be two lines of output, one for the a.out and one - # for the dSYM. - if debug_style == "dsym": - num_a_dot_out_entries += 1 - - error = self.check_image_list_result(num_a_dot_out_entries, 1) - # Even if this fails, MemoryPressureDetected should fix this. - lldb.SBDebugger.MemoryPressureDetected() - error_after_mpd = self.check_image_list_result(num_a_dot_out_entries, 1) - fail_msg = "" - if error != "": - fail_msg = "Error before MPD: " + error - - if error_after_mpd != "": - fail_msg = fail_msg + "\nError after MPD: " + error_after_mpd - if fail_msg != "": - self.fail(fail_msg) - - def check_image_list_result(self, num_a_dot_out, num_main_dot_o): - # Check the global module list, there should only be one a.out, and if we are - # doing dwarf in .o file, there should only be one .o file. This returns - # an error string on error - rather than asserting, so you can stage this - # failing. - image_cmd_result = lldb.SBCommandReturnObject() - interp = self.dbg.GetCommandInterpreter() - interp.HandleCommand("image list -g", image_cmd_result) - if self.TraceOn(): - print(f"Expected: a.out: {num_a_dot_out} main.o: {num_main_dot_o}") - print(image_cmd_result) - - image_list_str = image_cmd_result.GetOutput() - image_list = image_list_str.splitlines() - found_a_dot_out = 0 - found_main_dot_o = 0 - - for line in image_list: - # FIXME: force this to be at the end of the string: - if "a.out" in line: - found_a_dot_out += 1 - if "main.o" in line: - found_main_dot_o += 1 - - if num_a_dot_out != found_a_dot_out: - return f"Got {found_a_dot_out} number of a.out's, expected {num_a_dot_out}" - - if found_main_dot_o > 0 and num_main_dot_o != found_main_dot_o: - return f"Got {found_main_dot_o} number of main.o's, expected {num_main_dot_o}" - - return "" diff --git a/lldb/test/API/python_api/global_module_cache/one-print.c b/lldb/test/API/python_api/global_module_cache/one-print.c deleted file mode 100644 index f008f36c2554..000000000000 --- a/lldb/test/API/python_api/global_module_cache/one-print.c +++ /dev/null @@ -1,7 +0,0 @@ -#include <stdio.h> - -int main() { - int counter = 0; - printf("I only print one time: %d.\n", counter++); - return counter; -} diff --git a/lldb/test/API/python_api/global_module_cache/two-print.c b/lldb/test/API/python_api/global_module_cache/two-print.c deleted file mode 100644 index 96f68cbed83c..000000000000 --- a/lldb/test/API/python_api/global_module_cache/two-print.c +++ /dev/null @@ -1,8 +0,0 @@ -#include <stdio.h> - -int main() { - int counter = 0; - printf("I print one time: %d.\n", counter++); - printf("I print two times: %d.\n", counter++); - return counter; -} diff --git a/lldb/unittests/SymbolFile/PDB/SymbolFilePDBTests.cpp b/lldb/unittests/SymbolFile/PDB/SymbolFilePDBTests.cpp index acd381ccad13..cdaa4fafa4c8 100644 --- a/lldb/unittests/SymbolFile/PDB/SymbolFilePDBTests.cpp +++ b/lldb/unittests/SymbolFile/PDB/SymbolFilePDBTests.cpp @@ -362,10 +362,9 @@ TEST_F(SymbolFilePDBTests, TestSimpleClassTypes) { SymbolFilePDB *symfile = static_cast<SymbolFilePDB *>(module->GetSymbolFile()); llvm::pdb::IPDBSession &session = symfile->GetPDBSession(); - llvm::DenseSet<SymbolFile *> searched_files; - TypeMap results; - symfile->FindTypes(ConstString("Class"), CompilerDeclContext(), 0, - searched_files, results); + TypeResults query_results; + symfile->FindTypes(TypeQuery("Class"), query_results); + TypeMap &results = query_results.GetTypeMap(); EXPECT_EQ(1u, results.GetSize()); lldb::TypeSP udt_type = results.GetTypeAtIndex(0); EXPECT_EQ(ConstString("Class"), udt_type->GetName()); @@ -383,8 +382,6 @@ TEST_F(SymbolFilePDBTests, TestNestedClassTypes) { SymbolFilePDB *symfile = static_cast<SymbolFilePDB *>(module->GetSymbolFile()); llvm::pdb::IPDBSession &session = symfile->GetPDBSession(); - llvm::DenseSet<SymbolFile *> searched_files; - TypeMap results; auto clang_ast_ctx_or_err = symfile->GetTypeSystemForLanguage(lldb::eLanguageTypeC_plus_plus); @@ -394,8 +391,10 @@ TEST_F(SymbolFilePDBTests, TestNestedClassTypes) { llvm::dyn_cast_or_null<TypeSystemClang>(clang_ast_ctx_or_err->get()); EXPECT_NE(nullptr, clang_ast_ctx); - symfile->FindTypes(ConstString("Class"), CompilerDeclContext(), 0, - searched_files, results); + TypeResults query_results; + symfile->FindTypes(TypeQuery("Class"), query_results); + TypeMap &results = query_results.GetTypeMap(); + EXPECT_EQ(1u, results.GetSize()); auto Class = results.GetTypeAtIndex(0); @@ -413,10 +412,12 @@ TEST_F(SymbolFilePDBTests, TestNestedClassTypes) { // compiler type for both, but `FindTypes` may return more than one type // (with the same compiler type) because the symbols have different IDs. - TypeMap more_results; auto ClassCompilerDeclCtx = CompilerDeclContext(clang_ast_ctx, ClassDeclCtx); - symfile->FindTypes(ConstString("NestedClass"), ClassCompilerDeclCtx, 0, - searched_files, more_results); + TypeResults query_results_nested; + symfile->FindTypes( + TypeQuery(ClassCompilerDeclCtx, ConstString("NestedClass")), + query_results_nested); + TypeMap &more_results = query_results_nested.GetTypeMap(); EXPECT_LE(1u, more_results.GetSize()); lldb::TypeSP udt_type = more_results.GetTypeAtIndex(0); @@ -437,9 +438,6 @@ TEST_F(SymbolFilePDBTests, TestClassInNamespace) { SymbolFilePDB *symfile = static_cast<SymbolFilePDB *>(module->GetSymbolFile()); llvm::pdb::IPDBSession &session = symfile->GetPDBSession(); - llvm::DenseSet<SymbolFile *> searched_files; - TypeMap results; - auto clang_ast_ctx_or_err = symfile->GetTypeSystemForLanguage(lldb::eLanguageTypeC_plus_plus); ASSERT_THAT_EXPECTED(clang_ast_ctx_or_err, llvm::Succeeded()); @@ -456,12 +454,14 @@ TEST_F(SymbolFilePDBTests, TestClassInNamespace) { symfile->ParseDeclsForContext(CompilerDeclContext( clang_ast_ctx, static_cast<clang::DeclContext *>(tu))); - auto ns_namespace = + auto ns_namespace_decl_ctx = symfile->FindNamespace(ConstString("NS"), CompilerDeclContext(), true); - EXPECT_TRUE(ns_namespace.IsValid()); + EXPECT_TRUE(ns_namespace_decl_ctx.IsValid()); - symfile->FindTypes(ConstString("NSClass"), ns_namespace, 0, searched_files, - results); + TypeResults query_results; + symfile->FindTypes(TypeQuery(ns_namespace_decl_ctx, ConstString("NSClass")), + query_results); + TypeMap &results = query_results.GetTypeMap(); EXPECT_EQ(1u, results.GetSize()); lldb::TypeSP udt_type = results.GetTypeAtIndex(0); @@ -482,12 +482,12 @@ TEST_F(SymbolFilePDBTests, TestEnumTypes) { SymbolFilePDB *symfile = static_cast<SymbolFilePDB *>(module->GetSymbolFile()); llvm::pdb::IPDBSession &session = symfile->GetPDBSession(); - llvm::DenseSet<SymbolFile *> searched_files; const char *EnumsToCheck[] = {"Enum", "ShortEnum"}; for (auto Enum : EnumsToCheck) { - TypeMap results; - symfile->FindTypes(ConstString(Enum), CompilerDeclContext(), 0, - searched_files, results); + + TypeResults query_results; + symfile->FindTypes(TypeQuery(Enum), query_results); + TypeMap &results = query_results.GetTypeMap(); EXPECT_EQ(1u, results.GetSize()); lldb::TypeSP enum_type = results.GetTypeAtIndex(0); EXPECT_EQ(ConstString(Enum), enum_type->GetName()); @@ -527,16 +527,15 @@ TEST_F(SymbolFilePDBTests, TestTypedefs) { SymbolFilePDB *symfile = static_cast<SymbolFilePDB *>(module->GetSymbolFile()); llvm::pdb::IPDBSession &session = symfile->GetPDBSession(); - llvm::DenseSet<SymbolFile *> searched_files; TypeMap results; const char *TypedefsToCheck[] = {"ClassTypedef", "NSClassTypedef", "FuncPointerTypedef", "VariadicFuncPointerTypedef"}; for (auto Typedef : TypedefsToCheck) { - TypeMap results; - symfile->FindTypes(ConstString(Typedef), CompilerDeclContext(), 0, - searched_files, results); + TypeResults query_results; + symfile->FindTypes(TypeQuery(Typedef), query_results); + TypeMap &results = query_results.GetTypeMap(); EXPECT_EQ(1u, results.GetSize()); lldb::TypeSP typedef_type = results.GetTypeAtIndex(0); EXPECT_EQ(ConstString(Typedef), typedef_type->GetName()); @@ -578,22 +577,24 @@ TEST_F(SymbolFilePDBTests, TestMaxMatches) { SymbolFilePDB *symfile = static_cast<SymbolFilePDB *>(module->GetSymbolFile()); - llvm::DenseSet<SymbolFile *> searched_files; - TypeMap results; - const ConstString name("ClassTypedef"); - symfile->FindTypes(name, CompilerDeclContext(), 0, searched_files, results); - // Try to limit ourselves from 1 to 10 results, otherwise we could - // be doing this thousands of times. The idea is just to make sure - // that for a variety of values, the number of limited results - // always comes out to the number we are expecting. - uint32_t num_results = results.GetSize(); - uint32_t iterations = std::min(num_results, 10u); - for (uint32_t i = 1; i <= iterations; ++i) { - TypeMap more_results; - symfile->FindTypes(name, CompilerDeclContext(), i, searched_files, - more_results); - uint32_t num_limited_results = more_results.GetSize(); - EXPECT_EQ(i, num_limited_results); + + // Make a type query object we can use for all types and for one type + TypeQuery query("ClassTypedef"); + { + // Find all types that match + TypeResults query_results; + symfile->FindTypes(query, query_results); + TypeMap &results = query_results.GetTypeMap(); + EXPECT_GT(results.GetSize(), 1u); + } + + { + // Find a single type that matches + query.SetFindOne(true); + TypeResults query_results; + symfile->FindTypes(query, query_results); + TypeMap &results = query_results.GetTypeMap(); + EXPECT_EQ(results.GetSize(), 1u); } } @@ -604,10 +605,10 @@ TEST_F(SymbolFilePDBTests, TestNullName) { SymbolFilePDB *symfile = static_cast<SymbolFilePDB *>(module->GetSymbolFile()); - llvm::DenseSet<SymbolFile *> searched_files; - TypeMap results; - symfile->FindTypes(ConstString(), CompilerDeclContext(), 0, searched_files, - results); + + TypeResults query_results; + symfile->FindTypes(TypeQuery(llvm::StringRef()), query_results); + TypeMap &results = query_results.GetTypeMap(); EXPECT_EQ(0u, results.GetSize()); } diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 7fb3d70bbeff..5fcf65104694 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -1211,10 +1211,12 @@ The AMDGPU backend supports the following LLVM IR attributes. "amdgpu-flat-work-group-size" value, the implied occupancy bounds by the workgroup size takes precedence. - "amdgpu-ieee" true/false. Specify whether the function expects the IEEE field of the + "amdgpu-ieee" true/false. GFX6-GFX11 Only + Specify whether the function expects the IEEE field of the mode register to be set on entry. Overrides the default for the calling convention. - "amdgpu-dx10-clamp" true/false. Specify whether the function expects the DX10_CLAMP field of + "amdgpu-dx10-clamp" true/false. GFX6-GFX11 Only + Specify whether the function expects the DX10_CLAMP field of the mode register to be set on entry. Overrides the default for the calling convention. @@ -4390,21 +4392,21 @@ The fields used by CP for code objects before V3 also match those specified in ``COMPUTE_PGM_RSRC3`` configuration register. See - :ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-gfx11-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-gfx12-table`. 415:384 4 bytes COMPUTE_PGM_RSRC1 Compute Shader (CS) program settings used by CP to set up ``COMPUTE_PGM_RSRC1`` configuration register. See - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. 447:416 4 bytes COMPUTE_PGM_RSRC2 Compute Shader (CS) program settings used by CP to set up ``COMPUTE_PGM_RSRC2`` configuration register. See - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. 458:448 7 bits *See separate bits below.* Enable the setup of the SGPR user data registers (see @@ -4472,8 +4474,8 @@ The fields used by CP for code objects before V3 also match those specified in .. - .. table:: compute_pgm_rsrc1 for GFX6-GFX11 - :name: amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table + .. table:: compute_pgm_rsrc1 for GFX6-GFX12 + :name: amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table ======= ======= =============================== =========================================================================== Bits Size Field Name Description @@ -4642,17 +4644,27 @@ The fields used by CP for code objects before V3 also match those specified in CP is responsible for filling in ``COMPUTE_PGM_RSRC1.PRIV``. - 21 1 bit ENABLE_DX10_CLAMP Wavefront starts execution - with DX10 clamp mode - enabled. Used by the vector - ALU to force DX10 style - treatment of NaN's (when - set, clamp NaN to zero, - otherwise pass NaN - through). + 21 1 bit ENABLE_DX10_CLAMP GFX9-GFX11 + Wavefront starts execution + with DX10 clamp mode + enabled. Used by the vector + ALU to force DX10 style + treatment of NaN's (when + set, clamp NaN to zero, + otherwise pass NaN + through). - Used by CP to set up - ``COMPUTE_PGM_RSRC1.DX10_CLAMP``. + Used by CP to set up + ``COMPUTE_PGM_RSRC1.DX10_CLAMP``. + WG_RR_EN GFX12 + If 1, wavefronts are scheduled + in a round-robin fashion with + respect to the other wavefronts + of the SIMD. Otherwise, wavefronts + are scheduled in oldest age order. + + CP is responsible for filling in + ``COMPUTE_PGM_RSRC1.WG_RR_EN``. 22 1 bit DEBUG_MODE Must be 0. Start executing wavefront @@ -4661,21 +4673,24 @@ The fields used by CP for code objects before V3 also match those specified in CP is responsible for filling in ``COMPUTE_PGM_RSRC1.DEBUG_MODE``. - 23 1 bit ENABLE_IEEE_MODE Wavefront starts execution - with IEEE mode - enabled. Floating point - opcodes that support - exception flag gathering - will quiet and propagate - signaling-NaN inputs per - IEEE 754-2008. Min_dx10 and - max_dx10 become IEEE - 754-2008 compliant due to - signaling-NaN propagation - and quieting. + 23 1 bit ENABLE_IEEE_MODE GFX9-GFX11 + Wavefront starts execution + with IEEE mode + enabled. Floating point + opcodes that support + exception flag gathering + will quiet and propagate + signaling-NaN inputs per + IEEE 754-2008. Min_dx10 and + max_dx10 become IEEE + 754-2008 compliant due to + signaling-NaN propagation + and quieting. - Used by CP to set up - ``COMPUTE_PGM_RSRC1.IEEE_MODE``. + Used by CP to set up + ``COMPUTE_PGM_RSRC1.IEEE_MODE``. + DISABLE_PERF GFX12 + Reserved. Must be 0. 24 1 bit BULKY Must be 0. Only one work-group allowed @@ -4763,8 +4778,8 @@ The fields used by CP for code objects before V3 also match those specified in .. - .. table:: compute_pgm_rsrc2 for GFX6-GFX11 - :name: amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table + .. table:: compute_pgm_rsrc2 for GFX6-GFX12 + :name: amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table ======= ======= =============================== =========================================================================== Bits Size Field Name Description @@ -4957,8 +4972,8 @@ The fields used by CP for code objects before V3 also match those specified in .. - .. table:: compute_pgm_rsrc3 for GFX10-GFX11 - :name: amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-gfx11-table + .. table:: compute_pgm_rsrc3 for GFX10-GFX12 + :name: amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-gfx12-table ======= ======= =============================== =========================================================================== Bits Size Field Name Description @@ -5437,7 +5452,7 @@ There are different methods used for initializing flat scratch: specifies *Architected flat scratch*: If ENABLE_PRIVATE_SEGMENT is enabled in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table` then the FLAT_SCRATCH + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table` then the FLAT_SCRATCH register pair will be initialized to the 64-bit address of the base of scratch backing memory being managed by SPI for the queue executing the kernel dispatch plus the value of the wave's Scratch Wavefront Offset for use as the @@ -11819,7 +11834,7 @@ Wavefronts are executed in native mode with in-order reporting of loads and sample instructions. In this mode vmcnt reports completion of load, atomic with return and sample instructions in order, and the vscnt reports the completion of store and atomic without return in order. See ``MEM_ORDERED`` field in -:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. +:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. Wavefronts can be executed in WGP or CU wavefront execution mode: @@ -11835,7 +11850,7 @@ Wavefronts can be executed in WGP or CU wavefront execution mode: work-group synchronization. See ``WGP_MODE`` field in -:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table` and +:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table` and :ref:`amdgpu-target-features`. The code sequences used to implement the memory model for GFX10-GFX11 are defined in @@ -15375,123 +15390,125 @@ terminated by an ``.end_amdhsa_kernel`` directive. ======================================================== =================== ============ =================== Directive Default Supported On Description ======================================================== =================== ============ =================== - ``.amdhsa_group_segment_fixed_size`` 0 GFX6-GFX11 Controls GROUP_SEGMENT_FIXED_SIZE in + ``.amdhsa_group_segment_fixed_size`` 0 GFX6-GFX12 Controls GROUP_SEGMENT_FIXED_SIZE in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_private_segment_fixed_size`` 0 GFX6-GFX11 Controls PRIVATE_SEGMENT_FIXED_SIZE in + ``.amdhsa_private_segment_fixed_size`` 0 GFX6-GFX12 Controls PRIVATE_SEGMENT_FIXED_SIZE in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_kernarg_size`` 0 GFX6-GFX11 Controls KERNARG_SIZE in + ``.amdhsa_kernarg_size`` 0 GFX6-GFX12 Controls KERNARG_SIZE in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_user_sgpr_count`` 0 GFX6-GFX11 Controls USER_SGPR_COUNT in COMPUTE_PGM_RSRC2 - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table` + ``.amdhsa_user_sgpr_count`` 0 GFX6-GFX12 Controls USER_SGPR_COUNT in COMPUTE_PGM_RSRC2 + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table` ``.amdhsa_user_sgpr_private_segment_buffer`` 0 GFX6-GFX10 Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in (except :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. GFX940) - ``.amdhsa_user_sgpr_dispatch_ptr`` 0 GFX6-GFX11 Controls ENABLE_SGPR_DISPATCH_PTR in + ``.amdhsa_user_sgpr_dispatch_ptr`` 0 GFX6-GFX12 Controls ENABLE_SGPR_DISPATCH_PTR in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_user_sgpr_queue_ptr`` 0 GFX6-GFX11 Controls ENABLE_SGPR_QUEUE_PTR in + ``.amdhsa_user_sgpr_queue_ptr`` 0 GFX6-GFX12 Controls ENABLE_SGPR_QUEUE_PTR in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_user_sgpr_kernarg_segment_ptr`` 0 GFX6-GFX11 Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in + ``.amdhsa_user_sgpr_kernarg_segment_ptr`` 0 GFX6-GFX12 Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_user_sgpr_dispatch_id`` 0 GFX6-GFX11 Controls ENABLE_SGPR_DISPATCH_ID in + ``.amdhsa_user_sgpr_dispatch_id`` 0 GFX6-GFX12 Controls ENABLE_SGPR_DISPATCH_ID in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. ``.amdhsa_user_sgpr_flat_scratch_init`` 0 GFX6-GFX10 Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in (except :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. GFX940) - ``.amdhsa_user_sgpr_private_segment_size`` 0 GFX6-GFX11 Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in + ``.amdhsa_user_sgpr_private_segment_size`` 0 GFX6-GFX12 Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. - ``.amdhsa_wavefront_size32`` Target GFX10-GFX11 Controls ENABLE_WAVEFRONT_SIZE32 in + ``.amdhsa_wavefront_size32`` Target GFX10-GFX12 Controls ENABLE_WAVEFRONT_SIZE32 in Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. Specific (wavefrontsize64) - ``.amdhsa_uses_dynamic_stack`` 0 GFX6-GFX11 Controls USES_DYNAMIC_STACK in + ``.amdhsa_uses_dynamic_stack`` 0 GFX6-GFX12 Controls USES_DYNAMIC_STACK in :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. ``.amdhsa_system_sgpr_private_segment_wavefront_offset`` 0 GFX6-GFX10 Controls ENABLE_PRIVATE_SEGMENT in - (except :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. + (except :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. GFX940) ``.amdhsa_enable_private_segment`` 0 GFX940, Controls ENABLE_PRIVATE_SEGMENT in - GFX11 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. - ``.amdhsa_system_sgpr_workgroup_id_x`` 1 GFX6-GFX11 Controls ENABLE_SGPR_WORKGROUP_ID_X in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. - ``.amdhsa_system_sgpr_workgroup_id_y`` 0 GFX6-GFX11 Controls ENABLE_SGPR_WORKGROUP_ID_Y in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. - ``.amdhsa_system_sgpr_workgroup_id_z`` 0 GFX6-GFX11 Controls ENABLE_SGPR_WORKGROUP_ID_Z in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. - ``.amdhsa_system_sgpr_workgroup_info`` 0 GFX6-GFX11 Controls ENABLE_SGPR_WORKGROUP_INFO in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. - ``.amdhsa_system_vgpr_workitem_id`` 0 GFX6-GFX11 Controls ENABLE_VGPR_WORKITEM_ID in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. + GFX11-GFX12 :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. + ``.amdhsa_system_sgpr_workgroup_id_x`` 1 GFX6-GFX12 Controls ENABLE_SGPR_WORKGROUP_ID_X in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. + ``.amdhsa_system_sgpr_workgroup_id_y`` 0 GFX6-GFX12 Controls ENABLE_SGPR_WORKGROUP_ID_Y in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. + ``.amdhsa_system_sgpr_workgroup_id_z`` 0 GFX6-GFX12 Controls ENABLE_SGPR_WORKGROUP_ID_Z in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. + ``.amdhsa_system_sgpr_workgroup_info`` 0 GFX6-GFX12 Controls ENABLE_SGPR_WORKGROUP_INFO in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. + ``.amdhsa_system_vgpr_workitem_id`` 0 GFX6-GFX12 Controls ENABLE_VGPR_WORKITEM_ID in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. Possible values are defined in :ref:`amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table`. - ``.amdhsa_next_free_vgpr`` Required GFX6-GFX11 Maximum VGPR number explicitly referenced, plus one. + ``.amdhsa_next_free_vgpr`` Required GFX6-GFX12 Maximum VGPR number explicitly referenced, plus one. Used to calculate GRANULATED_WORKITEM_VGPR_COUNT in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. - ``.amdhsa_next_free_sgpr`` Required GFX6-GFX11 Maximum SGPR number explicitly referenced, plus one. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. + ``.amdhsa_next_free_sgpr`` Required GFX6-GFX12 Maximum SGPR number explicitly referenced, plus one. Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. ``.amdhsa_accum_offset`` Required GFX90A, Offset of a first AccVGPR in the unified register file. GFX940 Used to calculate ACCUM_OFFSET in :ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx90a-table`. - ``.amdhsa_reserve_vcc`` 1 GFX6-GFX11 Whether the kernel may use the special VCC SGPR. + ``.amdhsa_reserve_vcc`` 1 GFX6-GFX12 Whether the kernel may use the special VCC SGPR. Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. ``.amdhsa_reserve_flat_scratch`` 1 GFX7-GFX10 Whether the kernel may use flat instructions to access (except scratch memory. Used to calculate GFX940) GRANULATED_WAVEFRONT_SGPR_COUNT in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. ``.amdhsa_reserve_xnack_mask`` Target GFX8-GFX10 Whether the kernel may trigger XNACK replay. Feature Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in - Specific :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. + Specific :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. (xnack) - ``.amdhsa_float_round_mode_32`` 0 GFX6-GFX11 Controls FLOAT_ROUND_MODE_32 in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. + ``.amdhsa_float_round_mode_32`` 0 GFX6-GFX12 Controls FLOAT_ROUND_MODE_32 in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. Possible values are defined in :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`. - ``.amdhsa_float_round_mode_16_64`` 0 GFX6-GFX11 Controls FLOAT_ROUND_MODE_16_64 in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. + ``.amdhsa_float_round_mode_16_64`` 0 GFX6-GFX12 Controls FLOAT_ROUND_MODE_16_64 in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. Possible values are defined in :ref:`amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table`. - ``.amdhsa_float_denorm_mode_32`` 0 GFX6-GFX11 Controls FLOAT_DENORM_MODE_32 in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. + ``.amdhsa_float_denorm_mode_32`` 0 GFX6-GFX12 Controls FLOAT_DENORM_MODE_32 in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. Possible values are defined in :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`. - ``.amdhsa_float_denorm_mode_16_64`` 3 GFX6-GFX11 Controls FLOAT_DENORM_MODE_16_64 in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. + ``.amdhsa_float_denorm_mode_16_64`` 3 GFX6-GFX12 Controls FLOAT_DENORM_MODE_16_64 in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. Possible values are defined in :ref:`amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table`. ``.amdhsa_dx10_clamp`` 1 GFX6-GFX11 Controls ENABLE_DX10_CLAMP in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. ``.amdhsa_ieee_mode`` 1 GFX6-GFX11 Controls ENABLE_IEEE_MODE in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. - ``.amdhsa_fp16_overflow`` 0 GFX9-GFX11 Controls FP16_OVFL in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. + ``.amdhsa_round_robin_scheduling`` 0 GFX12 Controls ENABLE_WG_RR_EN in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. + ``.amdhsa_fp16_overflow`` 0 GFX9-GFX12 Controls FP16_OVFL in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. ``.amdhsa_tg_split`` Target GFX90A, Controls TG_SPLIT in Feature GFX940, :ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx90a-table`. - Specific GFX11 + Specific GFX11-GFX12 (tgsplit) - ``.amdhsa_workgroup_processor_mode`` Target GFX10-GFX11 Controls ENABLE_WGP_MODE in + ``.amdhsa_workgroup_processor_mode`` Target GFX10-GFX12 Controls ENABLE_WGP_MODE in Feature :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. Specific (cumode) - ``.amdhsa_memory_ordered`` 1 GFX10-GFX11 Controls MEM_ORDERED in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. - ``.amdhsa_forward_progress`` 0 GFX10-GFX11 Controls FWD_PROGRESS in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx11-table`. + ``.amdhsa_memory_ordered`` 1 GFX10-GFX12 Controls MEM_ORDERED in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. + ``.amdhsa_forward_progress`` 0 GFX10-GFX12 Controls FWD_PROGRESS in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx12-table`. ``.amdhsa_shared_vgpr_count`` 0 GFX10-GFX11 Controls SHARED_VGPR_COUNT in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-gfx11-table`. - ``.amdhsa_exception_fp_ieee_invalid_op`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. - ``.amdhsa_exception_fp_denorm_src`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_FP_DENORMAL_SOURCE in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. - ``.amdhsa_exception_fp_ieee_div_zero`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. - ``.amdhsa_exception_fp_ieee_overflow`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. - ``.amdhsa_exception_fp_ieee_underflow`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. - ``.amdhsa_exception_fp_ieee_inexact`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_IEEE_754_FP_INEXACT in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. - ``.amdhsa_exception_int_div_zero`` 0 GFX6-GFX11 Controls ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO in - :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx11-table`. + :ref:`amdgpu-amdhsa-compute_pgm_rsrc3-gfx10-gfx12-table`. + ``.amdhsa_exception_fp_ieee_invalid_op`` 0 GFX6-GFX12 Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. + ``.amdhsa_exception_fp_denorm_src`` 0 GFX6-GFX12 Controls ENABLE_EXCEPTION_FP_DENORMAL_SOURCE in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. + ``.amdhsa_exception_fp_ieee_div_zero`` 0 GFX6-GFX12 Controls ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. + ``.amdhsa_exception_fp_ieee_overflow`` 0 GFX6-GFX12 Controls ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. + ``.amdhsa_exception_fp_ieee_underflow`` 0 GFX6-GFX12 Controls ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. + ``.amdhsa_exception_fp_ieee_inexact`` 0 GFX6-GFX12 Controls ENABLE_EXCEPTION_IEEE_754_FP_INEXACT in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. + ``.amdhsa_exception_int_div_zero`` 0 GFX6-GFX12 Controls ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO in + :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`. ``.amdhsa_user_sgpr_kernarg_preload_length`` 0 GFX90A, Controls KERNARG_PRELOAD_SPEC_LENGTH in GFX940 :ref:`amdgpu-amdhsa-kernel-descriptor-v3-table`. ``.amdhsa_user_sgpr_kernarg_preload_offset`` 0 GFX90A, Controls KERNARG_PRELOAD_SPEC_OFFSET in diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 65dd0d83448e..842ebf453059 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -197,7 +197,7 @@ The primary goal of experimental support is to assist in the process of ratifica LLVM implements assembler support for the `0.8.0 draft specification <https://github.com/riscv/riscv-bfloat16/releases/tag/20230629>`_. ``experimental-zicfilp`` - LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.2.0>`__. + LLVM implements the `0.4 draft specification <https://github.com/riscv/riscv-cfi/releases/tag/v0.4.0>`__. ``experimental-zicond`` LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1>`__. diff --git a/llvm/docs/TableGen/index.rst b/llvm/docs/TableGen/index.rst index 00569274be3c..e916c152f5a4 100644 --- a/llvm/docs/TableGen/index.rst +++ b/llvm/docs/TableGen/index.rst @@ -283,6 +283,13 @@ See :doc:`TableGen BackEnds <./BackEnds>` for a list of available backends, and see the :doc:`TableGen Backend Developer's Guide <./BackGuide>` for information on how to write and debug a new backend. +Tools and Resources +=================== + +In addition to this documentation, a list of tools and resources for TableGen +can be found in TableGen's +`README <https://github.com/llvm/llvm-project/blob/main/llvm/utils/TableGen/README.md>`_. + TableGen Deficiencies ===================== diff --git a/llvm/include/llvm/Analysis/AliasSetTracker.h b/llvm/include/llvm/Analysis/AliasSetTracker.h index e485e1ff2f4c..4a952ccae7a0 100644 --- a/llvm/include/llvm/Analysis/AliasSetTracker.h +++ b/llvm/include/llvm/Analysis/AliasSetTracker.h @@ -330,7 +330,7 @@ public: /// These methods return true if inserting the instruction resulted in the /// addition of a new alias set (i.e., the pointer did not alias anything). /// - void add(Value *Ptr, LocationSize Size, const AAMDNodes &AAInfo); // Add a loc + void add(const MemoryLocation &Loc); void add(LoadInst *LI); void add(StoreInst *SI); void add(VAArgInst *VAAI); diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index fb6f3287e3d2..f5114fa40c70 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -1002,6 +1002,16 @@ public: /// more beneficial constant hoisting is). InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const; + + /// It can be advantageous to detach complex constants from their uses to make + /// their generation cheaper. This hook allows targets to report when such + /// transformations might negatively effect the code generation of the + /// underlying operation. The motivating example is divides whereby hoisting + /// constants prevents the code generator's ability to transform them into + /// combinations of simpler operations. + bool preferToKeepConstantsAttached(const Instruction &Inst, + const Function &Fn) const; + /// @} /// \name Vector Target Information @@ -1873,6 +1883,8 @@ public: virtual InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) = 0; + virtual bool preferToKeepConstantsAttached(const Instruction &Inst, + const Function &Fn) const = 0; virtual unsigned getNumberOfRegisters(unsigned ClassID) const = 0; virtual unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const = 0; @@ -2430,6 +2442,10 @@ public: TargetCostKind CostKind) override { return Impl.getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind); } + bool preferToKeepConstantsAttached(const Instruction &Inst, + const Function &Fn) const override { + return Impl.preferToKeepConstantsAttached(Inst, Fn); + } unsigned getNumberOfRegisters(unsigned ClassID) const override { return Impl.getNumberOfRegisters(ClassID); } diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index 5b612fd81306..1d8f523e9792 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -427,6 +427,11 @@ public: return TTI::TCC_Free; } + bool preferToKeepConstantsAttached(const Instruction &Inst, + const Function &Fn) const { + return false; + } + unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; } unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const { @@ -709,6 +714,7 @@ public: case Intrinsic::coro_subfn_addr: case Intrinsic::threadlocal_address: case Intrinsic::experimental_widenable_condition: + case Intrinsic::ssa_copy: // These intrinsics don't actually represent code after lowering. return 0; } diff --git a/llvm/include/llvm/BinaryFormat/ELF.h b/llvm/include/llvm/BinaryFormat/ELF.h index 40c795410f95..da38f6ef064f 100644 --- a/llvm/include/llvm/BinaryFormat/ELF.h +++ b/llvm/include/llvm/BinaryFormat/ELF.h @@ -1693,6 +1693,7 @@ enum : unsigned { enum : unsigned { GNU_PROPERTY_AARCH64_FEATURE_1_BTI = 1 << 0, GNU_PROPERTY_AARCH64_FEATURE_1_PAC = 1 << 1, + GNU_PROPERTY_AARCH64_FEATURE_1_GCS = 1 << 2, }; // x86 processor feature bits. diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index e05ce2890a08..5e7bdcdf72a4 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -545,6 +545,25 @@ public: return TargetTransformInfo::TCC_Expensive; } + bool preferToKeepConstantsAttached(const Instruction &Inst, + const Function &Fn) const { + switch (Inst.getOpcode()) { + default: + break; + case Instruction::SDiv: + case Instruction::SRem: + case Instruction::UDiv: + case Instruction::URem: { + if (!isa<ConstantInt>(Inst.getOperand(1))) + return false; + EVT VT = getTLI()->getValueType(DL, Inst.getType()); + return !getTLI()->isIntDivCheap(VT, Fn.getAttributes()); + } + }; + + return false; + } + unsigned getInliningThresholdMultiplier() const { return 1; } unsigned adjustInliningThreshold(const CallBase *CB) { return 0; } unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const { diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h index 2a8aa7b158ed..3d8646291bb0 100644 --- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h +++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h @@ -25,7 +25,10 @@ #include "llvm/Analysis/TypeBasedAliasAnalysis.h" #include "llvm/CodeGen/CallBrPrepare.h" #include "llvm/CodeGen/DwarfEHPrepare.h" +#include "llvm/CodeGen/ExpandMemCmp.h" #include "llvm/CodeGen/ExpandReductions.h" +#include "llvm/CodeGen/GCMetadata.h" +#include "llvm/CodeGen/IndirectBrExpand.h" #include "llvm/CodeGen/InterleavedAccess.h" #include "llvm/CodeGen/InterleavedLoadCombine.h" #include "llvm/CodeGen/JMCInstrumenter.h" @@ -626,7 +629,7 @@ void CodeGenPassBuilder<Derived>::addIRPasses(AddIRPass &addPass) const { // target lowering hook. if (!Opt.DisableMergeICmps) addPass(MergeICmpsPass()); - addPass(ExpandMemCmpPass()); + addPass(ExpandMemCmpPass(&TM)); } // Run GC lowering passes for builtin collectors diff --git a/llvm/include/llvm/CodeGen/ExpandMemCmp.h b/llvm/include/llvm/CodeGen/ExpandMemCmp.h new file mode 100644 index 000000000000..94a877854f32 --- /dev/null +++ b/llvm/include/llvm/CodeGen/ExpandMemCmp.h @@ -0,0 +1,29 @@ +//===--- ExpandMemCmp.h - Expand memcmp() to load/stores --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_EXPANDMEMCMP_H +#define LLVM_CODEGEN_EXPANDMEMCMP_H + +#include "llvm/IR/PassManager.h" + +namespace llvm { + +class TargetMachine; + +class ExpandMemCmpPass : public PassInfoMixin<ExpandMemCmpPass> { + const TargetMachine *TM; + +public: + explicit ExpandMemCmpPass(const TargetMachine *TM_) : TM(TM_) {} + + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + +} // namespace llvm + +#endif // LLVM_CODEGEN_EXPANDMEMCMP_H diff --git a/llvm/include/llvm/CodeGen/GCMetadata.h b/llvm/include/llvm/CodeGen/GCMetadata.h index 334c5c23b8fa..9e4e8342ea29 100644 --- a/llvm/include/llvm/CodeGen/GCMetadata.h +++ b/llvm/include/llvm/CodeGen/GCMetadata.h @@ -38,6 +38,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/IR/DebugLoc.h" #include "llvm/IR/GCStrategy.h" +#include "llvm/IR/PassManager.h" #include "llvm/Pass.h" #include <algorithm> #include <cstddef> @@ -101,6 +102,10 @@ public: GCFunctionInfo(const Function &F, GCStrategy &S); ~GCFunctionInfo(); + /// Handle invalidation explicitly. + bool invalidate(Function &F, const PreservedAnalyses &PA, + FunctionAnalysisManager::Invalidator &Inv); + /// getFunction - Return the function to which this metadata applies. const Function &getFunction() const { return F; } @@ -146,6 +151,41 @@ public: size_t live_size(const iterator &p) const { return roots_size(); } }; +struct GCStrategyMap { + StringMap<std::unique_ptr<GCStrategy>> StrategyMap; + + GCStrategyMap() = default; + GCStrategyMap(GCStrategyMap &&) = default; + + /// Handle invalidation explicitly. + bool invalidate(Module &M, const PreservedAnalyses &PA, + ModuleAnalysisManager::Invalidator &Inv); +}; + +/// An analysis pass which caches information about the entire Module. +/// Records a cache of the 'active' gc strategy objects for the current Module. +class CollectorMetadataAnalysis + : public AnalysisInfoMixin<CollectorMetadataAnalysis> { + friend struct AnalysisInfoMixin<CollectorMetadataAnalysis>; + static AnalysisKey Key; + +public: + using Result = GCStrategyMap; + Result run(Module &M, ModuleAnalysisManager &MAM); +}; + +/// An analysis pass which caches information about the Function. +/// Records the function level information used by GCRoots. +/// This pass depends on `CollectorMetadataAnalysis`. +class GCFunctionAnalysis : public AnalysisInfoMixin<GCFunctionAnalysis> { + friend struct AnalysisInfoMixin<GCFunctionAnalysis>; + static AnalysisKey Key; + +public: + using Result = GCFunctionInfo; + Result run(Function &F, FunctionAnalysisManager &FAM); +}; + /// An analysis pass which caches information about the entire Module. /// Records both the function level information used by GCRoots and a /// cache of the 'active' gc strategy objects for the current Module. diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h index f5d9f5f40881..73308925e914 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h @@ -54,10 +54,30 @@ enum { GICXXCustomAction_Invalid = 0, }; +/// The MatchTable is encoded as an array of bytes. +/// Thus, opcodes are expected to be <255. +/// +/// Operands can be variable-sized, their size is always after their name +/// in the docs, e.g. "Foo(4)" means that "Foo" takes 4 entries in the table, +/// so 4 bytes. "Foo()" +/// +/// As a general rule of thumb: +/// - Instruction & Operand IDs are ULEB128 +/// - LLT IDs are 1 byte +/// - Predicates and target opcodes, register and register class IDs are 2 +/// bytes. +/// - Indexes into the table are 4 bytes. +/// - Inline constants are 8 bytes +/// +/// Design notes: +/// - Inst/Op IDs have to be LEB128 because some targets generate +/// extremely long patterns which need more than 255 temporaries. +/// We could just use 2 bytes everytime, but then some targets like +/// X86/AMDGPU that have no need for it will pay the price all the time. enum { /// Begin a try-block to attempt a match and jump to OnFail if it is /// unsuccessful. - /// - OnFail - The MatchTable entry at which to resume if the match fails. + /// - OnFail(4) - The MatchTable entry at which to resume if the match fails. /// /// FIXME: This ought to take an argument indicating the number of try-blocks /// to exit on failure. It's usually one but the last match attempt of @@ -68,100 +88,103 @@ enum { GIM_Try, /// Switch over the opcode on the specified instruction - /// - InsnID - Instruction ID - /// - LowerBound - numerically minimum opcode supported - /// - UpperBound - numerically maximum + 1 opcode supported - /// - Default - failure jump target - /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets + /// - InsnID(ULEB128) - Instruction ID + /// - LowerBound(2) - numerically minimum opcode supported + /// - UpperBound(2) - numerically maximum + 1 opcode supported + /// - Default(4) - failure jump target + /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets GIM_SwitchOpcode, /// Switch over the LLT on the specified instruction operand - /// - InsnID - Instruction ID - /// - OpIdx - Operand index - /// - LowerBound - numerically minimum Type ID supported - /// - UpperBound - numerically maximum + 1 Type ID supported - /// - Default - failure jump target - /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - LowerBound(2) - numerically minimum Type ID supported + /// - UpperBound(2) - numerically maximum + 1 Type ID supported + /// - Default(4) - failure jump target + /// - JumpTable(4)... - (UpperBound - LowerBound) (at least 2) jump targets GIM_SwitchType, /// Record the specified instruction. /// The IgnoreCopies variant ignores COPY instructions. - /// - NewInsnID - Instruction ID to define - /// - InsnID - Instruction ID - /// - OpIdx - Operand index + /// - NewInsnID(ULEB128) - Instruction ID to define + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index GIM_RecordInsn, GIM_RecordInsnIgnoreCopies, /// Check the feature bits - /// - Expected features + /// Feature(2) - Expected features GIM_CheckFeatures, /// Check the opcode on the specified instruction - /// - InsnID - Instruction ID - /// - Expected opcode + /// - InsnID(ULEB128) - Instruction ID + /// - Opc(2) - Expected opcode GIM_CheckOpcode, /// Check the opcode on the specified instruction, checking 2 acceptable /// alternatives. - /// - InsnID - Instruction ID - /// - Expected opcode - /// - Alternative expected opcode + /// - InsnID(ULEB128) - Instruction ID + /// - Opc(2) - Expected opcode + /// - Opc(2) - Alternative expected opcode GIM_CheckOpcodeIsEither, /// Check the instruction has the right number of operands - /// - InsnID - Instruction ID - /// - Expected number of operands + /// - InsnID(ULEB128) - Instruction ID + /// - Ops(ULEB128) - Expected number of operands GIM_CheckNumOperands, + /// Check an immediate predicate on the specified instruction - /// - InsnID - Instruction ID - /// - The predicate to test + /// - InsnID(ULEB128) - Instruction ID + /// - Pred(2) - The predicate to test GIM_CheckI64ImmPredicate, /// Check an immediate predicate on the specified instruction via an APInt. - /// - InsnID - Instruction ID - /// - The predicate to test + /// - InsnID(ULEB128) - Instruction ID + /// - Pred(2) - The predicate to test GIM_CheckAPIntImmPredicate, /// Check a floating point immediate predicate on the specified instruction. - /// - InsnID - Instruction ID - /// - The predicate to test + /// - InsnID(ULEB128) - Instruction ID + /// - Pred(2) - The predicate to test GIM_CheckAPFloatImmPredicate, /// Check an immediate predicate on the specified instruction - /// - InsnID - Instruction ID - /// - OpIdx - Operand index - /// - The predicate to test + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - Pred(2) - The predicate to test GIM_CheckImmOperandPredicate, + /// Check a memory operation has the specified atomic ordering. - /// - InsnID - Instruction ID - /// - Ordering - The AtomicOrdering value + /// - InsnID(ULEB128) - Instruction ID + /// - Ordering(ULEB128) - The AtomicOrdering value GIM_CheckAtomicOrdering, GIM_CheckAtomicOrderingOrStrongerThan, GIM_CheckAtomicOrderingWeakerThan, + /// Check the size of the memory access for the given machine memory operand. - /// - InsnID - Instruction ID - /// - MMOIdx - MMO index - /// - Size - The size in bytes of the memory access + /// - InsnID(ULEB128) - Instruction ID + /// - MMOIdx(ULEB128) - MMO index + /// - Size(4) - The size in bytes of the memory access GIM_CheckMemorySizeEqualTo, /// Check the address space of the memory access for the given machine memory /// operand. - /// - InsnID - Instruction ID - /// - MMOIdx - MMO index - /// - NumAddrSpace - Number of valid address spaces - /// - AddrSpaceN - An allowed space of the memory access + /// - InsnID(ULEB128) - Instruction ID + /// - MMOIdx(ULEB128) - MMO index + /// - NumAddrSpace(ULEB128) - Number of valid address spaces + /// - AddrSpaceN(ULEB128) - An allowed space of the memory access /// - AddrSpaceN+1 ... GIM_CheckMemoryAddressSpace, /// Check the minimum alignment of the memory access for the given machine /// memory operand. - /// - InsnID - Instruction ID - /// - MMOIdx - MMO index - /// - MinAlign - Minimum acceptable alignment + /// - InsnID(ULEB128) - Instruction ID + /// - MMOIdx(ULEB128) - MMO index + /// - MinAlign(ULEB128) - Minimum acceptable alignment GIM_CheckMemoryAlignment, /// Check the size of the memory access for the given machine memory operand /// against the size of an operand. - /// - InsnID - Instruction ID - /// - MMOIdx - MMO index - /// - OpIdx - The operand index to compare the MMO against + /// - InsnID(ULEB128) - Instruction ID + /// - MMOIdx(ULEB128) - MMO index + /// - OpIdx(ULEB128) - The operand index to compare the MMO against GIM_CheckMemorySizeEqualToLLT, GIM_CheckMemorySizeLessThanLLT, GIM_CheckMemorySizeGreaterThanLLT, @@ -170,106 +193,117 @@ enum { /// constant. This is valid for both G_BUILD_VECTOR as well as /// G_BUILD_VECTOR_TRUNC. For AllOnes refers to individual bits, so a -1 /// element. - /// - InsnID - Instruction ID + /// - InsnID(ULEB128) - Instruction ID GIM_CheckIsBuildVectorAllOnes, GIM_CheckIsBuildVectorAllZeros, /// Check a trivial predicate which takes no arguments. /// This can be used by executors to implement custom flags that don't fit in /// target features. + /// - Pred(2) - Predicate ID to check. GIM_CheckSimplePredicate, /// Check a generic C++ instruction predicate - /// - InsnID - Instruction ID - /// - PredicateID - The ID of the predicate function to call + /// - InsnID(ULEB128) - Instruction ID + /// - PredicateID(2) - The ID of the predicate function to call GIM_CheckCxxInsnPredicate, /// Check if there's no use of the first result. - /// - InsnID - Instruction ID + /// - InsnID(ULEB128) - Instruction ID GIM_CheckHasNoUse, /// Check the type for the specified operand - /// - InsnID - Instruction ID - /// - OpIdx - Operand index - /// - Expected type + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - Ty(1) - Expected type GIM_CheckType, + /// Check the type of a pointer to any address space. - /// - InsnID - Instruction ID - /// - OpIdx - Operand index - /// - SizeInBits - The size of the pointer value in bits. + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - SizeInBits(ULEB128) - The size of the pointer value in bits. GIM_CheckPointerToAny, + /// Check the register bank for the specified operand - /// - InsnID - Instruction ID - /// - OpIdx - Operand index - /// - Expected register bank (specified as a register class) + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - RC(2) - Expected register bank (specified as a register class) GIM_CheckRegBankForClass, /// Check the operand matches a complex predicate - /// - InsnID - Instruction ID - /// - OpIdx - Operand index - /// - RendererID - The renderer to hold the result - /// - Complex predicate ID + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - RendererID(2) - The renderer to hold the result + /// - Pred(2) - Complex predicate ID GIM_CheckComplexPattern, /// Check the operand is a specific integer - /// - InsnID - Instruction ID - /// - OpIdx - Operand index - /// - Expected integer + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - Val(8) Expected integer GIM_CheckConstantInt, + + /// Check the operand is a specific 8-bit signed integer + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - Val(1) Expected integer + GIM_CheckConstantInt8, + /// Check the operand is a specific literal integer (i.e. MO.isImm() or /// MO.isCImm() is true). - /// - InsnID - Instruction ID - /// - OpIdx - Operand index - /// - Expected integer + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - Val(8) - Expected integer GIM_CheckLiteralInt, + /// Check the operand is a specific intrinsic ID - /// - InsnID - Instruction ID - /// - OpIdx - Operand index - /// - Expected Intrinsic ID + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - IID(2) - Expected Intrinsic ID GIM_CheckIntrinsicID, /// Check the operand is a specific predicate - /// - InsnID - Instruction ID - /// - OpIdx - Operand index - /// - Expected predicate + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - Pred(2) - Expected predicate GIM_CheckCmpPredicate, /// Check the specified operand is an MBB - /// - InsnID - Instruction ID - /// - OpIdx - Operand index + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index GIM_CheckIsMBB, /// Check the specified operand is an Imm - /// - InsnID - Instruction ID - /// - OpIdx - Operand index + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index GIM_CheckIsImm, /// Check if the specified operand is safe to fold into the current /// instruction. - /// - InsnID - Instruction ID + /// - InsnID(ULEB128) - Instruction ID GIM_CheckIsSafeToFold, /// Check the specified operands are identical. /// The IgnoreCopies variant looks through COPY instructions before /// comparing the operands. - /// - InsnID - Instruction ID - /// - OpIdx - Operand index - /// - OtherInsnID - Other instruction ID - /// - OtherOpIdx - Other operand index + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - OtherInsnID(ULEB128) - Other instruction ID + /// - OtherOpIdx(ULEB128) - Other operand index GIM_CheckIsSameOperand, GIM_CheckIsSameOperandIgnoreCopies, /// Check we can replace all uses of a register with another. - /// - OldInsnID - /// - OldOpIdx - /// - NewInsnID - /// - NewOpIdx + /// - OldInsnID(ULEB128) + /// - OldOpIdx(ULEB128) + /// - NewInsnID(ULEB128) + /// - NewOpIdx(ULEB128) GIM_CheckCanReplaceReg, /// Check that a matched instruction has, or doesn't have a MIFlag. /// - /// - InsnID - Instruction to check. - /// - Flag(s) - (can be one or more flags OR'd together) + /// - InsnID(ULEB128) - Instruction to check. + /// - Flags(4) - (can be one or more flags OR'd together) GIM_MIFlags, GIM_MIFlagsNot, @@ -277,15 +311,15 @@ enum { /// named operands that will be recorded in RecordedOperands. Names of these /// operands are referenced in predicate argument list. Emitter determines /// StoreIdx(corresponds to the order in which names appear in argument list). - /// - InsnID - Instruction ID - /// - OpIdx - Operand index - /// - StoreIdx - Store location in RecordedOperands. + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - StoreIdx(ULEB128) - Store location in RecordedOperands. GIM_RecordNamedOperand, /// Records an operand's register type into the set of temporary types. - /// - InsnID - Instruction ID - /// - OpIdx - Operand index - /// - TempTypeIdx - Temp Type Index, always negative. + /// - InsnID(ULEB128) - Instruction ID + /// - OpIdx(ULEB128) - Operand index + /// - TempTypeIdx(1) - Temp Type Index, always negative. GIM_RecordRegType, /// Fail the current try-block, or completely fail to match if there is no @@ -295,121 +329,133 @@ enum { //=== Renderers === /// Mutate an instruction - /// - NewInsnID - Instruction ID to define - /// - OldInsnID - Instruction ID to mutate - /// - NewOpcode - The new opcode to use + /// - NewInsnID(ULEB128) - Instruction ID to define + /// - OldInsnID(ULEB128) - Instruction ID to mutate + /// - NewOpcode(2) - The new opcode to use GIR_MutateOpcode, /// Build a new instruction - /// - InsnID - Instruction ID to define - /// - Opcode - The new opcode to use + /// - InsnID(ULEB128) - Instruction ID to define + /// - Opcode(2) - The new opcode to use GIR_BuildMI, /// Builds a constant and stores its result in a TempReg. - /// - TempRegID - Temp Register to define. - /// - Imm - The immediate to add + /// - TempRegID(ULEB128) - Temp Register to define. + /// - Imm(8) - The immediate to add GIR_BuildConstant, /// Copy an operand to the specified instruction - /// - NewInsnID - Instruction ID to modify - /// - OldInsnID - Instruction ID to copy from - /// - OpIdx - The operand to copy + /// - NewInsnID(ULEB128) - Instruction ID to modify + /// - OldInsnID(ULEB128) - Instruction ID to copy from + /// - OpIdx(ULEB128) - The operand to copy GIR_Copy, /// Copy an operand to the specified instruction or add a zero register if the /// operand is a zero immediate. - /// - NewInsnID - Instruction ID to modify - /// - OldInsnID - Instruction ID to copy from - /// - OpIdx - The operand to copy - /// - ZeroReg - The zero register to use + /// - NewInsnID(ULEB128) - Instruction ID to modify + /// - OldInsnID(ULEB128) - Instruction ID to copy from + /// - OpIdx(ULEB128) - The operand to copy + /// - ZeroReg(2) - The zero register to use GIR_CopyOrAddZeroReg, /// Copy an operand to the specified instruction - /// - NewInsnID - Instruction ID to modify - /// - OldInsnID - Instruction ID to copy from - /// - OpIdx - The operand to copy - /// - SubRegIdx - The subregister to copy + /// - NewInsnID(ULEB128) - Instruction ID to modify + /// - OldInsnID(ULEB128) - Instruction ID to copy from + /// - OpIdx(ULEB128) - The operand to copy + /// - SubRegIdx(2) - The subregister to copy GIR_CopySubReg, /// Add an implicit register def to the specified instruction - /// - InsnID - Instruction ID to modify - /// - RegNum - The register to add - /// - Flags - Register Flags + /// - InsnID(ULEB128) - Instruction ID to modify + /// - RegNum(2) - The register to add + /// - Flags(2) - Register Flags GIR_AddImplicitDef, /// Add an implicit register use to the specified instruction - /// - InsnID - Instruction ID to modify - /// - RegNum - The register to add + /// - InsnID(ULEB128) - Instruction ID to modify + /// - RegNum(2) - The register to add GIR_AddImplicitUse, /// Add an register to the specified instruction - /// - InsnID - Instruction ID to modify - /// - RegNum - The register to add + /// - InsnID(ULEB128) - Instruction ID to modify + /// - RegNum(2) - The register to add + /// - Flags(2) - Register Flags GIR_AddRegister, /// Marks the implicit def of a register as dead. - /// - InsnID - Instruction ID to modify - /// - OpIdx - The implicit def operand index + /// - InsnID(ULEB128) - Instruction ID to modify + /// - OpIdx(ULEB128) - The implicit def operand index /// /// OpIdx starts at 0 for the first implicit def. GIR_SetImplicitDefDead, /// Set or unset a MIFlag on an instruction. /// - /// - InsnID - Instruction to modify. - /// - Flag(s) - (can be one or more flags OR'd together) + /// - InsnID(ULEB128) - Instruction to modify. + /// - Flags(4) - (can be one or more flags OR'd together) GIR_SetMIFlags, GIR_UnsetMIFlags, /// Copy the MIFlags of a matched instruction into an /// output instruction. The flags are OR'd together. /// - /// - InsnID - Instruction to modify. - /// - OldInsnID - Matched instruction to copy flags from. + /// - InsnID(ULEB128) - Instruction to modify. + /// - OldInsnID(ULEB128) - Matched instruction to copy flags from. GIR_CopyMIFlags, /// Add a temporary register to the specified instruction - /// - InsnID - Instruction ID to modify - /// - TempRegID - The temporary register ID to add - /// - TempRegFlags - The register flags to set + /// - InsnID(ULEB128) - Instruction ID to modify + /// - TempRegID(ULEB128) - The temporary register ID to add + /// - TempRegFlags(2) - The register flags to set GIR_AddTempRegister, + /// Add a temporary register to the specified instruction without + /// setting any flags. + /// - InsnID(ULEB128) - Instruction ID to modify + /// - TempRegID(ULEB128) - The temporary register ID to add + GIR_AddSimpleTempRegister, + /// Add a temporary register to the specified instruction - /// - InsnID - Instruction ID to modify - /// - TempRegID - The temporary register ID to add - /// - TempRegFlags - The register flags to set - /// - SubRegIndex - The subregister index to set + /// - InsnID(ULEB128) - Instruction ID to modify + /// - TempRegID(ULEB128) - The temporary register ID to add + /// - TempRegFlags(2) - The register flags to set + /// - SubRegIndex(2) - The subregister index to set GIR_AddTempSubRegister, /// Add an immediate to the specified instruction - /// - InsnID - Instruction ID to modify - /// - Imm - The immediate to add + /// - InsnID(ULEB128) - Instruction ID to modify + /// - Imm(8) - The immediate to add GIR_AddImm, + /// Add signed 8 bit immediate to the specified instruction + /// - InsnID(ULEB128) - Instruction ID to modify + /// - Imm(1) - The immediate to add + GIR_AddImm8, + /// Add an CImm to the specified instruction - /// - InsnID - Instruction ID to modify - /// - Ty - Type of the constant immediate. - /// - Imm - The immediate to add + /// - InsnID(ULEB128) - Instruction ID to modify + /// - Ty(1) - Type of the constant immediate. + /// - Imm(8) - The immediate to add GIR_AddCImm, /// Render complex operands to the specified instruction - /// - InsnID - Instruction ID to modify - /// - RendererID - The renderer to call + /// - InsnID(ULEB128) - Instruction ID to modify + /// - RendererID(2) - The renderer to call GIR_ComplexRenderer, /// Render sub-operands of complex operands to the specified instruction - /// - InsnID - Instruction ID to modify - /// - RendererID - The renderer to call - /// - RenderOpID - The suboperand to render. + /// - InsnID(ULEB128) - Instruction ID to modify + /// - RendererID(2) - The renderer to call + /// - RenderOpID(ULEB128) - The suboperand to render. GIR_ComplexSubOperandRenderer, /// Render subregisters of suboperands of complex operands to the /// specified instruction - /// - InsnID - Instruction ID to modify - /// - RendererID - The renderer to call - /// - RenderOpID - The suboperand to render - /// - SubRegIdx - The subregister to extract + /// - InsnID(ULEB128) - Instruction ID to modify + /// - RendererID(2) - The renderer to call + /// - RenderOpID(ULEB128) - The suboperand to render + /// - SubRegIdx(2) - The subregister to extract GIR_ComplexSubOperandSubRegRenderer, /// Render operands to the specified instruction using a custom function - /// - InsnID - Instruction ID to modify - /// - OldInsnID - Instruction ID to get the matched operand from - /// - RendererFnID - Custom renderer function to call + /// - InsnID(ULEB128) - Instruction ID to modify + /// - OldInsnID(ULEB128) - Instruction ID to get the matched operand from + /// - RendererFnID(2) - Custom renderer function to call GIR_CustomRenderer, /// Calls a C++ function to perform an action when a match is complete. @@ -418,90 +464,85 @@ enum { /// This is less constrained than a custom renderer and can update /// instructions /// in the state. - /// - FnID - The function to call. + /// - FnID(2) - The function to call. /// TODO: Remove this at some point when combiners aren't reliant on it. It's /// a bit of a hack. GIR_CustomAction, /// Render operands to the specified instruction using a custom function, /// reading from a specific operand. - /// - InsnID - Instruction ID to modify - /// - OldInsnID - Instruction ID to get the matched operand from - /// - OpIdx - Operand index in OldInsnID the render function should read + /// - InsnID(ULEB128) - Instruction ID to modify + /// - OldInsnID(ULEB128) - Instruction ID to get the matched operand from + /// - OpIdx(ULEB128) - Operand index in OldInsnID the render function should + /// read /// from.. - /// - RendererFnID - Custom renderer function to call + /// - RendererFnID(2) - Custom renderer function to call GIR_CustomOperandRenderer, /// Render a G_CONSTANT operator as a sign-extended immediate. - /// - NewInsnID - Instruction ID to modify - /// - OldInsnID - Instruction ID to copy from + /// - NewInsnID(ULEB128) - Instruction ID to modify + /// - OldInsnID(ULEB128) - Instruction ID to copy from /// The operand index is implicitly 1. GIR_CopyConstantAsSImm, /// Render a G_FCONSTANT operator as a sign-extended immediate. - /// - NewInsnID - Instruction ID to modify - /// - OldInsnID - Instruction ID to copy from + /// - NewInsnID(ULEB128) - Instruction ID to modify + /// - OldInsnID(ULEB128) - Instruction ID to copy from /// The operand index is implicitly 1. GIR_CopyFConstantAsFPImm, /// Constrain an instruction operand to a register class. - /// - InsnID - Instruction ID to modify - /// - OpIdx - Operand index - /// - RCEnum - Register class enumeration value + /// - InsnID(ULEB128) - Instruction ID to modify + /// - OpIdx(ULEB128) - Operand index + /// - RCEnum(2) - Register class enumeration value GIR_ConstrainOperandRC, /// Constrain an instructions operands according to the instruction /// description. - /// - InsnID - Instruction ID to modify + /// - InsnID(ULEB128) - Instruction ID to modify GIR_ConstrainSelectedInstOperands, /// Merge all memory operands into instruction. - /// - InsnID - Instruction ID to modify - /// - MergeInsnID... - One or more Instruction ID to merge into the result. - /// - GIU_MergeMemOperands_EndOfList - Terminates the list of instructions to - /// merge. + /// - InsnID(ULEB128) - Instruction ID to modify + /// - NumInsnID(1) - Number of instruction IDs following this argument + /// - MergeInsnID(ULEB128)... - One or more Instruction ID to merge into the + /// result. GIR_MergeMemOperands, /// Erase from parent. - /// - InsnID - Instruction ID to erase + /// - InsnID(ULEB128) - Instruction ID to erase GIR_EraseFromParent, /// Create a new temporary register that's not constrained. - /// - TempRegID - The temporary register ID to initialize. - /// - Expected type + /// - TempRegID(ULEB128) - The temporary register ID to initialize. + /// - Ty(1) - Expected type GIR_MakeTempReg, /// Replaces all references to a register from an instruction /// with another register from another instruction. - /// - OldInsnID - /// - OldOpIdx - /// - NewInsnID - /// - NewOpIdx + /// - OldInsnID(ULEB128) + /// - OldOpIdx(ULEB128) + /// - NewInsnID(ULEB128) + /// - NewOpIdx(ULEB128) GIR_ReplaceReg, /// Replaces all references to a register with a temporary register. - /// - OldInsnID - /// - OldOpIdx - /// - TempRegIdx + /// - OldInsnID(ULEB128) + /// - OldOpIdx(ULEB128) + /// - TempRegIdx(ULEB128) GIR_ReplaceRegWithTempReg, /// A successful emission GIR_Done, /// Increment the rule coverage counter. - /// - RuleID - The ID of the rule that was covered. + /// - RuleID(4) - The ID of the rule that was covered. GIR_Coverage, /// Keeping track of the number of the GI opcodes. Must be the last entry. GIU_NumOpcodes, }; -enum { - /// Indicates the end of the variable-length MergeInsnID list in a - /// GIR_MergeMemOperands opcode. - GIU_MergeMemOperands_EndOfList = -1, -}; - /// Provides the logic to execute GlobalISel match tables, which are used by the /// instruction selector and instruction combiners as their engine to match and /// apply MIR patterns. @@ -595,14 +636,14 @@ protected: bool executeMatchTable(TgtExecutor &Exec, MatcherState &State, const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> &ExecInfo, - MachineIRBuilder &Builder, const int64_t *MatchTable, + MachineIRBuilder &Builder, const uint8_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, CodeGenCoverage *CoverageInfo) const; - virtual const int64_t *getMatchTable() const { + virtual const uint8_t *getMatchTable() const { llvm_unreachable("Should have been overridden by tablegen if used"); } @@ -647,6 +688,10 @@ protected: /// MI and IntoMI do not need to be in the same basic blocks, but MI must /// preceed IntoMI. bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const; + + template <typename Ty> static Ty readBytesAs(const uint8_t *MatchTable) { + return *reinterpret_cast<const Ty *>(MatchTable); + } }; } // end namespace llvm diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h index f0ee76c097bc..0a2709ef216b 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h @@ -33,6 +33,7 @@ #include "llvm/Support/CodeGenCoverage.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/LEB128.h" #include "llvm/Support/raw_ostream.h" #include <cassert> #include <cstddef> @@ -46,7 +47,7 @@ bool GIMatchTableExecutor::executeMatchTable( TgtExecutor &Exec, MatcherState &State, const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> &ExecInfo, - MachineIRBuilder &Builder, const int64_t *MatchTable, + MachineIRBuilder &Builder, const uint8_t *MatchTable, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures, @@ -92,28 +93,60 @@ bool GIMatchTableExecutor::executeMatchTable( // If the index is >= 0, it's an index in the type objects generated by // TableGen. If the index is <0, it's an index in the recorded types object. - auto getTypeFromIdx = [&](int64_t Idx) -> LLT { + const auto getTypeFromIdx = [&](int64_t Idx) -> LLT { if (Idx >= 0) return ExecInfo.TypeObjects[Idx]; return State.RecordedTypes[1 - Idx]; }; + const auto readULEB = [&]() { + unsigned N = 0; + uint64_t Val = decodeULEB128(MatchTable + CurrentIdx, &N); + CurrentIdx += N; + return Val; + }; + + // Convenience function to return a signed value. This avoids + // us forgetting to first cast to int8_t before casting to a + // wider signed int type. + // if we casted uint8 directly to a wider type we'd lose + // negative values. + const auto readS8 = [&]() { return (int8_t)MatchTable[CurrentIdx++]; }; + + const auto readU16 = [&]() { + auto V = readBytesAs<uint16_t>(MatchTable + CurrentIdx); + CurrentIdx += 2; + return V; + }; + + const auto readU32 = [&]() { + auto V = readBytesAs<uint32_t>(MatchTable + CurrentIdx); + CurrentIdx += 4; + return V; + }; + + const auto readU64 = [&]() { + auto V = readBytesAs<uint64_t>(MatchTable + CurrentIdx); + CurrentIdx += 8; + return V; + }; + while (true) { assert(CurrentIdx != ~0u && "Invalid MatchTable index"); - int64_t MatcherOpcode = MatchTable[CurrentIdx++]; + uint8_t MatcherOpcode = MatchTable[CurrentIdx++]; switch (MatcherOpcode) { case GIM_Try: { DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": Begin try-block\n"); - OnFailResumeAt.push_back(MatchTable[CurrentIdx++]); + OnFailResumeAt.push_back(readU32()); break; } case GIM_RecordInsn: case GIM_RecordInsnIgnoreCopies: { - int64_t NewInsnID = MatchTable[CurrentIdx++]; - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; + uint64_t NewInsnID = readULEB(); + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); // As an optimisation we require that MIs[0] is always the root. Refuse // any attempt to modify it. @@ -156,7 +189,7 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIM_CheckFeatures: { - int64_t ExpectedBitsetID = MatchTable[CurrentIdx++]; + uint16_t ExpectedBitsetID = readU16(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckFeatures(ExpectedBitsetID=" @@ -170,11 +203,11 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIM_CheckOpcode: case GIM_CheckOpcodeIsEither: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t Expected0 = MatchTable[CurrentIdx++]; - int64_t Expected1 = -1; + uint64_t InsnID = readULEB(); + uint16_t Expected0 = readU16(); + uint16_t Expected1 = -1; if (MatcherOpcode == GIM_CheckOpcodeIsEither) - Expected1 = MatchTable[CurrentIdx++]; + Expected1 = readU16(); assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); unsigned Opcode = State.MIs[InsnID]->getOpcode(); @@ -193,10 +226,10 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_SwitchOpcode: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t LowerBound = MatchTable[CurrentIdx++]; - int64_t UpperBound = MatchTable[CurrentIdx++]; - int64_t Default = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint16_t LowerBound = readU16(); + uint16_t UpperBound = readU16(); + uint32_t Default = readU32(); assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); const int64_t Opcode = State.MIs[InsnID]->getOpcode(); @@ -210,7 +243,10 @@ bool GIMatchTableExecutor::executeMatchTable( CurrentIdx = Default; break; } - CurrentIdx = MatchTable[CurrentIdx + (Opcode - LowerBound)]; + const auto EntryIdx = (Opcode - LowerBound); + // Each entry is 4 bytes + CurrentIdx = + readBytesAs<uint32_t>(MatchTable + CurrentIdx + (EntryIdx * 4)); if (!CurrentIdx) { CurrentIdx = Default; break; @@ -220,11 +256,11 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIM_SwitchType: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t LowerBound = MatchTable[CurrentIdx++]; - int64_t UpperBound = MatchTable[CurrentIdx++]; - int64_t Default = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint16_t LowerBound = readU16(); + uint16_t UpperBound = readU16(); + int64_t Default = readU32(); assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); @@ -254,7 +290,10 @@ bool GIMatchTableExecutor::executeMatchTable( CurrentIdx = Default; break; } - CurrentIdx = MatchTable[CurrentIdx + (TypeID - LowerBound)]; + const auto NumEntry = (TypeID - LowerBound); + // Each entry is 4 bytes + CurrentIdx = + readBytesAs<uint32_t>(MatchTable + CurrentIdx + (NumEntry * 4)); if (!CurrentIdx) { CurrentIdx = Default; break; @@ -264,8 +303,8 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIM_CheckNumOperands: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t Expected = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t Expected = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckNumOperands(MIs[" << InsnID << "], Expected=" << Expected << ")\n"); @@ -278,11 +317,10 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIM_CheckI64ImmPredicate: case GIM_CheckImmOperandPredicate: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatcherOpcode == GIM_CheckImmOperandPredicate - ? MatchTable[CurrentIdx++] - : 1; - int64_t Predicate = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + unsigned OpIdx = + MatcherOpcode == GIM_CheckImmOperandPredicate ? readULEB() : 1; + uint16_t Predicate = readU16(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckImmPredicate(MIs[" << InsnID << "]->getOperand(" << OpIdx @@ -306,8 +344,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckAPIntImmPredicate: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t Predicate = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint16_t Predicate = readU16(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckAPIntImmPredicate(MIs[" @@ -327,8 +365,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckAPFloatImmPredicate: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t Predicate = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint16_t Predicate = readU16(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckAPFloatImmPredicate(MIs[" @@ -349,7 +387,7 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIM_CheckIsBuildVectorAllOnes: case GIM_CheckIsBuildVectorAllZeros: { - int64_t InsnID = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx @@ -380,7 +418,7 @@ bool GIMatchTableExecutor::executeMatchTable( // Note: we don't check for invalid here because this is purely a hook to // allow some executors (such as the combiner) to check arbitrary, // contextless predicates, such as whether a rule is enabled or not. - int64_t Predicate = MatchTable[CurrentIdx++]; + uint16_t Predicate = readU16(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckSimplePredicate(Predicate=" @@ -393,8 +431,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckCxxInsnPredicate: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t Predicate = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint16_t Predicate = readU16(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckCxxPredicate(MIs[" @@ -408,7 +446,7 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckHasNoUse: { - int64_t InsnID = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckHasNoUse(MIs[" @@ -427,8 +465,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckAtomicOrdering: { - int64_t InsnID = MatchTable[CurrentIdx++]; - AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + auto Ordering = (AtomicOrdering)readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckAtomicOrdering(MIs[" << InsnID << "], " << (uint64_t)Ordering << ")\n"); @@ -444,8 +482,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckAtomicOrderingOrStrongerThan: { - int64_t InsnID = MatchTable[CurrentIdx++]; - AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + auto Ordering = (AtomicOrdering)readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckAtomicOrderingOrStrongerThan(MIs[" @@ -462,8 +500,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckAtomicOrderingWeakerThan: { - int64_t InsnID = MatchTable[CurrentIdx++]; - AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + auto Ordering = (AtomicOrdering)readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckAtomicOrderingWeakerThan(MIs[" @@ -480,10 +518,10 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckMemoryAddressSpace: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t MMOIdx = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t MMOIdx = readULEB(); // This accepts a list of possible address spaces. - const int NumAddrSpace = MatchTable[CurrentIdx++]; + const uint64_t NumAddrSpace = readULEB(); if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) { if (handleReject() == RejectAndGiveUp) @@ -500,8 +538,8 @@ bool GIMatchTableExecutor::executeMatchTable( const unsigned MMOAddrSpace = MMO->getAddrSpace(); bool Success = false; - for (int I = 0; I != NumAddrSpace; ++I) { - unsigned AddrSpace = MatchTable[CurrentIdx++]; + for (unsigned I = 0; I != NumAddrSpace; ++I) { + uint64_t AddrSpace = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << "addrspace(" << MMOAddrSpace << ") vs " << AddrSpace << '\n'); @@ -518,9 +556,9 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckMemoryAlignment: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t MMOIdx = MatchTable[CurrentIdx++]; - unsigned MinAlign = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t MMOIdx = readULEB(); + uint64_t MinAlign = readULEB(); assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); @@ -543,9 +581,9 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckMemorySizeEqualTo: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t MMOIdx = MatchTable[CurrentIdx++]; - uint64_t Size = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t MMOIdx = readULEB(); + uint32_t Size = readU32(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckMemorySizeEqual(MIs[" @@ -574,9 +612,9 @@ bool GIMatchTableExecutor::executeMatchTable( case GIM_CheckMemorySizeEqualToLLT: case GIM_CheckMemorySizeLessThanLLT: case GIM_CheckMemorySizeGreaterThanLLT: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t MMOIdx = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t MMOIdx = readULEB(); + uint64_t OpIdx = readULEB(); DEBUG_WITH_TYPE( TgtExecutor::getName(), @@ -624,9 +662,9 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckType: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t TypeID = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + int TypeID = readS8(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckType(MIs[" << InsnID << "]->getOperand(" << OpIdx @@ -640,9 +678,9 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckPointerToAny: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - uint64_t SizeInBits = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint64_t SizeInBits = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckPointerToAny(MIs[" @@ -671,9 +709,9 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_RecordNamedOperand: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - uint64_t StoreIdx = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint64_t StoreIdx = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_RecordNamedOperand(MIs[" @@ -685,16 +723,16 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_RecordRegType: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t TypeIdx = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + int TypeIdx = readS8(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_RecordRegType(MIs[" << InsnID << "]->getOperand(" << OpIdx << "), TypeIdx=" << TypeIdx << ")\n"); assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); - assert(TypeIdx <= 0 && "Temp types always have negative indexes!"); + assert(TypeIdx < 0 && "Temp types always have negative indexes!"); // Indexes start at -1. TypeIdx = 1 - TypeIdx; const auto &Op = State.MIs[InsnID]->getOperand(OpIdx); @@ -704,9 +742,9 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckRegBankForClass: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t RCEnum = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint16_t RCEnum = readU16(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckRegBankForClass(MIs[" << InsnID << "]->getOperand(" << OpIdx @@ -724,10 +762,10 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIM_CheckComplexPattern: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t RendererID = MatchTable[CurrentIdx++]; - int64_t ComplexPredicateID = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint16_t RendererID = readU16(); + uint16_t ComplexPredicateID = readU16(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": State.Renderers[" << RendererID << "] = GIM_CheckComplexPattern(MIs[" << InsnID @@ -746,10 +784,13 @@ bool GIMatchTableExecutor::executeMatchTable( break; } - case GIM_CheckConstantInt: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t Value = MatchTable[CurrentIdx++]; + case GIM_CheckConstantInt: + case GIM_CheckConstantInt8: { + const bool IsInt8 = (MatcherOpcode == GIM_CheckConstantInt8); + + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint64_t Value = IsInt8 ? (int64_t)readS8() : readU64(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckConstantInt(MIs[" << InsnID << "]->getOperand(" << OpIdx @@ -779,9 +820,9 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIM_CheckLiteralInt: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t Value = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + int64_t Value = readU64(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckLiteralInt(MIs[" << InsnID << "]->getOperand(" << OpIdx @@ -801,9 +842,9 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIM_CheckIntrinsicID: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t Value = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint16_t Value = readU16(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckIntrinsicID(MIs[" << InsnID << "]->getOperand(" << OpIdx @@ -816,9 +857,9 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckCmpPredicate: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t Value = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint16_t Value = readU16(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckCmpPredicate(MIs[" << InsnID << "]->getOperand(" << OpIdx @@ -831,8 +872,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckIsMBB: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckIsMBB(MIs[" << InsnID << "]->getOperand(" << OpIdx << "))\n"); @@ -844,8 +885,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckIsImm: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckIsImm(MIs[" << InsnID << "]->getOperand(" << OpIdx << "))\n"); @@ -857,7 +898,7 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckIsSafeToFold: { - int64_t InsnID = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckIsSafeToFold(MIs[" << InsnID << "])\n"); @@ -870,10 +911,10 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIM_CheckIsSameOperand: case GIM_CheckIsSameOperandIgnoreCopies: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t OtherInsnID = MatchTable[CurrentIdx++]; - int64_t OtherOpIdx = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint64_t OtherInsnID = readULEB(); + uint64_t OtherOpIdx = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckIsSameOperand(MIs[" << InsnID << "][" << OpIdx << "], MIs[" @@ -899,10 +940,10 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckCanReplaceReg: { - int64_t OldInsnID = MatchTable[CurrentIdx++]; - int64_t OldOpIdx = MatchTable[CurrentIdx++]; - int64_t NewInsnID = MatchTable[CurrentIdx++]; - int64_t NewOpIdx = MatchTable[CurrentIdx++]; + uint64_t OldInsnID = readULEB(); + uint64_t OldOpIdx = readULEB(); + uint64_t NewInsnID = readULEB(); + uint64_t NewOpIdx = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_CheckCanReplaceReg(MIs[" @@ -918,8 +959,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_MIFlags: { - int64_t InsnID = MatchTable[CurrentIdx++]; - uint32_t Flags = (uint32_t)MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint32_t Flags = readU32(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_MIFlags(MIs[" << InsnID @@ -931,8 +972,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_MIFlagsNot: { - int64_t InsnID = MatchTable[CurrentIdx++]; - uint32_t Flags = (uint32_t)MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint32_t Flags = readU32(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIM_MIFlagsNot(MIs[" << InsnID @@ -950,9 +991,9 @@ bool GIMatchTableExecutor::executeMatchTable( return false; break; case GIR_MutateOpcode: { - int64_t OldInsnID = MatchTable[CurrentIdx++]; - uint64_t NewInsnID = MatchTable[CurrentIdx++]; - int64_t NewOpcode = MatchTable[CurrentIdx++]; + uint64_t OldInsnID = readULEB(); + uint64_t NewInsnID = readULEB(); + uint16_t NewOpcode = readU16(); if (NewInsnID >= OutMIs.size()) OutMIs.resize(NewInsnID + 1); @@ -971,8 +1012,8 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_BuildMI: { - uint64_t NewInsnID = MatchTable[CurrentIdx++]; - int64_t Opcode = MatchTable[CurrentIdx++]; + uint64_t NewInsnID = readULEB(); + uint16_t Opcode = readU16(); if (NewInsnID >= OutMIs.size()) OutMIs.resize(NewInsnID + 1); @@ -984,8 +1025,8 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_BuildConstant: { - int64_t TempRegID = MatchTable[CurrentIdx++]; - int64_t Imm = MatchTable[CurrentIdx++]; + uint64_t TempRegID = readULEB(); + uint64_t Imm = readU64(); Builder.buildConstant(State.TempRegisters[TempRegID], Imm); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIR_BuildConstant(TempReg[" @@ -994,9 +1035,9 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_Copy: { - int64_t NewInsnID = MatchTable[CurrentIdx++]; - int64_t OldInsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; + uint64_t NewInsnID = readULEB(); + uint64_t OldInsnID = readULEB(); + uint64_t OpIdx = readULEB(); assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction"); OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx)); DEBUG_WITH_TYPE(TgtExecutor::getName(), @@ -1007,10 +1048,10 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_CopyOrAddZeroReg: { - int64_t NewInsnID = MatchTable[CurrentIdx++]; - int64_t OldInsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t ZeroReg = MatchTable[CurrentIdx++]; + uint64_t NewInsnID = readULEB(); + uint64_t OldInsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint16_t ZeroReg = readU16(); assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction"); MachineOperand &MO = State.MIs[OldInsnID]->getOperand(OpIdx); if (isOperandImmEqual(MO, 0, MRI)) @@ -1025,10 +1066,10 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_CopySubReg: { - int64_t NewInsnID = MatchTable[CurrentIdx++]; - int64_t OldInsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t SubRegIdx = MatchTable[CurrentIdx++]; + uint64_t NewInsnID = readULEB(); + uint64_t OldInsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint16_t SubRegIdx = readU16(); assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction"); OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(), 0, SubRegIdx); @@ -1040,9 +1081,9 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_AddImplicitDef: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t RegNum = MatchTable[CurrentIdx++]; - auto Flags = (uint64_t)MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint16_t RegNum = readU16(); + uint16_t Flags = readU16(); assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); Flags |= RegState::Implicit; OutMIs[InsnID].addDef(RegNum, Flags); @@ -1053,8 +1094,8 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_AddImplicitUse: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t RegNum = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint16_t RegNum = readU16(); assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); OutMIs[InsnID].addUse(RegNum, RegState::Implicit); DEBUG_WITH_TYPE(TgtExecutor::getName(), @@ -1064,9 +1105,9 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_AddRegister: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t RegNum = MatchTable[CurrentIdx++]; - uint64_t RegFlags = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint16_t RegNum = readU16(); + uint16_t RegFlags = readU16(); assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); OutMIs[InsnID].addReg(RegNum, RegFlags); DEBUG_WITH_TYPE(TgtExecutor::getName(), @@ -1076,8 +1117,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIR_SetImplicitDefDead: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIR_SetImplicitDefDead(OutMIs[" << InsnID << "], OpIdx=" << OpIdx << ")\n"); @@ -1087,8 +1128,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIR_SetMIFlags: { - int64_t InsnID = MatchTable[CurrentIdx++]; - uint32_t Flags = (uint32_t)MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint32_t Flags = readU32(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIR_SetMIFlags(OutMIs[" @@ -1098,8 +1139,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIR_UnsetMIFlags: { - int64_t InsnID = MatchTable[CurrentIdx++]; - uint32_t Flags = (uint32_t)MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint32_t Flags = readU32(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIR_UnsetMIFlags(OutMIs[" @@ -1109,8 +1150,8 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIR_CopyMIFlags: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OldInsnID = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OldInsnID = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIR_CopyMIFlags(OutMIs[" @@ -1119,14 +1160,17 @@ bool GIMatchTableExecutor::executeMatchTable( MI->setFlags(MI->getFlags() | State.MIs[OldInsnID]->getFlags()); break; } + case GIR_AddSimpleTempRegister: case GIR_AddTempRegister: case GIR_AddTempSubRegister: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t TempRegID = MatchTable[CurrentIdx++]; - uint64_t TempRegFlags = MatchTable[CurrentIdx++]; - unsigned SubReg = 0; + uint64_t InsnID = readULEB(); + uint64_t TempRegID = readULEB(); + uint16_t TempRegFlags = 0; + if (MatcherOpcode != GIR_AddSimpleTempRegister) + TempRegFlags = readU16(); + uint16_t SubReg = 0; if (MatcherOpcode == GIR_AddTempSubRegister) - SubReg = MatchTable[CurrentIdx++]; + SubReg = readU16(); assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); @@ -1141,9 +1185,11 @@ bool GIMatchTableExecutor::executeMatchTable( break; } + case GIR_AddImm8: case GIR_AddImm: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t Imm = MatchTable[CurrentIdx++]; + const bool IsAdd8 = (MatcherOpcode == GIR_AddImm8); + uint64_t InsnID = readULEB(); + uint64_t Imm = IsAdd8 ? (int64_t)readS8() : readU64(); assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); OutMIs[InsnID].addImm(Imm); DEBUG_WITH_TYPE(TgtExecutor::getName(), @@ -1153,9 +1199,9 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_AddCImm: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t TypeID = MatchTable[CurrentIdx++]; - int64_t Imm = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + int TypeID = readS8(); + uint64_t Imm = readU64(); assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); unsigned Width = ExecInfo.TypeObjects[TypeID].getScalarSizeInBits(); @@ -1170,8 +1216,8 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_ComplexRenderer: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t RendererID = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint16_t RendererID = readU16(); assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); for (const auto &RenderOpFn : State.Renderers[RendererID]) RenderOpFn(OutMIs[InsnID]); @@ -1181,9 +1227,9 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIR_ComplexSubOperandRenderer: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t RendererID = MatchTable[CurrentIdx++]; - int64_t RenderOpID = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint16_t RendererID = readU16(); + uint64_t RenderOpID = readULEB(); assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); State.Renderers[RendererID][RenderOpID](OutMIs[InsnID]); DEBUG_WITH_TYPE(TgtExecutor::getName(), @@ -1194,10 +1240,10 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIR_ComplexSubOperandSubRegRenderer: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t RendererID = MatchTable[CurrentIdx++]; - int64_t RenderOpID = MatchTable[CurrentIdx++]; - int64_t SubRegIdx = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint16_t RendererID = readU16(); + uint64_t RenderOpID = readULEB(); + uint16_t SubRegIdx = readU16(); MachineInstrBuilder &MI = OutMIs[InsnID]; assert(MI && "Attempted to add to undefined instruction"); State.Renderers[RendererID][RenderOpID](MI); @@ -1211,8 +1257,8 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_CopyConstantAsSImm: { - int64_t NewInsnID = MatchTable[CurrentIdx++]; - int64_t OldInsnID = MatchTable[CurrentIdx++]; + uint64_t NewInsnID = readULEB(); + uint64_t OldInsnID = readULEB(); assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction"); assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT"); @@ -1231,8 +1277,8 @@ bool GIMatchTableExecutor::executeMatchTable( // TODO: Needs a test case once we have a pattern that uses this. case GIR_CopyFConstantAsFPImm: { - int64_t NewInsnID = MatchTable[CurrentIdx++]; - int64_t OldInsnID = MatchTable[CurrentIdx++]; + uint64_t NewInsnID = readULEB(); + uint64_t OldInsnID = readULEB(); assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction"); assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_FCONSTANT && "Expected G_FCONSTANT"); @@ -1249,9 +1295,9 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_CustomRenderer: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OldInsnID = MatchTable[CurrentIdx++]; - int64_t RendererFnID = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OldInsnID = readULEB(); + uint16_t RendererFnID = readU16(); assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIR_CustomRenderer(OutMIs[" @@ -1263,7 +1309,7 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIR_CustomAction: { - int64_t FnID = MatchTable[CurrentIdx++]; + uint16_t FnID = readU16(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIR_CustomAction(FnID=" << FnID << ")\n"); @@ -1272,10 +1318,10 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIR_CustomOperandRenderer: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OldInsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t RendererFnID = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OldInsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint16_t RendererFnID = readU16(); assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); DEBUG_WITH_TYPE(TgtExecutor::getName(), @@ -1288,9 +1334,9 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIR_ConstrainOperandRC: { - int64_t InsnID = MatchTable[CurrentIdx++]; - int64_t OpIdx = MatchTable[CurrentIdx++]; - int64_t RCEnum = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t OpIdx = readULEB(); + uint16_t RCEnum = readU16(); assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); MachineInstr &I = *OutMIs[InsnID].getInstr(); MachineFunction &MF = *I.getParent()->getParent(); @@ -1306,7 +1352,7 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_ConstrainSelectedInstOperands: { - int64_t InsnID = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI, RBI); @@ -1318,18 +1364,18 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_MergeMemOperands: { - int64_t InsnID = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); + uint64_t NumInsn = MatchTable[CurrentIdx++]; assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIR_MergeMemOperands(OutMIs[" << InsnID << "]"); - int64_t MergeInsnID = GIU_MergeMemOperands_EndOfList; - while ((MergeInsnID = MatchTable[CurrentIdx++]) != - GIU_MergeMemOperands_EndOfList) { + for (unsigned K = 0; K < NumInsn; ++K) { + uint64_t NextID = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), - dbgs() << ", MIs[" << MergeInsnID << "]"); - for (const auto &MMO : State.MIs[MergeInsnID]->memoperands()) + dbgs() << ", MIs[" << NextID << "]"); + for (const auto &MMO : State.MIs[NextID]->memoperands()) OutMIs[InsnID].addMemOperand(MMO); } DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << ")\n"); @@ -1337,7 +1383,7 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_EraseFromParent: { - int64_t InsnID = MatchTable[CurrentIdx++]; + uint64_t InsnID = readULEB(); MachineInstr *MI = State.MIs[InsnID]; assert(MI && "Attempted to erase an undefined instruction"); DEBUG_WITH_TYPE(TgtExecutor::getName(), @@ -1354,8 +1400,8 @@ bool GIMatchTableExecutor::executeMatchTable( } case GIR_MakeTempReg: { - int64_t TempRegID = MatchTable[CurrentIdx++]; - int64_t TypeID = MatchTable[CurrentIdx++]; + uint64_t TempRegID = readULEB(); + int TypeID = readS8(); State.TempRegisters[TempRegID] = MRI.createGenericVirtualRegister(getTypeFromIdx(TypeID)); @@ -1365,10 +1411,10 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIR_ReplaceReg: { - int64_t OldInsnID = MatchTable[CurrentIdx++]; - int64_t OldOpIdx = MatchTable[CurrentIdx++]; - int64_t NewInsnID = MatchTable[CurrentIdx++]; - int64_t NewOpIdx = MatchTable[CurrentIdx++]; + uint64_t OldInsnID = readULEB(); + uint64_t OldOpIdx = readULEB(); + uint64_t NewInsnID = readULEB(); + uint64_t NewOpIdx = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIR_ReplaceReg(MIs[" @@ -1385,9 +1431,9 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIR_ReplaceRegWithTempReg: { - int64_t OldInsnID = MatchTable[CurrentIdx++]; - int64_t OldOpIdx = MatchTable[CurrentIdx++]; - int64_t TempRegID = MatchTable[CurrentIdx++]; + uint64_t OldInsnID = readULEB(); + uint64_t OldOpIdx = readULEB(); + uint64_t TempRegID = readULEB(); DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIR_ReplaceRegWithTempReg(MIs[" @@ -1404,7 +1450,7 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIR_Coverage: { - int64_t RuleID = MatchTable[CurrentIdx++]; + uint32_t RuleID = readU32(); assert(CoverageInfo); CoverageInfo->setCovered(RuleID); diff --git a/llvm/include/llvm/CodeGen/IndirectBrExpand.h b/llvm/include/llvm/CodeGen/IndirectBrExpand.h new file mode 100644 index 000000000000..f7d9d5df6fe2 --- /dev/null +++ b/llvm/include/llvm/CodeGen/IndirectBrExpand.h @@ -0,0 +1,28 @@ +//===- llvm/CodeGen/IndirectBrExpand.h -------------------------*- C++ -*--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_INDIRECTBREXPAND_H +#define LLVM_CODEGEN_INDIRECTBREXPAND_H + +#include "llvm/IR/PassManager.h" + +namespace llvm { + +class TargetMachine; + +class IndirectBrExpandPass : public PassInfoMixin<IndirectBrExpandPass> { + const TargetMachine *TM; + +public: + IndirectBrExpandPass(const TargetMachine *TM) : TM(TM) {} + PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM); +}; + +} // namespace llvm + +#endif // LLVM_CODEGEN_INDIRECTBREXPAND_H diff --git a/llvm/include/llvm/CodeGen/MachinePassRegistry.def b/llvm/include/llvm/CodeGen/MachinePassRegistry.def index 4e2bee49a71c..ba81dbadf4bd 100644 --- a/llvm/include/llvm/CodeGen/MachinePassRegistry.def +++ b/llvm/include/llvm/CodeGen/MachinePassRegistry.def @@ -16,6 +16,7 @@ #ifndef MODULE_ANALYSIS #define MODULE_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) #endif +MODULE_ANALYSIS("collector-metadata", CollectorMetadataAnalysis, ()) MODULE_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, (PIC)) #undef MODULE_ANALYSIS @@ -29,6 +30,7 @@ MODULE_PASS("jmc-instrumenter", JMCInstrumenterPass, ()) #ifndef FUNCTION_ANALYSIS #define FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) #endif +FUNCTION_ANALYSIS("gc-function", GCFunctionAnalysis, ()) FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, (PIC)) FUNCTION_ANALYSIS("targetir", TargetIRAnalysis, (std::move(TM.getTargetIRAnalysis()))) @@ -44,8 +46,10 @@ FUNCTION_PASS("dwarf-eh-prepare", DwarfEHPreparePass, (TM)) FUNCTION_PASS("ee-instrument", EntryExitInstrumenterPass, (false)) FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass, ()) FUNCTION_PASS("expand-large-fp-convert", ExpandLargeFpConvertPass, ()) +FUNCTION_PASS("expand-memcmp", ExpandMemCmpPass, (TM)) FUNCTION_PASS("expand-reductions", ExpandReductionsPass, ()) FUNCTION_PASS("expandvp", ExpandVectorPredicationPass, ()) +FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass, (TM)) FUNCTION_PASS("interleaved-access", InterleavedAccessPass, (TM)) FUNCTION_PASS("interleaved-load-combine", InterleavedLoadCombinePass, (TM)) FUNCTION_PASS("lower-constant-intrinsics", LowerConstantIntrinsicsPass, ()) @@ -127,9 +131,7 @@ MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, #endif DUMMY_FUNCTION_PASS("atomic-expand", AtomicExpandPass, ()) DUMMY_FUNCTION_PASS("codegenprepare", CodeGenPreparePass, ()) -DUMMY_FUNCTION_PASS("expandmemcmp", ExpandMemCmpPass, ()) DUMMY_FUNCTION_PASS("gc-lowering", GCLoweringPass, ()) -DUMMY_FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass, ()) DUMMY_FUNCTION_PASS("shadow-stack-gc-lowering", ShadowStackGCLoweringPass, ()) DUMMY_FUNCTION_PASS("stack-protector", StackProtectorPass, ()) #undef DUMMY_FUNCTION_PASS diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h index 80def6dfef49..ca9fbb1def76 100644 --- a/llvm/include/llvm/CodeGen/Passes.h +++ b/llvm/include/llvm/CodeGen/Passes.h @@ -520,7 +520,7 @@ namespace llvm { FunctionPass *createExpandLargeFpConvertPass(); // This pass expands memcmp() to load/stores. - FunctionPass *createExpandMemCmpPass(); + FunctionPass *createExpandMemCmpLegacyPass(); /// Creates Break False Dependencies pass. \see BreakFalseDeps.cpp FunctionPass *createBreakFalseDeps(); diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index 83fc208e7f7e..9088168b4c67 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -1401,6 +1401,13 @@ class AdvSIMD_SVE_Reduce_Intrinsic llvm_anyvector_ty], [IntrNoMem]>; +class AdvSIMD_SVE_V128_Reduce_Intrinsic + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [LLVMScalarOrSameVectorWidth<1, llvm_i1_ty>, + llvm_anyvector_ty], + [IntrNoMem]>; + + class AdvSIMD_SVE_SADDV_Reduce_Intrinsic : DefaultAttrsIntrinsic<[llvm_i64_ty], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, @@ -1723,6 +1730,15 @@ def int_aarch64_sve_sqsub_x : AdvSIMD_2VectorArg_Intrinsic; def int_aarch64_sve_uqadd_x : AdvSIMD_2VectorArg_Intrinsic; def int_aarch64_sve_uqsub_x : AdvSIMD_2VectorArg_Intrinsic; +def int_aarch64_sve_orqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; +def int_aarch64_sve_eorqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; +def int_aarch64_sve_andqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; +def int_aarch64_sve_smaxqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; +def int_aarch64_sve_umaxqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; +def int_aarch64_sve_sminqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; +def int_aarch64_sve_uminqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; + + // Shifts def int_aarch64_sve_asr : AdvSIMD_Pred2VectorArg_Intrinsic; @@ -2033,6 +2049,11 @@ def int_aarch64_sve_fmaxv : AdvSIMD_SVE_Reduce_Intrinsic; def int_aarch64_sve_fmaxnmv : AdvSIMD_SVE_Reduce_Intrinsic; def int_aarch64_sve_fminv : AdvSIMD_SVE_Reduce_Intrinsic; def int_aarch64_sve_fminnmv : AdvSIMD_SVE_Reduce_Intrinsic; +def int_aarch64_sve_addqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; +def int_aarch64_sve_fmaxnmqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; +def int_aarch64_sve_fminnmqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; +def int_aarch64_sve_fmaxqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; +def int_aarch64_sve_fminqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; // // Floating-point conversions diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index bc9f99783d98..09e88152e65d 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -227,6 +227,45 @@ def int_amdgcn_s_sendmsg_rtn : Intrinsic <[llvm_anyint_ty], [llvm_i32_ty], def int_amdgcn_s_barrier : ClangBuiltin<"__builtin_amdgcn_s_barrier">, Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn, IntrNoCallback, IntrNoFree]>; +def int_amdgcn_s_barrier_signal : ClangBuiltin<"__builtin_amdgcn_s_barrier_signal">, + Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn, + IntrNoCallback, IntrNoFree]>; + +def int_amdgcn_s_barrier_signal_var : ClangBuiltin<"__builtin_amdgcn_s_barrier_signal_var">, + Intrinsic<[], [llvm_i32_ty], [IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn, + IntrNoCallback, IntrNoFree]>; + +def int_amdgcn_s_barrier_signal_isfirst : ClangBuiltin<"__builtin_amdgcn_s_barrier_signal_isfirst">, + Intrinsic<[llvm_i1_ty], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects, IntrConvergent, + IntrWillReturn, IntrNoCallback, IntrNoFree]>; + +def int_amdgcn_s_barrier_signal_isfirst_var : ClangBuiltin<"__builtin_amdgcn_s_barrier_signal_isfirst_var">, + Intrinsic<[llvm_i1_ty], [llvm_i32_ty], [IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn, + IntrNoCallback, IntrNoFree]>; + +def int_amdgcn_s_barrier_init : ClangBuiltin<"__builtin_amdgcn_s_barrier_init">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrHasSideEffects, IntrConvergent, + IntrWillReturn, IntrNoCallback, IntrNoFree]>; + +def int_amdgcn_s_barrier_join : ClangBuiltin<"__builtin_amdgcn_s_barrier_join">, + Intrinsic<[], [llvm_i32_ty], [IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn, + IntrNoCallback, IntrNoFree]>; + +def int_amdgcn_s_wakeup_barrier : ClangBuiltin<"__builtin_amdgcn_s_wakeup_barrier">, + Intrinsic<[], [llvm_i32_ty], [IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn, + IntrNoCallback, IntrNoFree]>; + +def int_amdgcn_s_barrier_wait : ClangBuiltin<"__builtin_amdgcn_s_barrier_wait">, + Intrinsic<[], [llvm_i16_ty], [ImmArg<ArgIndex<0>>, IntrNoMem, IntrHasSideEffects, IntrConvergent, + IntrWillReturn, IntrNoCallback, IntrNoFree]>; + +def int_amdgcn_s_barrier_leave : ClangBuiltin<"__builtin_amdgcn_s_barrier_leave">, + Intrinsic<[llvm_i1_ty], [], [IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn, IntrNoCallback, IntrNoFree]>; + +def int_amdgcn_s_get_barrier_state : ClangBuiltin<"__builtin_amdgcn_s_get_barrier_state">, + Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn, + IntrNoCallback, IntrNoFree]>; + def int_amdgcn_wave_barrier : ClangBuiltin<"__builtin_amdgcn_wave_barrier">, Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrConvergent, IntrWillReturn, IntrNoCallback, IntrNoFree]>; diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index 66177f9b9f77..46b1e95c3c15 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -103,7 +103,7 @@ void initializeEdgeBundlesPass(PassRegistry&); void initializeEHContGuardCatchretPass(PassRegistry &); void initializeExpandLargeFpConvertLegacyPassPass(PassRegistry&); void initializeExpandLargeDivRemLegacyPassPass(PassRegistry&); -void initializeExpandMemCmpPassPass(PassRegistry&); +void initializeExpandMemCmpLegacyPassPass(PassRegistry &); void initializeExpandPostRAPass(PassRegistry&); void initializeExpandReductionsPass(PassRegistry&); void initializeExpandVectorPredicationPass(PassRegistry &); @@ -129,7 +129,7 @@ void initializeIVUsersWrapperPassPass(PassRegistry&); void initializeIfConverterPass(PassRegistry&); void initializeImmutableModuleSummaryIndexWrapperPassPass(PassRegistry&); void initializeImplicitNullChecksPass(PassRegistry&); -void initializeIndirectBrExpandPassPass(PassRegistry&); +void initializeIndirectBrExpandLegacyPassPass(PassRegistry &); void initializeInferAddressSpacesPass(PassRegistry&); void initializeInstSimplifyLegacyPassPass(PassRegistry &); void initializeInstructionCombiningPassPass(PassRegistry&); diff --git a/llvm/include/llvm/LinkAllPasses.h b/llvm/include/llvm/LinkAllPasses.h index bf990a1408fa..7a21876e565a 100644 --- a/llvm/include/llvm/LinkAllPasses.h +++ b/llvm/include/llvm/LinkAllPasses.h @@ -119,7 +119,7 @@ namespace { (void) llvm::createPostDomTree(); (void) llvm::createMergeICmpsLegacyPass(); (void) llvm::createExpandLargeDivRemPass(); - (void) llvm::createExpandMemCmpPass(); + (void)llvm::createExpandMemCmpLegacyPass(); (void) llvm::createExpandVectorPredicationPass(); std::string buf; llvm::raw_string_ostream os(buf); @@ -148,8 +148,7 @@ namespace { llvm::AliasAnalysis AA(TLI); llvm::BatchAAResults BAA(AA); llvm::AliasSetTracker X(BAA); - X.add(nullptr, llvm::LocationSize::beforeOrAfterPointer(), - llvm::AAMDNodes()); // for -print-alias-sets + X.add(llvm::MemoryLocation()); // for -print-alias-sets (void) llvm::AreStatisticsEnabled(); (void) llvm::sys::RunningOnValgrind(); } diff --git a/llvm/include/llvm/MC/MCFragment.h b/llvm/include/llvm/MC/MCFragment.h index c314fdd3aa69..a9b19dc56f16 100644 --- a/llvm/include/llvm/MC/MCFragment.h +++ b/llvm/include/llvm/MC/MCFragment.h @@ -428,7 +428,7 @@ public: } }; -class MCLEBFragment final : public MCEncodedFragmentWithFixups<10, 1> { +class MCLEBFragment final : public MCEncodedFragmentWithFixups<8, 0> { /// True if this is a sleb128, false if uleb128. bool IsSigned; @@ -437,7 +437,7 @@ class MCLEBFragment final : public MCEncodedFragmentWithFixups<10, 1> { public: MCLEBFragment(const MCExpr &Value, bool IsSigned, MCSection *Sec = nullptr) - : MCEncodedFragmentWithFixups<10, 1>(FT_LEB, false, Sec), + : MCEncodedFragmentWithFixups<8, 0>(FT_LEB, false, Sec), IsSigned(IsSigned), Value(&Value) { getContents().push_back(0); } diff --git a/llvm/include/llvm/Support/AMDHSAKernelDescriptor.h b/llvm/include/llvm/Support/AMDHSAKernelDescriptor.h index 0574f96e6e15..2de2cf4185d8 100644 --- a/llvm/include/llvm/Support/AMDHSAKernelDescriptor.h +++ b/llvm/include/llvm/Support/AMDHSAKernelDescriptor.h @@ -88,12 +88,18 @@ enum : uint8_t { // [GFX6-GFX9]. #define COMPUTE_PGM_RSRC1_GFX6_GFX9(NAME, SHIFT, WIDTH) \ AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX9_ ## NAME, SHIFT, WIDTH) +// [GFX6-GFX11]. +#define COMPUTE_PGM_RSRC1_GFX6_GFX11(NAME, SHIFT, WIDTH) \ + AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX11_##NAME, SHIFT, WIDTH) // GFX9+. #define COMPUTE_PGM_RSRC1_GFX9_PLUS(NAME, SHIFT, WIDTH) \ AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX9_PLUS_ ## NAME, SHIFT, WIDTH) // GFX10+. #define COMPUTE_PGM_RSRC1_GFX10_PLUS(NAME, SHIFT, WIDTH) \ AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX10_PLUS_ ## NAME, SHIFT, WIDTH) +// GFX12+. +#define COMPUTE_PGM_RSRC1_GFX12_PLUS(NAME, SHIFT, WIDTH) \ + AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX12_PLUS_##NAME, SHIFT, WIDTH) enum : int32_t { COMPUTE_PGM_RSRC1(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6), COMPUTE_PGM_RSRC1(GRANULATED_WAVEFRONT_SGPR_COUNT, 6, 4), @@ -103,9 +109,11 @@ enum : int32_t { COMPUTE_PGM_RSRC1(FLOAT_DENORM_MODE_32, 16, 2), COMPUTE_PGM_RSRC1(FLOAT_DENORM_MODE_16_64, 18, 2), COMPUTE_PGM_RSRC1(PRIV, 20, 1), - COMPUTE_PGM_RSRC1(ENABLE_DX10_CLAMP, 21, 1), + COMPUTE_PGM_RSRC1_GFX6_GFX11(ENABLE_DX10_CLAMP, 21, 1), + COMPUTE_PGM_RSRC1_GFX12_PLUS(ENABLE_WG_RR_EN, 21, 1), COMPUTE_PGM_RSRC1(DEBUG_MODE, 22, 1), - COMPUTE_PGM_RSRC1(ENABLE_IEEE_MODE, 23, 1), + COMPUTE_PGM_RSRC1_GFX6_GFX11(ENABLE_IEEE_MODE, 23, 1), + COMPUTE_PGM_RSRC1_GFX12_PLUS(DISABLE_PERF, 23, 1), COMPUTE_PGM_RSRC1(BULKY, 24, 1), COMPUTE_PGM_RSRC1(CDBG_USER, 25, 1), COMPUTE_PGM_RSRC1_GFX6_GFX8(RESERVED0, 26, 1), diff --git a/llvm/include/llvm/Support/AutoConvert.h b/llvm/include/llvm/Support/AutoConvert.h index bcf7473feac8..79566189d819 100644 --- a/llvm/include/llvm/Support/AutoConvert.h +++ b/llvm/include/llvm/Support/AutoConvert.h @@ -15,10 +15,26 @@ #define LLVM_SUPPORT_AUTOCONVERT_H #ifdef __MVS__ -#define CCSID_IBM_1047 1047 -#define CCSID_UTF_8 1208 +#include <_Ccsid.h> +#ifdef __cplusplus #include <system_error> +#endif // __cplusplus +#define CCSID_IBM_1047 1047 +#define CCSID_UTF_8 1208 +#define CCSID_ISO8859_1 819 + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus +int enableAutoConversion(int FD); +int disableAutoConversion(int FD); +int restoreStdHandleAutoConversion(int FD); +#ifdef __cplusplus +} +#endif // __cplusplus + +#ifdef __cplusplus namespace llvm { /// \brief Disable the z/OS enhanced ASCII auto-conversion for the file @@ -30,10 +46,14 @@ std::error_code disableAutoConversion(int FD); /// codepage. std::error_code enableAutoConversion(int FD); +/// Restore the z/OS enhanced ASCII auto-conversion for the std handle. +std::error_code restoreStdHandleAutoConversion(int FD); + /// \brief Set the tag information for a file descriptor. std::error_code setFileTag(int FD, int CCSID, bool Text); } // namespace llvm +#endif // __cplusplus #endif // __MVS__ diff --git a/llvm/include/llvm/Support/SystemZ/zOSSupport.h b/llvm/include/llvm/Support/SystemZ/zOSSupport.h index ee78147cb215..f9a61f887d5d 100644 --- a/llvm/include/llvm/Support/SystemZ/zOSSupport.h +++ b/llvm/include/llvm/Support/SystemZ/zOSSupport.h @@ -35,5 +35,13 @@ inline pid_t wait4(pid_t pid, int *wstatus, int options, return Result; } +// z/OS Unix System Services does not have strnlen() support, so the strnlen() +// function is implemented here. +inline std::size_t strnlen(const char *S, std::size_t MaxLen) { + const char *PtrToNullChar = + static_cast<const char *>(std::memchr(S, '\0', MaxLen)); + return PtrToNullChar ? PtrToNullChar - S : MaxLen; +} + #endif #endif diff --git a/llvm/include/llvm/Support/raw_ostream.h b/llvm/include/llvm/Support/raw_ostream.h index 1e01eb9ea19c..7c8d264afeff 100644 --- a/llvm/include/llvm/Support/raw_ostream.h +++ b/llvm/include/llvm/Support/raw_ostream.h @@ -16,6 +16,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/DataTypes.h" +#include "llvm/Support/Threading.h" #include <cassert> #include <cstddef> #include <cstdint> @@ -615,6 +616,8 @@ public: /// immediately destroyed. raw_fd_stream(StringRef Filename, std::error_code &EC); + raw_fd_stream(int fd, bool shouldClose); + /// This reads the \p Size bytes into a buffer pointed by \p Ptr. /// /// \param Ptr The start of the buffer to hold data to be read. @@ -631,6 +634,54 @@ public: }; //===----------------------------------------------------------------------===// +// Socket Streams +//===----------------------------------------------------------------------===// + +/// A raw stream for sockets reading/writing + +class raw_socket_stream; + +// Make sure that calls to WSAStartup and WSACleanup are balanced. +#ifdef _WIN32 +class WSABalancer { +public: + WSABalancer(); + ~WSABalancer(); +}; +#endif // _WIN32 + +class ListeningSocket { + int FD; + std::string SocketPath; + ListeningSocket(int SocketFD, StringRef SocketPath); +#ifdef _WIN32 + WSABalancer _; +#endif // _WIN32 + +public: + static Expected<ListeningSocket> createUnix( + StringRef SocketPath, + int MaxBacklog = llvm::hardware_concurrency().compute_thread_count()); + Expected<std::unique_ptr<raw_socket_stream>> accept(); + ListeningSocket(ListeningSocket &&LS); + ~ListeningSocket(); +}; +class raw_socket_stream : public raw_fd_stream { + uint64_t current_pos() const override { return 0; } +#ifdef _WIN32 + WSABalancer _; +#endif // _WIN32 + +public: + raw_socket_stream(int SocketFD); + /// Create a \p raw_socket_stream connected to the Unix domain socket at \p + /// SocketPath. + static Expected<std::unique_ptr<raw_socket_stream>> + createConnectedUnix(StringRef SocketPath); + ~raw_socket_stream(); +}; + +//===----------------------------------------------------------------------===// // Output Stream Adaptors //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Analysis/AliasSetTracker.cpp b/llvm/lib/Analysis/AliasSetTracker.cpp index debdd328ce53..99d20c7bef3b 100644 --- a/llvm/lib/Analysis/AliasSetTracker.cpp +++ b/llvm/lib/Analysis/AliasSetTracker.cpp @@ -375,9 +375,8 @@ AliasSet &AliasSetTracker::getAliasSetFor(const MemoryLocation &MemLoc) { return AliasSets.back(); } -void AliasSetTracker::add(Value *Ptr, LocationSize Size, - const AAMDNodes &AAInfo) { - addPointer(MemoryLocation(Ptr, Size, AAInfo), AliasSet::NoAccess); +void AliasSetTracker::add(const MemoryLocation &Loc) { + addPointer(Loc, AliasSet::NoAccess); } void AliasSetTracker::add(LoadInst *LI) { diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp index 9a9d06a81f49..0894560fd078 100644 --- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp +++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp @@ -666,7 +666,7 @@ public: /// Register a load and whether it is only read from. void addLoad(MemoryLocation &Loc, Type *AccessTy, bool IsReadOnly) { Value *Ptr = const_cast<Value*>(Loc.Ptr); - AST.add(Ptr, LocationSize::beforeOrAfterPointer(), Loc.AATags); + AST.add(Loc.getWithNewSize(LocationSize::beforeOrAfterPointer())); Accesses[MemAccessInfo(Ptr, false)].insert(AccessTy); if (IsReadOnly) ReadOnlyPtr.insert(Ptr); @@ -675,7 +675,7 @@ public: /// Register a store. void addStore(MemoryLocation &Loc, Type *AccessTy) { Value *Ptr = const_cast<Value*>(Loc.Ptr); - AST.add(Ptr, LocationSize::beforeOrAfterPointer(), Loc.AATags); + AST.add(Loc.getWithNewSize(LocationSize::beforeOrAfterPointer())); Accesses[MemAccessInfo(Ptr, true)].insert(AccessTy); } diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index 63b1b7567c8e..3f76dfdaac31 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -682,6 +682,11 @@ TargetTransformInfo::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, return Cost; } +bool TargetTransformInfo::preferToKeepConstantsAttached( + const Instruction &Inst, const Function &Fn) const { + return TTIImpl->preferToKeepConstantsAttached(Inst, Fn); +} + unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const { return TTIImpl->getNumberOfRegisters(ClassID); } diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp index 79a95ee0d747..7b73a7b11ddf 100644 --- a/llvm/lib/CodeGen/CodeGen.cpp +++ b/llvm/lib/CodeGen/CodeGen.cpp @@ -41,7 +41,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeEarlyTailDuplicatePass(Registry); initializeExpandLargeDivRemLegacyPassPass(Registry); initializeExpandLargeFpConvertLegacyPassPass(Registry); - initializeExpandMemCmpPassPass(Registry); + initializeExpandMemCmpLegacyPassPass(Registry); initializeExpandPostRAPass(Registry); initializeFEntryInserterPass(Registry); initializeFinalizeISelPass(Registry); @@ -53,7 +53,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeHardwareLoopsLegacyPass(Registry); initializeIfConverterPass(Registry); initializeImplicitNullChecksPass(Registry); - initializeIndirectBrExpandPassPass(Registry); + initializeIndirectBrExpandLegacyPassPass(Registry); initializeInterleavedLoadCombinePass(Registry); initializeInterleavedAccessPass(Registry); initializeJMCInstrumenterPass(Registry); diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index aa5cdd2e04a9..f9e791c73348 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -1384,7 +1384,8 @@ static bool SinkCast(CastInst *CI) { BasicBlock::iterator InsertPt = UserBB->getFirstInsertionPt(); assert(InsertPt != UserBB->end()); InsertedCast = CastInst::Create(CI->getOpcode(), CI->getOperand(0), - CI->getType(), "", &*InsertPt); + CI->getType(), ""); + InsertedCast->insertBefore(*UserBB, InsertPt); InsertedCast->setDebugLoc(CI->getDebugLoc()); } @@ -2058,12 +2059,13 @@ SinkShiftAndTruncate(BinaryOperator *ShiftI, Instruction *User, ConstantInt *CI, assert(InsertPt != TruncUserBB->end()); // Sink the shift if (ShiftI->getOpcode() == Instruction::AShr) - InsertedShift = BinaryOperator::CreateAShr(ShiftI->getOperand(0), CI, - "", &*InsertPt); + InsertedShift = + BinaryOperator::CreateAShr(ShiftI->getOperand(0), CI, ""); else - InsertedShift = BinaryOperator::CreateLShr(ShiftI->getOperand(0), CI, - "", &*InsertPt); + InsertedShift = + BinaryOperator::CreateLShr(ShiftI->getOperand(0), CI, ""); InsertedShift->setDebugLoc(ShiftI->getDebugLoc()); + InsertedShift->insertBefore(*TruncUserBB, InsertPt); // Sink the trunc BasicBlock::iterator TruncInsertPt = TruncUserBB->getFirstInsertionPt(); @@ -2162,11 +2164,12 @@ static bool OptimizeExtractBits(BinaryOperator *ShiftI, ConstantInt *CI, assert(InsertPt != UserBB->end()); if (ShiftI->getOpcode() == Instruction::AShr) - InsertedShift = BinaryOperator::CreateAShr(ShiftI->getOperand(0), CI, - "", &*InsertPt); + InsertedShift = + BinaryOperator::CreateAShr(ShiftI->getOperand(0), CI, ""); else - InsertedShift = BinaryOperator::CreateLShr(ShiftI->getOperand(0), CI, - "", &*InsertPt); + InsertedShift = + BinaryOperator::CreateLShr(ShiftI->getOperand(0), CI, ""); + InsertedShift->insertBefore(*UserBB, InsertPt); InsertedShift->setDebugLoc(ShiftI->getDebugLoc()); MadeChange = true; @@ -6628,7 +6631,8 @@ bool CodeGenPrepare::optimizeExtUses(Instruction *I) { if (!InsertedTrunc) { BasicBlock::iterator InsertPt = UserBB->getFirstInsertionPt(); assert(InsertPt != UserBB->end()); - InsertedTrunc = new TruncInst(I, Src->getType(), "", &*InsertPt); + InsertedTrunc = new TruncInst(I, Src->getType(), ""); + InsertedTrunc->insertBefore(*UserBB, InsertPt); InsertedInsts.insert(InsertedTrunc); } diff --git a/llvm/lib/CodeGen/ExpandMemCmp.cpp b/llvm/lib/CodeGen/ExpandMemCmp.cpp index e6ca14096249..bb84813569f4 100644 --- a/llvm/lib/CodeGen/ExpandMemCmp.cpp +++ b/llvm/lib/CodeGen/ExpandMemCmp.cpp @@ -11,6 +11,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/ExpandMemCmp.h" #include "llvm/ADT/Statistic.h" #include "llvm/Analysis/ConstantFolding.h" #include "llvm/Analysis/DomTreeUpdater.h" @@ -38,7 +39,7 @@ namespace llvm { class TargetLowering; } -#define DEBUG_TYPE "expandmemcmp" +#define DEBUG_TYPE "expand-memcmp" STATISTIC(NumMemCmpCalls, "Number of memcmp calls"); STATISTIC(NumMemCmpNotConstant, "Number of memcmp calls without constant size"); @@ -886,12 +887,24 @@ static bool expandMemCmp(CallInst *CI, const TargetTransformInfo *TTI, return true; } -class ExpandMemCmpPass : public FunctionPass { +// Returns true if a change was made. +static bool runOnBlock(BasicBlock &BB, const TargetLibraryInfo *TLI, + const TargetTransformInfo *TTI, const TargetLowering *TL, + const DataLayout &DL, ProfileSummaryInfo *PSI, + BlockFrequencyInfo *BFI, DomTreeUpdater *DTU); + +static PreservedAnalyses runImpl(Function &F, const TargetLibraryInfo *TLI, + const TargetTransformInfo *TTI, + const TargetLowering *TL, + ProfileSummaryInfo *PSI, + BlockFrequencyInfo *BFI, DominatorTree *DT); + +class ExpandMemCmpLegacyPass : public FunctionPass { public: static char ID; - ExpandMemCmpPass() : FunctionPass(ID) { - initializeExpandMemCmpPassPass(*PassRegistry::getPassRegistry()); + ExpandMemCmpLegacyPass() : FunctionPass(ID) { + initializeExpandMemCmpLegacyPassPass(*PassRegistry::getPassRegistry()); } bool runOnFunction(Function &F) override { @@ -928,25 +941,13 @@ private: LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU); FunctionPass::getAnalysisUsage(AU); } - - PreservedAnalyses runImpl(Function &F, const TargetLibraryInfo *TLI, - const TargetTransformInfo *TTI, - const TargetLowering *TL, ProfileSummaryInfo *PSI, - BlockFrequencyInfo *BFI, DominatorTree *DT); - // Returns true if a change was made. - bool runOnBlock(BasicBlock &BB, const TargetLibraryInfo *TLI, - const TargetTransformInfo *TTI, const TargetLowering *TL, - const DataLayout &DL, ProfileSummaryInfo *PSI, - BlockFrequencyInfo *BFI, DomTreeUpdater *DTU); }; -bool ExpandMemCmpPass::runOnBlock(BasicBlock &BB, const TargetLibraryInfo *TLI, - const TargetTransformInfo *TTI, - const TargetLowering *TL, - const DataLayout &DL, ProfileSummaryInfo *PSI, - BlockFrequencyInfo *BFI, - DomTreeUpdater *DTU) { - for (Instruction& I : BB) { +bool runOnBlock(BasicBlock &BB, const TargetLibraryInfo *TLI, + const TargetTransformInfo *TTI, const TargetLowering *TL, + const DataLayout &DL, ProfileSummaryInfo *PSI, + BlockFrequencyInfo *BFI, DomTreeUpdater *DTU) { + for (Instruction &I : BB) { CallInst *CI = dyn_cast<CallInst>(&I); if (!CI) { continue; @@ -961,8 +962,7 @@ bool ExpandMemCmpPass::runOnBlock(BasicBlock &BB, const TargetLibraryInfo *TLI, return false; } -PreservedAnalyses -ExpandMemCmpPass::runImpl(Function &F, const TargetLibraryInfo *TLI, +PreservedAnalyses runImpl(Function &F, const TargetLibraryInfo *TLI, const TargetTransformInfo *TTI, const TargetLowering *TL, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI, DominatorTree *DT) { @@ -994,17 +994,32 @@ ExpandMemCmpPass::runImpl(Function &F, const TargetLibraryInfo *TLI, } // namespace -char ExpandMemCmpPass::ID = 0; -INITIALIZE_PASS_BEGIN(ExpandMemCmpPass, "expandmemcmp", +PreservedAnalyses ExpandMemCmpPass::run(Function &F, + FunctionAnalysisManager &FAM) { + const auto *TL = TM->getSubtargetImpl(F)->getTargetLowering(); + const auto &TLI = FAM.getResult<TargetLibraryAnalysis>(F); + const auto &TTI = FAM.getResult<TargetIRAnalysis>(F); + auto *PSI = FAM.getResult<ModuleAnalysisManagerFunctionProxy>(F) + .getCachedResult<ProfileSummaryAnalysis>(*F.getParent()); + BlockFrequencyInfo *BFI = (PSI && PSI->hasProfileSummary()) + ? &FAM.getResult<BlockFrequencyAnalysis>(F) + : nullptr; + auto *DT = FAM.getCachedResult<DominatorTreeAnalysis>(F); + + return runImpl(F, &TLI, &TTI, TL, PSI, BFI, DT); +} + +char ExpandMemCmpLegacyPass::ID = 0; +INITIALIZE_PASS_BEGIN(ExpandMemCmpLegacyPass, DEBUG_TYPE, "Expand memcmp() to load/stores", false, false) INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(LazyBlockFrequencyInfoPass) INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass) INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) -INITIALIZE_PASS_END(ExpandMemCmpPass, "expandmemcmp", +INITIALIZE_PASS_END(ExpandMemCmpLegacyPass, DEBUG_TYPE, "Expand memcmp() to load/stores", false, false) -FunctionPass *llvm::createExpandMemCmpPass() { - return new ExpandMemCmpPass(); +FunctionPass *llvm::createExpandMemCmpLegacyPass() { + return new ExpandMemCmpLegacyPass(); } diff --git a/llvm/lib/CodeGen/GCMetadata.cpp b/llvm/lib/CodeGen/GCMetadata.cpp index 49e03b4b132c..cad7d1f1137b 100644 --- a/llvm/lib/CodeGen/GCMetadata.cpp +++ b/llvm/lib/CodeGen/GCMetadata.cpp @@ -24,6 +24,50 @@ using namespace llvm; +bool GCStrategyMap::invalidate(Module &M, const PreservedAnalyses &PA, + ModuleAnalysisManager::Invalidator &) { + for (const auto &F : M) { + if (F.isDeclaration() || !F.hasGC()) + continue; + if (!StrategyMap.contains(F.getGC())) + return true; + } + return false; +} + +AnalysisKey CollectorMetadataAnalysis::Key; + +CollectorMetadataAnalysis::Result +CollectorMetadataAnalysis::run(Module &M, ModuleAnalysisManager &MAM) { + Result R; + auto &Map = R.StrategyMap; + for (auto &F : M) { + if (F.isDeclaration() || !F.hasGC()) + continue; + if (auto GCName = F.getGC(); !Map.contains(GCName)) + Map[GCName] = getGCStrategy(GCName); + } + return R; +} + +AnalysisKey GCFunctionAnalysis::Key; + +GCFunctionAnalysis::Result +GCFunctionAnalysis::run(Function &F, FunctionAnalysisManager &FAM) { + assert(!F.isDeclaration() && "Can only get GCFunctionInfo for a definition!"); + assert(F.hasGC() && "Function doesn't have GC!"); + + auto &MAMProxy = FAM.getResult<ModuleAnalysisManagerFunctionProxy>(F); + assert( + MAMProxy.cachedResultExists<CollectorMetadataAnalysis>(*F.getParent()) && + "This pass need module analysis `collector-metadata`!"); + auto &Map = + MAMProxy.getCachedResult<CollectorMetadataAnalysis>(*F.getParent()) + ->StrategyMap; + GCFunctionInfo Info(F, *Map[F.getGC()]); + return Info; +} + INITIALIZE_PASS(GCModuleInfo, "collector-metadata", "Create Garbage Collector Module Metadata", false, false) @@ -34,6 +78,12 @@ GCFunctionInfo::GCFunctionInfo(const Function &F, GCStrategy &S) GCFunctionInfo::~GCFunctionInfo() = default; +bool GCFunctionInfo::invalidate(Function &F, const PreservedAnalyses &PA, + FunctionAnalysisManager::Invalidator &) { + auto PAC = PA.getChecker<GCFunctionAnalysis>(); + return !PAC.preserved() && !PAC.preservedSet<AllAnalysesOn<Function>>(); +} + // ----------------------------------------------------------------------------- char GCModuleInfo::ID = 0; diff --git a/llvm/lib/CodeGen/IndirectBrExpandPass.cpp b/llvm/lib/CodeGen/IndirectBrExpandPass.cpp index 012892166ae7..f7b931a3bdac 100644 --- a/llvm/lib/CodeGen/IndirectBrExpandPass.cpp +++ b/llvm/lib/CodeGen/IndirectBrExpandPass.cpp @@ -29,6 +29,7 @@ #include "llvm/ADT/Sequence.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Analysis/DomTreeUpdater.h" +#include "llvm/CodeGen/IndirectBrExpand.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/BasicBlock.h" @@ -48,14 +49,12 @@ using namespace llvm; namespace { -class IndirectBrExpandPass : public FunctionPass { - const TargetLowering *TLI = nullptr; - +class IndirectBrExpandLegacyPass : public FunctionPass { public: static char ID; // Pass identification, replacement for typeid - IndirectBrExpandPass() : FunctionPass(ID) { - initializeIndirectBrExpandPassPass(*PassRegistry::getPassRegistry()); + IndirectBrExpandLegacyPass() : FunctionPass(ID) { + initializeIndirectBrExpandLegacyPassPass(*PassRegistry::getPassRegistry()); } void getAnalysisUsage(AnalysisUsage &AU) const override { @@ -67,33 +66,41 @@ public: } // end anonymous namespace -char IndirectBrExpandPass::ID = 0; +static bool runImpl(Function &F, const TargetLowering *TLI, + DomTreeUpdater *DTU); + +PreservedAnalyses IndirectBrExpandPass::run(Function &F, + FunctionAnalysisManager &FAM) { + auto *STI = TM->getSubtargetImpl(F); + if (!STI->enableIndirectBrExpand()) + return PreservedAnalyses::all(); + + auto *TLI = STI->getTargetLowering(); + auto *DT = FAM.getCachedResult<DominatorTreeAnalysis>(F); + DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Lazy); + + bool Changed = runImpl(F, TLI, DT ? &DTU : nullptr); + if (!Changed) + return PreservedAnalyses::all(); + PreservedAnalyses PA; + PA.preserve<DominatorTreeAnalysis>(); + return PA; +} + +char IndirectBrExpandLegacyPass::ID = 0; -INITIALIZE_PASS_BEGIN(IndirectBrExpandPass, DEBUG_TYPE, +INITIALIZE_PASS_BEGIN(IndirectBrExpandLegacyPass, DEBUG_TYPE, "Expand indirectbr instructions", false, false) INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) -INITIALIZE_PASS_END(IndirectBrExpandPass, DEBUG_TYPE, +INITIALIZE_PASS_END(IndirectBrExpandLegacyPass, DEBUG_TYPE, "Expand indirectbr instructions", false, false) FunctionPass *llvm::createIndirectBrExpandPass() { - return new IndirectBrExpandPass(); + return new IndirectBrExpandLegacyPass(); } -bool IndirectBrExpandPass::runOnFunction(Function &F) { +bool runImpl(Function &F, const TargetLowering *TLI, DomTreeUpdater *DTU) { auto &DL = F.getParent()->getDataLayout(); - auto *TPC = getAnalysisIfAvailable<TargetPassConfig>(); - if (!TPC) - return false; - - auto &TM = TPC->getTM<TargetMachine>(); - auto &STI = *TM.getSubtargetImpl(F); - if (!STI.enableIndirectBrExpand()) - return false; - TLI = STI.getTargetLowering(); - - std::optional<DomTreeUpdater> DTU; - if (auto *DTWP = getAnalysisIfAvailable<DominatorTreeWrapperPass>()) - DTU.emplace(DTWP->getDomTree(), DomTreeUpdater::UpdateStrategy::Lazy); SmallVector<IndirectBrInst *, 1> IndirectBrs; @@ -268,3 +275,21 @@ bool IndirectBrExpandPass::runOnFunction(Function &F) { return true; } + +bool IndirectBrExpandLegacyPass::runOnFunction(Function &F) { + auto *TPC = getAnalysisIfAvailable<TargetPassConfig>(); + if (!TPC) + return false; + + auto &TM = TPC->getTM<TargetMachine>(); + auto &STI = *TM.getSubtargetImpl(F); + if (!STI.enableIndirectBrExpand()) + return false; + auto *TLI = STI.getTargetLowering(); + + std::optional<DomTreeUpdater> DTU; + if (auto *DTWP = getAnalysisIfAvailable<DominatorTreeWrapperPass>()) + DTU.emplace(DTWP->getDomTree(), DomTreeUpdater::UpdateStrategy::Lazy); + + return runImpl(F, TLI, DTU ? &*DTU : nullptr); +} diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp index 83d775055dfd..e7e8f6026834 100644 --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -500,11 +500,6 @@ bool MachineSinking::PerformSinkAndFold(MachineInstr &MI, return false; // Now we know we can fold the instruction in all its users. - if (UsedRegA) - MRI->clearKillFlags(UsedRegA); - if (UsedRegB) - MRI->clearKillFlags(UsedRegB); - for (auto &[SinkDst, MaybeAM] : SinkInto) { MachineInstr *New = nullptr; LLVM_DEBUG(dbgs() << "Sinking copy of"; MI.dump(); dbgs() << "into"; @@ -527,9 +522,25 @@ bool MachineSinking::PerformSinkAndFold(MachineInstr &MI, New = &*std::prev(InsertPt); if (!New->getDebugLoc()) New->setDebugLoc(SinkDst->getDebugLoc()); + + // The operand registers of the "sunk" instruction have their live range + // extended and their kill flags may no longer be correct. Conservatively + // clear the kill flags. + if (UsedRegA) + MRI->clearKillFlags(UsedRegA); + if (UsedRegB) + MRI->clearKillFlags(UsedRegB); } else { // Fold instruction into the addressing mode of a memory instruction. New = TII->emitLdStWithAddr(*SinkDst, MaybeAM); + + // The registers of the addressing mode may have their live range extended + // and their kill flags may no longer be correct. Conservatively clear the + // kill flags. + if (Register R = MaybeAM.BaseReg; R.isValid() && R.isVirtual()) + MRI->clearKillFlags(R); + if (Register R = MaybeAM.ScaledReg; R.isValid() && R.isVirtual()) + MRI->clearKillFlags(R); } LLVM_DEBUG(dbgs() << "yielding"; New->dump()); // Clear the StoreInstrCache, since we may invalidate it by erasing. diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index c067d87a9fd8..c1af37c8510f 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -1201,6 +1201,8 @@ bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP, << printMBBReference(MBB) << '\t' << CopyMI); } + const bool IsUndefCopy = CopyMI.getOperand(1).isUndef(); + // Remove CopyMI. // Note: This is fine to remove the copy before updating the live-ranges. // While updating the live-ranges, we only look at slot indices and @@ -1214,6 +1216,19 @@ bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP, LIS->pruneValue(*static_cast<LiveRange *>(&IntB), CopyIdx.getRegSlot(), &EndPoints); BValNo->markUnused(); + + if (IsUndefCopy) { + // We're introducing an undef phi def, and need to set undef on any users of + // the previously local def to avoid artifically extending the lifetime + // through the block. + for (MachineOperand &MO : MRI->use_nodbg_operands(IntB.reg())) { + const MachineInstr &MI = *MO.getParent(); + SlotIndex UseIdx = LIS->getInstructionIndex(MI); + if (!IntB.liveAt(UseIdx)) + MO.setIsUndef(true); + } + } + // Extend IntB to the EndPoints of its original live interval. LIS->extendToIndices(IntB, EndPoints); @@ -1596,8 +1611,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP, LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator()); } - if (NewMI.getOperand(0).getSubReg()) - NewMI.getOperand(0).setIsUndef(); + NewMI.setRegisterDefReadUndef(NewMI.getOperand(0).getReg()); // Transfer over implicit operands to the rematerialized instruction. for (MachineOperand &MO : ImplicitOps) diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index b82fe5fb99f9..f15d59d4e35b 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -868,7 +868,7 @@ void TargetPassConfig::addIRPasses() { // target lowering hook. if (!DisableMergeICmps) addPass(createMergeICmpsLegacyPass()); - addPass(createExpandMemCmpPass()); + addPass(createExpandMemCmpLegacyPass()); } // Run GC lowering passes for builtin collectors diff --git a/llvm/lib/IR/BasicBlock.cpp b/llvm/lib/IR/BasicBlock.cpp index f364c56a42c5..03b74b0480f0 100644 --- a/llvm/lib/IR/BasicBlock.cpp +++ b/llvm/lib/IR/BasicBlock.cpp @@ -73,7 +73,10 @@ void BasicBlock::convertToNewDbgValues() { SmallVector<DPValue *, 4> DPVals; for (Instruction &I : make_early_inc_range(InstList)) { assert(!I.DbgMarker && "DbgMarker already set on old-format instrs?"); - if (DbgValueInst *DVI = dyn_cast<DbgValueInst>(&I)) { + if (DbgVariableIntrinsic *DVI = dyn_cast<DbgVariableIntrinsic>(&I)) { + if (isa<DbgAssignIntrinsic>(DVI)) + continue; + // Convert this dbg.value to a DPValue. DPValue *Value = new DPValue(DVI); DPVals.push_back(Value); @@ -1088,6 +1091,8 @@ void BasicBlock::insertDPValueBefore(DPValue *DPV, // shouldn't be generated at times when there's no terminator. assert(Where != end()); assert(Where->getParent() == this); + if (!Where->DbgMarker) + createMarker(Where); bool InsertAtHead = Where.getHeadBit(); Where->DbgMarker->insertDPValue(DPV, InsertAtHead); } diff --git a/llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp b/llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp index 067ef39d9052..a3d4ba3a94f7 100644 --- a/llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp +++ b/llvm/lib/ObjCopy/MachO/MachOLayoutBuilder.cpp @@ -10,6 +10,7 @@ #include "llvm/Support/Alignment.h" #include "llvm/Support/Errc.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/SystemZ/zOSSupport.h" using namespace llvm; using namespace llvm::objcopy::macho; diff --git a/llvm/lib/ObjCopy/MachO/MachOObject.cpp b/llvm/lib/ObjCopy/MachO/MachOObject.cpp index 9a4abadc8710..d593d6788e11 100644 --- a/llvm/lib/ObjCopy/MachO/MachOObject.cpp +++ b/llvm/lib/ObjCopy/MachO/MachOObject.cpp @@ -8,6 +8,7 @@ #include "MachOObject.h" #include "llvm/ADT/SmallPtrSet.h" +#include "llvm/Support/SystemZ/zOSSupport.h" #include <unordered_set> using namespace llvm; diff --git a/llvm/lib/ObjCopy/MachO/MachOReader.cpp b/llvm/lib/ObjCopy/MachO/MachOReader.cpp index 25f8c020cde9..4549977c12c3 100644 --- a/llvm/lib/ObjCopy/MachO/MachOReader.cpp +++ b/llvm/lib/ObjCopy/MachO/MachOReader.cpp @@ -11,6 +11,7 @@ #include "llvm/BinaryFormat/MachO.h" #include "llvm/Object/MachO.h" #include "llvm/Support/Errc.h" +#include "llvm/Support/SystemZ/zOSSupport.h" #include <memory> using namespace llvm; diff --git a/llvm/lib/ObjectYAML/MachOEmitter.cpp b/llvm/lib/ObjectYAML/MachOEmitter.cpp index 6bcc2cee27ed..c08b389daea9 100644 --- a/llvm/lib/ObjectYAML/MachOEmitter.cpp +++ b/llvm/lib/ObjectYAML/MachOEmitter.cpp @@ -19,6 +19,7 @@ #include "llvm/Support/Error.h" #include "llvm/Support/FormatVariadic.h" #include "llvm/Support/LEB128.h" +#include "llvm/Support/SystemZ/zOSSupport.h" #include "llvm/Support/YAMLTraits.h" #include "llvm/Support/raw_ostream.h" diff --git a/llvm/lib/ObjectYAML/MachOYAML.cpp b/llvm/lib/ObjectYAML/MachOYAML.cpp index 86342c5501c7..82b2eaecec9b 100644 --- a/llvm/lib/ObjectYAML/MachOYAML.cpp +++ b/llvm/lib/ObjectYAML/MachOYAML.cpp @@ -14,6 +14,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/BinaryFormat/MachO.h" #include "llvm/Support/Format.h" +#include "llvm/Support/SystemZ/zOSSupport.h" #include "llvm/Support/YAMLTraits.h" #include "llvm/Support/raw_ostream.h" #include "llvm/TargetParser/Host.h" diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 302fac68782c..95b9fb7ad735 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -76,7 +76,10 @@ #include "llvm/CodeGen/DwarfEHPrepare.h" #include "llvm/CodeGen/ExpandLargeDivRem.h" #include "llvm/CodeGen/ExpandLargeFpConvert.h" +#include "llvm/CodeGen/ExpandMemCmp.h" +#include "llvm/CodeGen/GCMetadata.h" #include "llvm/CodeGen/HardwareLoops.h" +#include "llvm/CodeGen/IndirectBrExpand.h" #include "llvm/CodeGen/InterleavedAccess.h" #include "llvm/CodeGen/InterleavedLoadCombine.h" #include "llvm/CodeGen/JMCInstrumenter.h" diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def index 746446d61325..d8fc7cd8a231 100644 --- a/llvm/lib/Passes/PassRegistry.def +++ b/llvm/lib/Passes/PassRegistry.def @@ -19,6 +19,7 @@ #define MODULE_ANALYSIS(NAME, CREATE_PASS) #endif MODULE_ANALYSIS("callgraph", CallGraphAnalysis()) +MODULE_ANALYSIS("collector-metadata", CollectorMetadataAnalysis()) MODULE_ANALYSIS("inline-advisor", InlineAdvisorAnalysis()) MODULE_ANALYSIS("ir-similarity", IRSimilarityAnalysis()) MODULE_ANALYSIS("lcg", LazyCallGraphAnalysis()) @@ -235,6 +236,7 @@ FUNCTION_ANALYSIS("demanded-bits", DemandedBitsAnalysis()) FUNCTION_ANALYSIS("domfrontier", DominanceFrontierAnalysis()) FUNCTION_ANALYSIS("domtree", DominatorTreeAnalysis()) FUNCTION_ANALYSIS("func-properties", FunctionPropertiesAnalysis()) +FUNCTION_ANALYSIS("gc-function", GCFunctionAnalysis()) FUNCTION_ANALYSIS("inliner-size-estimator", InlineSizeEstimatorAnalysis()) FUNCTION_ANALYSIS("lazy-value-info", LazyValueAnalysis()) FUNCTION_ANALYSIS("loops", LoopAnalysis()) @@ -306,6 +308,7 @@ FUNCTION_PASS("dse", DSEPass()) FUNCTION_PASS("dwarf-eh-prepare", DwarfEHPreparePass(TM)) FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass(TM)) FUNCTION_PASS("expand-large-fp-convert", ExpandLargeFpConvertPass(TM)) +FUNCTION_PASS("expand-memcmp", ExpandMemCmpPass(TM)) FUNCTION_PASS("fix-irreducible", FixIrreduciblePass()) FUNCTION_PASS("flattencfg", FlattenCFGPass()) FUNCTION_PASS("float2int", Float2IntPass()) @@ -313,6 +316,7 @@ FUNCTION_PASS("guard-widening", GuardWideningPass()) FUNCTION_PASS("gvn-hoist", GVNHoistPass()) FUNCTION_PASS("gvn-sink", GVNSinkPass()) FUNCTION_PASS("helloworld", HelloWorldPass()) +FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass(TM)) FUNCTION_PASS("infer-address-spaces", InferAddressSpacesPass()) FUNCTION_PASS("infer-alignment", InferAlignmentPass()) FUNCTION_PASS("inject-tli-mappings", InjectTLIMappings()) diff --git a/llvm/lib/Support/AutoConvert.cpp b/llvm/lib/Support/AutoConvert.cpp index 4fb7e242c348..8170e553ac6e 100644 --- a/llvm/lib/Support/AutoConvert.cpp +++ b/llvm/lib/Support/AutoConvert.cpp @@ -14,21 +14,36 @@ #ifdef __MVS__ #include "llvm/Support/AutoConvert.h" +#include <cassert> #include <fcntl.h> #include <sys/stat.h> +#include <unistd.h> -std::error_code llvm::disableAutoConversion(int FD) { +static int savedStdHandleAutoConversionMode[3] = {-1, -1, -1}; + +int disableAutoConversion(int FD) { static const struct f_cnvrt Convert = { - SETCVTOFF, // cvtcmd - 0, // pccsid - (short)FT_BINARY, // fccsid + SETCVTOFF, // cvtcmd + 0, // pccsid + 0, // fccsid }; - if (fcntl(FD, F_CONTROL_CVT, &Convert) == -1) - return std::error_code(errno, std::generic_category()); - return std::error_code(); + + return fcntl(FD, F_CONTROL_CVT, &Convert); } -std::error_code llvm::enableAutoConversion(int FD) { +int restoreStdHandleAutoConversion(int FD) { + assert(FD == STDIN_FILENO || FD == STDOUT_FILENO || FD == STDERR_FILENO); + if (savedStdHandleAutoConversionMode[FD] == -1) + return 0; + struct f_cnvrt Cvt = { + savedStdHandleAutoConversionMode[FD], // cvtcmd + 0, // pccsid + 0, // fccsid + }; + return (fcntl(FD, F_CONTROL_CVT, &Cvt)); +} + +int enableAutoConversion(int FD) { struct f_cnvrt Query = { QUERYCVT, // cvtcmd 0, // pccsid @@ -36,17 +51,53 @@ std::error_code llvm::enableAutoConversion(int FD) { }; if (fcntl(FD, F_CONTROL_CVT, &Query) == -1) - return std::error_code(errno, std::generic_category()); + return -1; + + // We don't need conversion for UTF-8 tagged files. + // TODO: Remove the assumption of ISO8859-1 = UTF-8 here when we fully resolve + // problems related to UTF-8 tagged source files. + // When the pccsid is not ISO8859-1, autoconversion is still needed. + if (Query.pccsid == CCSID_ISO8859_1 && + (Query.fccsid == CCSID_UTF_8 || Query.fccsid == CCSID_ISO8859_1)) + return 0; + + // Save the state of std handles before we make changes to it. + if ((FD == STDIN_FILENO || FD == STDOUT_FILENO || FD == STDERR_FILENO) && + savedStdHandleAutoConversionMode[FD] == -1) + savedStdHandleAutoConversionMode[FD] = Query.cvtcmd; + + if (FD == STDOUT_FILENO || FD == STDERR_FILENO) + Query.cvtcmd = SETCVTON; + else + Query.cvtcmd = SETCVTALL; - Query.cvtcmd = SETCVTALL; Query.pccsid = (FD == STDIN_FILENO || FD == STDOUT_FILENO || FD == STDERR_FILENO) ? 0 : CCSID_UTF_8; // Assume untagged files to be IBM-1047 encoded. Query.fccsid = (Query.fccsid == FT_UNTAGGED) ? CCSID_IBM_1047 : Query.fccsid; - if (fcntl(FD, F_CONTROL_CVT, &Query) == -1) + return fcntl(FD, F_CONTROL_CVT, &Query); +} + +std::error_code llvm::disableAutoConversion(int FD) { + if (::disableAutoConversion(FD) == -1) + return std::error_code(errno, std::generic_category()); + + return std::error_code(); +} + +std::error_code llvm::enableAutoConversion(int FD) { + if (::enableAutoConversion(FD) == -1) return std::error_code(errno, std::generic_category()); + + return std::error_code(); +} + +std::error_code llvm::restoreStdHandleAutoConversion(int FD) { + if (::restoreStdHandleAutoConversion(FD) == -1) + return std::error_code(errno, std::generic_category()); + return std::error_code(); } diff --git a/llvm/lib/Support/CMakeLists.txt b/llvm/lib/Support/CMakeLists.txt index b96d62c7a622..80854d1d09d9 100644 --- a/llvm/lib/Support/CMakeLists.txt +++ b/llvm/lib/Support/CMakeLists.txt @@ -40,7 +40,7 @@ endif() if( MSVC OR MINGW ) # libuuid required for FOLDERID_Profile usage in lib/Support/Windows/Path.inc. # advapi32 required for CryptAcquireContextW in lib/Support/Windows/Path.inc. - set(system_libs ${system_libs} psapi shell32 ole32 uuid advapi32) + set(system_libs ${system_libs} psapi shell32 ole32 uuid advapi32 Ws2_32) elseif( CMAKE_HOST_UNIX ) if( HAVE_LIBRT ) set(system_libs ${system_libs} rt) diff --git a/llvm/lib/Support/InitLLVM.cpp b/llvm/lib/Support/InitLLVM.cpp index 2b7173b28940..7f475f42f3cb 100644 --- a/llvm/lib/Support/InitLLVM.cpp +++ b/llvm/lib/Support/InitLLVM.cpp @@ -8,6 +8,8 @@ #include "llvm/Support/InitLLVM.h" #include "llvm/ADT/StringRef.h" +#include "llvm/Support/AutoConvert.h" +#include "llvm/Support/Error.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/PrettyStackTrace.h" @@ -15,15 +17,31 @@ #include "llvm/Support/SwapByteOrder.h" #ifdef _WIN32 -#include "llvm/Support/Error.h" #include "llvm/Support/Windows/WindowsSupport.h" #endif +#ifdef __MVS__ +#include <unistd.h> + +void CleanupStdHandles(void *Cookie) { + llvm::raw_ostream *Outs = &llvm::outs(), *Errs = &llvm::errs(); + Outs->flush(); + Errs->flush(); + llvm::restoreStdHandleAutoConversion(STDIN_FILENO); + llvm::restoreStdHandleAutoConversion(STDOUT_FILENO); + llvm::restoreStdHandleAutoConversion(STDERR_FILENO); +} +#endif + using namespace llvm; using namespace llvm::sys; InitLLVM::InitLLVM(int &Argc, const char **&Argv, bool InstallPipeSignalExitHandler) { +#ifdef __MVS__ + // Bring stdin/stdout/stderr into a known state. + sys::AddSignalHandler(CleanupStdHandles, nullptr); +#endif if (InstallPipeSignalExitHandler) // The pipe signal handler must be installed before any other handlers are // registered. This is because the Unix \ref RegisterHandlers function does @@ -37,6 +55,20 @@ InitLLVM::InitLLVM(int &Argc, const char **&Argv, sys::PrintStackTraceOnErrorSignal(Argv[0]); install_out_of_memory_new_handler(); +#ifdef __MVS__ + + // We use UTF-8 as the internal character encoding. On z/OS, all external + // output is encoded in EBCDIC. In order to be able to read all + // error messages, we turn conversion to EBCDIC on for stderr fd. + std::string Banner = std::string(Argv[0]) + ": "; + ExitOnError ExitOnErr(Banner); + + // If turning on conversion for stderr fails then the error message + // may be garbled. There is no solution to this problem. + ExitOnErr(errorCodeToError(llvm::enableAutoConversion(STDERR_FILENO))); + ExitOnErr(errorCodeToError(llvm::enableAutoConversion(STDOUT_FILENO))); +#endif + #ifdef _WIN32 // We use UTF-8 as the internal character encoding. On Windows, // arguments passed to main() may not be encoded in UTF-8. In order @@ -61,4 +93,9 @@ InitLLVM::InitLLVM(int &Argc, const char **&Argv, #endif } -InitLLVM::~InitLLVM() { llvm_shutdown(); } +InitLLVM::~InitLLVM() { +#ifdef __MVS__ + CleanupStdHandles(nullptr); +#endif + llvm_shutdown(); +} diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 632274843006..85c34dd62063 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -174,7 +174,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zfbfmin", RISCVExtensionVersion{0, 8}}, - {"zicfilp", RISCVExtensionVersion{0, 2}}, + {"zicfilp", RISCVExtensionVersion{0, 4}}, {"zicond", RISCVExtensionVersion{1, 0}}, {"ztso", RISCVExtensionVersion{0, 1}}, diff --git a/llvm/lib/Support/Unix/Program.inc b/llvm/lib/Support/Unix/Program.inc index 895fdfc711e5..260719b2b58d 100644 --- a/llvm/lib/Support/Unix/Program.inc +++ b/llvm/lib/Support/Unix/Program.inc @@ -20,6 +20,7 @@ #include "Unix.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Config/config.h" +#include "llvm/Support/AutoConvert.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Errc.h" #include "llvm/Support/FileSystem.h" @@ -521,8 +522,12 @@ std::error_code llvm::sys::ChangeStdoutMode(fs::OpenFlags Flags) { } std::error_code llvm::sys::ChangeStdinToBinary() { +#ifdef __MVS__ + return disableAutoConversion(STDIN_FILENO); +#else // Do nothing, as Unix doesn't differentiate between text and binary. return std::error_code(); +#endif } std::error_code llvm::sys::ChangeStdoutToBinary() { diff --git a/llvm/lib/Support/raw_ostream.cpp b/llvm/lib/Support/raw_ostream.cpp index 8908e7b6a150..d7a1f91a27de 100644 --- a/llvm/lib/Support/raw_ostream.cpp +++ b/llvm/lib/Support/raw_ostream.cpp @@ -13,8 +13,10 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Config/config.h" +#include "llvm/Support/AutoConvert.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Duration.h" +#include "llvm/Support/Error.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Format.h" @@ -23,11 +25,17 @@ #include "llvm/Support/NativeFormatting.h" #include "llvm/Support/Process.h" #include "llvm/Support/Program.h" +#include "llvm/Support/Threading.h" #include <algorithm> #include <cerrno> #include <cstdio> #include <sys/stat.h> +#ifndef _WIN32 +#include <sys/socket.h> +#include <sys/un.h> +#endif // _WIN32 + // <fcntl.h> may provide O_BINARY. #if defined(HAVE_FCNTL_H) # include <fcntl.h> @@ -58,6 +66,13 @@ #include "llvm/Support/ConvertUTF.h" #include "llvm/Support/Signals.h" #include "llvm/Support/Windows/WindowsSupport.h" +// winsock2.h must be included before afunix.h. Briefly turn off clang-format to +// avoid error. +// clang-format off +#include <winsock2.h> +#include <afunix.h> +// clang-format on +#include <io.h> #endif using namespace llvm; @@ -644,7 +659,7 @@ raw_fd_ostream::raw_fd_ostream(int fd, bool shouldClose, bool unbuffered, // Check if this is a console device. This is not equivalent to isatty. IsWindowsConsole = ::GetFileType((HANDLE)::_get_osfhandle(fd)) == FILE_TYPE_CHAR; -#endif +#endif // _WIN32 // Get the starting position. off_t loc = ::lseek(FD, 0, SEEK_CUR); @@ -895,6 +910,10 @@ void raw_fd_ostream::anchor() {} raw_fd_ostream &llvm::outs() { // Set buffer settings to model stdout behavior. std::error_code EC; +#ifdef __MVS__ + EC = enableAutoConversion(STDOUT_FILENO); + assert(!EC); +#endif static raw_fd_ostream S("-", EC, sys::fs::OF_None); assert(!EC); return S; @@ -902,6 +921,10 @@ raw_fd_ostream &llvm::outs() { raw_fd_ostream &llvm::errs() { // Set standard error to be unbuffered and tied to outs() by default. +#ifdef __MVS__ + std::error_code EC = enableAutoConversion(STDOUT_FILENO); + assert(!EC); +#endif static raw_fd_ostream S(STDERR_FILENO, false, true); return S; } @@ -928,6 +951,9 @@ raw_fd_stream::raw_fd_stream(StringRef Filename, std::error_code &EC) EC = std::make_error_code(std::errc::invalid_argument); } +raw_fd_stream::raw_fd_stream(int fd, bool shouldClose) + : raw_fd_ostream(fd, shouldClose, false, OStreamKind::OK_FDStream) {} + ssize_t raw_fd_stream::read(char *Ptr, size_t Size) { assert(get_fd() >= 0 && "File already closed."); ssize_t Ret = ::read(get_fd(), (void *)Ptr, Size); @@ -943,6 +969,145 @@ bool raw_fd_stream::classof(const raw_ostream *OS) { } //===----------------------------------------------------------------------===// +// raw_socket_stream +//===----------------------------------------------------------------------===// + +#ifdef _WIN32 +WSABalancer::WSABalancer() { + WSADATA WsaData = {0}; + if (WSAStartup(MAKEWORD(2, 2), &WsaData) != 0) { + llvm::report_fatal_error("WSAStartup failed"); + } +} + +WSABalancer::~WSABalancer() { WSACleanup(); } + +#endif // _WIN32 + +static std::error_code getLastSocketErrorCode() { +#ifdef _WIN32 + return std::error_code(::WSAGetLastError(), std::system_category()); +#else + return std::error_code(errno, std::system_category()); +#endif +} + +ListeningSocket::ListeningSocket(int SocketFD, StringRef SocketPath) + : FD(SocketFD), SocketPath(SocketPath) {} + +ListeningSocket::ListeningSocket(ListeningSocket &&LS) + : FD(LS.FD), SocketPath(LS.SocketPath) { + LS.FD = -1; +} + +Expected<ListeningSocket> ListeningSocket::createUnix(StringRef SocketPath, + int MaxBacklog) { + +#ifdef _WIN32 + WSABalancer _; + SOCKET MaybeWinsocket = socket(AF_UNIX, SOCK_STREAM, 0); + if (MaybeWinsocket == INVALID_SOCKET) { +#else + int MaybeWinsocket = socket(AF_UNIX, SOCK_STREAM, 0); + if (MaybeWinsocket == -1) { +#endif + return llvm::make_error<StringError>(getLastSocketErrorCode(), + "socket create failed"); + } + + struct sockaddr_un Addr; + memset(&Addr, 0, sizeof(Addr)); + Addr.sun_family = AF_UNIX; + strncpy(Addr.sun_path, SocketPath.str().c_str(), sizeof(Addr.sun_path) - 1); + + if (bind(MaybeWinsocket, (struct sockaddr *)&Addr, sizeof(Addr)) == -1) { + std::error_code Err = getLastSocketErrorCode(); + if (Err == std::errc::address_in_use) + ::close(MaybeWinsocket); + return llvm::make_error<StringError>(Err, "Bind error"); + } + if (listen(MaybeWinsocket, MaxBacklog) == -1) { + return llvm::make_error<StringError>(getLastSocketErrorCode(), + "Listen error"); + } + int UnixSocket; +#ifdef _WIN32 + UnixSocket = _open_osfhandle(MaybeWinsocket, 0); +#else + UnixSocket = MaybeWinsocket; +#endif // _WIN32 + ListeningSocket ListenSocket(UnixSocket, SocketPath); + return ListenSocket; +} + +Expected<std::unique_ptr<raw_socket_stream>> ListeningSocket::accept() { + int AcceptFD; +#ifdef _WIN32 + SOCKET WinServerSock = _get_osfhandle(FD); + SOCKET WinAcceptSock = ::accept(WinServerSock, NULL, NULL); + AcceptFD = _open_osfhandle(WinAcceptSock, 0); +#else + AcceptFD = ::accept(FD, NULL, NULL); +#endif //_WIN32 + if (AcceptFD == -1) + return llvm::make_error<StringError>(getLastSocketErrorCode(), + "Accept failed"); + return std::make_unique<raw_socket_stream>(AcceptFD); +} + +ListeningSocket::~ListeningSocket() { + if (FD == -1) + return; + ::close(FD); + unlink(SocketPath.c_str()); +} + +static Expected<int> GetSocketFD(StringRef SocketPath) { +#ifdef _WIN32 + SOCKET MaybeWinsocket = socket(AF_UNIX, SOCK_STREAM, 0); + if (MaybeWinsocket == INVALID_SOCKET) { +#else + int MaybeWinsocket = socket(AF_UNIX, SOCK_STREAM, 0); + if (MaybeWinsocket == -1) { +#endif // _WIN32 + return llvm::make_error<StringError>(getLastSocketErrorCode(), + "Create socket failed"); + } + + struct sockaddr_un Addr; + memset(&Addr, 0, sizeof(Addr)); + Addr.sun_family = AF_UNIX; + strncpy(Addr.sun_path, SocketPath.str().c_str(), sizeof(Addr.sun_path) - 1); + + int status = connect(MaybeWinsocket, (struct sockaddr *)&Addr, sizeof(Addr)); + if (status == -1) { + return llvm::make_error<StringError>(getLastSocketErrorCode(), + "Connect socket failed"); + } +#ifdef _WIN32 + return _open_osfhandle(MaybeWinsocket, 0); +#else + return MaybeWinsocket; +#endif // _WIN32 +} + +raw_socket_stream::raw_socket_stream(int SocketFD) + : raw_fd_stream(SocketFD, true) {} + +Expected<std::unique_ptr<raw_socket_stream>> +raw_socket_stream::createConnectedUnix(StringRef SocketPath) { +#ifdef _WIN32 + WSABalancer _; +#endif // _WIN32 + Expected<int> FD = GetSocketFD(SocketPath); + if (!FD) + return FD.takeError(); + return std::make_unique<raw_socket_stream>(*FD); +} + +raw_socket_stream::~raw_socket_stream() {} + +//===----------------------------------------------------------------------===// // raw_string_ostream //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 21cafe9b6c44..50527e08a061 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -4063,11 +4063,11 @@ defm BFCLAMP_ZZZ : sve2p1_bfclamp<"bfclamp", int_aarch64_sve_fclamp>; // SME2.1 or SVE2.1 instructions //===----------------------------------------------------------------------===// let Predicates = [HasSVE2p1_or_HasSME2p1] in { -defm FADDQV : sve2p1_fp_reduction_q<0b000, "faddqv">; -defm FMAXNMQV : sve2p1_fp_reduction_q<0b100, "fmaxnmqv">; -defm FMINNMQV : sve2p1_fp_reduction_q<0b101, "fminnmqv">; -defm FMAXQV : sve2p1_fp_reduction_q<0b110, "fmaxqv">; -defm FMINQV : sve2p1_fp_reduction_q<0b111, "fminqv">; +defm FADDQV : sve2p1_fp_reduction_q<0b000, "faddqv", int_aarch64_sve_addqv>; +defm FMAXNMQV : sve2p1_fp_reduction_q<0b100, "fmaxnmqv", int_aarch64_sve_fmaxnmqv>; +defm FMINNMQV : sve2p1_fp_reduction_q<0b101, "fminnmqv", int_aarch64_sve_fminnmqv>; +defm FMAXQV : sve2p1_fp_reduction_q<0b110, "fmaxqv", int_aarch64_sve_fmaxqv>; +defm FMINQV : sve2p1_fp_reduction_q<0b111, "fminqv", int_aarch64_sve_fminqv>; defm DUPQ_ZZI : sve2p1_dupq<"dupq">; defm EXTQ_ZZI : sve2p1_extq<"extq", int_aarch64_sve_extq_lane>; @@ -4075,14 +4075,14 @@ defm EXTQ_ZZI : sve2p1_extq<"extq", int_aarch64_sve_extq_lane>; defm PMOV_PZI : sve2p1_vector_to_pred<"pmov", int_aarch64_sve_pmov_to_pred_lane, int_aarch64_sve_pmov_to_pred_lane_zero>; defm PMOV_ZIP : sve2p1_pred_to_vector<"pmov", int_aarch64_sve_pmov_to_vector_lane_merging, int_aarch64_sve_pmov_to_vector_lane_zeroing>; -defm ORQV_VPZ : sve2p1_int_reduce_q<0b1100, "orqv">; -defm EORQV_VPZ : sve2p1_int_reduce_q<0b1101, "eorqv">; -defm ANDQV_VPZ : sve2p1_int_reduce_q<0b1110, "andqv">; -defm ADDQV_VPZ : sve2p1_int_reduce_q<0b0001, "addqv">; -defm SMAXQV_VPZ : sve2p1_int_reduce_q<0b0100, "smaxqv">; -defm UMAXQV_VPZ : sve2p1_int_reduce_q<0b0101, "umaxqv">; -defm SMINQV_VPZ : sve2p1_int_reduce_q<0b0110, "sminqv">; -defm UMINQV_VPZ : sve2p1_int_reduce_q<0b0111, "uminqv">; +defm ORQV_VPZ : sve2p1_int_reduce_q<0b1100, "orqv", int_aarch64_sve_orqv>; +defm EORQV_VPZ : sve2p1_int_reduce_q<0b1101, "eorqv", int_aarch64_sve_eorqv>; +defm ANDQV_VPZ : sve2p1_int_reduce_q<0b1110, "andqv", int_aarch64_sve_andqv>; +defm ADDQV_VPZ : sve2p1_int_reduce_q<0b0001, "addqv", int_aarch64_sve_addqv>; +defm SMAXQV_VPZ : sve2p1_int_reduce_q<0b0100, "smaxqv", int_aarch64_sve_smaxqv>; +defm UMAXQV_VPZ : sve2p1_int_reduce_q<0b0101, "umaxqv", int_aarch64_sve_umaxqv>; +defm SMINQV_VPZ : sve2p1_int_reduce_q<0b0110, "sminqv", int_aarch64_sve_sminqv>; +defm UMINQV_VPZ : sve2p1_int_reduce_q<0b0111, "uminqv", int_aarch64_sve_uminqv>; defm ZIPQ1_ZZZ : sve2p1_permute_vec_elems_q<0b000, "zipq1", int_aarch64_sve_zipq1>; defm ZIPQ2_ZZZ : sve2p1_permute_vec_elems_q<0b001, "zipq2", int_aarch64_sve_zipq2>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index c0894e9c7068..9edf26052247 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -9963,10 +9963,14 @@ class sve2p1_fp_reduction_q<bits<2> sz, bits<3> opc, string mnemonic, let mayRaiseFPException = 1; } -multiclass sve2p1_fp_reduction_q<bits<3> opc, string mnemonic> { +multiclass sve2p1_fp_reduction_q<bits<3> opc, string mnemonic, SDPatternOperator op> { def _H : sve2p1_fp_reduction_q<0b01, opc, mnemonic, ZPR16, "8h">; def _S : sve2p1_fp_reduction_q<0b10, opc, mnemonic, ZPR32, "4s">; def _D : sve2p1_fp_reduction_q<0b11, opc, mnemonic, ZPR64, "2d">; + + def : SVE_2_Op_Pat<v8f16, op, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>; + def : SVE_2_Op_Pat<v4f32, op, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>; + def : SVE_2_Op_Pat<v2f64, op, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>; } @@ -10183,11 +10187,16 @@ class sve2p1_int_reduce_q<bits<2> sz, bits<4> opc, string mnemonic, let hasSideEffects = 0; } -multiclass sve2p1_int_reduce_q<bits<4> opc, string mnemonic> { +multiclass sve2p1_int_reduce_q<bits<4> opc, string mnemonic, SDPatternOperator op> { def _B : sve2p1_int_reduce_q<0b00, opc, mnemonic, ZPR8, "16b">; def _H : sve2p1_int_reduce_q<0b01, opc, mnemonic, ZPR16, "8h">; def _S : sve2p1_int_reduce_q<0b10, opc, mnemonic, ZPR32, "4s">; def _D : sve2p1_int_reduce_q<0b11, opc, mnemonic, ZPR64, "2d">; + + def : SVE_2_Op_Pat<v16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>; + def : SVE_2_Op_Pat<v8i16, op, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>; + def : SVE_2_Op_Pat<v4i32, op, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>; + def : SVE_2_Op_Pat<v2i64, op, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 1b75607e1dc3..89319527c410 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -36,6 +36,7 @@ FunctionPass *createSIAnnotateControlFlowPass(); FunctionPass *createSIFoldOperandsPass(); FunctionPass *createSIPeepholeSDWAPass(); FunctionPass *createSILowerI1CopiesPass(); +FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass(); FunctionPass *createSIShrinkInstructionsPass(); FunctionPass *createSILoadStoreOptimizerPass(); FunctionPass *createSIWholeQuadModePass(); @@ -162,6 +163,9 @@ extern char &SILowerWWMCopiesID; void initializeSILowerI1CopiesPass(PassRegistry &); extern char &SILowerI1CopiesID; +void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &); +extern char &AMDGPUGlobalISelDivergenceLoweringID; + void initializeSILowerSGPRSpillsPass(PassRegistry &); extern char &SILowerSGPRSpillsID; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 4bf1f1357b69..d317a733d433 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -426,7 +426,7 @@ amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor( memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor)); assert(isUInt<32>(PI.ScratchSize)); - assert(isUInt<32>(PI.getComputePGMRSrc1())); + assert(isUInt<32>(PI.getComputePGMRSrc1(STM))); assert(isUInt<32>(PI.getComputePGMRSrc2())); KernelDescriptor.group_segment_fixed_size = PI.LDSSize; @@ -435,7 +435,7 @@ amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor( Align MaxKernArgAlign; KernelDescriptor.kernarg_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign); - KernelDescriptor.compute_pgm_rsrc1 = PI.getComputePGMRSrc1(); + KernelDescriptor.compute_pgm_rsrc1 = PI.getComputePGMRSrc1(STM); KernelDescriptor.compute_pgm_rsrc2 = PI.getComputePGMRSrc2(); KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF); @@ -974,7 +974,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF, if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) { OutStreamer->emitInt32(R_00B848_COMPUTE_PGM_RSRC1); - OutStreamer->emitInt32(CurrentProgramInfo.getComputePGMRSrc1()); + OutStreamer->emitInt32(CurrentProgramInfo.getComputePGMRSrc1(STM)); OutStreamer->emitInt32(R_00B84C_COMPUTE_PGM_RSRC2); OutStreamer->emitInt32(CurrentProgramInfo.getComputePGMRSrc2()); @@ -1038,7 +1038,7 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF, MD->setNumUsedSgprs(CC, CurrentProgramInfo.NumSGPRsForWavesPerEU); if (MD->getPALMajorVersion() < 3) { - MD->setRsrc1(CC, CurrentProgramInfo.getPGMRSrc1(CC)); + MD->setRsrc1(CC, CurrentProgramInfo.getPGMRSrc1(CC, STM)); if (AMDGPU::isCompute(CC)) { MD->setRsrc2(CC, CurrentProgramInfo.getComputePGMRSrc2()); } else { @@ -1116,10 +1116,11 @@ void AMDGPUAsmPrinter::emitPALFunctionMetadata(const MachineFunction &MF) { const MachineFrameInfo &MFI = MF.getFrameInfo(); StringRef FnName = MF.getFunction().getName(); MD->setFunctionScratchSize(FnName, MFI.getStackSize()); + const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); // Set compute registers MD->setRsrc1(CallingConv::AMDGPU_CS, - CurrentProgramInfo.getPGMRSrc1(CallingConv::AMDGPU_CS)); + CurrentProgramInfo.getPGMRSrc1(CallingConv::AMDGPU_CS, ST)); MD->setRsrc2(CallingConv::AMDGPU_CS, CurrentProgramInfo.getComputePGMRSrc2()); // Set optional info @@ -1155,7 +1156,7 @@ void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out, AMDGPU::initDefaultAMDKernelCodeT(Out, &STM); Out.compute_pgm_resource_registers = - CurrentProgramInfo.getComputePGMRSrc1() | + CurrentProgramInfo.getComputePGMRSrc1(STM) | (CurrentProgramInfo.getComputePGMRSrc2() << 32); Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp index 4caa9cd9225b..87b1957c799e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp @@ -2199,7 +2199,7 @@ bool AMDGPUCodeGenPrepare::runOnFunction(Function &F) { auto *DTWP = getAnalysisIfAvailable<DominatorTreeWrapperPass>(); Impl.DT = DTWP ? &DTWP->getDomTree() : nullptr; Impl.HasUnsafeFPMath = hasUnsafeFPMath(F); - SIModeRegisterDefaults Mode(F); + SIModeRegisterDefaults Mode(F, *Impl.ST); Impl.HasFP32DenormalFlush = Mode.FP32Denormals == DenormalMode::getPreserveSign(); return Impl.run(F); @@ -2216,7 +2216,7 @@ PreservedAnalyses AMDGPUCodeGenPreparePass::run(Function &F, Impl.UA = &FAM.getResult<UniformityInfoAnalysis>(F); Impl.DT = FAM.getCachedResult<DominatorTreeAnalysis>(F); Impl.HasUnsafeFPMath = hasUnsafeFPMath(F); - SIModeRegisterDefaults Mode(F); + SIModeRegisterDefaults Mode(F, *Impl.ST); Impl.HasFP32DenormalFlush = Mode.FP32Denormals == DenormalMode::getPreserveSign(); PreservedAnalyses PA = PreservedAnalyses::none(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp index d48916670112..69dc78d33c83 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp @@ -29,6 +29,8 @@ static bool fnegFoldsIntoMI(const MachineInstr &MI) { case AMDGPU::G_FMAXNUM: case AMDGPU::G_FMINNUM_IEEE: case AMDGPU::G_FMAXNUM_IEEE: + case AMDGPU::G_FMINIMUM: + case AMDGPU::G_FMAXIMUM: case AMDGPU::G_FSIN: case AMDGPU::G_FPEXT: case AMDGPU::G_INTRINSIC_TRUNC: @@ -174,6 +176,10 @@ static unsigned inverseMinMax(unsigned Opc) { return AMDGPU::G_FMINNUM_IEEE; case AMDGPU::G_FMINNUM_IEEE: return AMDGPU::G_FMAXNUM_IEEE; + case AMDGPU::G_FMAXIMUM: + return AMDGPU::G_FMINIMUM; + case AMDGPU::G_FMINIMUM: + return AMDGPU::G_FMAXIMUM; case AMDGPU::G_AMDGPU_FMAX_LEGACY: return AMDGPU::G_AMDGPU_FMIN_LEGACY; case AMDGPU::G_AMDGPU_FMIN_LEGACY: @@ -207,6 +213,8 @@ bool AMDGPUCombinerHelper::matchFoldableFneg(MachineInstr &MI, case AMDGPU::G_FMAXNUM: case AMDGPU::G_FMINNUM_IEEE: case AMDGPU::G_FMAXNUM_IEEE: + case AMDGPU::G_FMINIMUM: + case AMDGPU::G_FMAXIMUM: case AMDGPU::G_AMDGPU_FMIN_LEGACY: case AMDGPU::G_AMDGPU_FMAX_LEGACY: // 0 doesn't have a negated inline immediate. @@ -304,6 +312,8 @@ void AMDGPUCombinerHelper::applyFoldableFneg(MachineInstr &MI, case AMDGPU::G_FMAXNUM: case AMDGPU::G_FMINNUM_IEEE: case AMDGPU::G_FMAXNUM_IEEE: + case AMDGPU::G_FMINIMUM: + case AMDGPU::G_FMAXIMUM: case AMDGPU::G_AMDGPU_FMIN_LEGACY: case AMDGPU::G_AMDGPU_FMAX_LEGACY: { NegateOperand(MatchInfo->getOperand(1)); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp new file mode 100644 index 000000000000..4cd8b1ec1051 --- /dev/null +++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp @@ -0,0 +1,68 @@ +//===-- AMDGPUGlobalISelDivergenceLowering.cpp ----------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +/// \file +/// GlobalISel pass that selects divergent i1 phis as lane mask phis. +/// Lane mask merging uses same algorithm as SDAG in SILowerI1Copies. +/// Handles all cases of temporal divergence. +/// For divergent non-phi i1 and uniform i1 uses outside of the cycle this pass +/// currently depends on LCSSA to insert phis with one incoming. +// +//===----------------------------------------------------------------------===// + +#include "AMDGPU.h" +#include "llvm/CodeGen/MachineFunctionPass.h" + +#define DEBUG_TYPE "amdgpu-global-isel-divergence-lowering" + +using namespace llvm; + +namespace { + +class AMDGPUGlobalISelDivergenceLowering : public MachineFunctionPass { +public: + static char ID; + +public: + AMDGPUGlobalISelDivergenceLowering() : MachineFunctionPass(ID) { + initializeAMDGPUGlobalISelDivergenceLoweringPass( + *PassRegistry::getPassRegistry()); + } + + bool runOnMachineFunction(MachineFunction &MF) override; + + StringRef getPassName() const override { + return "AMDGPU GlobalISel divergence lowering"; + } + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesCFG(); + MachineFunctionPass::getAnalysisUsage(AU); + } +}; + +} // End anonymous namespace. + +INITIALIZE_PASS_BEGIN(AMDGPUGlobalISelDivergenceLowering, DEBUG_TYPE, + "AMDGPU GlobalISel divergence lowering", false, false) +INITIALIZE_PASS_END(AMDGPUGlobalISelDivergenceLowering, DEBUG_TYPE, + "AMDGPU GlobalISel divergence lowering", false, false) + +char AMDGPUGlobalISelDivergenceLowering::ID = 0; + +char &llvm::AMDGPUGlobalISelDivergenceLoweringID = + AMDGPUGlobalISelDivergenceLowering::ID; + +FunctionPass *llvm::createAMDGPUGlobalISelDivergenceLoweringPass() { + return new AMDGPUGlobalISelDivergenceLowering(); +} + +bool AMDGPUGlobalISelDivergenceLowering::runOnMachineFunction( + MachineFunction &MF) { + return false; +} diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index a6d1da94b890..66ba08ef0dc1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -132,7 +132,7 @@ bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { } #endif Subtarget = &MF.getSubtarget<GCNSubtarget>(); - Mode = SIModeRegisterDefaults(MF.getFunction()); + Mode = SIModeRegisterDefaults(MF.getFunction(), *Subtarget); return SelectionDAGISel::runOnMachineFunction(MF); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index fcbdf51b03c1..9d7443012e3d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -585,6 +585,8 @@ static bool fnegFoldsIntoOpcode(unsigned Opc) { case ISD::FMAXNUM: case ISD::FMINNUM_IEEE: case ISD::FMAXNUM_IEEE: + case ISD::FMINIMUM: + case ISD::FMAXIMUM: case ISD::SELECT: case ISD::FSIN: case ISD::FTRUNC: @@ -4572,6 +4574,10 @@ static unsigned inverseMinMax(unsigned Opc) { return ISD::FMINNUM_IEEE; case ISD::FMINNUM_IEEE: return ISD::FMAXNUM_IEEE; + case ISD::FMAXIMUM: + return ISD::FMINIMUM; + case ISD::FMINIMUM: + return ISD::FMAXIMUM; case AMDGPUISD::FMAX_LEGACY: return AMDGPUISD::FMIN_LEGACY; case AMDGPUISD::FMIN_LEGACY: @@ -4695,6 +4701,8 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N, case ISD::FMINNUM: case ISD::FMAXNUM_IEEE: case ISD::FMINNUM_IEEE: + case ISD::FMINIMUM: + case ISD::FMAXIMUM: case AMDGPUISD::FMAX_LEGACY: case AMDGPUISD::FMIN_LEGACY: { // fneg (fmaxnum x, y) -> fminnum (fneg x), (fneg y) @@ -5305,6 +5313,8 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(FMED3) NODE_NAME_CASE(SMED3) NODE_NAME_CASE(UMED3) + NODE_NAME_CASE(FMAXIMUM3) + NODE_NAME_CASE(FMINIMUM3) NODE_NAME_CASE(FDOT2) NODE_NAME_CASE(URECIP) NODE_NAME_CASE(DIV_SCALE) @@ -5759,6 +5769,8 @@ bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op, case AMDGPUISD::FMED3: case AMDGPUISD::FMIN3: case AMDGPUISD::FMAX3: + case AMDGPUISD::FMINIMUM3: + case AMDGPUISD::FMAXIMUM3: case AMDGPUISD::FMAD_FTZ: { if (SNaN) return true; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h index 6841067e31b3..827fb106b551 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -449,6 +449,8 @@ enum NodeType : unsigned { FMED3, SMED3, UMED3, + FMAXIMUM3, + FMINIMUM3, FDOT2, URECIP, DIV_SCALE, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td index fd38739876c4..82f58ea38fd0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td @@ -170,6 +170,11 @@ def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp, [/*SDNPCommutative, SDNPAssociative*/] >; +// out = max(a, b, c) a, b and c are floats. Operation is IEEE2019 compliant. +def AMDGPUfmaximum3 : SDNode<"AMDGPUISD::FMAXIMUM3", SDTFPTernaryOp, + [/*SDNPCommutative, SDNPAssociative*/] +>; + // out = max(a, b, c) a, b, and c are signed ints def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp, [/*SDNPCommutative, SDNPAssociative*/] @@ -185,6 +190,11 @@ def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp, [/*SDNPCommutative, SDNPAssociative*/] >; +// out = min(a, b, c) a, b and c are floats. Operation is IEEE2019 compliant. +def AMDGPUfminimum3 : SDNode<"AMDGPUISD::FMINIMUM3", SDTFPTernaryOp, + [/*SDNPCommutative, SDNPAssociative*/] +>; + // out = min(a, b, c) a, b and c are signed ints def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp, [/*SDNPCommutative, SDNPAssociative*/] diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index d24c7da964ce..75fac09d0b99 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -1791,6 +1791,19 @@ bool AMDGPUInstructionSelector::selectSBarrier(MachineInstr &MI) const { return true; } } + + // On GFX12 lower s_barrier into s_barrier_signal_imm and s_barrier_wait + if (STI.hasSplitBarriers()) { + MachineBasicBlock *MBB = MI.getParent(); + const DebugLoc &DL = MI.getDebugLoc(); + BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::S_BARRIER_SIGNAL_IMM)) + .addImm(AMDGPU::Barrier::WORKGROUP); + BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::S_BARRIER_WAIT)) + .addImm(AMDGPU::Barrier::WORKGROUP); + MI.eraseFromParent(); + return true; + } + return selectImpl(MI, *CoverageInfo); } @@ -2137,6 +2150,16 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS( break; case Intrinsic::amdgcn_ds_bvh_stack_rtn: return selectDSBvhStackIntrinsic(I); + case Intrinsic::amdgcn_s_barrier_init: + case Intrinsic::amdgcn_s_barrier_join: + case Intrinsic::amdgcn_s_wakeup_barrier: + case Intrinsic::amdgcn_s_get_barrier_state: + return selectNamedBarrierInst(I, IntrinsicID); + case Intrinsic::amdgcn_s_barrier_signal_isfirst: + case Intrinsic::amdgcn_s_barrier_signal_isfirst_var: + return selectSBarrierSignalIsfirst(I, IntrinsicID); + case Intrinsic::amdgcn_s_barrier_leave: + return selectSBarrierLeave(I); } return selectImpl(I, *CoverageInfo); } @@ -5239,6 +5262,135 @@ AMDGPUInstructionSelector::selectVOP3PMadMixMods(MachineOperand &Root) const { }}; } +bool AMDGPUInstructionSelector::selectSBarrierSignalIsfirst( + MachineInstr &I, Intrinsic::ID IntrID) const { + MachineBasicBlock *MBB = I.getParent(); + const DebugLoc &DL = I.getDebugLoc(); + Register CCReg = I.getOperand(0).getReg(); + + bool HasM0 = IntrID == Intrinsic::amdgcn_s_barrier_signal_isfirst_var; + + if (HasM0) { + auto CopyMIB = BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::M0) + .addReg(I.getOperand(2).getReg()); + BuildMI(*MBB, &I, DL, TII.get(AMDGPU::S_BARRIER_SIGNAL_ISFIRST_M0)); + if (!constrainSelectedInstRegOperands(*CopyMIB, TII, TRI, RBI)) + return false; + } else { + BuildMI(*MBB, &I, DL, TII.get(AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM)) + .addImm(I.getOperand(2).getImm()); + } + + BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), CCReg).addReg(AMDGPU::SCC); + + I.eraseFromParent(); + return RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32_XM0_XEXECRegClass, + *MRI); +} + +unsigned getNamedBarrierOp(bool HasInlineConst, Intrinsic::ID IntrID) { + if (HasInlineConst) { + switch (IntrID) { + default: + llvm_unreachable("not a named barrier op"); + case Intrinsic::amdgcn_s_barrier_init: + return AMDGPU::S_BARRIER_INIT_IMM; + case Intrinsic::amdgcn_s_barrier_join: + return AMDGPU::S_BARRIER_JOIN_IMM; + case Intrinsic::amdgcn_s_wakeup_barrier: + return AMDGPU::S_WAKEUP_BARRIER_IMM; + case Intrinsic::amdgcn_s_get_barrier_state: + return AMDGPU::S_GET_BARRIER_STATE_IMM; + }; + } else { + switch (IntrID) { + default: + llvm_unreachable("not a named barrier op"); + case Intrinsic::amdgcn_s_barrier_init: + return AMDGPU::S_BARRIER_INIT_M0; + case Intrinsic::amdgcn_s_barrier_join: + return AMDGPU::S_BARRIER_JOIN_M0; + case Intrinsic::amdgcn_s_wakeup_barrier: + return AMDGPU::S_WAKEUP_BARRIER_M0; + case Intrinsic::amdgcn_s_get_barrier_state: + return AMDGPU::S_GET_BARRIER_STATE_M0; + }; + } +} + +bool AMDGPUInstructionSelector::selectNamedBarrierInst( + MachineInstr &I, Intrinsic::ID IntrID) const { + MachineBasicBlock *MBB = I.getParent(); + const DebugLoc &DL = I.getDebugLoc(); + MachineOperand BarOp = IntrID == Intrinsic::amdgcn_s_get_barrier_state + ? I.getOperand(2) + : I.getOperand(1); + std::optional<int64_t> BarValImm = + getIConstantVRegSExtVal(BarOp.getReg(), *MRI); + Register M0Val; + Register TmpReg0; + + // For S_BARRIER_INIT, member count will always be read from M0[16:22] + if (IntrID == Intrinsic::amdgcn_s_barrier_init) { + Register MemberCount = I.getOperand(2).getReg(); + TmpReg0 = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); + // TODO: This should be expanded during legalization so that the the S_LSHL + // and S_OR can be constant-folded + BuildMI(*MBB, &I, DL, TII.get(AMDGPU::S_LSHL_B32), TmpReg0) + .addImm(16) + .addReg(MemberCount); + M0Val = TmpReg0; + } + + // If not inlinable, get reference to barrier depending on the instruction + if (!BarValImm) { + if (IntrID == Intrinsic::amdgcn_s_barrier_init) { + // If reference to barrier id is not an inlinable constant then it must be + // referenced with M0[4:0]. Perform an OR with the member count to include + // it in M0 for S_BARRIER_INIT. + Register TmpReg1 = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); + BuildMI(*MBB, &I, DL, TII.get(AMDGPU::S_OR_B32), TmpReg1) + .addReg(BarOp.getReg()) + .addReg(TmpReg0); + M0Val = TmpReg1; + } else { + M0Val = BarOp.getReg(); + } + } + + // Build copy to M0 if needed. For S_BARRIER_INIT, M0 is always required. + if (M0Val) { + auto CopyMIB = + BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::M0).addReg(M0Val); + constrainSelectedInstRegOperands(*CopyMIB, TII, TRI, RBI); + } + + MachineInstrBuilder MIB; + unsigned Opc = getNamedBarrierOp(BarValImm.has_value(), IntrID); + MIB = BuildMI(*MBB, &I, DL, TII.get(Opc)); + + if (IntrID == Intrinsic::amdgcn_s_get_barrier_state) + MIB.addDef(I.getOperand(0).getReg()); + + if (BarValImm) + MIB.addImm(*BarValImm); + + I.eraseFromParent(); + return true; +} +bool AMDGPUInstructionSelector::selectSBarrierLeave(MachineInstr &I) const { + MachineBasicBlock *BB = I.getParent(); + const DebugLoc &DL = I.getDebugLoc(); + Register CCReg = I.getOperand(0).getReg(); + + BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_BARRIER_LEAVE)); + BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg).addReg(AMDGPU::SCC); + + I.eraseFromParent(); + return RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32_XM0_XEXECRegClass, + *MRI); +} + void AMDGPUInstructionSelector::renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index c93e3de66d40..00ff1747ce57 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -149,6 +149,9 @@ private: bool selectSMFMACIntrin(MachineInstr &I) const; bool selectWaveAddress(MachineInstr &I) const; bool selectStackRestore(MachineInstr &MI) const; + bool selectNamedBarrierInst(MachineInstr &I, Intrinsic::ID IID) const; + bool selectSBarrierSignalIsfirst(MachineInstr &I, Intrinsic::ID IID) const; + bool selectSBarrierLeave(MachineInstr &I) const; std::pair<Register, unsigned> selectVOP3ModsImpl(MachineOperand &Root, bool IsCanonicalizing = true, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td index d2d09a0b1fc5..121026aca603 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td @@ -252,6 +252,8 @@ def umin_oneuse : HasOneUseBinOp<umin>; def fminnum_oneuse : HasOneUseBinOp<fminnum>; def fmaxnum_oneuse : HasOneUseBinOp<fmaxnum>; +def fminimum_oneuse : HasOneUseBinOp<fminimum>; +def fmaximum_oneuse : HasOneUseBinOp<fmaximum>; def fminnum_ieee_oneuse : HasOneUseBinOp<fminnum_ieee>; def fmaxnum_ieee_oneuse : HasOneUseBinOp<fmaxnum_ieee>; diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 2cf804e3348e..489b4f5a8d86 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -1959,20 +1959,25 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, .widenScalarToNextPow2(0) .scalarize(0); - getActionDefinitionsBuilder({ - // TODO: Verify V_BFI_B32 is generated from expanded bit ops - G_FCOPYSIGN, + getActionDefinitionsBuilder( + {// TODO: Verify V_BFI_B32 is generated from expanded bit ops + G_FCOPYSIGN, - G_ATOMIC_CMPXCHG_WITH_SUCCESS, - G_ATOMICRMW_NAND, - G_ATOMICRMW_FSUB, - G_READ_REGISTER, - G_WRITE_REGISTER, + G_ATOMIC_CMPXCHG_WITH_SUCCESS, G_ATOMICRMW_NAND, G_ATOMICRMW_FSUB, + G_READ_REGISTER, G_WRITE_REGISTER, - G_SADDO, G_SSUBO, + G_SADDO, G_SSUBO}) + .lower(); - // TODO: Implement - G_FMINIMUM, G_FMAXIMUM}).lower(); + if (ST.hasIEEEMinMax()) { + getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM}) + .legalFor(FPTypesPK16) + .clampMaxNumElements(0, S16, 2) + .scalarize(0); + } else { + // TODO: Implement + getActionDefinitionsBuilder({G_FMINIMUM, G_FMAXIMUM}).lower(); + } getActionDefinitionsBuilder({G_MEMCPY, G_MEMCPY_INLINE, G_MEMMOVE, G_MEMSET}) .lower(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 62996a3b3fb7..03b6d19b2b3c 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -3101,6 +3101,22 @@ void AMDGPURegisterBankInfo::applyMappingImpl( applyDefaultMapping(OpdMapper); constrainOpWithReadfirstlane(B, MI, 8); // M0 return; + case Intrinsic::amdgcn_s_barrier_signal_var: + case Intrinsic::amdgcn_s_barrier_join: + case Intrinsic::amdgcn_s_wakeup_barrier: + constrainOpWithReadfirstlane(B, MI, 1); + return; + case Intrinsic::amdgcn_s_barrier_signal_isfirst_var: + constrainOpWithReadfirstlane(B, MI, 2); + return; + case Intrinsic::amdgcn_s_barrier_init: + constrainOpWithReadfirstlane(B, MI, 1); + constrainOpWithReadfirstlane(B, MI, 2); + return; + case Intrinsic::amdgcn_s_get_barrier_state: { + constrainOpWithReadfirstlane(B, MI, 2); + return; + } default: { if (const AMDGPU::RsrcIntrinsic *RSrcIntrin = AMDGPU::lookupRsrcIntrinsic(IntrID)) { @@ -3727,14 +3743,17 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case AMDGPU::G_INTRINSIC_ROUNDEVEN: case AMDGPU::G_FMINNUM: case AMDGPU::G_FMAXNUM: + case AMDGPU::G_FMINIMUM: + case AMDGPU::G_FMAXIMUM: case AMDGPU::G_INTRINSIC_TRUNC: case AMDGPU::G_STRICT_FADD: case AMDGPU::G_STRICT_FSUB: case AMDGPU::G_STRICT_FMUL: case AMDGPU::G_STRICT_FMA: { - unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); - if (Subtarget.hasSALUFloatInsts() && (Size == 32 || Size == 16) && - isSALUMapping(MI)) + LLT Ty = MRI.getType(MI.getOperand(0).getReg()); + unsigned Size = Ty.getSizeInBits(); + if (Subtarget.hasSALUFloatInsts() && Ty.isScalar() && + (Size == 32 || Size == 16) && isSALUMapping(MI)) return getDefaultMappingSOP(MI); return getDefaultMappingVOP(MI); } @@ -4830,7 +4849,34 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { getVGPROpMapping(MI.getOperand(5).getReg(), MRI, *TRI); // %data1 break; } - + case Intrinsic::amdgcn_s_barrier_signal_var: + case Intrinsic::amdgcn_s_barrier_join: + case Intrinsic::amdgcn_s_wakeup_barrier: + OpdsMapping[1] = getSGPROpMapping(MI.getOperand(1).getReg(), MRI, *TRI); + break; + case Intrinsic::amdgcn_s_barrier_init: + OpdsMapping[1] = getSGPROpMapping(MI.getOperand(1).getReg(), MRI, *TRI); + OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI); + break; + case Intrinsic::amdgcn_s_barrier_signal_isfirst_var: { + const unsigned ResultSize = 1; + OpdsMapping[0] = + AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, ResultSize); + OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI); + break; + } + case Intrinsic::amdgcn_s_barrier_signal_isfirst: + case Intrinsic::amdgcn_s_barrier_leave: { + const unsigned ResultSize = 1; + OpdsMapping[0] = + AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, ResultSize); + break; + } + case Intrinsic::amdgcn_s_get_barrier_state: { + OpdsMapping[0] = getSGPROpMapping(MI.getOperand(0).getReg(), MRI, *TRI); + OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI); + break; + } default: return getInvalidInstructionMapping(); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 97db19064f6f..0cc048ef0e85 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -375,6 +375,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() { initializeAMDGPUDAGToDAGISelPass(*PR); initializeGCNDPPCombinePass(*PR); initializeSILowerI1CopiesPass(*PR); + initializeAMDGPUGlobalISelDivergenceLoweringPass(*PR); initializeSILowerWWMCopiesPass(*PR); initializeSILowerSGPRSpillsPass(*PR); initializeSIFixSGPRCopiesPass(*PR); @@ -1255,6 +1256,7 @@ bool GCNPassConfig::addLegalizeMachineIR() { void GCNPassConfig::addPreRegBankSelect() { bool IsOptNone = getOptLevel() == CodeGenOptLevel::None; addPass(createAMDGPUPostLegalizeCombiner(IsOptNone)); + addPass(createAMDGPUGlobalISelDivergenceLoweringPass()); } bool GCNPassConfig::addRegBankSelect() { @@ -1499,13 +1501,13 @@ bool GCNTargetMachine::parseMachineFunctionInfo( static_cast<const yaml::SIMachineFunctionInfo &>(MFI_); MachineFunction &MF = PFS.MF; SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); + const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); if (MFI->initializeBaseYamlFields(YamlMFI, MF, PFS, Error, SourceRange)) return true; if (MFI->Occupancy == 0) { // Fixup the subtarget dependent default value. - const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); MFI->Occupancy = ST.computeOccupancy(MF.getFunction(), MFI->getLDSSize()); } @@ -1659,8 +1661,10 @@ bool GCNTargetMachine::parseMachineFunctionInfo( MFI->ArgInfo.WorkItemIDZ, 0, 0))) return true; - MFI->Mode.IEEE = YamlMFI.Mode.IEEE; - MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp; + if (ST.hasIEEEMode()) + MFI->Mode.IEEE = YamlMFI.Mode.IEEE; + if (ST.hasDX10ClampMode()) + MFI->Mode.DX10Clamp = YamlMFI.Mode.DX10Clamp; // FIXME: Move proper support for denormal-fp-math into base MachineFunction MFI->Mode.FP32Denormals.Input = YamlMFI.Mode.FP32InputDenormals diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp index 3316659671bd..d754058d4f06 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -296,7 +296,7 @@ GCNTTIImpl::GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F) ST(static_cast<const GCNSubtarget *>(TM->getSubtargetImpl(F))), TLI(ST->getTargetLowering()), CommonTTI(TM, F), IsGraphics(AMDGPU::isGraphics(F.getCallingConv())) { - SIModeRegisterDefaults Mode(F); + SIModeRegisterDefaults Mode(F, *ST); HasFP32Denormals = Mode.FP32Denormals != DenormalMode::getPreserveSign(); HasFP64FP16Denormals = Mode.FP64FP16Denormals != DenormalMode::getPreserveSign(); @@ -1163,8 +1163,8 @@ bool GCNTTIImpl::areInlineCompatible(const Function *Caller, // FIXME: dx10_clamp can just take the caller setting, but there seems to be // no way to support merge for backend defined attributes. - SIModeRegisterDefaults CallerMode(*Caller); - SIModeRegisterDefaults CalleeMode(*Callee); + SIModeRegisterDefaults CallerMode(*Caller, *CallerST); + SIModeRegisterDefaults CalleeMode(*Callee, *CalleeST); if (!CallerMode.isInlineCompatible(CalleeMode)) return false; diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 92427335c0ad..ced2a1214af8 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -893,6 +893,7 @@ public: bool isSDelayALU() const; bool isHwreg() const; bool isSendMsg() const; + bool isSplitBarrier() const; bool isSwizzle() const; bool isSMRDOffset8() const; bool isSMEMOffset() const; @@ -1856,6 +1857,7 @@ static const fltSemantics *getOpFltSemantics(uint8_t OperandType) { case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: case AMDGPU::OPERAND_REG_IMM_V2INT32: case AMDGPU::OPERAND_KIMM32: + case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: return &APFloat::IEEEsingle(); case AMDGPU::OPERAND_REG_IMM_INT64: case AMDGPU::OPERAND_REG_IMM_FP64: @@ -2185,7 +2187,8 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: case AMDGPU::OPERAND_REG_IMM_V2INT32: case AMDGPU::OPERAND_KIMM32: - case AMDGPU::OPERAND_KIMM16: { + case AMDGPU::OPERAND_KIMM16: + case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: { bool lost; APFloat FPLiteral(APFloat::IEEEdouble(), Literal); // Convert literal to single precision @@ -2226,6 +2229,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: case AMDGPU::OPERAND_REG_IMM_V2INT32: case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: + case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: if (isSafeTruncation(Val, 32) && AMDGPU::isInlinableLiteral32(static_cast<int32_t>(Val), AsmParser->hasInv2PiInlineImm())) { @@ -5342,11 +5346,17 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() { COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, Val, ValRange); } else if (ID == ".amdhsa_dx10_clamp") { + if (IVersion.Major >= 12) + return Error(IDRange.Start, "directive unsupported on gfx12+", IDRange); PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, - COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, Val, ValRange); + COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP, Val, + ValRange); } else if (ID == ".amdhsa_ieee_mode") { - PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE, - Val, ValRange); + if (IVersion.Major >= 12) + return Error(IDRange.Start, "directive unsupported on gfx12+", IDRange); + PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, + COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE, Val, + ValRange); } else if (ID == ".amdhsa_fp16_overflow") { if (IVersion.Major < 9) return Error(IDRange.Start, "directive requires gfx9+", IDRange); @@ -5409,6 +5419,12 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() { PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2, COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO, Val, ValRange); + } else if (ID == ".amdhsa_round_robin_scheduling") { + if (IVersion.Major < 12) + return Error(IDRange.Start, "directive requires gfx12+", IDRange); + PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, + COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN, Val, + ValRange); } else { return Error(IDRange.Start, "unknown .amdhsa_kernel directive", IDRange); } @@ -5562,6 +5578,18 @@ bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID, } Lex(); + if (ID == "enable_dx10_clamp") { + if (G_00B848_DX10_CLAMP(Header.compute_pgm_resource_registers) && + isGFX12Plus()) + return TokError("enable_dx10_clamp=1 is not allowed on GFX12+"); + } + + if (ID == "enable_ieee_mode") { + if (G_00B848_IEEE_MODE(Header.compute_pgm_resource_registers) && + isGFX12Plus()) + return TokError("enable_ieee_mode=1 is not allowed on GFX12+"); + } + if (ID == "enable_wavefront_size32") { if (Header.code_properties & AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32) { if (!isGFX10Plus()) @@ -9137,3 +9165,9 @@ bool AMDGPUOperand::isWaitVDST() const { bool AMDGPUOperand::isWaitEXP() const { return isImmTy(ImmTyWaitEXP) && isUInt<3>(getImm()); } + +//===----------------------------------------------------------------------===// +// Split Barrier +//===----------------------------------------------------------------------===// + +bool AMDGPUOperand::isSplitBarrier() const { return isInlinableImm(MVT::i32); } diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt index 53a33f8210d2..2c92e7a07388 100644 --- a/llvm/lib/Target/AMDGPU/CMakeLists.txt +++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt @@ -55,6 +55,7 @@ add_llvm_target(AMDGPUCodeGen AMDGPUCtorDtorLowering.cpp AMDGPUExportClustering.cpp AMDGPUFrameLowering.cpp + AMDGPUGlobalISelDivergenceLowering.cpp AMDGPUGlobalISelUtils.cpp AMDGPUHSAMetadataStreamer.cpp AMDGPUInsertDelayAlu.cpp diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index ed019d26c1df..1cfc5af571c1 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -107,6 +107,13 @@ static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, return addOperand(Inst, DAsm->decodeBoolReg(Val)); } +static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val, + uint64_t Addr, + const MCDisassembler *Decoder) { + auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); + return addOperand(Inst, DAsm->decodeSplitBarrier(Val)); +} + #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ uint64_t /*Addr*/, \ @@ -1747,6 +1754,10 @@ MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { : decodeSrcOp(OPW32, Val); } +MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const { + return decodeSrcOp(OPW32, Val); +} + bool AMDGPUDisassembler::isVI() const { return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); } @@ -1868,12 +1879,16 @@ MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) return MCDisassembler::Fail; - PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); + if (!isGFX12Plus()) + PRINT_DIRECTIVE(".amdhsa_dx10_clamp", + COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP); if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) return MCDisassembler::Fail; - PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); + if (!isGFX12Plus()) + PRINT_DIRECTIVE(".amdhsa_ieee_mode", + COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE); if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) return MCDisassembler::Fail; @@ -1899,6 +1914,11 @@ MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); } + + if (isGFX12Plus()) + PRINT_DIRECTIVE(".amdhsa_round_robin_scheduling", + COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN); + return MCDisassembler::Success; } diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h index 7e233dcb54ea..233581949d71 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h @@ -251,6 +251,7 @@ public: MCOperand decodeSDWAVopcDst(unsigned Val) const; MCOperand decodeBoolReg(unsigned Val) const; + MCOperand decodeSplitBarrier(unsigned Val) const; int getTTmpIdx(unsigned Val) const; diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index 2eed024af60a..af9bab7cfe97 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -1206,12 +1206,27 @@ public: return hasKernargPreload() && !hasGFX940Insts(); } + // \returns true if the target has split barriers feature + bool hasSplitBarriers() const { return getGeneration() >= GFX12; } + // \returns true if FP8/BF8 VOP1 form of conversion to F32 is unreliable. bool hasCvtFP8VOP1Bug() const { return true; } // \returns true is CSUB atomics support a no-return form. bool hasAtomicCSubNoRtnInsts() const { return HasAtomicCSubNoRtnInsts; } + // \returns true if the target has DX10_CLAMP kernel descriptor mode bit + bool hasDX10ClampMode() const { return getGeneration() < GFX12; } + + // \returns true if the target has IEEE kernel descriptor mode bit + bool hasIEEEMode() const { return getGeneration() < GFX12; } + + // \returns true if the target has IEEE fminimum/fmaximum instructions + bool hasIEEEMinMax() const { return getGeneration() >= GFX12; } + + // \returns true if the target has WG_RR_MODE kernel descriptor mode bit + bool hasRrWGMode() const { return getGeneration() >= GFX12; } + /// \returns SGPR allocation granularity supported by the subtarget. unsigned getSGPRAllocGranule() const { return AMDGPU::IsaInfo::getSGPRAllocGranule(this); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index 57f74ae08b35..6280ff55ad24 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -708,6 +708,7 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo, case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: case MCOI::OPERAND_IMMEDIATE: + case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: printImmediate32(Op.getImm(), STI, O); break; case AMDGPU::OPERAND_REG_IMM_INT64: diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp index 80e7ca2b39d1..b403d69d9ff1 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp @@ -262,6 +262,7 @@ AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO, case AMDGPU::OPERAND_REG_IMM_V2FP32: case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: + case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: return getLit32Encoding(static_cast<uint32_t>(Imm), STI); case AMDGPU::OPERAND_REG_IMM_INT64: diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp index eba8e49a46f8..a855cf585205 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp @@ -451,12 +451,12 @@ void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD, compute_pgm_rsrc1, amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); - PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, - compute_pgm_rsrc1, - amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); - PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, - compute_pgm_rsrc1, - amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); + if (IVersion.Major < 12) { + PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD, compute_pgm_rsrc1, + amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP); + PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD, compute_pgm_rsrc1, + amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE); + } if (IVersion.Major >= 9) PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD, compute_pgm_rsrc1, @@ -478,6 +478,9 @@ void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor( PRINT_FIELD(OS, ".amdhsa_shared_vgpr_count", KD, compute_pgm_rsrc3, amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); } + if (IVersion.Major >= 12) + PRINT_FIELD(OS, ".amdhsa_round_robin_scheduling", KD, compute_pgm_rsrc1, + amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN); PRINT_FIELD( OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, compute_pgm_rsrc2, diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h index 9b2f52c1286e..b291400a947c 100644 --- a/llvm/lib/Target/AMDGPU/SIDefines.h +++ b/llvm/lib/Target/AMDGPU/SIDefines.h @@ -213,6 +213,9 @@ enum OperandType : unsigned { OPERAND_REG_INLINE_C_V2INT32, OPERAND_REG_INLINE_C_V2FP32, + // Operand for split barrier inline constant + OPERAND_INLINE_SPLIT_BARRIER_INT32, + /// Operand with 32-bit immediate that uses the constant bus. OPERAND_KIMM32, OPERAND_KIMM16, @@ -1026,6 +1029,12 @@ enum Register_Flag : uint8_t { } // namespace AMDGPU +namespace AMDGPU { +namespace Barrier { +enum Type { TRAP = -2, WORKGROUP = -1 }; +} // namespace Barrier +} // namespace AMDGPU + // clang-format off #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 @@ -1120,6 +1129,9 @@ enum Register_Flag : uint8_t { #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) #define C_00B848_DX10_CLAMP 0xFFDFFFFF +#define S_00B848_RR_WG_MODE(x) (((x) & 0x1) << 21) +#define G_00B848_RR_WG_MODE(x) (((x) >> 21) & 0x1) +#define C_00B848_RR_WG_MODE 0xFFDFFFFF #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) #define C_00B848_DEBUG_MODE 0xFFBFFFFF @@ -1136,8 +1148,6 @@ enum Register_Flag : uint8_t { #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1) #define C_00B848_FWD_PROGRESS 0x7FFFFFFF -// clang-format on - // Helpers for setting FLOAT_MODE #define FP_ROUND_ROUND_TO_NEAREST 0 #define FP_ROUND_ROUND_TO_INF 1 @@ -1179,6 +1189,9 @@ enum Register_Flag : uint8_t { #define R_SPILLED_SGPRS 0x4 #define R_SPILLED_VGPRS 0x8 + +// clang-format on + } // End namespace llvm #endif diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 85cc3cfec19c..708f212e204a 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -763,6 +763,10 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, if (Subtarget->hasMad64_32()) setOperationAction({ISD::SMUL_LOHI, ISD::UMUL_LOHI}, MVT::i32, Custom); + if (Subtarget->hasIEEEMinMax()) + setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, + {MVT::f16, MVT::f32, MVT::f64, MVT::v2f16}, Legal); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, {MVT::Other, MVT::f32, MVT::v4f32, MVT::i16, MVT::f16, MVT::v2i16, MVT::v2f16, MVT::i128}, @@ -800,6 +804,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, ISD::FMAXNUM, ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE, + ISD::FMINIMUM, + ISD::FMAXIMUM, ISD::FMA, ISD::SMIN, ISD::SMAX, @@ -8623,6 +8629,31 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, M->getVTList(), Ops, M->getMemoryVT(), M->getMemOperand()); } + case Intrinsic::amdgcn_s_get_barrier_state: { + SDValue Chain = Op->getOperand(0); + SmallVector<SDValue, 2> Ops; + unsigned Opc; + bool IsInlinableBarID = false; + int64_t BarID; + + if (isa<ConstantSDNode>(Op->getOperand(2))) { + BarID = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue(); + IsInlinableBarID = AMDGPU::isInlinableIntLiteral(BarID); + } + + if (IsInlinableBarID) { + Opc = AMDGPU::S_GET_BARRIER_STATE_IMM; + SDValue K = DAG.getTargetConstant(BarID, DL, MVT::i32); + Ops.push_back(K); + } else { + Opc = AMDGPU::S_GET_BARRIER_STATE_M0; + SDValue M0Val = copyToM0(DAG, Chain, DL, Op.getOperand(2)); + Ops.push_back(M0Val.getValue(0)); + } + + auto NewMI = DAG.getMachineNode(Opc, DL, Op->getVTList(), Ops); + return SDValue(NewMI, 0); + } default: if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr = @@ -8800,13 +8831,29 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, return SDValue(DAG.getMachineNode(Opc, DL, Op->getVTList(), Ops), 0); } case Intrinsic::amdgcn_s_barrier: { + const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); if (getTargetMachine().getOptLevel() > CodeGenOptLevel::None) { - const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); unsigned WGSize = ST.getFlatWorkGroupSizes(MF.getFunction()).second; if (WGSize <= ST.getWavefrontSize()) return SDValue(DAG.getMachineNode(AMDGPU::WAVE_BARRIER, DL, MVT::Other, Op.getOperand(0)), 0); } + + // On GFX12 lower s_barrier into s_barrier_signal_imm and s_barrier_wait + if (ST.hasSplitBarriers()) { + SDValue K = + DAG.getTargetConstant(AMDGPU::Barrier::WORKGROUP, DL, MVT::i32); + SDValue BarSignal = + SDValue(DAG.getMachineNode(AMDGPU::S_BARRIER_SIGNAL_IMM, DL, + MVT::Other, K, Op.getOperand(0)), + 0); + SDValue BarWait = + SDValue(DAG.getMachineNode(AMDGPU::S_BARRIER_WAIT, DL, MVT::Other, K, + BarSignal.getValue(0)), + 0); + return BarWait; + } + return SDValue(); }; case Intrinsic::amdgcn_tbuffer_store: { @@ -9192,7 +9239,76 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, case Intrinsic::amdgcn_end_cf: return SDValue(DAG.getMachineNode(AMDGPU::SI_END_CF, DL, MVT::Other, Op->getOperand(2), Chain), 0); + case Intrinsic::amdgcn_s_barrier_init: + case Intrinsic::amdgcn_s_barrier_join: + case Intrinsic::amdgcn_s_wakeup_barrier: { + SDValue Chain = Op->getOperand(0); + SmallVector<SDValue, 2> Ops; + SDValue BarOp = Op->getOperand(2); + unsigned Opc; + bool IsInlinableBarID = false; + int64_t BarVal; + + if (isa<ConstantSDNode>(BarOp)) { + BarVal = cast<ConstantSDNode>(BarOp)->getSExtValue(); + IsInlinableBarID = AMDGPU::isInlinableIntLiteral(BarVal); + } + + if (IsInlinableBarID) { + switch (IntrinsicID) { + default: + return SDValue(); + case Intrinsic::amdgcn_s_barrier_init: + Opc = AMDGPU::S_BARRIER_INIT_IMM; + break; + case Intrinsic::amdgcn_s_barrier_join: + Opc = AMDGPU::S_BARRIER_JOIN_IMM; + break; + case Intrinsic::amdgcn_s_wakeup_barrier: + Opc = AMDGPU::S_WAKEUP_BARRIER_IMM; + break; + } + + SDValue K = DAG.getTargetConstant(BarVal, DL, MVT::i32); + Ops.push_back(K); + } else { + switch (IntrinsicID) { + default: + return SDValue(); + case Intrinsic::amdgcn_s_barrier_init: + Opc = AMDGPU::S_BARRIER_INIT_M0; + break; + case Intrinsic::amdgcn_s_barrier_join: + Opc = AMDGPU::S_BARRIER_JOIN_M0; + break; + case Intrinsic::amdgcn_s_wakeup_barrier: + Opc = AMDGPU::S_WAKEUP_BARRIER_M0; + break; + } + } + + if (IntrinsicID == Intrinsic::amdgcn_s_barrier_init) { + SDValue M0Val; + // Member count will be read from M0[16:22] + M0Val = DAG.getNode(ISD::SHL, DL, MVT::i32, Op.getOperand(3), + DAG.getShiftAmountConstant(16, MVT::i32, DL)); + if (!IsInlinableBarID) { + // If reference to barrier id is not an inline constant then it must be + // referenced with M0[4:0]. Perform an OR with the member count to + // include it in M0. + M0Val = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, + Op.getOperand(2), M0Val), + 0); + } + Ops.push_back(copyToM0(DAG, Chain, DL, M0Val).getValue(0)); + } else if (!IsInlinableBarID) { + Ops.push_back(copyToM0(DAG, Chain, DL, BarOp).getValue(0)); + } + + auto NewMI = DAG.getMachineNode(Opc, DL, Op->getVTList(), Ops); + return SDValue(NewMI, 0); + } default: { if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr = AMDGPU::getImageDimIntrinsicInfo(IntrinsicID)) @@ -11786,10 +11902,14 @@ bool SITargetLowering::isCanonicalized(SelectionDAG &DAG, SDValue Op, case ISD::FMAXNUM: case ISD::FMINNUM_IEEE: case ISD::FMAXNUM_IEEE: + case ISD::FMINIMUM: + case ISD::FMAXIMUM: case AMDGPUISD::CLAMP: case AMDGPUISD::FMED3: case AMDGPUISD::FMAX3: - case AMDGPUISD::FMIN3: { + case AMDGPUISD::FMIN3: + case AMDGPUISD::FMAXIMUM3: + case AMDGPUISD::FMINIMUM3: { // FIXME: Shouldn't treat the generic operations different based these. // However, we aren't really required to flush the result from // minnum/maxnum.. @@ -11943,7 +12063,9 @@ bool SITargetLowering::isCanonicalized(Register Reg, MachineFunction &MF, case AMDGPU::G_FMINNUM: case AMDGPU::G_FMAXNUM: case AMDGPU::G_FMINNUM_IEEE: - case AMDGPU::G_FMAXNUM_IEEE: { + case AMDGPU::G_FMAXNUM_IEEE: + case AMDGPU::G_FMINIMUM: + case AMDGPU::G_FMAXIMUM: { if (Subtarget->supportsMinMaxDenormModes() || // FIXME: denormalsEnabledForType is broken for dynamic denormalsEnabledForType(MRI.getType(Reg), MF)) @@ -12131,6 +12253,8 @@ static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) { case ISD::FMAXNUM: case ISD::FMAXNUM_IEEE: return AMDGPUISD::FMAX3; + case ISD::FMAXIMUM: + return AMDGPUISD::FMAXIMUM3; case ISD::SMAX: return AMDGPUISD::SMAX3; case ISD::UMAX: @@ -12138,6 +12262,8 @@ static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) { case ISD::FMINNUM: case ISD::FMINNUM_IEEE: return AMDGPUISD::FMIN3; + case ISD::FMINIMUM: + return AMDGPUISD::FMINIMUM3; case ISD::SMIN: return AMDGPUISD::SMIN3; case ISD::UMIN: @@ -12497,7 +12623,9 @@ SDValue SITargetLowering::performExtractVectorEltCombine( case ISD::FMAXNUM: case ISD::FMINNUM: case ISD::FMAXNUM_IEEE: - case ISD::FMINNUM_IEEE: { + case ISD::FMINNUM_IEEE: + case ISD::FMAXIMUM: + case ISD::FMINIMUM: { SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, ResVT, Vec.getOperand(0), Idx); SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, ResVT, @@ -13759,6 +13887,8 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N, case ISD::FMINNUM: case ISD::FMAXNUM_IEEE: case ISD::FMINNUM_IEEE: + case ISD::FMAXIMUM: + case ISD::FMINIMUM: case ISD::SMAX: case ISD::SMIN: case ISD::UMAX: diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp index ede4841b8a5f..c16583f6a7f9 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp @@ -452,7 +452,9 @@ public: // FLAT instruction. WaitEventType getVmemWaitEventType(const MachineInstr &Inst) const { assert(SIInstrInfo::isVMEM(Inst) || SIInstrInfo::isFLAT(Inst)); - if (!ST->hasVscnt()) + // LDS DMA loads are also stores, but on the LDS side. On the VMEM side + // these should use VM_CNT. + if (!ST->hasVscnt() || SIInstrInfo::mayWriteLDSThroughDMA(Inst)) return VMEM_ACCESS; if (Inst.mayStore() && !SIInstrInfo::isAtomicRet(Inst)) { // FLAT and SCRATCH instructions may access scratch. Other VMEM @@ -544,14 +546,6 @@ void WaitcntBrackets::setExpScore(const MachineInstr *MI, } } -// MUBUF and FLAT LDS DMA operations need a wait on vmcnt before LDS written -// can be accessed. A load from LDS to VMEM does not need a wait. -static bool mayWriteLDSThroughDMA(const MachineInstr &MI) { - return SIInstrInfo::isVALU(MI) && - (SIInstrInfo::isMUBUF(MI) || SIInstrInfo::isFLAT(MI)) && - MI.getOpcode() != AMDGPU::BUFFER_STORE_LDS_DWORD; -} - void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII, const SIRegisterInfo *TRI, const MachineRegisterInfo *MRI, @@ -703,7 +697,10 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII, setRegScore(RegNo, T, CurrScore); } } - if (Inst.mayStore() && (TII->isDS(Inst) || mayWriteLDSThroughDMA(Inst))) { + if (Inst.mayStore() && + (TII->isDS(Inst) || TII->mayWriteLDSThroughDMA(Inst))) { + // MUBUF and FLAT LDS DMA operations need a wait on vmcnt before LDS + // written can be accessed. A load from LDS to VMEM does not need a wait. setRegScore(SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS, T, CurrScore); } } @@ -1178,7 +1175,7 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(MachineInstr &MI, if (AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::FLAT_ADDRESS) continue; // No need to wait before load from VMEM to LDS. - if (mayWriteLDSThroughDMA(MI)) + if (TII->mayWriteLDSThroughDMA(MI)) continue; unsigned RegNo = SQ_MAX_PGM_VGPRS + EXTRA_VGPR_LDS; // VM_CNT is only relevant to vgpr or LDS. @@ -1504,6 +1501,11 @@ void SIInsertWaitcnts::updateEventWaitcntAfter(MachineInstr &Inst, break; case AMDGPU::S_MEMTIME: case AMDGPU::S_MEMREALTIME: + case AMDGPU::S_BARRIER_SIGNAL_ISFIRST_M0: + case AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM: + case AMDGPU::S_BARRIER_LEAVE: + case AMDGPU::S_GET_BARRIER_STATE_M0: + case AMDGPU::S_GET_BARRIER_STATE_IMM: ScoreBrackets->updateByEvent(TII, TRI, MRI, SMEM_ACCESS, Inst); break; } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index d4e4526795f3..d4746b559d92 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -4118,7 +4118,8 @@ bool SIInstrInfo::isInlineConstant(const MachineOperand &MO, case AMDGPU::OPERAND_REG_IMM_V2INT32: case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: case AMDGPU::OPERAND_REG_INLINE_AC_INT32: - case AMDGPU::OPERAND_REG_INLINE_AC_FP32: { + case AMDGPU::OPERAND_REG_INLINE_AC_FP32: + case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: { int32_t Trunc = static_cast<int32_t>(Imm); return AMDGPU::isInlinableLiteral32(Trunc, ST.hasInv2PiInlineImm()); } @@ -4559,6 +4560,12 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI, } break; } + case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: + if (!MI.getOperand(i).isImm() || !isInlineConstant(MI, i)) { + ErrInfo = "Expected inline constant for operand."; + return false; + } + break; case MCOI::OPERAND_IMMEDIATE: case AMDGPU::OPERAND_KIMM32: // Check if this operand is an immediate. @@ -5255,11 +5262,15 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const { case AMDGPU::S_SUB_F32: return AMDGPU::V_SUB_F32_e64; case AMDGPU::S_MIN_F32: return AMDGPU::V_MIN_F32_e64; case AMDGPU::S_MAX_F32: return AMDGPU::V_MAX_F32_e64; + case AMDGPU::S_MINIMUM_F32: return AMDGPU::V_MINIMUM_F32_e64; + case AMDGPU::S_MAXIMUM_F32: return AMDGPU::V_MAXIMUM_F32_e64; case AMDGPU::S_MUL_F32: return AMDGPU::V_MUL_F32_e64; case AMDGPU::S_ADD_F16: return AMDGPU::V_ADD_F16_fake16_e64; case AMDGPU::S_SUB_F16: return AMDGPU::V_SUB_F16_fake16_e64; case AMDGPU::S_MIN_F16: return AMDGPU::V_MIN_F16_fake16_e64; case AMDGPU::S_MAX_F16: return AMDGPU::V_MAX_F16_fake16_e64; + case AMDGPU::S_MINIMUM_F16: return AMDGPU::V_MINIMUM_F16_e64; + case AMDGPU::S_MAXIMUM_F16: return AMDGPU::V_MAXIMUM_F16_e64; case AMDGPU::S_MUL_F16: return AMDGPU::V_MUL_F16_fake16_e64; case AMDGPU::S_CVT_PK_RTZ_F16_F32: return AMDGPU::V_CVT_PKRTZ_F16_F32_e64; case AMDGPU::S_FMAC_F32: return AMDGPU::V_FMAC_F32_e64; @@ -7101,6 +7112,26 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist, Inst.eraseFromParent(); return; } + case AMDGPU::S_MINIMUM_F32: + case AMDGPU::S_MAXIMUM_F32: + case AMDGPU::S_MINIMUM_F16: + case AMDGPU::S_MAXIMUM_F16: { + const DebugLoc &DL = Inst.getDebugLoc(); + Register NewDst = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); + MachineInstr *NewInstr = BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst) + .addImm(0) // src0_modifiers + .add(Inst.getOperand(1)) + .addImm(0) // src1_modifiers + .add(Inst.getOperand(2)) + .addImm(0) // clamp + .addImm(0); // omod + MRI.replaceRegWith(Inst.getOperand(0).getReg(), NewDst); + + legalizeOperands(*NewInstr, MDT); + addUsersToMoveToVALUWorklist(NewDst, MRI, Worklist); + Inst.eraseFromParent(); + return; + } } if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) { diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index e794d8cf7cc2..32a81d67cc24 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -546,6 +546,14 @@ public: return get(Opcode).TSFlags & SIInstrFlags::DS; } + static bool isLDSDMA(const MachineInstr &MI) { + return isVALU(MI) && (isMUBUF(MI) || isFLAT(MI)); + } + + bool isLDSDMA(uint16_t Opcode) { + return isVALU(Opcode) && (isMUBUF(Opcode) || isFLAT(Opcode)); + } + static bool isGWS(const MachineInstr &MI) { return MI.getDesc().TSFlags & SIInstrFlags::GWS; } @@ -667,6 +675,10 @@ public: SIInstrFlags::IsAtomicNoRet); } + static bool mayWriteLDSThroughDMA(const MachineInstr &MI) { + return isLDSDMA(MI) && MI.getOpcode() != AMDGPU::BUFFER_STORE_LDS_DWORD; + } + static bool isWQM(const MachineInstr &MI) { return MI.getDesc().TSFlags & SIInstrFlags::WQM; } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 9e60bdda5ef3..6c106b8b68b5 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -919,6 +919,13 @@ def InterpAttr : CustomOperand<i32>; def InterpAttrChan : ImmOperand<i32>; +def SplitBarrier : ImmOperand<i32> { + let OperandNamespace = "AMDGPU"; + let OperandType = "OPERAND_INLINE_SPLIT_BARRIER_INT32"; + let DecoderMethod = "decodeSplitBarrier"; + let PrintMethod = "printOperand"; +} + def VReg32OrOffClass : AsmOperandClass { let Name = "VReg32OrOff"; let ParserMethod = "parseVReg32OrOff"; diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 9362fe5d9678..f9bc623abcd0 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -3441,6 +3441,12 @@ defm : Int16Med3Pat<V_MED3_I16_e64, smin, smax>; defm : Int16Med3Pat<V_MED3_U16_e64, umin, umax>; } // End Predicates = [isGFX9Plus] +let OtherPredicates = [isGFX12Plus] in { +def : FPMinMaxPat<V_MINIMUMMAXIMUM_F32_e64, f32, DivergentBinFrag<fmaximum>, fminimum_oneuse>; +def : FPMinMaxPat<V_MAXIMUMMINIMUM_F32_e64, f32, DivergentBinFrag<fminimum>, fmaximum_oneuse>; +def : FPMinMaxPat<V_MINIMUMMAXIMUM_F16_e64, f16, DivergentBinFrag<fmaximum>, fminimum_oneuse>; +def : FPMinMaxPat<V_MAXIMUMMINIMUM_F16_e64, f16, DivergentBinFrag<fminimum>, fmaximum_oneuse>; +} // Convert a floating-point power of 2 to the integer exponent. def FPPow2ToExponentXForm : SDNodeXForm<fpimm, [{ diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index e0c23e40e19d..48c341917dde 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -37,7 +37,7 @@ const GCNTargetMachine &getTM(const GCNSubtarget *STI) { SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F, const GCNSubtarget *STI) - : AMDGPUMachineFunction(F, *STI), Mode(F), GWSResourcePSV(getTM(STI)), + : AMDGPUMachineFunction(F, *STI), Mode(F, *STI), GWSResourcePSV(getTM(STI)), UserSGPRInfo(F, *STI), WorkGroupIDX(false), WorkGroupIDY(false), WorkGroupIDZ(false), WorkGroupInfo(false), LDSKernelId(false), PrivateSegmentWaveByteOffset(false), WorkItemIDX(false), diff --git a/llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp b/llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp index ffed268244ed..2684a1e3c335 100644 --- a/llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp +++ b/llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.cpp @@ -7,20 +7,26 @@ //===----------------------------------------------------------------------===// #include "SIModeRegisterDefaults.h" +#include "GCNSubtarget.h" using namespace llvm; -SIModeRegisterDefaults::SIModeRegisterDefaults(const Function &F) { +SIModeRegisterDefaults::SIModeRegisterDefaults(const Function &F, + const GCNSubtarget &ST) { *this = getDefaultForCallingConv(F.getCallingConv()); - StringRef IEEEAttr = F.getFnAttribute("amdgpu-ieee").getValueAsString(); - if (!IEEEAttr.empty()) - IEEE = IEEEAttr == "true"; + if (ST.hasIEEEMode()) { + StringRef IEEEAttr = F.getFnAttribute("amdgpu-ieee").getValueAsString(); + if (!IEEEAttr.empty()) + IEEE = IEEEAttr == "true"; + } - StringRef DX10ClampAttr = - F.getFnAttribute("amdgpu-dx10-clamp").getValueAsString(); - if (!DX10ClampAttr.empty()) - DX10Clamp = DX10ClampAttr == "true"; + if (ST.hasDX10ClampMode()) { + StringRef DX10ClampAttr = + F.getFnAttribute("amdgpu-dx10-clamp").getValueAsString(); + if (!DX10ClampAttr.empty()) + DX10Clamp = DX10ClampAttr == "true"; + } StringRef DenormF32Attr = F.getFnAttribute("denormal-fp-math-f32").getValueAsString(); diff --git a/llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.h b/llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.h index 58e2c67c248b..9fbd74c3eede 100644 --- a/llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.h +++ b/llvm/lib/Target/AMDGPU/SIModeRegisterDefaults.h @@ -14,6 +14,8 @@ namespace llvm { +class GCNSubtarget; + // Track defaults for fields in the MODE register. struct SIModeRegisterDefaults { /// Floating point opcodes that support exception flag gathering quiet and @@ -40,7 +42,7 @@ struct SIModeRegisterDefaults { FP32Denormals(DenormalMode::getIEEE()), FP64FP16Denormals(DenormalMode::getIEEE()) {} - SIModeRegisterDefaults(const Function &F); + SIModeRegisterDefaults(const Function &F, const GCNSubtarget &ST); static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) { SIModeRegisterDefaults Mode; diff --git a/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp index b6839c8308d8..9ed7aacc0538 100644 --- a/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIProgramInfo.cpp @@ -15,27 +15,48 @@ // #include "SIProgramInfo.h" +#include "GCNSubtarget.h" #include "SIDefines.h" #include "Utils/AMDGPUBaseInfo.h" using namespace llvm; -uint64_t SIProgramInfo::getComputePGMRSrc1() const { - return S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) | - S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) | - S_00B848_PRIV(Priv) | S_00B848_DX10_CLAMP(DX10Clamp) | - S_00B848_DEBUG_MODE(DebugMode) | S_00B848_IEEE_MODE(IEEEMode) | - S_00B848_WGP_MODE(WgpMode) | S_00B848_MEM_ORDERED(MemOrdered); +uint64_t SIProgramInfo::getComputePGMRSrc1(const GCNSubtarget &ST) const { + uint64_t Reg = S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) | + S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) | + S_00B848_PRIV(Priv) | S_00B848_DEBUG_MODE(DebugMode) | + S_00B848_WGP_MODE(WgpMode) | S_00B848_MEM_ORDERED(MemOrdered); + + if (ST.hasDX10ClampMode()) + Reg |= S_00B848_DX10_CLAMP(DX10Clamp); + + if (ST.hasIEEEMode()) + Reg |= S_00B848_IEEE_MODE(IEEEMode); + + if (ST.hasRrWGMode()) + Reg |= S_00B848_RR_WG_MODE(RrWgMode); + + return Reg; } -uint64_t SIProgramInfo::getPGMRSrc1(CallingConv::ID CC) const { +uint64_t SIProgramInfo::getPGMRSrc1(CallingConv::ID CC, + const GCNSubtarget &ST) const { if (AMDGPU::isCompute(CC)) { - return getComputePGMRSrc1(); + return getComputePGMRSrc1(ST); } uint64_t Reg = S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) | S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) | - S_00B848_PRIV(Priv) | S_00B848_DX10_CLAMP(DX10Clamp) | - S_00B848_DEBUG_MODE(DebugMode) | S_00B848_IEEE_MODE(IEEEMode); + S_00B848_PRIV(Priv) | S_00B848_DEBUG_MODE(DebugMode); + + if (ST.hasDX10ClampMode()) + Reg |= S_00B848_DX10_CLAMP(DX10Clamp); + + if (ST.hasIEEEMode()) + Reg |= S_00B848_IEEE_MODE(IEEEMode); + + if (ST.hasRrWGMode()) + Reg |= S_00B848_RR_WG_MODE(RrWgMode); + switch (CC) { case CallingConv::AMDGPU_PS: Reg |= S_00B028_MEM_ORDERED(MemOrdered); diff --git a/llvm/lib/Target/AMDGPU/SIProgramInfo.h b/llvm/lib/Target/AMDGPU/SIProgramInfo.h index aab127e49463..8c26789f936c 100644 --- a/llvm/lib/Target/AMDGPU/SIProgramInfo.h +++ b/llvm/lib/Target/AMDGPU/SIProgramInfo.h @@ -21,6 +21,8 @@ namespace llvm { +class GCNSubtarget; + /// Track resource usage for kernels / entry functions. struct SIProgramInfo { // Fields set in PGM_RSRC1 pm4 packet. @@ -34,6 +36,7 @@ struct SIProgramInfo { uint32_t IEEEMode = 0; uint32_t WgpMode = 0; // GFX10+ uint32_t MemOrdered = 0; // GFX10+ + uint32_t RrWgMode = 0; // GFX12+ uint64_t ScratchSize = 0; // State used to calculate fields set in PGM_RSRC2 pm4 packet. @@ -85,8 +88,8 @@ struct SIProgramInfo { SIProgramInfo() = default; /// Compute the value of the ComputePGMRsrc1 register. - uint64_t getComputePGMRSrc1() const; - uint64_t getPGMRSrc1(CallingConv::ID CC) const; + uint64_t getComputePGMRSrc1(const GCNSubtarget &ST) const; + uint64_t getPGMRSrc1(CallingConv::ID CC, const GCNSubtarget &ST) const; /// Compute the value of the ComputePGMRsrc2 register. uint64_t getComputePGMRSrc2() const; diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 9ff64968ef01..50c4d279cfe2 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -438,6 +438,89 @@ let SubtargetPredicate = HasSALUFloatInsts, Uses = [MODE], } // End SubtargetPredicate = HasSALUFloatInsts, Uses = [MODE] // SchedRW = [WriteSFPU], isReMaterializable = 1 +let hasSideEffects = 1 in { +let has_sdst = 0 in { +let Uses = [M0] in { +def S_BARRIER_SIGNAL_M0 : SOP1_Pseudo <"s_barrier_signal m0", (outs), (ins), + "", [(int_amdgcn_s_barrier_signal_var M0)]>{ + let SchedRW = [WriteBarrier]; + let isConvergent = 1; +} + +def S_BARRIER_SIGNAL_ISFIRST_M0 : SOP1_Pseudo <"s_barrier_signal_isfirst m0", (outs), (ins), + "", [(set SCC, (int_amdgcn_s_barrier_signal_isfirst_var M0))]>{ + let Defs = [SCC]; + let SchedRW = [WriteBarrier]; + let isConvergent = 1; +} + +def S_BARRIER_INIT_M0 : SOP1_Pseudo <"s_barrier_init m0", (outs), (ins), + "", []>{ + let SchedRW = [WriteBarrier]; + let isConvergent = 1; +} + +def S_BARRIER_INIT_IMM : SOP1_Pseudo <"s_barrier_init", (outs), + (ins SplitBarrier:$src0), "$src0", []>{ + let SchedRW = [WriteBarrier]; + let isConvergent = 1; +} + +def S_BARRIER_JOIN_M0 : SOP1_Pseudo <"s_barrier_join m0", (outs), (ins), + "", []>{ + let SchedRW = [WriteBarrier]; + let isConvergent = 1; +} + +def S_WAKEUP_BARRIER_M0 : SOP1_Pseudo <"s_wakeup_barrier m0", (outs), (ins), + "", []>{ + let SchedRW = [WriteBarrier]; + let isConvergent = 1; +} +} // End Uses = [M0] + +def S_BARRIER_SIGNAL_IMM : SOP1_Pseudo <"s_barrier_signal", (outs), + (ins SplitBarrier:$src0), "$src0", [(int_amdgcn_s_barrier_signal timm:$src0)]>{ + let SchedRW = [WriteBarrier]; + let isConvergent = 1; +} + +def S_BARRIER_SIGNAL_ISFIRST_IMM : SOP1_Pseudo <"s_barrier_signal_isfirst", (outs), + (ins SplitBarrier:$src0), "$src0", [(set SCC, (int_amdgcn_s_barrier_signal_isfirst timm:$src0))]>{ + let Defs = [SCC]; + let SchedRW = [WriteBarrier]; + let isConvergent = 1; +} + +def S_BARRIER_JOIN_IMM : SOP1_Pseudo <"s_barrier_join", (outs), + (ins SplitBarrier:$src0), "$src0", []>{ + let SchedRW = [WriteBarrier]; + let isConvergent = 1; +} + +def S_WAKEUP_BARRIER_IMM : SOP1_Pseudo <"s_wakeup_barrier", (outs), + (ins SplitBarrier:$src0), "$src0", []>{ + let SchedRW = [WriteBarrier]; + let isConvergent = 1; + + +} +} // End has_sdst = 0 + +def S_GET_BARRIER_STATE_IMM : SOP1_Pseudo <"s_get_barrier_state", (outs SSrc_b32:$sdst), + (ins SplitBarrier:$src0), "$sdst, $src0", []>{ + let SchedRW = [WriteBarrier]; + let isConvergent = 1; +} + +def S_GET_BARRIER_STATE_M0 : SOP1_Pseudo <"s_get_barrier_state $sdst, m0", (outs SSrc_b32:$sdst), + (ins), "", []>{ + let Uses = [M0]; + let SchedRW = [WriteBarrier]; + let isConvergent = 1; +} +} // End hasSideEffects = 1 + //===----------------------------------------------------------------------===// // SOP2 Instructions //===----------------------------------------------------------------------===// @@ -847,6 +930,15 @@ let SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1, } // End SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1, // Uses = [MODE], SchedRW = [WriteSFPU] +// On GFX12 MIN/MAX instructions do not read MODE register. +let SubtargetPredicate = isGFX12Plus, mayRaiseFPException = 1, isCommutable = 1, + isReMaterializable = 1, SchedRW = [WriteSFPU] in { + def S_MINIMUM_F32 : SOP2_F32_Inst<"s_minimum_f32", fminimum>; + def S_MAXIMUM_F32 : SOP2_F32_Inst<"s_maximum_f32", fmaximum>; + def S_MINIMUM_F16 : SOP2_F16_Inst<"s_minimum_f16", fminimum>; + def S_MAXIMUM_F16 : SOP2_F16_Inst<"s_maximum_f16", fmaximum>; +} + //===----------------------------------------------------------------------===// // SOPK Instructions //===----------------------------------------------------------------------===// @@ -1473,6 +1565,21 @@ def S_BARRIER : SOPP_Pseudo <"s_barrier", (ins), "", let isConvergent = 1; } +def S_BARRIER_WAIT : SOPP_Pseudo <"s_barrier_wait", (ins i16imm:$simm16), "$simm16", + [(int_amdgcn_s_barrier_wait timm:$simm16)]> { + let SchedRW = [WriteBarrier]; + let isConvergent = 1; +} + +def S_BARRIER_LEAVE : SOPP_Pseudo <"s_barrier_leave", (ins), "", + [(set SCC, (int_amdgcn_s_barrier_leave))]> { + let SchedRW = [WriteBarrier]; + let simm16 = 0; + let fixed_imm = 1; + let isConvergent = 1; + let Defs = [SCC]; +} + def S_WAKEUP : SOPP_Pseudo <"s_wakeup", (ins) > { let SubtargetPredicate = isGFX8Plus; let simm16 = 0; @@ -1878,6 +1985,18 @@ defm S_SWAPPC_B64 : SOP1_Real_gfx11_gfx12<0x049>; defm S_RFE_B64 : SOP1_Real_gfx11_gfx12<0x04a>; defm S_SENDMSG_RTN_B32 : SOP1_Real_gfx11_gfx12<0x04c>; defm S_SENDMSG_RTN_B64 : SOP1_Real_gfx11_gfx12<0x04d>; +defm S_BARRIER_SIGNAL_M0 : SOP1_M0_Real_gfx12<0x04e>; +defm S_BARRIER_SIGNAL_ISFIRST_M0 : SOP1_M0_Real_gfx12<0x04f>; +defm S_GET_BARRIER_STATE_M0 : SOP1_M0_Real_gfx12<0x050>; +defm S_BARRIER_INIT_M0 : SOP1_M0_Real_gfx12<0x051>; +defm S_BARRIER_JOIN_M0 : SOP1_M0_Real_gfx12<0x052>; +defm S_WAKEUP_BARRIER_M0 : SOP1_M0_Real_gfx12<0x057>; +defm S_BARRIER_SIGNAL_IMM : SOP1_Real_gfx12<0x04e>; +defm S_BARRIER_SIGNAL_ISFIRST_IMM : SOP1_Real_gfx12<0x04f>; +defm S_GET_BARRIER_STATE_IMM : SOP1_Real_gfx12<0x050>; +defm S_BARRIER_INIT_IMM : SOP1_Real_gfx12<0x051>; +defm S_BARRIER_JOIN_IMM : SOP1_Real_gfx12<0x052>; +defm S_WAKEUP_BARRIER_IMM : SOP1_Real_gfx12<0x057>; //===----------------------------------------------------------------------===// // SOP1 - GFX1150, GFX12 @@ -2017,6 +2136,10 @@ defm S_MIN_NUM_F32 : SOP2_Real_Renamed_gfx12<0x042, S_MIN_F32, "s_min_num_f32">; defm S_MAX_NUM_F32 : SOP2_Real_Renamed_gfx12<0x043, S_MAX_F32, "s_max_num_f32">; defm S_MIN_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04b, S_MIN_F16, "s_min_num_f16">; defm S_MAX_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04c, S_MAX_F16, "s_max_num_f16">; +defm S_MINIMUM_F32 : SOP2_Real_gfx12<0x04f>; +defm S_MAXIMUM_F32 : SOP2_Real_gfx12<0x050>; +defm S_MINIMUM_F16 : SOP2_Real_gfx12<0x051>; +defm S_MAXIMUM_F16 : SOP2_Real_gfx12<0x052>; defm S_ADD_CO_U32 : SOP2_Real_Renamed_gfx12<0x000, S_ADD_U32, "s_add_co_u32">; defm S_SUB_CO_U32 : SOP2_Real_Renamed_gfx12<0x001, S_SUB_U32, "s_sub_co_u32">; @@ -2365,6 +2488,8 @@ multiclass SOPP_Real_32_Renamed_gfx12<bits<7> op, SOPP_Pseudo backing_pseudo, st } defm S_WAIT_ALU : SOPP_Real_32_Renamed_gfx12<0x008, S_WAITCNT_DEPCTR, "s_wait_alu">; +defm S_BARRIER_WAIT : SOPP_Real_32_gfx12<0x014>; +defm S_BARRIER_LEAVE : SOPP_Real_32_gfx12<0x015>; //===----------------------------------------------------------------------===// // SOPP - GFX11, GFX12. diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index ede70c3f3404..a30e4cc67448 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -1147,10 +1147,17 @@ amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor( AMDHSA_BITS_SET(KD.compute_pgm_rsrc1, amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE); - AMDHSA_BITS_SET(KD.compute_pgm_rsrc1, - amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, 1); - AMDHSA_BITS_SET(KD.compute_pgm_rsrc1, - amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE, 1); + if (Version.Major >= 12) { + AMDHSA_BITS_SET(KD.compute_pgm_rsrc1, + amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN, 0); + AMDHSA_BITS_SET(KD.compute_pgm_rsrc1, + amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_DISABLE_PERF, 0); + } else { + AMDHSA_BITS_SET(KD.compute_pgm_rsrc1, + amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP, 1); + AMDHSA_BITS_SET(KD.compute_pgm_rsrc1, + amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE, 1); + } AMDHSA_BITS_SET(KD.compute_pgm_rsrc2, amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, 1); if (Version.Major >= 10) { diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h index bd333ed2cca7..d63b0d6a6e78 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -1238,6 +1238,7 @@ inline unsigned getOperandSize(const MCOperandInfo &OpInfo) { case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: case AMDGPU::OPERAND_KIMM32: case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4 + case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32: return 4; case AMDGPU::OPERAND_REG_IMM_INT64: diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp index cbdbf1c16f9f..25e628e5cbc5 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp @@ -74,6 +74,16 @@ bool isReallyAClobber(const Value *Ptr, MemoryDef *Def, AAResults *AA) { if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(DefInst)) { switch (II->getIntrinsicID()) { case Intrinsic::amdgcn_s_barrier: + case Intrinsic::amdgcn_s_barrier_signal: + case Intrinsic::amdgcn_s_barrier_signal_var: + case Intrinsic::amdgcn_s_barrier_signal_isfirst: + case Intrinsic::amdgcn_s_barrier_signal_isfirst_var: + case Intrinsic::amdgcn_s_barrier_init: + case Intrinsic::amdgcn_s_barrier_join: + case Intrinsic::amdgcn_s_barrier_wait: + case Intrinsic::amdgcn_s_barrier_leave: + case Intrinsic::amdgcn_s_get_barrier_state: + case Intrinsic::amdgcn_s_wakeup_barrier: case Intrinsic::amdgcn_wave_barrier: case Intrinsic::amdgcn_sched_barrier: case Intrinsic::amdgcn_sched_group_barrier: diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index 617773b34ae9..685c9ac6a2be 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -161,6 +161,19 @@ defm V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", V_MUL_PROF<VOP_I32_I32_I32>, mulhu defm V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", V_MUL_PROF<VOP_I32_I32_I32>>; defm V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", V_MUL_PROF<VOP_I32_I32_I32>, mulhs>; } // End SchedRW = [WriteIntMul] + +let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in { +defm V_MINIMUM_F32 : VOP3Inst <"v_minimum_f32", VOP3_Profile<VOP_F32_F32_F32>, DivergentBinFrag<fminimum>>; +defm V_MAXIMUM_F32 : VOP3Inst <"v_maximum_f32", VOP3_Profile<VOP_F32_F32_F32>, DivergentBinFrag<fmaximum>>; +defm V_MINIMUM_F16 : VOP3Inst <"v_minimum_f16", VOP3_Profile<VOP_F16_F16_F16>, DivergentBinFrag<fminimum>>; +defm V_MAXIMUM_F16 : VOP3Inst <"v_maximum_f16", VOP3_Profile<VOP_F16_F16_F16>, DivergentBinFrag<fmaximum>>; + +let SchedRW = [WriteDoubleAdd] in { +defm V_MINIMUM_F64 : VOP3Inst <"v_minimum_f64", VOP3_Profile<VOP_F64_F64_F64>, fminimum>; +defm V_MAXIMUM_F64 : VOP3Inst <"v_maximum_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaximum>; +} // End SchedRW = [WriteDoubleAdd] +} // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 + } // End isReMaterializable = 1 let Uses = [MODE, VCC, EXEC] in { @@ -211,6 +224,11 @@ let mayRaiseFPException = 0 in { defm V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>; } // End mayRaiseFPException = 0 +let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in { + defm V_MINIMUM3_F32 : VOP3Inst <"v_minimum3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfminimum3>; + defm V_MAXIMUM3_F32 : VOP3Inst <"v_maximum3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmaximum3>; +} // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 + let isCommutable = 1 in { defm V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; defm V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; @@ -555,6 +573,11 @@ defm V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3 defm V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>; defm V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>; +let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in { + defm V_MINIMUM3_F16 : VOP3Inst <"v_minimum3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfminimum3>; + defm V_MAXIMUM3_F16 : VOP3Inst <"v_maximum3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmaximum3>; +} // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 + defm V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; defm V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>; @@ -805,6 +828,13 @@ let SubtargetPredicate = isGFX11Plus in { defm V_CVT_PK_U16_F32 : VOP3Inst<"v_cvt_pk_u16_f32", VOP3_Profile<VOP_V2I16_F32_F32>>; } // End SubtargetPredicate = isGFX11Plus +let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in { + defm V_MAXIMUMMINIMUM_F32 : VOP3Inst<"v_maximumminimum_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; + defm V_MINIMUMMAXIMUM_F32 : VOP3Inst<"v_minimummaximum_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>; + defm V_MAXIMUMMINIMUM_F16 : VOP3Inst<"v_maximumminimum_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>; + defm V_MINIMUMMAXIMUM_F16 : VOP3Inst<"v_minimummaximum_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>; +} // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 + let SubtargetPredicate = HasDot9Insts, IsDOT=1 in { defm V_DOT2_F16_F16 : VOP3Inst<"v_dot2_f16_f16", VOP3_DOT_Profile<VOP_F16_V2F16_V2F16_F16>, int_amdgcn_fdot2_f16_f16>; defm V_DOT2_BF16_BF16 : VOP3Inst<"v_dot2_bf16_bf16", VOP3_DOT_Profile<VOP_I16_V2I16_V2I16_I16>, int_amdgcn_fdot2_bf16_bf16>; @@ -862,14 +892,28 @@ defm V_MIN3_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x229, "V_MIN3_F32", defm V_MAX3_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x22a, "V_MAX3_F32", "v_max3_num_f32">; defm V_MIN3_NUM_F16 : VOP3_Realtriple_with_name_gfx12<0x22b, "V_MIN3_F16", "v_min3_num_f16">; defm V_MAX3_NUM_F16 : VOP3_Realtriple_with_name_gfx12<0x22c, "V_MAX3_F16", "v_max3_num_f16">; +defm V_MINIMUM3_F32 : VOP3Only_Realtriple_gfx12<0x22d>; +defm V_MAXIMUM3_F32 : VOP3Only_Realtriple_gfx12<0x22e>; +defm V_MINIMUM3_F16 : VOP3Only_Realtriple_t16_gfx12<0x22f>; +defm V_MAXIMUM3_F16 : VOP3Only_Realtriple_t16_gfx12<0x230>; defm V_MED3_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x231, "V_MED3_F32", "v_med3_num_f32">; defm V_MED3_NUM_F16 : VOP3_Realtriple_with_name_gfx12<0x232, "V_MED3_F16", "v_med3_num_f16">; defm V_MINMAX_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x268, "V_MINMAX_F32", "v_minmax_num_f32">; defm V_MAXMIN_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x269, "V_MAXMIN_F32", "v_maxmin_num_f32">; defm V_MINMAX_NUM_F16 : VOP3_Realtriple_with_name_gfx12<0x26a, "V_MINMAX_F16", "v_minmax_num_f16">; defm V_MAXMIN_NUM_F16 : VOP3_Realtriple_with_name_gfx12<0x26b, "V_MAXMIN_F16", "v_maxmin_num_f16">; +defm V_MINIMUMMAXIMUM_F32 : VOP3Only_Realtriple_gfx12<0x26c>; +defm V_MAXIMUMMINIMUM_F32 : VOP3Only_Realtriple_gfx12<0x26d>; +defm V_MINIMUMMAXIMUM_F16 : VOP3Only_Realtriple_t16_gfx12<0x26e>; +defm V_MAXIMUMMINIMUM_F16 : VOP3Only_Realtriple_t16_gfx12<0x26f>; defm V_MAD_CO_U64_U32 : VOP3be_Real_with_name_gfx12<0x2fe, "V_MAD_U64_U32", "v_mad_co_u64_u32">; defm V_MAD_CO_I64_I32 : VOP3be_Real_with_name_gfx12<0x2ff, "V_MAD_I64_I32", "v_mad_co_i64_i32">; +defm V_MINIMUM_F64 : VOP3Only_Real_Base_gfx12<0x341>; +defm V_MAXIMUM_F64 : VOP3Only_Real_Base_gfx12<0x342>; +defm V_MINIMUM_F32 : VOP3Only_Realtriple_gfx12<0x365>; +defm V_MAXIMUM_F32 : VOP3Only_Realtriple_gfx12<0x366>; +defm V_MINIMUM_F16 : VOP3Only_Realtriple_t16_gfx12<0x367>; +defm V_MAXIMUM_F16 : VOP3Only_Realtriple_t16_gfx12<0x368>; //===----------------------------------------------------------------------===// // GFX11, GFX12 diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td index eb8990238268..d3cefb339d9e 100644 --- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td @@ -108,6 +108,11 @@ defm V_PK_MIN_I16 : VOP3PInst<"v_pk_min_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I1 defm V_PK_MIN_U16 : VOP3PInst<"v_pk_min_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, umin>; defm V_PK_MAX_I16 : VOP3PInst<"v_pk_max_i16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, smax>; defm V_PK_MAX_U16 : VOP3PInst<"v_pk_max_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>, umax>; + +let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in { +defm V_PK_MAXIMUM_F16 : VOP3PInst<"v_pk_maximum_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16>, fmaximum>; +defm V_PK_MINIMUM_F16 : VOP3PInst<"v_pk_minimum_f16", VOP3P_Profile<VOP_V2F16_V2F16_V2F16>, fminimum>; +} // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 } defm V_PK_SUB_U16 : VOP3PInst<"v_pk_sub_u16", VOP3P_Profile<VOP_V2I16_V2I16_V2I16>>; @@ -1003,6 +1008,9 @@ multiclass VOP3P_Real_with_name_gfx12<bits<7> op, defm V_PK_MIN_NUM_F16 : VOP3P_Real_with_name_gfx12<0x1b, "V_PK_MIN_F16", "v_pk_min_num_f16">; defm V_PK_MAX_NUM_F16 : VOP3P_Real_with_name_gfx12<0x1c, "V_PK_MAX_F16", "v_pk_max_num_f16">; +defm V_PK_MINIMUM_F16 : VOP3P_Real_gfx12<0x1d>; +defm V_PK_MAXIMUM_F16 : VOP3P_Real_gfx12<0x1e>; + //===----------------------------------------------------------------------===// // GFX11 //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp index ccbb650c6536..5e2106e9184f 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -484,7 +484,10 @@ void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo, if (!MI->getOperand(OpNo).isImm()) return printOperand(MI, OpNo, STI, O); - O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2); + uint64_t Imm = MI->getOperand(OpNo).getImm() << 2; + if (!TT.isPPC64()) + Imm = static_cast<uint32_t>(Imm); + O << formatHex(Imm); } void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo, diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index 6151faf403aa..375e63654db1 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -798,6 +798,7 @@ def directbrtarget : Operand<OtherVT> { def absdirectbrtarget : Operand<OtherVT> { let PrintMethod = "printAbsBranchOperand"; let EncoderMethod = "getAbsDirectBrEncoding"; + let DecoderMethod = "decodeDirectBrTarget"; let ParserMatchClass = PPCDirectBrAsmOperand; } def PPCCondBrAsmOperand : AsmOperandClass { @@ -814,6 +815,7 @@ def condbrtarget : Operand<OtherVT> { def abscondbrtarget : Operand<OtherVT> { let PrintMethod = "printAbsBranchOperand"; let EncoderMethod = "getAbsCondBrEncoding"; + let DecoderMethod = "decodeCondBrTarget"; let ParserMatchClass = PPCCondBrAsmOperand; } def calltarget : Operand<iPTR> { @@ -826,6 +828,7 @@ def calltarget : Operand<iPTR> { def abscalltarget : Operand<iPTR> { let PrintMethod = "printAbsBranchOperand"; let EncoderMethod = "getAbsDirectBrEncoding"; + let DecoderMethod = "decodeDirectBrTarget"; let ParserMatchClass = PPCDirectBrAsmOperand; } def PPCCRBitMaskOperand : AsmOperandClass { diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 0b682b0cbb33..c0462dc4b0bc 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1363,9 +1363,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setPrefFunctionAlignment(Subtarget.getPrefFunctionAlignment()); setPrefLoopAlignment(Subtarget.getPrefLoopAlignment()); - // Jumps are expensive, compared to logic - setJumpIsExpensive(); - setTargetDAGCombine({ISD::INTRINSIC_VOID, ISD::INTRINSIC_W_CHAIN, ISD::INTRINSIC_WO_CHAIN, ISD::ADD, ISD::SUB, ISD::AND, ISD::OR, ISD::XOR, ISD::SETCC, ISD::SELECT}); diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index 096d7ce0cb64..bc04b9f768e5 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -1291,9 +1291,20 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) { if (RISCVII::hasVLOp(TSFlags)) { MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI)); if (VLOp.isReg()) { + Register Reg = VLOp.getReg(); + MachineInstr *VLOpDef = MRI->getVRegDef(Reg); + // Erase the AVL operand from the instruction. VLOp.setReg(RISCV::NoRegister); VLOp.setIsKill(false); + + // If the AVL was an immediate > 31, then it would have been emitted + // as an ADDI. However, the ADDI might not have been used in the + // vsetvli, or a vsetvli might not have been emitted, so it may be + // dead now. + if (VLOpDef && TII->isAddImmediate(*VLOpDef, Reg) && + MRI->use_nodbg_empty(Reg)) + VLOpDef->eraseFromParent(); } MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false, /*isImp*/ true)); diff --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp index 6b85de15947c..f37b4dc938d3 100644 --- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp @@ -964,12 +964,17 @@ static void cacheDIVar(FrameDataInfo &FrameData, continue; SmallVector<DbgDeclareInst *, 1> DDIs; - findDbgDeclares(DDIs, V); - auto *I = llvm::find_if(DDIs, [](DbgDeclareInst *DDI) { - return DDI->getExpression()->getNumElements() == 0; - }); - if (I != DDIs.end()) - DIVarCache.insert({V, (*I)->getVariable()}); + SmallVector<DPValue *, 1> DPVs; + findDbgDeclares(DDIs, V, &DPVs); + auto CacheIt = [&DIVarCache, V](auto &Container) { + auto *I = llvm::find_if(Container, [](auto *DDI) { + return DDI->getExpression()->getNumElements() == 0; + }); + if (I != Container.end()) + DIVarCache.insert({V, (*I)->getVariable()}); + }; + CacheIt(DDIs); + CacheIt(DPVs); } } @@ -1121,15 +1126,25 @@ static void buildFrameDebugInfo(Function &F, coro::Shape &Shape, "Coroutine with switch ABI should own Promise alloca"); SmallVector<DbgDeclareInst *, 1> DIs; - findDbgDeclares(DIs, PromiseAlloca); - if (DIs.empty()) + SmallVector<DPValue *, 1> DPVs; + findDbgDeclares(DIs, PromiseAlloca, &DPVs); + + DILocalVariable *PromiseDIVariable = nullptr; + DILocation *DILoc = nullptr; + if (!DIs.empty()) { + DbgDeclareInst *PromiseDDI = DIs.front(); + PromiseDIVariable = PromiseDDI->getVariable(); + DILoc = PromiseDDI->getDebugLoc().get(); + } else if (!DPVs.empty()) { + DPValue *PromiseDPV = DPVs.front(); + PromiseDIVariable = PromiseDPV->getVariable(); + DILoc = PromiseDPV->getDebugLoc().get(); + } else { return; + } - DbgDeclareInst *PromiseDDI = DIs.front(); - DILocalVariable *PromiseDIVariable = PromiseDDI->getVariable(); DILocalScope *PromiseDIScope = PromiseDIVariable->getScope(); DIFile *DFile = PromiseDIScope->getFile(); - DILocation *DILoc = PromiseDDI->getDebugLoc().get(); unsigned LineNum = PromiseDIVariable->getLine(); DICompositeType *FrameDITy = DBuilder.createStructType( @@ -1243,7 +1258,7 @@ static void buildFrameDebugInfo(Function &F, coro::Shape &Shape, auto *FrameDIVar = DBuilder.createAutoVariable(PromiseDIScope, "__coro_frame", DFile, LineNum, FrameDITy, true, DINode::FlagArtificial); - assert(FrameDIVar->isValidLocationForIntrinsic(PromiseDDI->getDebugLoc())); + assert(FrameDIVar->isValidLocationForIntrinsic(DILoc)); // Subprogram would have ContainedNodes field which records the debug // variables it contained. So we need to add __coro_frame to the @@ -1261,9 +1276,17 @@ static void buildFrameDebugInfo(Function &F, coro::Shape &Shape, 7, (MDTuple::get(F.getContext(), RetainedNodesVec))); } - DBuilder.insertDeclare(Shape.FramePtr, FrameDIVar, - DBuilder.createExpression(), DILoc, - Shape.getInsertPtAfterFramePtr()); + if (UseNewDbgInfoFormat) { + DPValue *NewDPV = new DPValue(ValueAsMetadata::get(Shape.FramePtr), + FrameDIVar, DBuilder.createExpression(), + DILoc, DPValue::LocationType::Declare); + BasicBlock::iterator It = Shape.getInsertPtAfterFramePtr(); + It->getParent()->insertDPValueBefore(NewDPV, It); + } else { + DBuilder.insertDeclare(Shape.FramePtr, FrameDIVar, + DBuilder.createExpression(), DILoc, + &*Shape.getInsertPtAfterFramePtr()); + } } // Build a struct that will keep state for an active coroutine. @@ -1771,7 +1794,7 @@ static void insertSpills(const FrameDataInfo &FrameData, coro::Shape &Shape) { if (auto *Arg = dyn_cast<Argument>(Def)) { // For arguments, we will place the store instruction right after // the coroutine frame pointer instruction, i.e. coro.begin. - InsertPt = Shape.getInsertPtAfterFramePtr()->getIterator(); + InsertPt = Shape.getInsertPtAfterFramePtr(); // If we're spilling an Argument, make sure we clear 'nocapture' // from the coroutine function. @@ -1788,7 +1811,7 @@ static void insertSpills(const FrameDataInfo &FrameData, coro::Shape &Shape) { if (!DT.dominates(CB, I)) { // If it is not dominated by CoroBegin, then spill should be // inserted immediately after CoroFrame is computed. - InsertPt = Shape.getInsertPtAfterFramePtr()->getIterator(); + InsertPt = Shape.getInsertPtAfterFramePtr(); } else if (auto *II = dyn_cast<InvokeInst>(I)) { // If we are spilling the result of the invoke instruction, split // the normal edge and insert the spill in the new block. @@ -1843,7 +1866,8 @@ static void insertSpills(const FrameDataInfo &FrameData, coro::Shape &Shape) { SpillAlignment, E.first->getName() + Twine(".reload")); SmallVector<DbgDeclareInst *, 1> DIs; - findDbgDeclares(DIs, Def); + SmallVector<DPValue *, 1> DPVs; + findDbgDeclares(DIs, Def, &DPVs); // Try best to find dbg.declare. If the spill is a temp, there may not // be a direct dbg.declare. Walk up the load chain to find one from an // alias. @@ -1858,24 +1882,36 @@ static void insertSpills(const FrameDataInfo &FrameData, coro::Shape &Shape) { if (!isa<AllocaInst, LoadInst>(CurDef)) break; DIs.clear(); - findDbgDeclares(DIs, CurDef); + DPVs.clear(); + findDbgDeclares(DIs, CurDef, &DPVs); } } - for (DbgDeclareInst *DDI : DIs) { + auto SalvageOne = [&](auto *DDI) { bool AllowUnresolved = false; // This dbg.declare is preserved for all coro-split function // fragments. It will be unreachable in the main function, and // processed by coro::salvageDebugInfo() by CoroCloner. - DIBuilder(*CurrentBlock->getParent()->getParent(), AllowUnresolved) - .insertDeclare(CurrentReload, DDI->getVariable(), - DDI->getExpression(), DDI->getDebugLoc(), - &*Builder.GetInsertPoint()); + if (UseNewDbgInfoFormat) { + DPValue *NewDPV = + new DPValue(ValueAsMetadata::get(CurrentReload), + DDI->getVariable(), DDI->getExpression(), + DDI->getDebugLoc(), DPValue::LocationType::Declare); + Builder.GetInsertPoint()->getParent()->insertDPValueBefore( + NewDPV, Builder.GetInsertPoint()); + } else { + DIBuilder(*CurrentBlock->getParent()->getParent(), AllowUnresolved) + .insertDeclare(CurrentReload, DDI->getVariable(), + DDI->getExpression(), DDI->getDebugLoc(), + &*Builder.GetInsertPoint()); + } // This dbg.declare is for the main function entry point. It // will be deleted in all coro-split functions. - coro::salvageDebugInfo(ArgToAllocaMap, DDI, Shape.OptimizeFrame, + coro::salvageDebugInfo(ArgToAllocaMap, *DDI, Shape.OptimizeFrame, false /*UseEntryValue*/); - } + }; + for_each(DIs, SalvageOne); + for_each(DPVs, SalvageOne); } // If we have a single edge PHINode, remove it and replace it with a @@ -1893,6 +1929,10 @@ static void insertSpills(const FrameDataInfo &FrameData, coro::Shape &Shape) { // Replace all uses of CurrentValue in the current instruction with // reload. U->replaceUsesOfWith(Def, CurrentReload); + // Instructions are added to Def's user list if the attached + // debug records use Def. Update those now. + for (auto &DPV : U->getDbgValueRange()) + DPV.replaceVariableLocationOp(Def, CurrentReload, true); } } @@ -1943,9 +1983,12 @@ static void insertSpills(const FrameDataInfo &FrameData, coro::Shape &Shape) { G->setName(Alloca->getName() + Twine(".reload.addr")); SmallVector<DbgVariableIntrinsic *, 4> DIs; - findDbgUsers(DIs, Alloca); + SmallVector<DPValue *> DPValues; + findDbgUsers(DIs, Alloca, &DPValues); for (auto *DVI : DIs) DVI->replaceUsesOfWith(Alloca, G); + for (auto *DPV : DPValues) + DPV->replaceVariableLocationOp(Alloca, G); for (Instruction *I : UsersToUpdate) { // It is meaningless to retain the lifetime intrinsics refer for the @@ -1959,7 +2002,7 @@ static void insertSpills(const FrameDataInfo &FrameData, coro::Shape &Shape) { I->replaceUsesOfWith(Alloca, G); } } - Builder.SetInsertPoint(Shape.getInsertPtAfterFramePtr()); + Builder.SetInsertPoint(&*Shape.getInsertPtAfterFramePtr()); for (const auto &A : FrameData.Allocas) { AllocaInst *Alloca = A.Alloca; if (A.MayWriteBeforeCoroBegin) { @@ -2020,7 +2063,7 @@ static void insertSpills(const FrameDataInfo &FrameData, coro::Shape &Shape) { isa<BitCastInst>(Inst); }); if (HasAccessingPromiseBeforeCB) { - Builder.SetInsertPoint(Shape.getInsertPtAfterFramePtr()); + Builder.SetInsertPoint(&*Shape.getInsertPtAfterFramePtr()); auto *G = GetFramePointer(PA); auto *Value = Builder.CreateLoad(PA->getAllocatedType(), PA); Builder.CreateStore(Value, G); @@ -2802,21 +2845,16 @@ static void collectFrameAlloca(AllocaInst *AI, coro::Shape &Shape, Visitor.getMayWriteBeforeCoroBegin()); } -void coro::salvageDebugInfo( - SmallDenseMap<Argument *, AllocaInst *, 4> &ArgToAllocaMap, - DbgVariableIntrinsic *DVI, bool OptimizeFrame, bool UseEntryValue) { - Function *F = DVI->getFunction(); +static std::optional<std::pair<Value &, DIExpression &>> +salvageDebugInfoImpl(SmallDenseMap<Argument *, AllocaInst *, 4> &ArgToAllocaMap, + bool OptimizeFrame, bool UseEntryValue, Function *F, + Value *Storage, DIExpression *Expr, + bool SkipOutermostLoad) { IRBuilder<> Builder(F->getContext()); auto InsertPt = F->getEntryBlock().getFirstInsertionPt(); while (isa<IntrinsicInst>(InsertPt)) ++InsertPt; Builder.SetInsertPoint(&F->getEntryBlock(), InsertPt); - DIExpression *Expr = DVI->getExpression(); - // Follow the pointer arithmetic all the way to the incoming - // function argument and convert into a DIExpression. - bool SkipOutermostLoad = !isa<DbgValueInst>(DVI); - Value *Storage = DVI->getVariableLocationOp(0); - Value *OriginalStorage = Storage; while (auto *Inst = dyn_cast_or_null<Instruction>(Storage)) { if (auto *LdInst = dyn_cast<LoadInst>(Inst)) { @@ -2848,7 +2886,7 @@ void coro::salvageDebugInfo( SkipOutermostLoad = false; } if (!Storage) - return; + return std::nullopt; auto *StorageAsArg = dyn_cast<Argument>(Storage); const bool IsSwiftAsyncArg = @@ -2884,8 +2922,30 @@ void coro::salvageDebugInfo( Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore); } - DVI->replaceVariableLocationOp(OriginalStorage, Storage); - DVI->setExpression(Expr); + return {{*Storage, *Expr}}; +} + +void coro::salvageDebugInfo( + SmallDenseMap<Argument *, AllocaInst *, 4> &ArgToAllocaMap, + DbgVariableIntrinsic &DVI, bool OptimizeFrame, bool UseEntryValue) { + + Function *F = DVI.getFunction(); + // Follow the pointer arithmetic all the way to the incoming + // function argument and convert into a DIExpression. + bool SkipOutermostLoad = !isa<DbgValueInst>(DVI); + Value *OriginalStorage = DVI.getVariableLocationOp(0); + + auto SalvagedInfo = ::salvageDebugInfoImpl( + ArgToAllocaMap, OptimizeFrame, UseEntryValue, F, OriginalStorage, + DVI.getExpression(), SkipOutermostLoad); + if (!SalvagedInfo) + return; + + Value *Storage = &SalvagedInfo->first; + DIExpression *Expr = &SalvagedInfo->second; + + DVI.replaceVariableLocationOp(OriginalStorage, Storage); + DVI.setExpression(Expr); // We only hoist dbg.declare today since it doesn't make sense to hoist // dbg.value since it does not have the same function wide guarantees that // dbg.declare does. @@ -2896,7 +2956,44 @@ void coro::salvageDebugInfo( else if (isa<Argument>(Storage)) InsertPt = F->getEntryBlock().begin(); if (InsertPt) - DVI->moveBefore(*(*InsertPt)->getParent(), *InsertPt); + DVI.moveBefore(*(*InsertPt)->getParent(), *InsertPt); + } +} + +void coro::salvageDebugInfo( + SmallDenseMap<Argument *, AllocaInst *, 4> &ArgToAllocaMap, DPValue &DPV, + bool OptimizeFrame, bool UseEntryValue) { + + Function *F = DPV.getFunction(); + // Follow the pointer arithmetic all the way to the incoming + // function argument and convert into a DIExpression. + bool SkipOutermostLoad = DPV.getType() == DPValue::LocationType::Declare; + Value *OriginalStorage = DPV.getVariableLocationOp(0); + + auto SalvagedInfo = ::salvageDebugInfoImpl( + ArgToAllocaMap, OptimizeFrame, UseEntryValue, F, OriginalStorage, + DPV.getExpression(), SkipOutermostLoad); + if (!SalvagedInfo) + return; + + Value *Storage = &SalvagedInfo->first; + DIExpression *Expr = &SalvagedInfo->second; + + DPV.replaceVariableLocationOp(OriginalStorage, Storage); + DPV.setExpression(Expr); + // We only hoist dbg.declare today since it doesn't make sense to hoist + // dbg.value since it does not have the same function wide guarantees that + // dbg.declare does. + if (DPV.getType() == DPValue::LocationType::Declare) { + std::optional<BasicBlock::iterator> InsertPt; + if (auto *I = dyn_cast<Instruction>(Storage)) + InsertPt = I->getInsertionPointAfterDef(); + else if (isa<Argument>(Storage)) + InsertPt = F->getEntryBlock().begin(); + if (InsertPt) { + DPV.removeFromParent(); + (*InsertPt)->getParent()->insertDPValueBefore(&DPV, *InsertPt); + } } } @@ -3087,10 +3184,15 @@ void coro::buildCoroutineFrame( for (auto &Iter : FrameData.Spills) { auto *V = Iter.first; SmallVector<DbgValueInst *, 16> DVIs; - findDbgValues(DVIs, V); + SmallVector<DPValue *, 16> DPVs; + findDbgValues(DVIs, V, &DPVs); for (DbgValueInst *DVI : DVIs) if (Checker.isDefinitionAcrossSuspend(*V, DVI)) FrameData.Spills[V].push_back(DVI); + // Add the instructions which carry debug info that is in the frame. + for (DPValue *DPV : DPVs) + if (Checker.isDefinitionAcrossSuspend(*V, DPV->Marker->MarkedInstr)) + FrameData.Spills[V].push_back(DPV->Marker->MarkedInstr); } LLVM_DEBUG(dumpSpills("Spills", FrameData.Spills)); diff --git a/llvm/lib/Transforms/Coroutines/CoroInternal.h b/llvm/lib/Transforms/Coroutines/CoroInternal.h index 0856c4925cc5..fb16a4090689 100644 --- a/llvm/lib/Transforms/Coroutines/CoroInternal.h +++ b/llvm/lib/Transforms/Coroutines/CoroInternal.h @@ -32,7 +32,10 @@ void replaceCoroFree(CoroIdInst *CoroId, bool Elide); /// OptimizeFrame is false. void salvageDebugInfo( SmallDenseMap<Argument *, AllocaInst *, 4> &ArgToAllocaMap, - DbgVariableIntrinsic *DVI, bool OptimizeFrame, bool IsEntryPoint); + DbgVariableIntrinsic &DVI, bool OptimizeFrame, bool IsEntryPoint); +void salvageDebugInfo( + SmallDenseMap<Argument *, AllocaInst *, 4> &ArgToAllocaMap, DPValue &DPV, + bool OptimizeFrame, bool UseEntryValue); // Keeps data and helper functions for lowering coroutine intrinsics. struct LowererBase { @@ -240,10 +243,13 @@ struct LLVM_LIBRARY_VISIBILITY Shape { return nullptr; } - Instruction *getInsertPtAfterFramePtr() const { - if (auto *I = dyn_cast<Instruction>(FramePtr)) - return I->getNextNode(); - return &cast<Argument>(FramePtr)->getParent()->getEntryBlock().front(); + BasicBlock::iterator getInsertPtAfterFramePtr() const { + if (auto *I = dyn_cast<Instruction>(FramePtr)) { + BasicBlock::iterator It = std::next(I->getIterator()); + It.setHeadBit(true); // Copy pre-RemoveDIs behaviour. + return It; + } + return cast<Argument>(FramePtr)->getParent()->getEntryBlock().begin(); } /// Allocate memory according to the rules of the active lowering. diff --git a/llvm/lib/Transforms/Coroutines/CoroSplit.cpp b/llvm/lib/Transforms/Coroutines/CoroSplit.cpp index 244580f503d5..7758b52abc20 100644 --- a/llvm/lib/Transforms/Coroutines/CoroSplit.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroSplit.cpp @@ -725,13 +725,17 @@ static void replaceSwiftErrorOps(Function &F, coro::Shape &Shape, } /// Returns all DbgVariableIntrinsic in F. -static SmallVector<DbgVariableIntrinsic *, 8> +static std::pair<SmallVector<DbgVariableIntrinsic *, 8>, SmallVector<DPValue *>> collectDbgVariableIntrinsics(Function &F) { SmallVector<DbgVariableIntrinsic *, 8> Intrinsics; - for (auto &I : instructions(F)) + SmallVector<DPValue *> DPValues; + for (auto &I : instructions(F)) { + for (DPValue &DPV : I.getDbgValueRange()) + DPValues.push_back(&DPV); if (auto *DVI = dyn_cast<DbgVariableIntrinsic>(&I)) Intrinsics.push_back(DVI); - return Intrinsics; + } + return {Intrinsics, DPValues}; } void CoroCloner::replaceSwiftErrorOps() { @@ -739,15 +743,17 @@ void CoroCloner::replaceSwiftErrorOps() { } void CoroCloner::salvageDebugInfo() { - SmallVector<DbgVariableIntrinsic *, 8> Worklist = - collectDbgVariableIntrinsics(*NewF); + auto [Worklist, DPValues] = collectDbgVariableIntrinsics(*NewF); SmallDenseMap<Argument *, AllocaInst *, 4> ArgToAllocaMap; // Only 64-bit ABIs have a register we can refer to with the entry value. bool UseEntryValue = llvm::Triple(OrigF.getParent()->getTargetTriple()).isArch64Bit(); for (DbgVariableIntrinsic *DVI : Worklist) - coro::salvageDebugInfo(ArgToAllocaMap, DVI, Shape.OptimizeFrame, + coro::salvageDebugInfo(ArgToAllocaMap, *DVI, Shape.OptimizeFrame, + UseEntryValue); + for (DPValue *DPV : DPValues) + coro::salvageDebugInfo(ArgToAllocaMap, *DPV, Shape.OptimizeFrame, UseEntryValue); // Remove all salvaged dbg.declare intrinsics that became @@ -757,7 +763,7 @@ void CoroCloner::salvageDebugInfo() { return !isPotentiallyReachable(&NewF->getEntryBlock(), BB, nullptr, &DomTree); }; - for (DbgVariableIntrinsic *DVI : Worklist) { + auto RemoveOne = [&](auto *DVI) { if (IsUnreachableBlock(DVI->getParent())) DVI->eraseFromParent(); else if (isa_and_nonnull<AllocaInst>(DVI->getVariableLocationOp(0))) { @@ -770,7 +776,9 @@ void CoroCloner::salvageDebugInfo() { if (!Uses) DVI->eraseFromParent(); } - } + }; + for_each(Worklist, RemoveOne); + for_each(DPValues, RemoveOne); } void CoroCloner::replaceEntryBlock() { @@ -1243,7 +1251,7 @@ static void updateCoroFrame(coro::Shape &Shape, Function *ResumeFn, Function *DestroyFn, Function *CleanupFn) { assert(Shape.ABI == coro::ABI::Switch); - IRBuilder<> Builder(Shape.getInsertPtAfterFramePtr()); + IRBuilder<> Builder(&*Shape.getInsertPtAfterFramePtr()); auto *ResumeAddr = Builder.CreateStructGEP( Shape.FrameTy, Shape.FramePtr, coro::Shape::SwitchFieldIndex::Resume, @@ -2039,10 +2047,13 @@ splitCoroutine(Function &F, SmallVectorImpl<Function *> &Clones, // original function. The Cloner has already salvaged debug info in the new // coroutine funclets. SmallDenseMap<Argument *, AllocaInst *, 4> ArgToAllocaMap; - for (auto *DDI : collectDbgVariableIntrinsics(F)) - coro::salvageDebugInfo(ArgToAllocaMap, DDI, Shape.OptimizeFrame, + auto [DbgInsts, DPValues] = collectDbgVariableIntrinsics(F); + for (auto *DDI : DbgInsts) + coro::salvageDebugInfo(ArgToAllocaMap, *DDI, Shape.OptimizeFrame, + false /*UseEntryValue*/); + for (DPValue *DPV : DPValues) + coro::salvageDebugInfo(ArgToAllocaMap, *DPV, Shape.OptimizeFrame, false /*UseEntryValue*/); - return Shape; } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp index 104c73602223..1539fa9a3269 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -4227,12 +4227,9 @@ InstCombinerImpl::foldCommutativeIntrinsicOverSelects(IntrinsicInst &II) { assert(II.isCommutative()); Value *A, *B, *C; - bool LHSIsSelect = - match(II.getOperand(0), m_Select(m_Value(A), m_Value(B), m_Value(C))); - bool RHSIsSymmetricalSelect = match( - II.getOperand(1), m_Select(m_Specific(A), m_Specific(C), m_Specific(B))); - - if (LHSIsSelect && RHSIsSymmetricalSelect) { + if (match(II.getOperand(0), m_Select(m_Value(A), m_Value(B), m_Value(C))) && + match(II.getOperand(1), + m_Select(m_Specific(A), m_Specific(C), m_Specific(B)))) { replaceOperand(II, 0, B); replaceOperand(II, 1, C); return &II; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index 8d5866e98a8e..e5566578869d 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -1205,6 +1205,38 @@ Instruction *InstCombinerImpl::commonIDivTransforms(BinaryOperator &I) { } } + // (X * Y) / (X * Z) --> Y / Z (and commuted variants) + if (match(Op0, m_Mul(m_Value(X), m_Value(Y)))) { + auto OB0HasNSW = cast<OverflowingBinaryOperator>(Op0)->hasNoSignedWrap(); + auto OB0HasNUW = cast<OverflowingBinaryOperator>(Op0)->hasNoUnsignedWrap(); + + auto CreateDivOrNull = [&](Value *A, Value *B) -> Instruction * { + auto OB1HasNSW = cast<OverflowingBinaryOperator>(Op1)->hasNoSignedWrap(); + auto OB1HasNUW = + cast<OverflowingBinaryOperator>(Op1)->hasNoUnsignedWrap(); + const APInt *C1, *C2; + if (IsSigned && OB0HasNSW) { + if (OB1HasNSW && match(B, m_APInt(C1)) && !C1->isAllOnes()) + return BinaryOperator::CreateSDiv(A, B); + } + if (!IsSigned && OB0HasNUW) { + if (OB1HasNUW) + return BinaryOperator::CreateUDiv(A, B); + if (match(A, m_APInt(C1)) && match(B, m_APInt(C2)) && C2->ule(*C1)) + return BinaryOperator::CreateUDiv(A, B); + } + return nullptr; + }; + + if (match(Op1, m_c_Mul(m_Specific(X), m_Value(Z)))) { + if (auto *Val = CreateDivOrNull(Y, Z)) + return Val; + } + if (match(Op1, m_c_Mul(m_Specific(Y), m_Value(Z)))) { + if (auto *Val = CreateDivOrNull(X, Z)) + return Val; + } + } return nullptr; } @@ -1375,20 +1407,7 @@ Instruction *InstCombinerImpl::visitUDiv(BinaryOperator &I) { if (Instruction *NarrowDiv = narrowUDivURem(I, *this)) return NarrowDiv; - // If the udiv operands are non-overflowing multiplies with a common operand, - // then eliminate the common factor: - // (A * B) / (A * X) --> B / X (and commuted variants) - // TODO: The code would be reduced if we had m_c_NUWMul pattern matching. - // TODO: If -reassociation handled this generally, we could remove this. Value *A, *B; - if (match(Op0, m_NUWMul(m_Value(A), m_Value(B)))) { - if (match(Op1, m_NUWMul(m_Specific(A), m_Value(X))) || - match(Op1, m_NUWMul(m_Value(X), m_Specific(A)))) - return BinaryOperator::CreateUDiv(B, X); - if (match(Op1, m_NUWMul(m_Specific(B), m_Value(X))) || - match(Op1, m_NUWMul(m_Value(X), m_Specific(B)))) - return BinaryOperator::CreateUDiv(A, X); - } // Look through a right-shift to find the common factor: // ((Op1 *nuw A) >> B) / Op1 --> A >> B diff --git a/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp b/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp index 3e5d979f11cc..1fb9d7fff32f 100644 --- a/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp +++ b/llvm/lib/Transforms/Scalar/ConstantHoisting.cpp @@ -523,7 +523,8 @@ void ConstantHoistingPass::collectConstantCandidates(Function &Fn) { if (!DT->isReachableFromEntry(&BB)) continue; for (Instruction &Inst : BB) - collectConstantCandidates(ConstCandMap, &Inst); + if (!TTI->preferToKeepConstantsAttached(Inst, Fn)) + collectConstantCandidates(ConstCandMap, &Inst); } } diff --git a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp index fafbe17583f5..18266ba07898 100644 --- a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp +++ b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp @@ -1109,6 +1109,16 @@ void State::addInfoFor(BasicBlock &BB) { CmpI->getOperand(1))); } +#ifndef NDEBUG +static void dumpUnpackedICmp(raw_ostream &OS, ICmpInst::Predicate Pred, + Value *LHS, Value *RHS) { + OS << "icmp " << Pred << ' '; + LHS->printAsOperand(OS, /*PrintType=*/true); + OS << ", "; + RHS->printAsOperand(OS, /*PrintType=*/false); +} +#endif + namespace { /// Helper to keep track of a condition and if it should be treated as negated /// for reproducer construction. @@ -1241,10 +1251,9 @@ static void generateReproducer(CmpInst *Cond, Module *M, if (Entry.Pred == ICmpInst::BAD_ICMP_PREDICATE) continue; - LLVM_DEBUG( - dbgs() << " Materializing assumption icmp " << Entry.Pred << ' '; - Entry.LHS->printAsOperand(dbgs(), /*PrintType=*/true); dbgs() << ", "; - Entry.RHS->printAsOperand(dbgs(), /*PrintType=*/false); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << " Materializing assumption "; + dumpUnpackedICmp(dbgs(), Entry.Pred, Entry.LHS, Entry.RHS); + dbgs() << "\n"); CloneInstructions({Entry.LHS, Entry.RHS}, CmpInst::isSigned(Entry.Pred)); auto *Cmp = Builder.CreateICmp(Entry.Pred, Entry.LHS, Entry.RHS); @@ -1260,14 +1269,12 @@ static void generateReproducer(CmpInst *Cond, Module *M, assert(!verifyFunction(*F, &dbgs())); } -static std::optional<bool> checkCondition(CmpInst *Cmp, ConstraintInfo &Info, - unsigned NumIn, unsigned NumOut, +static std::optional<bool> checkCondition(CmpInst::Predicate Pred, Value *A, + Value *B, Instruction *CheckInst, + ConstraintInfo &Info, unsigned NumIn, + unsigned NumOut, Instruction *ContextInst) { - LLVM_DEBUG(dbgs() << "Checking " << *Cmp << "\n"); - - CmpInst::Predicate Pred = Cmp->getPredicate(); - Value *A = Cmp->getOperand(0); - Value *B = Cmp->getOperand(1); + LLVM_DEBUG(dbgs() << "Checking " << *CheckInst << "\n"); auto R = Info.getConstraintForSolving(Pred, A, B); if (R.empty() || !R.isValid(Info)){ @@ -1292,13 +1299,10 @@ static std::optional<bool> checkCondition(CmpInst *Cmp, ConstraintInfo &Info, return std::nullopt; LLVM_DEBUG({ - if (*ImpliedCondition) { - dbgs() << "Condition " << *Cmp; - } else { - auto InversePred = Cmp->getInversePredicate(); - dbgs() << "Condition " << CmpInst::getPredicateName(InversePred) << " " - << *A << ", " << *B; - } + dbgs() << "Condition "; + dumpUnpackedICmp( + dbgs(), *ImpliedCondition ? Pred : CmpInst::getInversePredicate(Pred), + A, B); dbgs() << " implied by dominating constraints\n"; CSToUse.dump(); }); @@ -1338,8 +1342,9 @@ static bool checkAndReplaceCondition( return true; }; - if (auto ImpliedCondition = - checkCondition(Cmp, Info, NumIn, NumOut, ContextInst)) + if (auto ImpliedCondition = checkCondition( + Cmp->getPredicate(), Cmp->getOperand(0), Cmp->getOperand(1), Cmp, + Info, NumIn, NumOut, ContextInst)) return ReplaceCmpWithConstant(Cmp, *ImpliedCondition); return false; } @@ -1380,9 +1385,10 @@ static bool checkAndSecondOpImpliedByFirst( bool Changed = false; // Check if the second condition can be simplified now. - if (auto ImpliedCondition = - checkCondition(cast<ICmpInst>(And->getOperand(1)), Info, CB.NumIn, - CB.NumOut, CB.getContextInst())) { + ICmpInst *Cmp = cast<ICmpInst>(And->getOperand(1)); + if (auto ImpliedCondition = checkCondition( + Cmp->getPredicate(), Cmp->getOperand(0), Cmp->getOperand(1), Cmp, + Info, CB.NumIn, CB.NumOut, CB.getContextInst())) { And->setOperand(1, ConstantInt::getBool(And->getType(), *ImpliedCondition)); Changed = true; } @@ -1408,9 +1414,8 @@ void ConstraintInfo::addFact(CmpInst::Predicate Pred, Value *A, Value *B, if (!R.isValid(*this) || R.isNe()) return; - LLVM_DEBUG(dbgs() << "Adding '" << Pred << " "; - A->printAsOperand(dbgs(), false); dbgs() << ", "; - B->printAsOperand(dbgs(), false); dbgs() << "'\n"); + LLVM_DEBUG(dbgs() << "Adding '"; dumpUnpackedICmp(dbgs(), Pred, A, B); + dbgs() << "'\n"); bool Added = false; auto &CSToUse = getCS(R.IsSigned); if (R.Coefficients.empty()) @@ -1616,10 +1621,8 @@ static bool eliminateConstraints(Function &F, DominatorTree &DT, LoopInfo &LI, } auto AddFact = [&](CmpInst::Predicate Pred, Value *A, Value *B) { - LLVM_DEBUG(dbgs() << "fact to add to the system: " - << CmpInst::getPredicateName(Pred) << " "; - A->printAsOperand(dbgs()); dbgs() << ", "; - B->printAsOperand(dbgs(), false); dbgs() << "\n"); + LLVM_DEBUG(dbgs() << "fact to add to the system: "; + dumpUnpackedICmp(dbgs(), Pred, A, B); dbgs() << "\n"); if (Info.getCS(CmpInst::isSigned(Pred)).size() > MaxRows) { LLVM_DEBUG( dbgs() diff --git a/llvm/lib/Transforms/Scalar/LICM.cpp b/llvm/lib/Transforms/Scalar/LICM.cpp index d0afe09ce41d..9117378568b7 100644 --- a/llvm/lib/Transforms/Scalar/LICM.cpp +++ b/llvm/lib/Transforms/Scalar/LICM.cpp @@ -193,7 +193,7 @@ static Instruction *cloneInstructionInExitBlock( static void eraseInstruction(Instruction &I, ICFLoopSafetyInfo &SafetyInfo, MemorySSAUpdater &MSSAU); -static void moveInstructionBefore(Instruction &I, Instruction &Dest, +static void moveInstructionBefore(Instruction &I, BasicBlock::iterator Dest, ICFLoopSafetyInfo &SafetyInfo, MemorySSAUpdater &MSSAU, ScalarEvolution *SE); @@ -1011,7 +1011,8 @@ bool llvm::hoistRegion(DomTreeNode *N, AAResults *AA, LoopInfo *LI, LLVM_DEBUG(dbgs() << "LICM rehoisting to " << HoistPoint->getParent()->getNameOrAsOperand() << ": " << *I << "\n"); - moveInstructionBefore(*I, *HoistPoint, *SafetyInfo, MSSAU, SE); + moveInstructionBefore(*I, HoistPoint->getIterator(), *SafetyInfo, MSSAU, + SE); HoistPoint = I; Changed = true; } @@ -1491,16 +1492,17 @@ static void eraseInstruction(Instruction &I, ICFLoopSafetyInfo &SafetyInfo, I.eraseFromParent(); } -static void moveInstructionBefore(Instruction &I, Instruction &Dest, +static void moveInstructionBefore(Instruction &I, BasicBlock::iterator Dest, ICFLoopSafetyInfo &SafetyInfo, MemorySSAUpdater &MSSAU, ScalarEvolution *SE) { SafetyInfo.removeInstruction(&I); - SafetyInfo.insertInstructionTo(&I, Dest.getParent()); - I.moveBefore(&Dest); + SafetyInfo.insertInstructionTo(&I, Dest->getParent()); + I.moveBefore(*Dest->getParent(), Dest); if (MemoryUseOrDef *OldMemAcc = cast_or_null<MemoryUseOrDef>( MSSAU.getMemorySSA()->getMemoryAccess(&I))) - MSSAU.moveToPlace(OldMemAcc, Dest.getParent(), MemorySSA::BeforeTerminator); + MSSAU.moveToPlace(OldMemAcc, Dest->getParent(), + MemorySSA::BeforeTerminator); if (SE) SE->forgetBlockAndLoopDispositions(&I); } @@ -1747,10 +1749,11 @@ static void hoist(Instruction &I, const DominatorTree *DT, const Loop *CurLoop, if (isa<PHINode>(I)) // Move the new node to the end of the phi list in the destination block. - moveInstructionBefore(I, *Dest->getFirstNonPHI(), *SafetyInfo, MSSAU, SE); + moveInstructionBefore(I, Dest->getFirstNonPHIIt(), *SafetyInfo, MSSAU, SE); else // Move the new node to the destination block, before its terminator. - moveInstructionBefore(I, *Dest->getTerminator(), *SafetyInfo, MSSAU, SE); + moveInstructionBefore(I, Dest->getTerminator()->getIterator(), *SafetyInfo, + MSSAU, SE); I.updateLocationAfterHoist(); diff --git a/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp b/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp index 13e06c79d0d7..9d5e6693c0e5 100644 --- a/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp +++ b/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp @@ -266,6 +266,11 @@ bool LoopVersioningLICM::legalLoopMemoryAccesses() { for (const auto &A : AS) { Value *Ptr = A.getValue(); // Alias tracker should have pointers of same data type. + // + // FIXME: check no longer effective since opaque pointers? + // If the intent is to check that the memory accesses use the + // same data type (such that LICM can promote them), then we + // can no longer see this from the pointer value types. TypeCheck = (TypeCheck && (SomePtr->getType() == Ptr->getType())); } // At least one alias tracker should have pointers of same data type. diff --git a/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp b/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp index 76280ed492b3..504f4430dc2c 100644 --- a/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp +++ b/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp @@ -708,12 +708,13 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { // as U1'' and U1' scopes will not be compatible wrt to the local restrict // Clone the llvm.experimental.noalias.decl again for the NewHeader. - Instruction *NewHeaderInsertionPoint = &(*NewHeader->getFirstNonPHI()); + BasicBlock::iterator NewHeaderInsertionPoint = + NewHeader->getFirstNonPHIIt(); for (NoAliasScopeDeclInst *NAD : NoAliasDeclInstructions) { LLVM_DEBUG(dbgs() << " Cloning llvm.experimental.noalias.scope.decl:" << *NAD << "\n"); Instruction *NewNAD = NAD->clone(); - NewNAD->insertBefore(NewHeaderInsertionPoint); + NewNAD->insertBefore(*NewHeader, NewHeaderInsertionPoint); } // Scopes must now be duplicated, once for OrigHeader and once for diff --git a/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp b/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp index 5c3776683d5d..47c6bcbaf26e 100644 --- a/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp +++ b/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp @@ -322,8 +322,9 @@ void MemoryOpRemark::visitVariable(const Value *V, // Try to get an llvm.dbg.declare, which has a DILocalVariable giving us the // real debug info name and size of the variable. SmallVector<DbgDeclareInst *, 1> DbgDeclares; - findDbgDeclares(DbgDeclares, const_cast<Value *>(V)); - for (const DbgVariableIntrinsic *DVI : DbgDeclares) { + SmallVector<DPValue *, 1> DPValues; + findDbgDeclares(DbgDeclares, const_cast<Value *>(V), &DPValues); + auto FindDI = [&](const auto *DVI) { if (DILocalVariable *DILV = DVI->getVariable()) { std::optional<uint64_t> DISize = getSizeInBytes(DILV->getSizeInBits()); VariableInfo Var{DILV->getName(), DISize}; @@ -332,7 +333,10 @@ void MemoryOpRemark::visitVariable(const Value *V, FoundDI = true; } } - } + }; + for_each(DbgDeclares, FindDI); + for_each(DPValues, FindDI); + if (FoundDI) { assert(!Result.empty()); return; diff --git a/llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll b/llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll index 1565a138b93d..d58f3348e41f 100644 --- a/llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll +++ b/llvm/test/Analysis/CostModel/ARM/intrinsic-cost-kinds.ll @@ -42,6 +42,10 @@ declare float @llvm.vector.reduce.fmax.v16f32(<16 x float>) declare void @llvm.memcpy.p0.p0.i32(ptr, ptr, i32, i1) +declare i32 @llvm.ssa.copy.i32(i32) +declare float @llvm.ssa.copy.f32(float) +declare ptr @llvm.ssa.copy.p0(ptr) + define void @smax(i32 %a, i32 %b, <16 x i32> %va, <16 x i32> %vb) { ; THRU-LABEL: 'smax' ; THRU-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %s = call i32 @llvm.smax.i32(i32 %a, i32 %b) @@ -333,3 +337,35 @@ define void @memcpy(ptr %a, ptr %b, i32 %c) { call void @llvm.memcpy.p0.p0.i32(ptr align 1 %a, ptr align 1 %b, i32 32, i1 false) ret void } + +define void @ssa_copy() { + ; CHECK: %{{.*}} = llvm.intr.ssa.copy %{{.*}} : f32 +; THRU-LABEL: 'ssa_copy' +; THRU-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i = call i32 @llvm.ssa.copy.i32(i32 undef) +; THRU-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f = call float @llvm.ssa.copy.f32(float undef) +; THRU-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p = call ptr @llvm.ssa.copy.p0(ptr undef) +; THRU-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; +; LATE-LABEL: 'ssa_copy' +; LATE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i = call i32 @llvm.ssa.copy.i32(i32 undef) +; LATE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f = call float @llvm.ssa.copy.f32(float undef) +; LATE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p = call ptr @llvm.ssa.copy.p0(ptr undef) +; LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; +; SIZE-LABEL: 'ssa_copy' +; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i = call i32 @llvm.ssa.copy.i32(i32 undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f = call float @llvm.ssa.copy.f32(float undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p = call ptr @llvm.ssa.copy.p0(ptr undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; +; SIZE_LATE-LABEL: 'ssa_copy' +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %i = call i32 @llvm.ssa.copy.i32(i32 undef) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %f = call float @llvm.ssa.copy.f32(float undef) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %p = call ptr @llvm.ssa.copy.p0(ptr undef) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void +; + %i = call i32 @llvm.ssa.copy.i32(i32 undef) + %f = call float @llvm.ssa.copy.f32(float undef) + %p = call ptr @llvm.ssa.copy.p0(ptr undef) + ret void +} diff --git a/llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir b/llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir new file mode 100644 index 000000000000..1303776230f1 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sink-and-fold-clear-kill-flags.mir @@ -0,0 +1,193 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc --run-pass=machine-sink %s -o - | FileCheck %s + +# Test that the "killed" flags are cleared in the ORRWrs and SUBSWrr instructions +# in 'f and @g, respectively + +--- | + source_filename = "crash.ll" + target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" + target triple = "aarch64-linux" + + define i32 @f(ptr %image, i32 %i) { + entry: + %add = add i32 %i, 1 + %idx = zext i32 %add to i64 + br label %A + + A: ; preds = %B, %A, %entry + %sunkaddr = getelementptr i8, ptr %image, i64 %idx + %0 = load i8, ptr %sunkaddr, align 1 + %cmp153 = icmp eq i8 %0, 0 + br i1 %cmp153, label %B, label %A + + B: ; preds = %A + store i32 0, ptr %image, align 1 + br label %A + } + + define i32 @g(i32 %i, i32 %j) { + entry: + %add = add i32 %i, %j + %neg = sub i32 0, %i + br label %A + + A: ; preds = %B, %A, %entry + %0 = call i8 @h(i32 %add) + %c = icmp eq i8 %0, 0 + br i1 %c, label %B, label %A + + B: ; preds = %A + %1 = call i8 @h(i32 %neg) + br label %A + } + + declare i8 @h(i32) + +... +--- +name: f +alignment: 4 +tracksRegLiveness: true +registers: + - { id: 0, class: gpr64, preferred-register: '' } + - { id: 1, class: gpr64common, preferred-register: '' } + - { id: 2, class: gpr32common, preferred-register: '' } + - { id: 3, class: gpr32common, preferred-register: '' } + - { id: 4, class: gpr32, preferred-register: '' } + - { id: 5, class: gpr32, preferred-register: '' } + - { id: 6, class: gpr32, preferred-register: '' } +liveins: + - { reg: '$x0', virtual-reg: '%1' } + - { reg: '$w1', virtual-reg: '%2' } +body: | + ; CHECK-LABEL: name: f + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $x0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x0 + ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32common = ADDWri [[COPY]], 1, 0 + ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[ADDWri]], 0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.A: + ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[LDRBBroW:%[0-9]+]]:gpr32 = LDRBBroW [[COPY1]], [[ADDWri]], 0, 0 :: (load (s8) from %ir.sunkaddr) + ; CHECK-NEXT: CBNZW killed [[LDRBBroW]], %bb.1 + ; CHECK-NEXT: B %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.B: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr + ; CHECK-NEXT: STRWui [[COPY2]], [[COPY1]], 0 :: (store (s32) into %ir.image, align 1) + ; CHECK-NEXT: B %bb.1 + bb.0.entry: + successors: %bb.1(0x80000000) + liveins: $x0, $w1 + + %2:gpr32common = COPY $w1 + %1:gpr64common = COPY $x0 + %3:gpr32common = ADDWri %2, 1, 0 + %4:gpr32 = ORRWrs $wzr, killed %3, 0 + %0:gpr64 = SUBREG_TO_REG 0, killed %4, %subreg.sub_32 + + bb.1.A: + successors: %bb.2(0x30000000), %bb.1(0x50000000) + + %5:gpr32 = LDRBBroX %1, %0, 0, 0 :: (load (s8) from %ir.sunkaddr) + CBNZW killed %5, %bb.1 + B %bb.2 + + bb.2.B: + successors: %bb.1(0x80000000) + + %6:gpr32 = COPY $wzr + STRWui %6, %1, 0 :: (store (s32) into %ir.image, align 1) + B %bb.1 +... +--- +name: g +alignment: 4 +registers: + - { id: 0, class: gpr32all, preferred-register: '' } + - { id: 1, class: gpr32all, preferred-register: '' } + - { id: 2, class: gpr32, preferred-register: '' } + - { id: 3, class: gpr32, preferred-register: '' } + - { id: 4, class: gpr32, preferred-register: '' } + - { id: 5, class: gpr32, preferred-register: '' } + - { id: 6, class: gpr32, preferred-register: '' } + - { id: 7, class: gpr32, preferred-register: '' } + - { id: 8, class: gpr32common, preferred-register: '' } + - { id: 9, class: gpr32all, preferred-register: '' } +liveins: + - { reg: '$w0', virtual-reg: '%2' } + - { reg: '$w1', virtual-reg: '%3' } +body: | + ; CHECK-LABEL: name: g + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr + ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY1]], implicit-def dead $nzcv + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY [[SUBSWrr]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.A: + ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: $w0 = ADDWrr [[COPY1]], [[COPY]] + ; CHECK-NEXT: BL @h, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: $wzr = ANDSWri [[COPY4]], 7, implicit-def $nzcv + ; CHECK-NEXT: Bcc 1, %bb.1, implicit $nzcv + ; CHECK-NEXT: B %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.B: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: $w0 = COPY [[COPY3]] + ; CHECK-NEXT: BL @h, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: B %bb.1 + bb.0.entry: + successors: %bb.1(0x80000000) + liveins: $w0, $w1 + + %3:gpr32 = COPY $w1 + %2:gpr32 = COPY $w0 + %4:gpr32 = ADDWrr %2, killed %3 + %0:gpr32all = COPY %4 + %5:gpr32 = COPY $wzr + %6:gpr32 = SUBSWrr %5, killed %2, implicit-def dead $nzcv + %1:gpr32all = COPY %6 + + bb.1.A: + successors: %bb.2(0x30000000), %bb.1(0x50000000) + + ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp + $w0 = COPY %0 + BL @h, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp + %7:gpr32 = COPY $w0 + $wzr = ANDSWri %7, 7, implicit-def $nzcv + Bcc 1, %bb.1, implicit $nzcv + B %bb.2 + + bb.2.B: + successors: %bb.1(0x80000000) + + ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp + $w0 = COPY %1 + BL @h, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp + B %bb.1 + +... diff --git a/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-fp-reduce.ll b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-fp-reduce.ll new file mode 100644 index 000000000000..7957366fce3b --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-fp-reduce.ll @@ -0,0 +1,189 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2p1 < %s | FileCheck %s +; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sme2p1 < %s | FileCheck %s + +; +; FMAXNMQV +; + +define <8 x half> @fmaxnmqv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) { +; CHECK-LABEL: fmaxnmqv_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxnmqv v0.8h, p0, z0.h +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.aarch64.sve.fmaxnmqv.v8f16.nxv8f16(<vscale x 8 x i1> %pg, + <vscale x 8 x half> %a) + ret <8 x half> %res +} + +define <4 x float> @fmaxnmqv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) { +; CHECK-LABEL: fmaxnmqv_f32: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxnmqv v0.4s, p0, z0.s +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.aarch64.sve.fmaxnmqv.v4f32.nxv4f32(<vscale x 4 x i1> %pg, + <vscale x 4 x float> %a) + ret <4 x float> %res +} + +define <2 x double> @fmaxnmqv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) { +; CHECK-LABEL: fmaxnmqv_f64: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxnmqv v0.2d, p0, z0.d +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.aarch64.sve.fmaxnmqv.v2f64.nxv2f64(<vscale x 2 x i1> %pg, + <vscale x 2 x double> %a) + ret <2 x double> %res +} + +; +; FMINNMQV +; + +define <8 x half> @fminnmqv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) { +; CHECK-LABEL: fminnmqv_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: fminnmqv v0.8h, p0, z0.h +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.aarch64.sve.fminnmqv.v8f16.nxv8f16(<vscale x 8 x i1> %pg, + <vscale x 8 x half> %a) + ret <8 x half> %res +} + +define <4 x float> @fminnmqv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) { +; CHECK-LABEL: fminnmqv_f32: +; CHECK: // %bb.0: +; CHECK-NEXT: fminnmqv v0.4s, p0, z0.s +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.aarch64.sve.fminnmqv.v4f32.nxv4f32(<vscale x 4 x i1> %pg, + <vscale x 4 x float> %a) + ret <4 x float> %res +} + +define <2 x double> @fminnmqv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) { +; CHECK-LABEL: fminnmqv_f64: +; CHECK: // %bb.0: +; CHECK-NEXT: fminnmqv v0.2d, p0, z0.d +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.aarch64.sve.fminnmqv.v2f64.nxv2f64(<vscale x 2 x i1> %pg, + <vscale x 2 x double> %a) + ret <2 x double> %res +} + +; +; FADDQV +; + +define <8 x half> @faddqv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) { +; CHECK-LABEL: faddqv_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: faddqv v0.8h, p0, z0.h +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.aarch64.sve.addqv.v8f16.nxv8f16(<vscale x 8 x i1> %pg, + <vscale x 8 x half> %a) + ret <8 x half> %res +} + +define <4 x float> @faddqv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) { +; CHECK-LABEL: faddqv_f32: +; CHECK: // %bb.0: +; CHECK-NEXT: faddqv v0.4s, p0, z0.s +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.aarch64.sve.addqv.v4f32.nxv4f32(<vscale x 4 x i1> %pg, + <vscale x 4 x float> %a) + ret <4 x float> %res +} + +define <2 x double> @faddqv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) { +; CHECK-LABEL: faddqv_f64: +; CHECK: // %bb.0: +; CHECK-NEXT: faddqv v0.2d, p0, z0.d +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.aarch64.sve.addqv.v2f64.nxv2f64(<vscale x 2 x i1> %pg, + <vscale x 2 x double> %a) + ret <2 x double> %res +} + +; +; FMINQV +; + +define <8 x half> @fminqv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) { +; CHECK-LABEL: fminqv_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: fminqv v0.8h, p0, z0.h +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.aarch64.sve.fminqv.v8f16.nxv8f16(<vscale x 8 x i1> %pg, + <vscale x 8 x half> %a) + ret <8 x half> %res +} + +define <4 x float> @fminqv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) { +; CHECK-LABEL: fminqv_f32: +; CHECK: // %bb.0: +; CHECK-NEXT: fminqv v0.4s, p0, z0.s +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.aarch64.sve.fminqv.v4f32.nxv4f32(<vscale x 4 x i1> %pg, + <vscale x 4 x float> %a) + ret <4 x float> %res +} + +define <2 x double> @fminqv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) { +; CHECK-LABEL: fminqv_f64: +; CHECK: // %bb.0: +; CHECK-NEXT: fminqv v0.2d, p0, z0.d +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.aarch64.sve.fminqv.v2f64.nxv2f64(<vscale x 2 x i1> %pg, + <vscale x 2 x double> %a) + ret <2 x double> %res +} + +; +; FMAXQV +; + +define <8 x half> @fmaxqv_f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) { +; CHECK-LABEL: fmaxqv_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxqv v0.8h, p0, z0.h +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.aarch64.sve.fmaxqv.v8f16.nxv8f16(<vscale x 8 x i1> %pg, + <vscale x 8 x half> %a) + ret <8 x half> %res +} + +define <4 x float> @fmaxqv_f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) { +; CHECK-LABEL: fmaxqv_f32: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxqv v0.4s, p0, z0.s +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.aarch64.sve.fmaxqv.v4f32.nxv4f32(<vscale x 4 x i1> %pg, + <vscale x 4 x float> %a) + ret <4 x float> %res +} + +define <2 x double> @fmaxqv_f64(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) { +; CHECK-LABEL: fmaxqv_f64: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxqv v0.2d, p0, z0.d +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.aarch64.sve.fmaxqv.v2f64.nxv2f64(<vscale x 2 x i1> %pg, + <vscale x 2 x double> %a) + ret <2 x double> %res +} + +declare <8 x half> @llvm.aarch64.sve.fmaxnmqv.v8f16.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) +declare <4 x float> @llvm.aarch64.sve.fmaxnmqv.v4f32.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) +declare <2 x double> @llvm.aarch64.sve.fmaxnmqv.v2f64.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) +declare <8 x half> @llvm.aarch64.sve.fminnmqv.v8f16.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) +declare <4 x float> @llvm.aarch64.sve.fminnmqv.v4f32.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) +declare <2 x double> @llvm.aarch64.sve.fminnmqv.v2f64.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) +declare <8 x half> @llvm.aarch64.sve.addqv.v8f16.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) +declare <4 x float> @llvm.aarch64.sve.addqv.v4f32.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) +declare <2 x double> @llvm.aarch64.sve.addqv.v2f64.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) +declare <8 x half> @llvm.aarch64.sve.fminqv.v8f16.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) +declare <4 x float> @llvm.aarch64.sve.fminqv.v4f32.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) +declare <2 x double> @llvm.aarch64.sve.fminqv.v2f64.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) +declare <8 x half> @llvm.aarch64.sve.fmaxqv.v8f16.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>) +declare <4 x float> @llvm.aarch64.sve.fmaxqv.v4f32.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>) +declare <2 x double> @llvm.aarch64.sve.fmaxqv.v2f64.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>) diff --git a/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-int-reduce.ll b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-int-reduce.ll new file mode 100644 index 000000000000..a730ba9c9320 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-int-reduce.ll @@ -0,0 +1,356 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2p1 < %s | FileCheck %s +; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sme2p1 < %s | FileCheck %s + +; +; ORQV +; + +define <16 x i8> @orqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { +; CHECK-LABEL: orqv_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: orqv v0.16b, p0, z0.b +; CHECK-NEXT: ret + %res = call <16 x i8> @llvm.aarch64.sve.orqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a); + ret <16 x i8> %res +} + +define <8 x i16> @orqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { +; CHECK-LABEL: orqv_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: orqv v0.8h, p0, z0.h +; CHECK-NEXT: ret + %res = call <8 x i16> @llvm.aarch64.sve.orqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a); + ret <8 x i16> %res +} + +define <4 x i32> @orqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { +; CHECK-LABEL: orqv_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: orqv v0.4s, p0, z0.s +; CHECK-NEXT: ret + %res = call <4 x i32> @llvm.aarch64.sve.orqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a); + ret <4 x i32> %res +} + +define <2 x i64> @orqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { +; CHECK-LABEL: orqv_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: orqv v0.2d, p0, z0.d +; CHECK-NEXT: ret + %res = call <2 x i64> @llvm.aarch64.sve.orqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a); + ret <2 x i64> %res +} + +; +; EORQV +; + +define <16 x i8> @eorqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { +; CHECK-LABEL: eorqv_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: eorqv v0.16b, p0, z0.b +; CHECK-NEXT: ret + %res = call <16 x i8> @llvm.aarch64.sve.eorqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a); + ret <16 x i8> %res +} + +define <8 x i16> @eorqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { +; CHECK-LABEL: eorqv_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: eorqv v0.8h, p0, z0.h +; CHECK-NEXT: ret + %res = call <8 x i16> @llvm.aarch64.sve.eorqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a); + ret <8 x i16> %res +} + +define <4 x i32> @eorqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { +; CHECK-LABEL: eorqv_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: eorqv v0.4s, p0, z0.s +; CHECK-NEXT: ret + %res = call <4 x i32> @llvm.aarch64.sve.eorqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a); + ret <4 x i32> %res +} + +define <2 x i64> @eorqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { +; CHECK-LABEL: eorqv_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: eorqv v0.2d, p0, z0.d +; CHECK-NEXT: ret + %res = call <2 x i64> @llvm.aarch64.sve.eorqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a); + ret <2 x i64> %res +} + +; +; ANDQV +; + +define <16 x i8> @andqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { +; CHECK-LABEL: andqv_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: andqv v0.16b, p0, z0.b +; CHECK-NEXT: ret + %res = call <16 x i8> @llvm.aarch64.sve.andqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a); + ret <16 x i8> %res +} + +define <8 x i16> @andqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { +; CHECK-LABEL: andqv_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: andqv v0.8h, p0, z0.h +; CHECK-NEXT: ret + %res = call <8 x i16> @llvm.aarch64.sve.andqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a); + ret <8 x i16> %res +} + +define <4 x i32> @andqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { +; CHECK-LABEL: andqv_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: andqv v0.4s, p0, z0.s +; CHECK-NEXT: ret + %res = call <4 x i32> @llvm.aarch64.sve.andqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a); + ret <4 x i32> %res +} + +define <2 x i64> @andqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { +; CHECK-LABEL: andqv_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: andqv v0.2d, p0, z0.d +; CHECK-NEXT: ret + %res = call <2 x i64> @llvm.aarch64.sve.andqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a); + ret <2 x i64> %res +} + +; +; ADDQV +; + +define <16 x i8> @addqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { +; CHECK-LABEL: addqv_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: addqv v0.16b, p0, z0.b +; CHECK-NEXT: ret + %res = call <16 x i8> @llvm.aarch64.sve.addqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a); + ret <16 x i8> %res +} + +define <8 x i16> @addqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { +; CHECK-LABEL: addqv_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: addqv v0.8h, p0, z0.h +; CHECK-NEXT: ret + %res = call <8 x i16> @llvm.aarch64.sve.addqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a); + ret <8 x i16> %res +} + +define <4 x i32> @addqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { +; CHECK-LABEL: addqv_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: addqv v0.4s, p0, z0.s +; CHECK-NEXT: ret + %res = call <4 x i32> @llvm.aarch64.sve.addqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a); + ret <4 x i32> %res +} + +define <2 x i64> @addqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { +; CHECK-LABEL: addqv_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: addqv v0.2d, p0, z0.d +; CHECK-NEXT: ret + %res = call <2 x i64> @llvm.aarch64.sve.addqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a); + ret <2 x i64> %res +} + +; +; SMAXQV +; + +define <16 x i8> @smaxqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { +; CHECK-LABEL: smaxqv_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: smaxqv v0.16b, p0, z0.b +; CHECK-NEXT: ret + %res = call <16 x i8> @llvm.aarch64.sve.smaxqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a); + ret <16 x i8> %res +} + +define <8 x i16> @smaxqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { +; CHECK-LABEL: smaxqv_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: smaxqv v0.8h, p0, z0.h +; CHECK-NEXT: ret + %res = call <8 x i16> @llvm.aarch64.sve.smaxqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a); + ret <8 x i16> %res +} + +define <4 x i32> @smaxqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { +; CHECK-LABEL: smaxqv_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: smaxqv v0.4s, p0, z0.s +; CHECK-NEXT: ret + %res = call <4 x i32> @llvm.aarch64.sve.smaxqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a); + ret <4 x i32> %res +} + +define <2 x i64> @smaxqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { +; CHECK-LABEL: smaxqv_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: smaxqv v0.2d, p0, z0.d +; CHECK-NEXT: ret + %res = call <2 x i64> @llvm.aarch64.sve.smaxqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a); + ret <2 x i64> %res +} + +; +; UMAXQV +; + +define <16 x i8> @umaxqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { +; CHECK-LABEL: umaxqv_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: umaxqv v0.16b, p0, z0.b +; CHECK-NEXT: ret + %res = call <16 x i8> @llvm.aarch64.sve.umaxqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a); + ret <16 x i8> %res +} + +define <8 x i16> @umaxqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { +; CHECK-LABEL: umaxqv_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: umaxqv v0.8h, p0, z0.h +; CHECK-NEXT: ret + %res = call <8 x i16> @llvm.aarch64.sve.umaxqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a); + ret <8 x i16> %res +} + +define <4 x i32> @umaxqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { +; CHECK-LABEL: umaxqv_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: umaxqv v0.4s, p0, z0.s +; CHECK-NEXT: ret + %res = call <4 x i32> @llvm.aarch64.sve.umaxqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a); + ret <4 x i32> %res +} + +define <2 x i64> @umaxqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { +; CHECK-LABEL: umaxqv_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: umaxqv v0.2d, p0, z0.d +; CHECK-NEXT: ret + %res = call <2 x i64> @llvm.aarch64.sve.umaxqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a); + ret <2 x i64> %res +} + +; +; SMINQV +; + +define <16 x i8> @sminqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { +; CHECK-LABEL: sminqv_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: sminqv v0.16b, p0, z0.b +; CHECK-NEXT: ret + %res = call <16 x i8> @llvm.aarch64.sve.sminqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a); + ret <16 x i8> %res +} + +define <8 x i16> @sminqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { +; CHECK-LABEL: sminqv_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: sminqv v0.8h, p0, z0.h +; CHECK-NEXT: ret + %res = call <8 x i16> @llvm.aarch64.sve.sminqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a); + ret <8 x i16> %res +} + +define <4 x i32> @sminqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { +; CHECK-LABEL: sminqv_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: sminqv v0.4s, p0, z0.s +; CHECK-NEXT: ret + %res = call <4 x i32> @llvm.aarch64.sve.sminqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a); + ret <4 x i32> %res +} + +define <2 x i64> @sminqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { +; CHECK-LABEL: sminqv_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: sminqv v0.2d, p0, z0.d +; CHECK-NEXT: ret + %res = call <2 x i64> @llvm.aarch64.sve.sminqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a); + ret <2 x i64> %res +} + +; +; UMINQV +; + +define <16 x i8> @uminqv_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { +; CHECK-LABEL: uminqv_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: uminqv v0.16b, p0, z0.b +; CHECK-NEXT: ret + %res = call <16 x i8> @llvm.aarch64.sve.uminqv.v16i8.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a); + ret <16 x i8> %res +} + +define <8 x i16> @uminqv_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { +; CHECK-LABEL: uminqv_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: uminqv v0.8h, p0, z0.h +; CHECK-NEXT: ret + %res = call <8 x i16> @llvm.aarch64.sve.uminqv.v8i16.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a); + ret <8 x i16> %res +} + +define <4 x i32> @uminqv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { +; CHECK-LABEL: uminqv_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: uminqv v0.4s, p0, z0.s +; CHECK-NEXT: ret + %res = call <4 x i32> @llvm.aarch64.sve.uminqv.v4i32.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a); + ret <4 x i32> %res +} + +define <2 x i64> @uminqv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { +; CHECK-LABEL: uminqv_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: uminqv v0.2d, p0, z0.d +; CHECK-NEXT: ret + %res = call <2 x i64> @llvm.aarch64.sve.uminqv.v2i64.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a); + ret <2 x i64> %res +} + +declare <16 x i8> @llvm.aarch64.sve.orqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) +declare <8 x i16> @llvm.aarch64.sve.orqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) +declare <4 x i32> @llvm.aarch64.sve.orqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) +declare <2 x i64> @llvm.aarch64.sve.orqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) +declare <16 x i8> @llvm.aarch64.sve.eorqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) +declare <8 x i16> @llvm.aarch64.sve.eorqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) +declare <4 x i32> @llvm.aarch64.sve.eorqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) +declare <2 x i64> @llvm.aarch64.sve.eorqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) +declare <16 x i8> @llvm.aarch64.sve.andqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) +declare <8 x i16> @llvm.aarch64.sve.andqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) +declare <4 x i32> @llvm.aarch64.sve.andqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) +declare <2 x i64> @llvm.aarch64.sve.andqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) +declare <16 x i8> @llvm.aarch64.sve.addqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) +declare <8 x i16> @llvm.aarch64.sve.addqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) +declare <4 x i32> @llvm.aarch64.sve.addqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) +declare <2 x i64> @llvm.aarch64.sve.addqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) +declare <16 x i8> @llvm.aarch64.sve.smaxqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) +declare <8 x i16> @llvm.aarch64.sve.smaxqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) +declare <4 x i32> @llvm.aarch64.sve.smaxqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) +declare <2 x i64> @llvm.aarch64.sve.smaxqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) +declare <16 x i8> @llvm.aarch64.sve.umaxqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) +declare <8 x i16> @llvm.aarch64.sve.umaxqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) +declare <4 x i32> @llvm.aarch64.sve.umaxqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) +declare <2 x i64> @llvm.aarch64.sve.umaxqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) +declare <16 x i8> @llvm.aarch64.sve.sminqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) +declare <8 x i16> @llvm.aarch64.sve.sminqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) +declare <4 x i32> @llvm.aarch64.sve.sminqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) +declare <2 x i64> @llvm.aarch64.sve.sminqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) +declare <16 x i8> @llvm.aarch64.sve.uminqv.v16i8.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>) +declare <8 x i16> @llvm.aarch64.sve.uminqv.v8i16.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>) +declare <4 x i32> @llvm.aarch64.sve.uminqv.v4i32.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>) +declare <2 x i64> @llvm.aarch64.sve.uminqv.v2i64.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll index ea46f4d2d419..62e5bce23664 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s define float @test_fmed3_f32_known_nnan_ieee_true(float %a) #0 { ; GFX10-LABEL: test_fmed3_f32_known_nnan_ieee_true: @@ -7,6 +8,12 @@ define float @test_fmed3_f32_known_nnan_ieee_true(float %a) #0 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_fmed3_f32_known_nnan_ieee_true: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul float %a, 2.0 %fmed = call nnan float @llvm.amdgcn.fmed3.f32(float %fmul, float 0.0, float 1.0) ret float %fmed @@ -18,6 +25,12 @@ define half @test_fmed3_f16_known_nnan_ieee_false(half %a) #1 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_fmed3_f16_known_nnan_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul half %a, 2.0 %fmed = call nnan half @llvm.amdgcn.fmed3.f16(half %fmul, half 0.0, half 1.0) ret half %fmed @@ -31,6 +44,14 @@ define float @test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true(float %a) #2 { ; GFX10-NEXT: v_max_f32_e32 v0, v0, v0 ; GFX10-NEXT: v_min_f32_e64 v0, 0x41200000, v0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_min_num_f32_e64 v0, 0x41200000, v0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmin = call float @llvm.minnum.f32(float %a, float 10.0) %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmin, float 0.0, float 1.0) ret float %fmed @@ -43,6 +64,12 @@ define float @test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp_true: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul float %a, 2.0 %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmul, float 1.0, float 0.0) ret float %fmed @@ -56,6 +83,12 @@ define float @test_fmed3_global_nnan(float %a) #3 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_fmed3_global_nnan: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul float %a, 2.0 %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmul, float 0.0, float 1.0) ret float %fmed @@ -73,6 +106,12 @@ define float @test_fmed3_f32_maybe_NaN_ieee_false(float %a) #1 { ; GFX10-NEXT: v_mul_f32_e32 v0, 2.0, v0 ; GFX10-NEXT: v_med3_f32 v0, v0, 1.0, 0 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_fmed3_f32_maybe_NaN_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul float %a, 2.0 %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmul, float 1.0, float 0.0) ret float %fmed @@ -87,6 +126,14 @@ define float @test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false(float %a) #4 { ; GFX10-NEXT: v_min_f32_e32 v0, 0x41200000, v0 ; GFX10-NEXT: v_med3_f32 v0, v0, 0, 1.0 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_min_num_f32_e64 v0, 0x41200000, v0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmin = call float @llvm.minnum.f32(float %a, float 10.0) %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmin, float 0.0, float 1.0) ret float %fmed @@ -99,6 +146,12 @@ define float @test_fmed3_maybe_SNaN_input_ieee_true_dx10clamp_true(float %a) #2 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_fmed3_maybe_SNaN_input_ieee_true_dx10clamp_true: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul float %a, 2.0 %fmed = call float @llvm.amdgcn.fmed3.f32(float %fmul, float 0.0, float 1.0) ret float %fmed diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll index 4f75d205cda3..bba3687dbbc2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s define float @test_min_max_ValK0_K1_f32(float %a) #0 { ; GFX10-LABEL: test_min_max_ValK0_K1_f32: @@ -7,6 +8,12 @@ define float @test_min_max_ValK0_K1_f32(float %a) #0 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_ValK0_K1_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul float %a, 2.0 %maxnum = call nnan float @llvm.maxnum.f32(float %fmul, float 0.0) %fmed = call nnan float @llvm.minnum.f32(float %maxnum, float 1.0) @@ -19,6 +26,12 @@ define double @test_min_max_K0Val_K1_f64(double %a) #1 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], 2.0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_K0Val_K1_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f64_e64 v[0:1], v[0:1], 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul double %a, 2.0 %maxnum = call nnan double @llvm.maxnum.f64(double 0.0, double %fmul) %fmed = call nnan double @llvm.minnum.f64(double %maxnum, double 1.0) @@ -32,6 +45,12 @@ define half @test_min_K1max_ValK0_f16(half %a) #2 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_K1max_ValK0_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul half %a, 2.0 %maxnum = call half @llvm.maxnum.f16(half %fmul, half 0.0) %fmed = call half @llvm.minnum.f16(half 1.0, half %maxnum) @@ -44,6 +63,12 @@ define <2 x half> @test_min_K1max_K0Val_f16(<2 x half> %a) #1 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_pk_mul_f16 v0, v0, 2.0 op_sel_hi:[1,0] clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_K1max_K0Val_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_pk_mul_f16 v0, v0, 2.0 op_sel_hi:[1,0] clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul <2 x half> %a, <half 2.0, half 2.0> %maxnum = call nnan <2 x half> @llvm.maxnum.v2f16(<2 x half> <half 0.0, half 0.0>, <2 x half> %fmul) %fmed = call nnan <2 x half> @llvm.minnum.v2f16(<2 x half> <half 1.0, half 1.0>, <2 x half> %maxnum) @@ -56,6 +81,12 @@ define <2 x half> @test_min_max_splat_padded_with_undef(<2 x half> %a) #2 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_pk_mul_f16 v0, v0, 2.0 op_sel_hi:[1,0] clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_splat_padded_with_undef: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_pk_mul_f16 v0, v0, 2.0 op_sel_hi:[1,0] clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul <2 x half> %a, <half 2.0, half 2.0> %maxnum = call <2 x half> @llvm.maxnum.v2f16(<2 x half> <half 0.0, half undef>, <2 x half> %fmul) %fmed = call <2 x half> @llvm.minnum.v2f16(<2 x half> <half 1.0, half undef>, <2 x half> %maxnum) @@ -70,6 +101,12 @@ define float @test_max_min_ValK1_K0_f32(float %a) #0 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_min_ValK1_K0_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul float %a, 2.0 %minnum = call nnan float @llvm.minnum.f32(float %fmul, float 1.0) %fmed = call nnan float @llvm.maxnum.f32(float %minnum, float 0.0) @@ -82,6 +119,12 @@ define double @test_max_min_K1Val_K0_f64(double %a) #1 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], 2.0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_min_K1Val_K0_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f64_e64 v[0:1], v[0:1], 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul double %a, 2.0 %minnum = call nnan double @llvm.minnum.f64(double 1.0, double %fmul) %fmed = call nnan double @llvm.maxnum.f64(double %minnum, double 0.0) @@ -94,6 +137,12 @@ define half @test_max_K0min_ValK1_f16(half %a) #0 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_K0min_ValK1_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul half %a, 2.0 %minnum = call nnan half @llvm.minnum.f16(half %fmul, half 1.0) %fmed = call nnan half @llvm.maxnum.f16(half 0.0, half %minnum) @@ -107,6 +156,12 @@ define <2 x half> @test_max_K0min_K1Val_v2f16(<2 x half> %a) #1 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_pk_mul_f16 v0, v0, 2.0 op_sel_hi:[1,0] clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_K0min_K1Val_v2f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_pk_mul_f16 v0, v0, 2.0 op_sel_hi:[1,0] clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul <2 x half> %a, <half 2.0, half 2.0> %minnum = call nnan <2 x half> @llvm.minnum.v2f16(<2 x half> <half 1.0, half undef>, <2 x half> %fmul) %fmed = call nnan <2 x half> @llvm.maxnum.v2f16(<2 x half> <half undef, half 0.0>, <2 x half> %minnum) @@ -121,6 +176,12 @@ define float @test_min_max_global_nnan(float %a) #3 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_max_f32_e64 v0, v0, v0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_global_nnan: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v0, v0, v0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %maxnum = call float @llvm.maxnum.f32(float %a, float 0.0) %fmed = call float @llvm.minnum.f32(float %maxnum, float 1.0) ret float %fmed @@ -132,6 +193,12 @@ define float @test_max_min_global_nnan(float %a) #3 { ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: v_max_f32_e64 v0, v0, v0 clamp ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_min_global_nnan: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v0, v0, v0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %minnum = call float @llvm.minnum.f32(float %a, float 1.0) %fmed = call float @llvm.maxnum.f32(float %minnum, float 0.0) ret float %fmed @@ -149,6 +216,12 @@ define float @test_min_max_K0_gt_K1(float %a) #0 { ; GFX10-NEXT: v_max_f32_e32 v0, 1.0, v0 ; GFX10-NEXT: v_min_f32_e32 v0, 0, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_K0_gt_K1: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_maxmin_num_f32 v0, v0, 1.0, 0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %maxnum = call nnan float @llvm.maxnum.f32(float %a, float 1.0) %fmed = call nnan float @llvm.minnum.f32(float %maxnum, float 0.0) ret float %fmed @@ -162,6 +235,12 @@ define float @test_max_min_K0_gt_K1(float %a) #0 { ; GFX10-NEXT: v_min_f32_e32 v0, 0, v0 ; GFX10-NEXT: v_max_f32_e32 v0, 1.0, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_min_K0_gt_K1: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_minmax_num_f32 v0, v0, 0, 1.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %minnum = call nnan float @llvm.minnum.f32(float %a, float 0.0) %fmed = call nnan float @llvm.maxnum.f32(float %minnum, float 1.0) ret float %fmed @@ -178,6 +257,12 @@ define float @test_min_max_maybe_NaN_input_ieee_false(float %a) #1 { ; GFX10-NEXT: v_max_f32_e32 v0, 0, v0 ; GFX10-NEXT: v_min_f32_e32 v0, 1.0, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_maybe_NaN_input_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul float %a, 2.0 %maxnum = call float @llvm.maxnum.f32(float %fmul, float 0.0) %fmed = call float @llvm.minnum.f32(float %maxnum, float 1.0) @@ -192,6 +277,12 @@ define float @test_min_max_maybe_NaN_input_ieee_true_dx10clamp_false(float %a) # ; GFX10-NEXT: v_mul_f32_e32 v0, 2.0, v0 ; GFX10-NEXT: v_med3_f32 v0, v0, 0, 1.0 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_maybe_NaN_input_ieee_true_dx10clamp_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f32_e64 v0, v0, 2.0 clamp +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul float %a, 2.0 %maxnum = call float @llvm.maxnum.f32(float %fmul, float 0.0) %fmed = call float @llvm.minnum.f32(float %maxnum, float 1.0) @@ -208,6 +299,14 @@ define float @test_max_min_maybe_NaN_input_ieee_true(float %a) #0 { ; GFX10-NEXT: v_min_f32_e32 v0, 1.0, v0 ; GFX10-NEXT: v_max_f32_e32 v0, 0, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_min_maybe_NaN_input_ieee_true: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f32_e32 v0, 2.0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_minmax_num_f32 v0, v0, 1.0, 0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul float %a, 2.0 %minnum = call float @llvm.minnum.f32(float %fmul, float 1.0) %fmed = call float @llvm.maxnum.f32(float %minnum, float 0.0) @@ -222,6 +321,14 @@ define float @test_max_min_maybe_NaN_input_ieee_false(float %a) #1 { ; GFX10-NEXT: v_min_f32_e32 v0, 1.0, v0 ; GFX10-NEXT: v_max_f32_e32 v0, 0, v0 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_min_maybe_NaN_input_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_mul_f32_e32 v0, 2.0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_minmax_num_f32 v0, v0, 1.0, 0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %fmul = fmul float %a, 2.0 %minnum = call float @llvm.minnum.f32(float %fmul, float 1.0) %fmed = call float @llvm.maxnum.f32(float %minnum, float 0.0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll new file mode 100644 index 000000000000..ccf4e84fbbbd --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll @@ -0,0 +1,336 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc -global-isel -amdgpu-global-isel-risky-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s + +; Divergent phis that don't require lowering using lane mask merging + +; - divergent phi that has divergent incoming value (this makes it divergent) +; but is reachable through only one path - branch instruction that chooses +; path is uniform + +; - divergent phi that is used only inside the loop and has incoming from +; previous iteration. After phi-elimination (rewrite lane mask in phi def with +; lane mask value from previous iteration), phi will hold lane mask valid for +; current iteration which is fine since it is not used outside of the loop. + +; And one more that is tricky (is branch divergent or not ?) +; "amdgpu-flat-work-group-size"="1,1" aka single lane execution does not stop +; shader from activating multiple lanes by using some intrinsic (entering wwm +; and using dpp instructions) +; - there are cases with single lane execution where branch instructions are not +; lowered to si_if (or other intrinsic branches) - with intention to use +; uniform branch after instruction selection? +; PhiIncomingAnalysis does not recognize G_BRCOND as divergent branch and does +; not perform lane mask merging + + + +define amdgpu_ps void @divergent_i1_phi_uniform_branch(ptr addrspace(1) %out, i32 %tid, i32 inreg %cond, ptr addrspace(1) %dummyaddr) { +; GFX10-LABEL: divergent_i1_phi_uniform_branch: +; GFX10: ; %bb.0: ; %A +; GFX10-NEXT: s_cmp_lg_u32 s0, 0 +; GFX10-NEXT: s_cbranch_scc0 .LBB0_2 +; GFX10-NEXT: ; %bb.1: +; GFX10-NEXT: v_cmp_le_u32_e64 s0, 6, v2 +; GFX10-NEXT: s_branch .LBB0_3 +; GFX10-NEXT: .LBB0_2: ; %dummy +; GFX10-NEXT: v_mov_b32_e32 v5, 0x7b +; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 1, v2 +; GFX10-NEXT: global_store_dword v[3:4], v5, off +; GFX10-NEXT: .LBB0_3: ; %exit +; GFX10-NEXT: v_cndmask_b32_e64 v2, 2, 1, s0 +; GFX10-NEXT: global_store_dword v[0:1], v2, off +; GFX10-NEXT: s_endpgm +A: + %val_A = icmp uge i32 %tid, 6 + %cmp = icmp eq i32 %cond, 0 + br i1 %cmp, label %dummy, label %exit + +dummy: + store i32 123, ptr addrspace(1) %dummyaddr + br label %B + +B: + %val_B = icmp ult i32 %tid, 1 + br label %exit + +exit: + %phi = phi i1 [ %val_A, %A ], [ %val_B, %B ] + %sel = select i1 %phi, i32 1, i32 2 + store i32 %sel, ptr addrspace(1) %out + ret void +} + +; Fix me - there is no need to merge lane masks here +define amdgpu_ps void @divergent_i1_phi_uniform_branch_simple(ptr addrspace(1) %out, i32 %tid, i32 inreg %cond) { +; GFX10-LABEL: divergent_i1_phi_uniform_branch_simple: +; GFX10: ; %bb.0: ; %A +; GFX10-NEXT: s_cmp_lg_u32 s0, 0 +; GFX10-NEXT: s_cbranch_scc0 .LBB1_2 +; GFX10-NEXT: ; %bb.1: +; GFX10-NEXT: v_cmp_le_u32_e64 s0, 6, v2 +; GFX10-NEXT: s_branch .LBB1_3 +; GFX10-NEXT: .LBB1_2: ; %B +; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 1, v2 +; GFX10-NEXT: .LBB1_3: ; %exit +; GFX10-NEXT: v_cndmask_b32_e64 v2, 2, 1, s0 +; GFX10-NEXT: global_store_dword v[0:1], v2, off +; GFX10-NEXT: s_endpgm +A: + %val_A = icmp uge i32 %tid, 6 + %cmp = icmp eq i32 %cond, 0 + br i1 %cmp, label %B, label %exit + +B: + %val_B = icmp ult i32 %tid, 1 + br label %exit + +exit: + %phi = phi i1 [ %val_A, %A ], [ %val_B, %B ] + %sel = select i1 %phi, i32 1, i32 2 + store i32 %sel, ptr addrspace(1) %out + ret void +} + + +; Divergent i1 phi that uses value from previous iteration. +; Used only inside the loop (variable name is bool_counter) +define void @divergent_i1_phi_used_inside_loop(float %val, ptr %addr) { +; GFX10-LABEL: divergent_i1_phi_used_inside_loop: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_mov_b32 s4, 0 +; GFX10-NEXT: v_mov_b32_e32 v3, 1 +; GFX10-NEXT: v_mov_b32_e32 v4, s4 +; GFX10-NEXT: .LBB2_1: ; %loop +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_cvt_f32_u32_e32 v5, v4 +; GFX10-NEXT: v_xor_b32_e32 v3, 1, v3 +; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v4 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v0 +; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_cbranch_execnz .LBB2_1 +; GFX10-NEXT: ; %bb.2: ; %exit +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: v_and_b32_e32 v0, 1, v3 +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo +; GFX10-NEXT: flat_store_dword v[1:2], v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_setpc_b64 s[30:31] +entry: + br label %loop + +loop: + %counter = phi i32 [ 0, %entry ], [ %counterPlus1, %loop ] + %bool_counter = phi i1 [ true, %entry ], [ %neg_bool_counter, %loop ] + %neg_bool_counter = xor i1 %bool_counter, true + %fcounter = uitofp i32 %counter to float + %cond = fcmp ogt float %fcounter, %val + %counterPlus1 = add i32 %counter, 1 + br i1 %cond, label %exit, label %loop + +exit: + %select = select i1 %neg_bool_counter, float 1.000000e+00, float 0.000000e+00 + store float %select, ptr %addr + ret void +} + +define void @divergent_i1_phi_used_inside_loop_bigger_loop_body(float %val, float %pre_cond_val, ptr %addr, ptr %addr_if, ptr %addr_else) { +; GFX10-LABEL: divergent_i1_phi_used_inside_loop_bigger_loop_body: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, 1.0, v1 +; GFX10-NEXT: s_mov_b32 s4, 0 +; GFX10-NEXT: v_mov_b32_e32 v8, 0x3e8 +; GFX10-NEXT: v_mov_b32_e32 v9, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-NEXT: s_branch .LBB3_2 +; GFX10-NEXT: .LBB3_1: ; %loop_body +; GFX10-NEXT: ; in Loop: Header=BB3_2 Depth=1 +; GFX10-NEXT: v_cvt_f32_u32_e32 v10, v9 +; GFX10-NEXT: v_xor_b32_e32 v1, 1, v1 +; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v9 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v0 +; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_cbranch_execz .LBB3_6 +; GFX10-NEXT: .LBB3_2: ; %loop_start +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_cmp_ge_i32_e32 vcc_lo, 0x3e8, v9 +; GFX10-NEXT: s_mov_b32 s5, 1 +; GFX10-NEXT: s_cbranch_vccz .LBB3_4 +; GFX10-NEXT: ; %bb.3: ; %else +; GFX10-NEXT: ; in Loop: Header=BB3_2 Depth=1 +; GFX10-NEXT: s_mov_b32 s5, 0 +; GFX10-NEXT: flat_store_dword v[6:7], v8 +; GFX10-NEXT: .LBB3_4: ; %Flow +; GFX10-NEXT: ; in Loop: Header=BB3_2 Depth=1 +; GFX10-NEXT: s_xor_b32 s5, s5, 1 +; GFX10-NEXT: s_and_b32 s5, s5, 1 +; GFX10-NEXT: s_cmp_lg_u32 s5, 0 +; GFX10-NEXT: s_cbranch_scc1 .LBB3_1 +; GFX10-NEXT: ; %bb.5: ; %if +; GFX10-NEXT: ; in Loop: Header=BB3_2 Depth=1 +; GFX10-NEXT: flat_store_dword v[4:5], v8 +; GFX10-NEXT: s_branch .LBB3_1 +; GFX10-NEXT: .LBB3_6: ; %exit +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: v_and_b32_e32 v0, 1, v1 +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo +; GFX10-NEXT: flat_store_dword v[2:3], v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_setpc_b64 s[30:31] +entry: + %pre_cond = fcmp ogt float %pre_cond_val, 1.0 + br label %loop_start + +loop_start: + %counter = phi i32 [ 0, %entry ], [ %counterPlus1, %loop_body ] + %bool_counter = phi i1 [ %pre_cond, %entry ], [ %neg_bool_counter, %loop_body ] + %cond_break = icmp sgt i32 %counter, 1000 + br i1 %cond_break, label %if, label %else + +if: + store i32 1000, ptr %addr_if + br label %loop_body + +else: + store i32 1000, ptr %addr_else + br label %loop_body + +loop_body: + %neg_bool_counter = xor i1 %bool_counter, true + %fcounter = uitofp i32 %counter to float + %cond = fcmp ogt float %fcounter, %val + %counterPlus1 = add i32 %counter, 1 + br i1 %cond, label %exit, label %loop_start + +exit: + %select = select i1 %neg_bool_counter, float 1.000000e+00, float 0.000000e+00 + store float %select, ptr %addr + ret void +} + +; There is a divergent, according to machine uniformity info, g_brcond branch +; here, not lowered to si_if because of "amdgpu-flat-work-group-size"="1,1". +define amdgpu_cs void @single_lane_execution_attribute(i32 inreg %.userdata0, <3 x i32> inreg %.WorkgroupId, <3 x i32> %.LocalInvocationId) #0 { +; GFX10-LABEL: single_lane_execution_attribute: +; GFX10: ; %bb.0: ; %.entry +; GFX10-NEXT: s_mov_b32 s12, 0 +; GFX10-NEXT: s_getpc_b64 s[4:5] +; GFX10-NEXT: s_mov_b32 s13, -1 +; GFX10-NEXT: s_mov_b32 s2, s0 +; GFX10-NEXT: s_and_b64 s[4:5], s[4:5], s[12:13] +; GFX10-NEXT: s_mov_b32 s3, s12 +; GFX10-NEXT: v_mbcnt_lo_u32_b32 v1, -1, 0 +; GFX10-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3] +; GFX10-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0 +; GFX10-NEXT: s_mov_b32 s2, 1 +; GFX10-NEXT: v_mbcnt_hi_u32_b32 v2, -1, v1 +; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v2 +; GFX10-NEXT: v_and_b32_e32 v3, 1, v2 +; GFX10-NEXT: v_xor_b32_e32 v3, 1, v3 +; GFX10-NEXT: v_and_b32_e32 v3, 1, v3 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: buffer_load_dword v1, v1, s[4:7], 0 offen +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3 +; GFX10-NEXT: ; implicit-def: $vgpr3 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 0, v1 +; GFX10-NEXT: s_cbranch_vccnz .LBB4_4 +; GFX10-NEXT: ; %bb.1: ; %.preheader.preheader +; GFX10-NEXT: v_mov_b32_e32 v4, s12 +; GFX10-NEXT: v_mov_b32_e32 v3, s12 +; GFX10-NEXT: .LBB4_2: ; %.preheader +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: buffer_load_dword v5, v4, s[4:7], 0 offen +; GFX10-NEXT: v_add_nc_u32_e32 v2, -1, v2 +; GFX10-NEXT: v_add_nc_u32_e32 v4, 4, v4 +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v2 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_add_nc_u32_e32 v3, v5, v3 +; GFX10-NEXT: s_cbranch_vccnz .LBB4_2 +; GFX10-NEXT: ; %bb.3: ; %.preheader._crit_edge +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v1 +; GFX10-NEXT: s_or_b32 s2, s0, vcc_lo +; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s2 +; GFX10-NEXT: s_mov_b32 s2, 0 +; GFX10-NEXT: .LBB4_4: ; %Flow +; GFX10-NEXT: s_and_b32 s2, s2, 1 +; GFX10-NEXT: s_cmp_lg_u32 s2, 0 +; GFX10-NEXT: s_cbranch_scc0 .LBB4_6 +; GFX10-NEXT: ; %bb.5: ; %.19 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 +; GFX10-NEXT: v_or_b32_e32 v3, 2, v1 +; GFX10-NEXT: .LBB4_6: ; %.22 +; GFX10-NEXT: v_add_lshl_u32 v0, v0, s1, 2 +; GFX10-NEXT: buffer_store_dword v3, v0, s[8:11], 0 offen +; GFX10-NEXT: s_endpgm +.entry: + %.0 = call i64 @llvm.amdgcn.s.getpc() + %.1 = and i64 %.0, -4294967296 + %.2 = zext i32 %.userdata0 to i64 + %.3 = or i64 %.1, %.2 + %.4 = inttoptr i64 %.3 to ptr addrspace(4) + %.5 = getelementptr i8, ptr addrspace(4) %.4, i64 16 + %.6 = load <4 x i32>, ptr addrspace(4) %.5, align 16 + %.7 = load <4 x i32>, ptr addrspace(4) %.4, align 16 + %.8 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %.9 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %.8) + %.fr11 = freeze i32 %.9 + %.idx = shl i32 %.fr11, 2 + %.10 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %.7, i32 %.idx, i32 0, i32 0) + %.11 = icmp eq i32 %.10, 0 + %.12 = and i32 %.fr11, 1 + %.not = icmp eq i32 %.12, 0 + br i1 %.not, label %.19, label %.preheader + +.preheader: ; preds = %.entry, %.preheader + %._96.02 = phi i32 [ %.15, %.preheader ], [ 0, %.entry ] + %._50.01 = phi i32 [ %.14, %.preheader ], [ 0, %.entry ] + %.idx5 = shl i32 %._96.02, 2 + %.13 = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %.7, i32 %.idx5, i32 0, i32 0) + %.14 = add i32 %.13, %._50.01 + %.15 = add nuw i32 %._96.02, 1 + %.exitcond.not = icmp eq i32 %.15, %.fr11 + br i1 %.exitcond.not, label %.preheader._crit_edge, label %.preheader + +.preheader._crit_edge: ; preds = %.preheader + %.16 = icmp eq i32 %.14, %.10 + %.17 = or i1 %.11, %.16 + %.18 = zext i1 %.17 to i32 + br label %.22 + +.19: ; preds = %.entry + %.20 = zext i1 %.11 to i32 + %.21 = or i32 %.20, 2 + br label %.22 + +.22: ; preds = %.19, %.preheader._crit_edge + %._51.0 = phi i32 [ %.18, %.preheader._crit_edge ], [ %.21, %.19 ] + %.WorkgroupId.i0 = extractelement <3 x i32> %.WorkgroupId, i64 0 + %.LocalInvocationId.i0 = extractelement <3 x i32> %.LocalInvocationId, i64 0 + %.i0 = add i32 %.LocalInvocationId.i0, %.WorkgroupId.i0 + %.idx6 = shl i32 %.i0, 2 + call void @llvm.amdgcn.raw.buffer.store.i32(i32 %._51.0, <4 x i32> %.6, i32 %.idx6, i32 0, i32 0) + ret void +} + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none) +declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare i64 @llvm.amdgcn.s.getpc() + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read) +declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32 immarg) + +; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write) +declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32 immarg) + +attributes #0 = { nounwind memory(readwrite) "amdgpu-flat-work-group-size"="1,1" } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir new file mode 100644 index 000000000000..d314ebe355f5 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir @@ -0,0 +1,610 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering %s -o - | FileCheck -check-prefix=GFX10 %s + +--- | + define void @divergent_i1_phi_uniform_branch() {ret void} + define void @divergent_i1_phi_uniform_branch_simple() {ret void} + define void @divergent_i1_phi_used_inside_loop() {ret void} + define void @divergent_i1_phi_used_inside_loop_bigger_loop_body() {ret void} + define void @_amdgpu_cs_main() #0 {ret void} + + attributes #0 = {"amdgpu-flat-work-group-size"="1,1"} +... + +--- +name: divergent_i1_phi_uniform_branch +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: divergent_i1_phi_uniform_branch + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x30000000), %bb.2(0x50000000) + ; GFX10-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr0 + ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr4 + ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C]] + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY3]](s32), [[C1]] + ; GFX10-NEXT: G_BRCOND [[ICMP1]](s1), %bb.2 + ; GFX10-NEXT: G_BR %bb.1 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.3(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 123 + ; GFX10-NEXT: G_STORE [[C2]](s32), [[MV1]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: G_BR %bb.3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.4(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s1) = G_PHI %14(s1), %bb.3, [[ICMP]](s1), %bb.0 + ; GFX10-NEXT: G_BR %bb.4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.2(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C3]] + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI]](s1), [[C5]], [[C4]] + ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.1(0x30000000), %bb.2(0x50000000) + liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $vgpr2 + %4:_(s32) = COPY $sgpr0 + %5:_(s32) = COPY $vgpr3 + %6:_(s32) = COPY $vgpr4 + %7:_(p1) = G_MERGE_VALUES %5(s32), %6(s32) + %8:_(s32) = G_CONSTANT i32 6 + %9:_(s1) = G_ICMP intpred(uge), %3(s32), %8 + %10:_(s32) = G_CONSTANT i32 0 + %11:_(s1) = G_ICMP intpred(ne), %4(s32), %10 + G_BRCOND %11(s1), %bb.2 + G_BR %bb.1 + + bb.1: + successors: %bb.3(0x80000000) + + %12:_(s32) = G_CONSTANT i32 123 + G_STORE %12(s32), %7(p1) :: (store (s32), addrspace 1) + G_BR %bb.3 + + bb.2: + successors: %bb.4(0x80000000) + + %13:_(s1) = G_PHI %14(s1), %bb.3, %9(s1), %bb.0 + G_BR %bb.4 + + bb.3: + successors: %bb.2(0x80000000) + + %15:_(s32) = G_CONSTANT i32 1 + %14:_(s1) = G_ICMP intpred(ult), %3(s32), %15 + G_BR %bb.2 + + bb.4: + %16:_(s32) = G_CONSTANT i32 2 + %17:_(s32) = G_CONSTANT i32 1 + %18:_(s32) = G_SELECT %13(s1), %17, %16 + G_STORE %18(s32), %2(p1) :: (store (s32), addrspace 1) + S_ENDPGM 0 +... + +--- +name: divergent_i1_phi_uniform_branch_simple +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: divergent_i1_phi_uniform_branch_simple + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x30000000), %bb.2(0x50000000) + ; GFX10-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr0 + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C]] + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY3]](s32), [[C1]] + ; GFX10-NEXT: G_BRCOND [[ICMP1]](s1), %bb.2 + ; GFX10-NEXT: G_BR %bb.1 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C2]] + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1 + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI]](s1), [[C4]], [[C3]] + ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.1(0x30000000), %bb.2(0x50000000) + liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $vgpr2 + %4:_(s32) = COPY $sgpr0 + %5:_(s32) = G_CONSTANT i32 6 + %6:_(s1) = G_ICMP intpred(uge), %3(s32), %5 + %7:_(s32) = G_CONSTANT i32 0 + %8:_(s1) = G_ICMP intpred(ne), %4(s32), %7 + G_BRCOND %8(s1), %bb.2 + G_BR %bb.1 + + bb.1: + successors: %bb.2(0x80000000) + + %9:_(s32) = G_CONSTANT i32 1 + %10:_(s1) = G_ICMP intpred(ult), %3(s32), %9 + + bb.2: + %11:_(s1) = G_PHI %6(s1), %bb.0, %10(s1), %bb.1 + %12:_(s32) = G_CONSTANT i32 2 + %13:_(s32) = G_CONSTANT i32 1 + %14:_(s32) = G_SELECT %11(s1), %13, %12 + G_STORE %14(s32), %2(p1) :: (store (s32), addrspace 1) + S_ENDPGM 0 +... + +--- +name: divergent_i1_phi_used_inside_loop +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: divergent_i1_phi_used_inside_loop + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C1]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %9(s32), %bb.1 + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s1) = G_PHI [[C]](s1), %bb.0, %11(s1), %bb.1 + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI2]], [[C2]] + ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI1]](s32) + ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]] + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C3]] + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[XOR]](s1), %bb.1 + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32) + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI3]](s1), [[C5]], [[C4]] + ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32)) + ; GFX10-NEXT: SI_RETURN + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s32) = COPY $vgpr2 + %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32) + %4:_(s1) = G_CONSTANT i1 true + %5:_(s32) = G_CONSTANT i32 0 + + bb.1: + successors: %bb.2(0x04000000), %bb.1(0x7c000000) + + %6:_(s32) = G_PHI %7(s32), %bb.1, %5(s32), %bb.0 + %8:_(s32) = G_PHI %5(s32), %bb.0, %9(s32), %bb.1 + %10:_(s1) = G_PHI %4(s1), %bb.0, %11(s1), %bb.1 + %12:_(s1) = G_CONSTANT i1 true + %11:_(s1) = G_XOR %10, %12 + %13:_(s32) = G_UITOFP %8(s32) + %14:_(s1) = G_FCMP floatpred(ogt), %13(s32), %0 + %15:_(s32) = G_CONSTANT i32 1 + %9:_(s32) = G_ADD %8, %15 + %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %14(s1), %6(s32) + SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 + + bb.2: + %16:_(s1) = G_PHI %11(s1), %bb.1 + %17:_(s32) = G_PHI %7(s32), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %17(s32) + %18:_(s32) = G_FCONSTANT float 0.000000e+00 + %19:_(s32) = G_FCONSTANT float 1.000000e+00 + %20:_(s32) = G_SELECT %16(s1), %19, %18 + G_STORE %20(s32), %3(p0) :: (store (s32)) + SI_RETURN +... + +--- +name: divergent_i1_phi_used_inside_loop_bigger_loop_body +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: divergent_i1_phi_used_inside_loop_bigger_loop_body + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) + ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4 + ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5 + ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32) + ; GFX10-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6 + ; GFX10-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7 + ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY1]](s32), [[C1]] + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %15(s32), %bb.5, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %17(s32), %bb.5 + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s1) = G_PHI [[FCMP]](s1), %bb.0, %19(s1), %bb.5 + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[PHI1]](s32), [[C3]] + ; GFX10-NEXT: G_BRCOND [[ICMP]](s1), %bb.4 + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI %24(s1), %bb.4, [[C2]](s1), %bb.1 + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI3]], [[C4]] + ; GFX10-NEXT: G_BRCOND [[XOR]](s1), %bb.5 + ; GFX10-NEXT: G_BR %bb.3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.5(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000 + ; GFX10-NEXT: G_STORE [[C5]](s32), [[MV1]](p0) :: (store (s32)) + ; GFX10-NEXT: G_BR %bb.5 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: successors: %bb.2(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s1) = G_CONSTANT i1 false + ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000 + ; GFX10-NEXT: G_STORE [[C7]](s32), [[MV2]](p0) :: (store (s32)) + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.5: + ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[PHI2]], [[C8]] + ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI1]](s32) + ; GFX10-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]] + ; GFX10-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C9]] + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[FCMP1]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.6 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.6: + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s1) = G_PHI [[XOR1]](s1), %bb.5 + ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.5 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI5]](s32) + ; GFX10-NEXT: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX10-NEXT: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI4]](s1), [[C11]], [[C10]] + ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32)) + ; GFX10-NEXT: SI_RETURN + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s32) = COPY $vgpr2 + %3:_(s32) = COPY $vgpr3 + %4:_(p0) = G_MERGE_VALUES %2(s32), %3(s32) + %5:_(s32) = COPY $vgpr4 + %6:_(s32) = COPY $vgpr5 + %7:_(p0) = G_MERGE_VALUES %5(s32), %6(s32) + %8:_(s32) = COPY $vgpr6 + %9:_(s32) = COPY $vgpr7 + %10:_(p0) = G_MERGE_VALUES %8(s32), %9(s32) + %11:_(s32) = G_CONSTANT i32 0 + %12:_(s32) = G_FCONSTANT float 1.000000e+00 + %13:_(s1) = G_FCMP floatpred(ogt), %1(s32), %12 + + bb.1: + successors: %bb.4(0x40000000), %bb.2(0x40000000) + + %14:_(s32) = G_PHI %15(s32), %bb.5, %11(s32), %bb.0 + %16:_(s32) = G_PHI %11(s32), %bb.0, %17(s32), %bb.5 + %18:_(s1) = G_PHI %13(s1), %bb.0, %19(s1), %bb.5 + %20:_(s1) = G_CONSTANT i1 true + %21:_(s32) = G_CONSTANT i32 1000 + %22:_(s1) = G_ICMP intpred(sle), %16(s32), %21 + G_BRCOND %22(s1), %bb.4 + G_BR %bb.2 + + bb.2: + successors: %bb.3(0x40000000), %bb.5(0x40000000) + + %23:_(s1) = G_PHI %24(s1), %bb.4, %20(s1), %bb.1 + %25:_(s1) = G_CONSTANT i1 true + %26:_(s1) = G_XOR %23, %25 + G_BRCOND %26(s1), %bb.5 + G_BR %bb.3 + + bb.3: + successors: %bb.5(0x80000000) + + %27:_(s32) = G_CONSTANT i32 1000 + G_STORE %27(s32), %7(p0) :: (store (s32)) + G_BR %bb.5 + + bb.4: + successors: %bb.2(0x80000000) + + %24:_(s1) = G_CONSTANT i1 false + %28:_(s32) = G_CONSTANT i32 1000 + G_STORE %28(s32), %10(p0) :: (store (s32)) + G_BR %bb.2 + + bb.5: + successors: %bb.6(0x04000000), %bb.1(0x7c000000) + + %29:_(s1) = G_CONSTANT i1 true + %19:_(s1) = G_XOR %18, %29 + %30:_(s32) = G_UITOFP %16(s32) + %31:_(s1) = G_FCMP floatpred(ogt), %30(s32), %0 + %32:_(s32) = G_CONSTANT i32 1 + %17:_(s32) = G_ADD %16, %32 + %15:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %31(s1), %14(s32) + SI_LOOP %15(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.6 + + bb.6: + %33:_(s1) = G_PHI %19(s1), %bb.5 + %34:_(s32) = G_PHI %15(s32), %bb.5 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %34(s32) + %35:_(s32) = G_FCONSTANT float 0.000000e+00 + %36:_(s32) = G_FCONSTANT float 1.000000e+00 + %37:_(s32) = G_SELECT %33(s1), %36, %35 + G_STORE %37(s32), %4(p0) :: (store (s32)) + SI_RETURN +... + +--- +name: _amdgpu_cs_main +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: _amdgpu_cs_main + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; GFX10-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1 + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; GFX10-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.getpc) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296 + ; GFX10-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[INT]], [[C]] + ; GFX10-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32) + ; GFX10-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[ZEXT]] + ; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[OR]](s64) + ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[INTTOPTR]](p4) :: (load (<8 x s32>)) + ; GFX10-NEXT: [[BITCAST:%[0-9]+]]:_(s256) = G_BITCAST [[LOAD]](<8 x s32>) + ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s128) = G_TRUNC [[BITCAST]](s256) + ; GFX10-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[TRUNC]](s128) + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; GFX10-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), [[C2]](s32), [[C1]](s32) + ; GFX10-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.hi), [[C2]](s32), [[INT1]](s32) + ; GFX10-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[INT2]] + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FREEZE]], [[C3]](s32) + ; GFX10-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_BUFFER_LOAD [[BITCAST1]](<4 x s32>), [[C1]](s32), [[SHL]], [[C1]], 0, 0, 0 :: (load (s32), align 1, addrspace 8) + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AMDGPU_BUFFER_LOAD]](s32), [[C1]] + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[FREEZE]], [[C4]] + ; GFX10-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[AND1]](s32) + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[TRUNC1]], [[C5]] + ; GFX10-NEXT: G_BRCOND [[XOR]](s1), %bb.2 + ; GFX10-NEXT: G_BR %bb.1 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.3(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: G_BR %bb.3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %30(s32), %bb.4, [[DEF]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s1) = G_PHI %32(s1), %bb.4, [[C5]](s1), %bb.0 + ; GFX10-NEXT: G_BRCOND [[PHI1]](s1), %bb.5 + ; GFX10-NEXT: G_BR %bb.6 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %34(s32), %bb.3, [[C6]](s32), %bb.1 + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI %36(s32), %bb.3, [[FREEZE]](s32), %bb.1 + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI %38(s32), %bb.3, [[C6]](s32), %bb.1 + ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:_(s32) = G_AMDGPU_BUFFER_LOAD [[BITCAST1]](<4 x s32>), [[C7]](s32), [[PHI2]], [[C7]], 0, 0, 0 :: (load (s32), align 1, addrspace 8) + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AMDGPU_BUFFER_LOAD1]], [[PHI4]] + ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI3]], [[C8]] + ; GFX10-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; GFX10-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C9]] + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD1]](s32), [[C7]] + ; GFX10-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3 + ; GFX10-NEXT: G_BR %bb.4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: successors: %bb.2(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s32) = G_PHI [[ADD]](s32), %bb.3 + ; GFX10-NEXT: [[C10:%[0-9]+]]:_(s1) = G_CONSTANT i1 false + ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[PHI5]](s32), [[AMDGPU_BUFFER_LOAD]] + ; GFX10-NEXT: [[OR1:%[0-9]+]]:_(s1) = G_OR [[ICMP]], [[ICMP2]] + ; GFX10-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s1) + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.5: + ; GFX10-NEXT: successors: %bb.6(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1) + ; GFX10-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[C11]] + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.6: + ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[PHI]](s32), %bb.2, [[OR2]](s32), %bb.5 + ; GFX10-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[LOAD]](<8 x s32>) + ; GFX10-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY1]] + ; GFX10-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ADD3]], [[C12]](s32) + ; GFX10-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: G_AMDGPU_BUFFER_STORE [[PHI6]](s32), [[UV1]](<4 x s32>), [[C13]](s32), [[SHL1]], [[C13]], 0, 0, 0 :: (store (s32), align 1, addrspace 8) + ; GFX10-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2 + + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = COPY $sgpr1 + %2:_(s32) = COPY $vgpr0 + %3:_(s32) = G_IMPLICIT_DEF + %4:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.getpc) + %5:_(s64) = G_CONSTANT i64 -4294967296 + %6:_(s64) = G_AND %4, %5 + %7:_(s64) = G_ZEXT %0(s32) + %8:_(s64) = G_OR %6, %7 + %9:_(p4) = G_INTTOPTR %8(s64) + %10:_(<8 x s32>) = G_LOAD %9(p4) :: (load (<8 x s32>)) + %11:_(s256) = G_BITCAST %10(<8 x s32>) + %12:_(s128) = G_TRUNC %11(s256) + %13:_(<4 x s32>) = G_BITCAST %12(s128) + %15:_(s32) = G_CONSTANT i32 0 + %14:_(s32) = G_CONSTANT i32 -1 + %16:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %14(s32), %15(s32) + %17:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.hi), %14(s32), %16(s32) + %18:_(s32) = G_FREEZE %17 + %19:_(s32) = G_CONSTANT i32 2 + %20:_(s32) = G_SHL %18, %19(s32) + %21:_(s32) = G_AMDGPU_BUFFER_LOAD %13(<4 x s32>), %15(s32), %20, %15, 0, 0, 0 :: (load (s32), align 1, addrspace 8) + %22:_(s1) = G_ICMP intpred(eq), %21(s32), %15 + %23:_(s32) = G_CONSTANT i32 1 + %24:_(s32) = G_AND %18, %23 + %25:_(s1) = G_TRUNC %24(s32) + %26:_(s1) = G_CONSTANT i1 true + %27:_(s1) = G_XOR %25, %26 + G_BRCOND %27(s1), %bb.2 + G_BR %bb.1 + + bb.1: + successors: %bb.3(0x80000000) + + %28:_(s32) = G_CONSTANT i32 0 + G_BR %bb.3 + + bb.2: + successors: %bb.5(0x40000000), %bb.6(0x40000000) + + %29:_(s32) = G_PHI %30(s32), %bb.4, %3(s32), %bb.0 + %31:_(s1) = G_PHI %32(s1), %bb.4, %26(s1), %bb.0 + G_BRCOND %31(s1), %bb.5 + G_BR %bb.6 + + bb.3: + successors: %bb.4(0x04000000), %bb.3(0x7c000000) + + %33:_(s32) = G_PHI %34(s32), %bb.3, %28(s32), %bb.1 + %35:_(s32) = G_PHI %36(s32), %bb.3, %18(s32), %bb.1 + %37:_(s32) = G_PHI %38(s32), %bb.3, %28(s32), %bb.1 + %39:_(s32) = G_CONSTANT i32 0 + %40:_(s32) = G_AMDGPU_BUFFER_LOAD %13(<4 x s32>), %39(s32), %33, %39, 0, 0, 0 :: (load (s32), align 1, addrspace 8) + %38:_(s32) = G_ADD %40, %37 + %41:_(s32) = G_CONSTANT i32 -1 + %36:_(s32) = G_ADD %35, %41 + %42:_(s32) = G_CONSTANT i32 4 + %34:_(s32) = G_ADD %33, %42 + %43:_(s1) = G_ICMP intpred(ne), %36(s32), %39 + G_BRCOND %43(s1), %bb.3 + G_BR %bb.4 + + bb.4: + successors: %bb.2(0x80000000) + + %44:_(s32) = G_PHI %38(s32), %bb.3 + %32:_(s1) = G_CONSTANT i1 false + %45:_(s1) = G_ICMP intpred(eq), %44(s32), %21 + %46:_(s1) = G_OR %22, %45 + %30:_(s32) = G_ZEXT %46(s1) + G_BR %bb.2 + + bb.5: + successors: %bb.6(0x80000000) + + %47:_(s32) = G_ZEXT %22(s1) + %48:_(s32) = G_CONSTANT i32 2 + %49:_(s32) = G_OR %47, %48 + + bb.6: + %50:_(s32) = G_PHI %29(s32), %bb.2, %49(s32), %bb.5 + %51:_(<4 x s32>), %52:_(<4 x s32>) = G_UNMERGE_VALUES %10(<8 x s32>) + %53:_(s32) = G_ADD %2, %1 + %54:_(s32) = G_CONSTANT i32 2 + %55:_(s32) = G_SHL %53, %54(s32) + %56:_(s32) = G_CONSTANT i32 0 + G_AMDGPU_BUFFER_STORE %50(s32), %52(<4 x s32>), %56(s32), %55, %56, 0, 0, 0 :: (store (s32), align 1, addrspace 8) + S_ENDPGM 0 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll new file mode 100644 index 000000000000..34dedfe10365 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll @@ -0,0 +1,512 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -amdgpu-global-isel-risky-select -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s + +; This file contains various tests that have divergent i1s used outside of +; the loop. These are lane masks is sgpr and need to have correct value in +; corresponding bit at the iteration lane exits the loop. +; Achieved by merging lane mask with same lane mask from previous iteration +; and using that merged lane mask outside of the loop. + +; Phi used outside of the loop directly (loopfinder will figure out that it +; needs to merge lane mask across all iterations) +define void @divergent_i1_phi_used_outside_loop(float %val, float %pre.cond.val, ptr %addr) { +; GFX10-LABEL: divergent_i1_phi_used_outside_loop: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, 1.0, v1 +; GFX10-NEXT: s_mov_b32 s4, 0 +; GFX10-NEXT: v_mov_b32_e32 v1, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo +; GFX10-NEXT: .LBB0_1: ; %loop +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_cvt_f32_u32_e32 v6, v1 +; GFX10-NEXT: v_mov_b32_e32 v5, v4 +; GFX10-NEXT: v_add_nc_u32_e32 v1, 1, v1 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v0 +; GFX10-NEXT: v_xor_b32_e32 v4, 1, v5 +; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_cbranch_execnz .LBB0_1 +; GFX10-NEXT: ; %bb.2: ; %exit +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: v_and_b32_e32 v0, 1, v5 +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo +; GFX10-NEXT: flat_store_dword v[2:3], v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_setpc_b64 s[30:31] +entry: + %pre.cond = fcmp ogt float %pre.cond.val, 1.0 + br label %loop + +loop: + %counter = phi i32 [ 0, %entry ], [ %counter.plus.1, %loop ] + %bool.counter = phi i1 [ %pre.cond, %entry ], [ %neg.bool.counter, %loop ] + %neg.bool.counter = xor i1 %bool.counter, true + %f.counter = uitofp i32 %counter to float + %cond = fcmp ogt float %f.counter, %val + %counter.plus.1 = add i32 %counter, 1 + br i1 %cond, label %exit, label %loop + +exit: + %select = select i1 %bool.counter, float 1.000000e+00, float 0.000000e+00 + store float %select, ptr %addr + ret void +} + +define void @divergent_i1_phi_used_outside_loop_larger_loop_body(float %val, ptr addrspace(1) %a, ptr %addr) { +; GFX10-LABEL: divergent_i1_phi_used_outside_loop_larger_loop_body: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_mov_b32 s4, -1 +; GFX10-NEXT: v_mov_b32_e32 v5, 1 +; GFX10-NEXT: v_mov_b32_e32 v0, s4 +; GFX10-NEXT: s_branch .LBB1_2 +; GFX10-NEXT: .LBB1_1: ; %loop.cond +; GFX10-NEXT: ; in Loop: Header=BB1_2 Depth=1 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: v_add_nc_u32_e32 v0, 1, v0 +; GFX10-NEXT: v_add_co_u32 v1, s4, v1, 4 +; GFX10-NEXT: v_add_co_ci_u32_e64 v2, s4, 0, v2, s4 +; GFX10-NEXT: v_cmp_le_i32_e32 vcc_lo, 10, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s6 +; GFX10-NEXT: s_cbranch_vccz .LBB1_4 +; GFX10-NEXT: .LBB1_2: ; %loop.start +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_and_b32_e32 v5, 1, v5 +; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, v5 +; GFX10-NEXT: s_mov_b32 s6, s5 +; GFX10-NEXT: s_and_saveexec_b32 s4, s5 +; GFX10-NEXT: s_cbranch_execz .LBB1_1 +; GFX10-NEXT: ; %bb.3: ; %is.eq.zero +; GFX10-NEXT: ; in Loop: Header=BB1_2 Depth=1 +; GFX10-NEXT: global_load_dword v5, v[1:2], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 0, v5 +; GFX10-NEXT: s_branch .LBB1_1 +; GFX10-NEXT: .LBB1_4: ; %exit +; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s5 +; GFX10-NEXT: flat_store_dword v[3:4], v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_setpc_b64 s[30:31] +entry: + br label %loop.start + +loop.start: + %i = phi i32 [ 0, %entry ], [ %i.plus.1, %loop.cond ] + %all.eq.zero = phi i1 [ true, %entry ], [ %eq.zero, %loop.cond ] + br i1 %all.eq.zero, label %is.eq.zero, label %loop.cond + +is.eq.zero: + %a.plus.i = getelementptr i32, ptr addrspace(1) %a, i32 %i + %elt.i = load i32, ptr addrspace(1) %a.plus.i + %elt.i.eq.zero = icmp eq i32 %elt.i, 0 + br label %loop.cond + +loop.cond: + %eq.zero = phi i1 [ %all.eq.zero, %loop.start ], [ %elt.i.eq.zero, %is.eq.zero ] + %cond = icmp slt i32 %i, 10 + %i.plus.1 = add i32 %i, 1 + br i1 %cond, label %exit, label %loop.start + +exit: + %select = select i1 %all.eq.zero, float 1.000000e+00, float 0.000000e+00 + store float %select, ptr %addr + ret void +} + +; Non-phi used outside of the loop + +define void @divergent_i1_xor_used_outside_loop(float %val, float %pre.cond.val, ptr %addr) { +; GFX10-LABEL: divergent_i1_xor_used_outside_loop: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_lt_f32_e32 vcc_lo, 1.0, v1 +; GFX10-NEXT: s_mov_b32 s4, 0 +; GFX10-NEXT: v_mov_b32_e32 v4, s4 +; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo +; GFX10-NEXT: .LBB2_1: ; %loop +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_cvt_f32_u32_e32 v5, v4 +; GFX10-NEXT: v_xor_b32_e32 v1, 1, v1 +; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v4 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v0 +; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_cbranch_execnz .LBB2_1 +; GFX10-NEXT: ; %bb.2: ; %exit +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: v_and_b32_e32 v0, 1, v1 +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo +; GFX10-NEXT: flat_store_dword v[2:3], v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_setpc_b64 s[30:31] +entry: + %pre.cond = fcmp ogt float %pre.cond.val, 1.0 + br label %loop + +loop: + %counter = phi i32 [ 0, %entry ], [ %counter.plus.1, %loop ] + %bool.counter = phi i1 [ %pre.cond, %entry ], [ %neg.bool.counter, %loop ] + %neg.bool.counter = xor i1 %bool.counter, true + %f.counter = uitofp i32 %counter to float + %cond = fcmp ogt float %f.counter, %val + %counter.plus.1 = add i32 %counter, 1 + br i1 %cond, label %exit, label %loop + +exit: + %select = select i1 %neg.bool.counter, float 1.000000e+00, float 0.000000e+00 + store float %select, ptr %addr + ret void +} + +;void xor(int num_elts, int* a, int* addr) { +;for(int i=0; i<num_elts; ++i) { +; if(a[i]==0) +; return; +;} +;addr[0] = 5 +;return; +;} + +define void @divergent_i1_xor_used_outside_loop_larger_loop_body(i32 %num.elts, ptr addrspace(1) %a, ptr %addr) { +; GFX10-LABEL: divergent_i1_xor_used_outside_loop_larger_loop_body: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX10-NEXT: s_mov_b32 s5, 0 +; GFX10-NEXT: s_mov_b32 s6, -1 +; GFX10-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB3_6 +; GFX10-NEXT: ; %bb.1: ; %loop.start.preheader +; GFX10-NEXT: v_mov_b32_e32 v5, s5 +; GFX10-NEXT: s_branch .LBB3_3 +; GFX10-NEXT: .LBB3_2: ; %Flow +; GFX10-NEXT: ; in Loop: Header=BB3_3 Depth=1 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s8 +; GFX10-NEXT: s_xor_b32 s7, s7, 1 +; GFX10-NEXT: s_and_b32 s6, exec_lo, s6 +; GFX10-NEXT: s_or_b32 s5, s6, s5 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5 +; GFX10-NEXT: s_cbranch_execz .LBB3_5 +; GFX10-NEXT: .LBB3_3: ; %loop.start +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5 +; GFX10-NEXT: s_mov_b32 s6, -1 +; GFX10-NEXT: s_mov_b32 s7, 1 +; GFX10-NEXT: v_lshlrev_b64 v[6:7], 2, v[5:6] +; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v1, v6 +; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v2, v7, vcc_lo +; GFX10-NEXT: global_load_dword v6, v[6:7], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6 +; GFX10-NEXT: s_and_saveexec_b32 s8, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB3_2 +; GFX10-NEXT: ; %bb.4: ; %loop.cond +; GFX10-NEXT: ; in Loop: Header=BB3_3 Depth=1 +; GFX10-NEXT: v_add_nc_u32_e32 v6, 1, v5 +; GFX10-NEXT: v_cmp_lt_i32_e64 s6, v5, v0 +; GFX10-NEXT: s_mov_b32 s7, 0 +; GFX10-NEXT: v_mov_b32_e32 v5, v6 +; GFX10-NEXT: s_branch .LBB3_2 +; GFX10-NEXT: .LBB3_5: ; %loop.exit.guard +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s5 +; GFX10-NEXT: s_and_b32 s5, 1, s7 +; GFX10-NEXT: v_cmp_ne_u32_e64 s6, 0, s5 +; GFX10-NEXT: .LBB3_6: ; %Flow1 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_and_saveexec_b32 s4, s6 +; GFX10-NEXT: s_cbranch_execz .LBB3_8 +; GFX10-NEXT: ; %bb.7: ; %block.after.loop +; GFX10-NEXT: v_mov_b32_e32 v0, 5 +; GFX10-NEXT: flat_store_dword v[3:4], v0 +; GFX10-NEXT: .LBB3_8: ; %exit +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_setpc_b64 s[30:31] +entry: + %start.cond = icmp eq i32 %num.elts, 0 + br i1 %start.cond, label %loop.start, label %block.after.loop + +loop.start: + %i = phi i32 [ 0, %entry ], [ %i.plus.1, %loop.cond ] + %a.plus.i = getelementptr i32, ptr addrspace(1) %a, i32 %i + %elt.i = load i32, ptr addrspace(1) %a.plus.i + %elt.i.eq.zero = icmp eq i32 %elt.i, 0 + br i1 %elt.i.eq.zero, label %exit, label %loop.cond + +loop.cond: + %cond = icmp slt i32 %i, %num.elts + %i.plus.1 = add i32 %i, 1 + br i1 %cond, label %block.after.loop, label %loop.start + +block.after.loop: + store i32 5, ptr %addr + br label %exit + +exit: + ret void +} + + +;void icmp(int num_elts, int* a, int* addr) { +;for(;;) { +; if(a[i]==0) +; return; +;} +;addr[0] = 5 +;return; +;} + +define void @divergent_i1_icmp_used_outside_loop(i32 %v0, i32 %v1, ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr %addr) { +; GFX10-LABEL: divergent_i1_icmp_used_outside_loop: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_mov_b32 s5, 0 +; GFX10-NEXT: v_mov_b32_e32 v5, s5 +; GFX10-NEXT: s_branch .LBB4_2 +; GFX10-NEXT: .LBB4_1: ; %Flow +; GFX10-NEXT: ; in Loop: Header=BB4_2 Depth=1 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s7 +; GFX10-NEXT: s_and_b32 s4, 1, s6 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s4 +; GFX10-NEXT: s_or_b32 s5, s4, s5 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s5 +; GFX10-NEXT: s_cbranch_execz .LBB4_6 +; GFX10-NEXT: .LBB4_2: ; %cond.block.0 +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_mov_b32_e32 v4, v5 +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v4 +; GFX10-NEXT: s_and_saveexec_b32 s6, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB4_4 +; GFX10-NEXT: ; %bb.3: ; %if.block.0 +; GFX10-NEXT: ; in Loop: Header=BB4_2 Depth=1 +; GFX10-NEXT: v_ashrrev_i32_e32 v5, 31, v4 +; GFX10-NEXT: v_lshlrev_b64 v[8:9], 2, v[4:5] +; GFX10-NEXT: v_add_co_u32 v8, s4, v2, v8 +; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s4, v3, v9, s4 +; GFX10-NEXT: global_store_dword v[8:9], v4, off +; GFX10-NEXT: .LBB4_4: ; %loop.break.block +; GFX10-NEXT: ; in Loop: Header=BB4_2 Depth=1 +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s6 +; GFX10-NEXT: v_cmp_ne_u32_e64 s4, v1, v4 +; GFX10-NEXT: s_mov_b32 s6, 1 +; GFX10-NEXT: ; implicit-def: $vgpr5 +; GFX10-NEXT: s_and_saveexec_b32 s7, s4 +; GFX10-NEXT: s_cbranch_execz .LBB4_1 +; GFX10-NEXT: ; %bb.5: ; %loop.cond +; GFX10-NEXT: ; in Loop: Header=BB4_2 Depth=1 +; GFX10-NEXT: v_add_nc_u32_e32 v5, 1, v4 +; GFX10-NEXT: s_mov_b32 s6, 0 +; GFX10-NEXT: s_branch .LBB4_1 +; GFX10-NEXT: .LBB4_6: ; %cond.block.1 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s5 +; GFX10-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB4_8 +; GFX10-NEXT: ; %bb.7: ; %if.block.1 +; GFX10-NEXT: global_store_dword v[6:7], v4, off +; GFX10-NEXT: .LBB4_8: ; %exit +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_setpc_b64 s[30:31] +entry: + br label %loop.start + +loop.start: + %i = phi i32 [ 0, %entry ], [ %i.plus.1, %loop.cond ] + br label %cond.block.0 + +cond.block.0: + %cond.0 = icmp eq i32 %v0, %i + br i1 %cond.0, label %if.block.0, label %loop.break.block + +if.block.0: + %a.plus.i = getelementptr i32, ptr addrspace(1) %a, i32 %i + store i32 %i, ptr addrspace(1) %a.plus.i + br label %loop.break.block + +loop.break.block: + %cond.1 = icmp eq i32 %v1, %i + br i1 %cond.1, label %cond.block.1, label %loop.cond + +loop.cond: + ; no cond, infinite loop with one break + %i.plus.1 = add i32 %i, 1 + br label %loop.start + +cond.block.1: + %cond.2 = icmp eq i32 %v0, %i + br i1 %cond.2, label %if.block.1, label %exit + +if.block.1: + store i32 %i, ptr addrspace(1) %c + br label %exit + +exit: + ret void +} + + +; bool all_eq_zero = true; +; i32 i = 0; +; do { +; if(all_eq_zero) +; all_eq_zero = (a[i] == 0); +; +; i += 1; +; } while ( i < n ) + +; *addr = all_eq_zero ? 1.0 : 0.0; + +; check that all elements in an array of size n are zero, loop has divergent +; exit condition based on array size, but zero check does not break out of the +; loop but instead skips zero check in remaining iterations +; llpc "freezes" zero check since it is (via phi) used in a conditional branch +define amdgpu_ps void @divergent_i1_freeze_used_outside_loop(i32 %n, ptr addrspace(1) %a, ptr %addr) { +; GFX10-LABEL: divergent_i1_freeze_used_outside_loop: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, 0 +; GFX10-NEXT: v_mov_b32_e32 v6, 1 +; GFX10-NEXT: v_mov_b32_e32 v5, s0 +; GFX10-NEXT: s_branch .LBB5_2 +; GFX10-NEXT: .LBB5_1: ; %loop.cond +; GFX10-NEXT: ; in Loop: Header=BB5_2 Depth=1 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX10-NEXT: v_add_nc_u32_e32 v7, 1, v5 +; GFX10-NEXT: v_cmp_lt_i32_e32 vcc_lo, v5, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s1 +; GFX10-NEXT: v_mov_b32_e32 v5, v7 +; GFX10-NEXT: s_or_b32 s0, vcc_lo, s0 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s0 +; GFX10-NEXT: s_cbranch_execz .LBB5_4 +; GFX10-NEXT: .LBB5_2: ; %loop.start +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_and_b32_e32 v6, 1, v6 +; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, v6 +; GFX10-NEXT: s_and_saveexec_b32 s2, s1 +; GFX10-NEXT: s_cbranch_execz .LBB5_1 +; GFX10-NEXT: ; %bb.3: ; %is.eq.zero +; GFX10-NEXT: ; in Loop: Header=BB5_2 Depth=1 +; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5 +; GFX10-NEXT: v_lshlrev_b64 v[6:7], 2, v[5:6] +; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v1, v6 +; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v2, v7, vcc_lo +; GFX10-NEXT: global_load_dword v6, v[6:7], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 0, v6 +; GFX10-NEXT: s_branch .LBB5_1 +; GFX10-NEXT: .LBB5_4: ; %exit +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s1 +; GFX10-NEXT: flat_store_dword v[3:4], v0 +; GFX10-NEXT: s_endpgm +entry: + br label %loop.start + +loop.start: + %i = phi i32 [ 0, %entry ], [ %i.plus.1, %loop.cond ] + %all.eq.zero = phi i1 [ true, %entry ], [ %eq.zero.fr, %loop.cond ] + br i1 %all.eq.zero, label %is.eq.zero, label %loop.cond + +is.eq.zero: + %a.plus.i = getelementptr i32, ptr addrspace(1) %a, i32 %i + %elt.i = load i32, ptr addrspace(1) %a.plus.i + %elt.i.eq.zero = icmp eq i32 %elt.i, 0 + br label %loop.cond + +loop.cond: + %eq.zero = phi i1 [ %all.eq.zero, %loop.start ], [ %elt.i.eq.zero, %is.eq.zero ] + %eq.zero.fr = freeze i1 %eq.zero + %cond = icmp slt i32 %i, %n + %i.plus.1 = add i32 %i, 1 + br i1 %cond, label %exit, label %loop.start + +exit: + %select = select i1 %eq.zero.fr, float 1.000000e+00, float 0.000000e+00 + store float %select, ptr %addr + ret void +} + +; Divergent i1 phi from structurize-cfg used outside of the loop +define amdgpu_cs void @loop_with_1break(ptr addrspace(1) %x, ptr addrspace(1) %a, ptr addrspace(1) %a.break) { +; GFX10-LABEL: loop_with_1break: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, 0 +; GFX10-NEXT: v_mov_b32_e32 v6, s0 +; GFX10-NEXT: s_branch .LBB6_2 +; GFX10-NEXT: .LBB6_1: ; %Flow +; GFX10-NEXT: ; in Loop: Header=BB6_2 Depth=1 +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX10-NEXT: s_and_b32 s1, exec_lo, s2 +; GFX10-NEXT: s_or_b32 s0, s1, s0 +; GFX10-NEXT: s_and_b32 s1, 1, s3 +; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, s1 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s0 +; GFX10-NEXT: s_cbranch_execz .LBB6_4 +; GFX10-NEXT: .LBB6_2: ; %A +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_ashrrev_i32_e32 v7, 31, v6 +; GFX10-NEXT: s_mov_b32 s2, -1 +; GFX10-NEXT: s_mov_b32 s3, 1 +; GFX10-NEXT: v_lshlrev_b64 v[7:8], 2, v[6:7] +; GFX10-NEXT: v_add_co_u32 v9, vcc_lo, v2, v7 +; GFX10-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, v3, v8, vcc_lo +; GFX10-NEXT: global_load_dword v9, v[9:10], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9 +; GFX10-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB6_1 +; GFX10-NEXT: ; %bb.3: ; %loop.body +; GFX10-NEXT: ; in Loop: Header=BB6_2 Depth=1 +; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v0, v7 +; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, v1, v8, vcc_lo +; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v6 +; GFX10-NEXT: v_cmp_gt_u32_e64 s2, 0x64, v6 +; GFX10-NEXT: s_mov_b32 s3, 0 +; GFX10-NEXT: global_load_dword v9, v[7:8], off +; GFX10-NEXT: v_mov_b32_e32 v6, v10 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v9 +; GFX10-NEXT: global_store_dword v[7:8], v9, off +; GFX10-NEXT: s_branch .LBB6_1 +; GFX10-NEXT: .LBB6_4: ; %loop.exit.guard +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX10-NEXT: s_and_saveexec_b32 s0, s1 +; GFX10-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX10-NEXT: s_cbranch_execz .LBB6_6 +; GFX10-NEXT: ; %bb.5: ; %break.body +; GFX10-NEXT: v_mov_b32_e32 v0, 10 +; GFX10-NEXT: global_store_dword v[4:5], v0, off +; GFX10-NEXT: .LBB6_6: ; %exit +; GFX10-NEXT: s_endpgm +entry: + br label %A + +A: + %counter = phi i32 [ %counter.plus.1, %loop.body ], [ 0, %entry ] + %a.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %a, i32 %counter + %a.val = load i32, ptr addrspace(1) %a.plus.counter + %a.cond = icmp eq i32 %a.val, 0 + br i1 %a.cond, label %break.body, label %loop.body + +break.body: + store i32 10, ptr addrspace(1) %a.break + br label %exit + +loop.body: + %x.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %x, i32 %counter + %x.val = load i32, ptr addrspace(1) %x.plus.counter + %x.val.plus.1 = add i32 %x.val, 1 + store i32 %x.val.plus.1, ptr addrspace(1) %x.plus.counter + %counter.plus.1 = add i32 %counter, 1 + %x.cond = icmp ult i32 %counter, 100 + br i1 %x.cond, label %exit, label %A + +exit: + ret void +} + diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir new file mode 100644 index 000000000000..92463714ec69 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir @@ -0,0 +1,914 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering %s -o - | FileCheck -check-prefix=GFX10 %s + +--- +name: divergent_i1_phi_used_outside_loop +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: divergent_i1_phi_used_outside_loop + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY1]](s32), [[C1]] + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %9(s32), %bb.1, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %11(s32), %bb.1 + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s1) = G_PHI [[FCMP]](s1), %bb.0, %13(s1), %bb.1 + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI2]], [[C2]] + ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI1]](s32) + ; GFX10-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]] + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C3]] + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[FCMP1]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[PHI2]](s1), %bb.1 + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32) + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI3]](s1), [[C5]], [[C4]] + ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32)) + ; GFX10-NEXT: SI_RETURN + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s32) = COPY $vgpr2 + %3:_(s32) = COPY $vgpr3 + %4:_(p0) = G_MERGE_VALUES %2(s32), %3(s32) + %5:_(s32) = G_CONSTANT i32 0 + %6:_(s32) = G_FCONSTANT float 1.000000e+00 + %7:_(s1) = G_FCMP floatpred(ogt), %1(s32), %6 + + bb.1: + successors: %bb.2(0x04000000), %bb.1(0x7c000000) + + %8:_(s32) = G_PHI %9(s32), %bb.1, %5(s32), %bb.0 + %10:_(s32) = G_PHI %5(s32), %bb.0, %11(s32), %bb.1 + %12:_(s1) = G_PHI %7(s1), %bb.0, %13(s1), %bb.1 + %14:_(s1) = G_CONSTANT i1 true + %13:_(s1) = G_XOR %12, %14 + %15:_(s32) = G_UITOFP %10(s32) + %16:_(s1) = G_FCMP floatpred(ogt), %15(s32), %0 + %17:_(s32) = G_CONSTANT i32 1 + %11:_(s32) = G_ADD %10, %17 + %9:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %16(s1), %8(s32) + SI_LOOP %9(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 + + bb.2: + %18:_(s1) = G_PHI %12(s1), %bb.1 + %19:_(s32) = G_PHI %9(s32), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %19(s32) + %20:_(s32) = G_FCONSTANT float 0.000000e+00 + %21:_(s32) = G_FCONSTANT float 1.000000e+00 + %22:_(s32) = G_SELECT %18(s1), %21, %20 + G_STORE %22(s32), %4(p0) :: (store (s32)) + SI_RETURN +... + +--- +name: divergent_i1_phi_used_outside_loop_larger_loop_body +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: divergent_i1_phi_used_outside_loop_larger_loop_body + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr4 + ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %9(s32), %bb.3 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(p1) = G_PHI [[MV]](p1), %bb.0, %11(p1), %bb.3 + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_PHI [[C1]](s1), %bb.0, %13(s1), %bb.3 + ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[PHI2]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.3(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PHI1]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C2]] + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[ICMP]](s1), %bb.2, [[PHI2]](s1), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32) + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 + ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[PHI1]], [[C3]](s64) + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[PHI]], [[C4]] + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[ADD]](s32), [[C5]] + ; GFX10-NEXT: G_BRCOND [[ICMP1]](s1), %bb.1 + ; GFX10-NEXT: G_BR %bb.4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s1) = G_PHI [[PHI2]](s1), %bb.3 + ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI4]](s1), [[C7]], [[C6]] + ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV1]](p0) :: (store (s32)) + ; GFX10-NEXT: SI_RETURN + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + + %0:_(s32) = COPY $vgpr1 + %1:_(s32) = COPY $vgpr2 + %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $vgpr3 + %4:_(s32) = COPY $vgpr4 + %5:_(p0) = G_MERGE_VALUES %3(s32), %4(s32) + %6:_(s32) = G_CONSTANT i32 -1 + %7:_(s1) = G_CONSTANT i1 true + + bb.1: + successors: %bb.2(0x40000000), %bb.3(0x40000000) + + %8:_(s32) = G_PHI %6(s32), %bb.0, %9(s32), %bb.3 + %10:_(p1) = G_PHI %2(p1), %bb.0, %11(p1), %bb.3 + %12:sreg_32_xm0_xexec(s1) = G_PHI %7(s1), %bb.0, %13(s1), %bb.3 + %14:sreg_32_xm0_xexec(s32) = SI_IF %12(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 + + bb.2: + successors: %bb.3(0x80000000) + + %15:_(s32) = G_LOAD %10(p1) :: (load (s32), addrspace 1) + %16:_(s32) = G_CONSTANT i32 0 + %17:_(s1) = G_ICMP intpred(eq), %15(s32), %16 + + bb.3: + successors: %bb.4(0x04000000), %bb.1(0x7c000000) + + %13:_(s1) = G_PHI %17(s1), %bb.2, %12(s1), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %14(s32) + %18:_(s64) = G_CONSTANT i64 4 + %11:_(p1) = G_PTR_ADD %10, %18(s64) + %19:_(s32) = G_CONSTANT i32 1 + %9:_(s32) = nsw G_ADD %8, %19 + %20:_(s32) = G_CONSTANT i32 10 + %21:_(s1) = G_ICMP intpred(sge), %9(s32), %20 + G_BRCOND %21(s1), %bb.1 + G_BR %bb.4 + + bb.4: + %22:_(s1) = G_PHI %12(s1), %bb.3 + %23:_(s32) = G_FCONSTANT float 0.000000e+00 + %24:_(s32) = G_FCONSTANT float 1.000000e+00 + %25:_(s32) = G_SELECT %22(s1), %24, %23 + G_STORE %25(s32), %5(p0) :: (store (s32)) + SI_RETURN +... + +--- +name: divergent_i1_xor_used_outside_loop +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: divergent_i1_xor_used_outside_loop + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY1]](s32), [[C1]] + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %9(s32), %bb.1, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %11(s32), %bb.1 + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s1) = G_PHI [[FCMP]](s1), %bb.0, %13(s1), %bb.1 + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI2]], [[C2]] + ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI1]](s32) + ; GFX10-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]] + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C3]] + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[FCMP1]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[XOR]](s1), %bb.1 + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32) + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI3]](s1), [[C5]], [[C4]] + ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32)) + ; GFX10-NEXT: SI_RETURN + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s32) = COPY $vgpr2 + %3:_(s32) = COPY $vgpr3 + %4:_(p0) = G_MERGE_VALUES %2(s32), %3(s32) + %5:_(s32) = G_CONSTANT i32 0 + %6:_(s32) = G_FCONSTANT float 1.000000e+00 + %7:_(s1) = G_FCMP floatpred(ogt), %1(s32), %6 + + bb.1: + successors: %bb.2(0x04000000), %bb.1(0x7c000000) + + %8:_(s32) = G_PHI %9(s32), %bb.1, %5(s32), %bb.0 + %10:_(s32) = G_PHI %5(s32), %bb.0, %11(s32), %bb.1 + %12:_(s1) = G_PHI %7(s1), %bb.0, %13(s1), %bb.1 + %14:_(s1) = G_CONSTANT i1 true + %13:_(s1) = G_XOR %12, %14 + %15:_(s32) = G_UITOFP %10(s32) + %16:_(s1) = G_FCMP floatpred(ogt), %15(s32), %0 + %17:_(s32) = G_CONSTANT i32 1 + %11:_(s32) = G_ADD %10, %17 + %9:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %16(s1), %8(s32) + SI_LOOP %9(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 + + bb.2: + %18:_(s1) = G_PHI %13(s1), %bb.1 + %19:_(s32) = G_PHI %9(s32), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %19(s32) + %20:_(s32) = G_FCONSTANT float 0.000000e+00 + %21:_(s32) = G_FCONSTANT float 1.000000e+00 + %22:_(s32) = G_SELECT %18(s1), %21, %20 + G_STORE %22(s32), %4(p0) :: (store (s32)) + SI_RETURN +... + +--- +name: divergent_i1_xor_used_outside_loop_larger_loop_body +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: divergent_i1_xor_used_outside_loop_larger_loop_body + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4 + ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32) + ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.1 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.3(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: G_BR %bb.3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_PHI %14(s1), %bb.8, [[C1]](s1), %bb.0 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32) + ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[PHI]](s1), %bb.6, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.5 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.7(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C2]](s32), %bb.1, %17(s32), %bb.7 + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %19(s32), %bb.7, [[C2]](s32), %bb.1 + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI2]](s32) + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C4]](s32) + ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL]](s64) + ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C5]] + ; GFX10-NEXT: [[SI_IF2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: successors: %bb.7(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s1) = G_CONSTANT i1 false + ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C7]] + ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[PHI2]](s32), [[COPY]] + ; GFX10-NEXT: G_BR %bb.7 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.5: + ; GFX10-NEXT: successors: %bb.6(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 + ; GFX10-NEXT: G_STORE [[C8]](s32), [[MV1]](p0) :: (store (s32)) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.6: + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32) + ; GFX10-NEXT: SI_RETURN + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.7: + ; GFX10-NEXT: successors: %bb.8(0x04000000), %bb.3(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[ADD]](s32), %bb.4, [[DEF]](s32), %bb.3 + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s1) = G_PHI [[C6]](s1), %bb.4, [[C3]](s1), %bb.3 + ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s1) = G_PHI [[ICMP2]](s1), %bb.4, [[C3]](s1), %bb.3 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF2]](s32) + ; GFX10-NEXT: [[C9:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI4]], [[C9]] + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI5]](s1), [[PHI1]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.8 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.8: + ; GFX10-NEXT: successors: %bb.2(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s1) = G_PHI [[XOR]](s1), %bb.7 + ; GFX10-NEXT: [[PHI7:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.7 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI7]](s32) + ; GFX10-NEXT: G_BR %bb.2 + bb.0: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s32) = COPY $vgpr2 + %3:_(p1) = G_MERGE_VALUES %1(s32), %2(s32) + %4:_(s32) = COPY $vgpr3 + %5:_(s32) = COPY $vgpr4 + %6:_(p0) = G_MERGE_VALUES %4(s32), %5(s32) + %7:_(s32) = G_IMPLICIT_DEF + %8:_(s32) = G_CONSTANT i32 0 + %9:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), %0(s32), %8 + %10:_(s1) = G_CONSTANT i1 true + %11:sreg_32_xm0_xexec(s32) = SI_IF %9(s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.1 + + bb.1: + successors: %bb.3(0x80000000) + + %12:_(s32) = G_CONSTANT i32 0 + G_BR %bb.3 + + bb.2: + successors: %bb.5(0x40000000), %bb.6(0x40000000) + + %13:sreg_32_xm0_xexec(s1) = G_PHI %14(s1), %bb.8, %10(s1), %bb.0 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %11(s32) + %15:sreg_32_xm0_xexec(s32) = SI_IF %13(s1), %bb.6, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.5 + + bb.3: + successors: %bb.4(0x40000000), %bb.7(0x40000000) + + %16:_(s32) = G_PHI %12(s32), %bb.1, %17(s32), %bb.7 + %18:_(s32) = G_PHI %19(s32), %bb.7, %12(s32), %bb.1 + %20:_(s1) = G_CONSTANT i1 true + %21:_(s64) = G_SEXT %18(s32) + %22:_(s32) = G_CONSTANT i32 2 + %23:_(s64) = G_SHL %21, %22(s32) + %24:_(p1) = G_PTR_ADD %3, %23(s64) + %25:_(s32) = G_LOAD %24(p1) :: (load (s32), addrspace 1) + %26:_(s32) = G_CONSTANT i32 0 + %27:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %25(s32), %26 + %28:sreg_32_xm0_xexec(s32) = SI_IF %27(s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.4 + + bb.4: + successors: %bb.7(0x80000000) + + %29:_(s1) = G_CONSTANT i1 false + %30:_(s32) = G_CONSTANT i32 1 + %31:_(s32) = G_ADD %18, %30 + %32:_(s1) = G_ICMP intpred(slt), %18(s32), %0 + G_BR %bb.7 + + bb.5: + successors: %bb.6(0x80000000) + + %33:_(s32) = G_CONSTANT i32 5 + G_STORE %33(s32), %6(p0) :: (store (s32)) + + bb.6: + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32) + SI_RETURN + + bb.7: + successors: %bb.8(0x04000000), %bb.3(0x7c000000) + + %19:_(s32) = G_PHI %31(s32), %bb.4, %7(s32), %bb.3 + %34:_(s1) = G_PHI %29(s1), %bb.4, %20(s1), %bb.3 + %35:_(s1) = G_PHI %32(s1), %bb.4, %20(s1), %bb.3 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %28(s32) + %36:_(s1) = G_CONSTANT i1 true + %37:_(s1) = G_XOR %34, %36 + %17:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %35(s1), %16(s32) + SI_LOOP %17(s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.8 + + bb.8: + successors: %bb.2(0x80000000) + + %14:_(s1) = G_PHI %37(s1), %bb.7 + %38:_(s32) = G_PHI %17(s32), %bb.7 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %38(s32) + G_BR %bb.2 +... + +--- +name: divergent_i1_icmp_used_outside_loop +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: divergent_i1_icmp_used_outside_loop + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) + ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr6 + ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr7 + ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %11(s32), %bb.6, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %13(s32), %bb.6 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[PHI1]] + ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.4(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32) + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C1]](s32) + ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL]](s64) + ; GFX10-NEXT: G_STORE [[PHI1]](s32), [[PTR_ADD]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32) + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[PHI1]] + ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.6, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.5 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.5: + ; GFX10-NEXT: successors: %bb.6(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 false + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C4]] + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.6: + ; GFX10-NEXT: successors: %bb.7(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ADD]](s32), %bb.5, [[DEF]](s32), %bb.4 + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C3]](s1), %bb.5, [[C2]](s1), %bb.4 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32) + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI3]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.7 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.7: + ; GFX10-NEXT: successors: %bb.8(0x40000000), %bb.9(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.6 + ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_PHI [[ICMP]](s1), %bb.6 + ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[PHI1]](s32), %bb.6 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32) + ; GFX10-NEXT: [[SI_IF2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[PHI5]](s1), %bb.9, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.8 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.8: + ; GFX10-NEXT: successors: %bb.9(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: G_STORE [[PHI6]](s32), [[MV1]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.9: + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF2]](s32) + ; GFX10-NEXT: SI_RETURN + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s32) = COPY $vgpr2 + %3:_(s32) = COPY $vgpr3 + %4:_(p1) = G_MERGE_VALUES %2(s32), %3(s32) + %5:_(s32) = COPY $vgpr6 + %6:_(s32) = COPY $vgpr7 + %7:_(p1) = G_MERGE_VALUES %5(s32), %6(s32) + %8:_(s32) = G_CONSTANT i32 0 + %9:_(s32) = G_IMPLICIT_DEF + + bb.1: + successors: %bb.2(0x80000000) + + %10:_(s32) = G_PHI %11(s32), %bb.6, %8(s32), %bb.0 + %12:_(s32) = G_PHI %8(s32), %bb.0, %13(s32), %bb.6 + + bb.2: + successors: %bb.3(0x40000000), %bb.4(0x40000000) + + %14:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), %0(s32), %12 + %15:sreg_32_xm0_xexec(s32) = SI_IF %14(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.3 + + bb.3: + successors: %bb.4(0x80000000) + + %16:_(s64) = G_SEXT %12(s32) + %17:_(s32) = G_CONSTANT i32 2 + %18:_(s64) = G_SHL %16, %17(s32) + %19:_(p1) = G_PTR_ADD %4, %18(s64) + G_STORE %12(s32), %19(p1) :: (store (s32), addrspace 1) + + bb.4: + successors: %bb.5(0x40000000), %bb.6(0x40000000) + + %20:_(s1) = G_CONSTANT i1 true + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32) + %21:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %1(s32), %12 + %22:sreg_32_xm0_xexec(s32) = SI_IF %21(s1), %bb.6, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.5 + + bb.5: + successors: %bb.6(0x80000000) + + %23:_(s1) = G_CONSTANT i1 false + %24:_(s32) = G_CONSTANT i32 1 + %25:_(s32) = G_ADD %12, %24 + + bb.6: + successors: %bb.7(0x04000000), %bb.1(0x7c000000) + + %13:_(s32) = G_PHI %25(s32), %bb.5, %9(s32), %bb.4 + %26:_(s1) = G_PHI %23(s1), %bb.5, %20(s1), %bb.4 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %22(s32) + %11:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %26(s1), %10(s32) + SI_LOOP %11(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.7 + + bb.7: + successors: %bb.8(0x40000000), %bb.9(0x40000000) + + %27:_(s32) = G_PHI %11(s32), %bb.6 + %28:sreg_32_xm0_xexec(s1) = G_PHI %14(s1), %bb.6 + %29:_(s32) = G_PHI %12(s32), %bb.6 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %27(s32) + %30:sreg_32_xm0_xexec(s32) = SI_IF %28(s1), %bb.9, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.8 + + bb.8: + successors: %bb.9(0x80000000) + + G_STORE %29(s32), %7(p1) :: (store (s32), addrspace 1) + + bb.9: + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %30(s32) + SI_RETURN +... + +--- +name: divergent_i1_freeze_used_outside_loop +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: divergent_i1_freeze_used_outside_loop + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4 + ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %10(s32), %bb.3, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %12(s32), %bb.3 + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_PHI [[C1]](s1), %bb.0, %14(s1), %bb.3 + ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[PHI2]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.3(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32) + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32) + ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL]](s64) + ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C3]] + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[ICMP]](s1), %bb.2, [[PHI2]](s1), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32) + ; GFX10-NEXT: [[FREEZE:%[0-9]+]]:_(s1) = G_FREEZE [[PHI3]] + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C4]] + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[PHI1]](s32), [[COPY]] + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[ICMP1]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s1) = G_PHI [[FREEZE]](s1), %bb.3 + ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.3 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI5]](s32) + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI4]](s1), [[C6]], [[C5]] + ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV1]](p0) :: (store (s32)) + ; GFX10-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s32) = COPY $vgpr2 + %3:_(p1) = G_MERGE_VALUES %1(s32), %2(s32) + %4:_(s32) = COPY $vgpr3 + %5:_(s32) = COPY $vgpr4 + %6:_(p0) = G_MERGE_VALUES %4(s32), %5(s32) + %7:_(s32) = G_CONSTANT i32 0 + %8:_(s1) = G_CONSTANT i1 true + + bb.1: + successors: %bb.2(0x40000000), %bb.3(0x40000000) + + %9:_(s32) = G_PHI %10(s32), %bb.3, %7(s32), %bb.0 + %11:_(s32) = G_PHI %7(s32), %bb.0, %12(s32), %bb.3 + %13:sreg_32_xm0_xexec(s1) = G_PHI %8(s1), %bb.0, %14(s1), %bb.3 + %15:sreg_32_xm0_xexec(s32) = SI_IF %13(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 + + bb.2: + successors: %bb.3(0x80000000) + + %16:_(s64) = G_SEXT %11(s32) + %17:_(s32) = G_CONSTANT i32 2 + %18:_(s64) = G_SHL %16, %17(s32) + %19:_(p1) = G_PTR_ADD %3, %18(s64) + %20:_(s32) = G_LOAD %19(p1) :: (load (s32), addrspace 1) + %21:_(s32) = G_CONSTANT i32 0 + %22:_(s1) = G_ICMP intpred(eq), %20(s32), %21 + + bb.3: + successors: %bb.4(0x04000000), %bb.1(0x7c000000) + + %23:_(s1) = G_PHI %22(s1), %bb.2, %13(s1), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32) + %14:_(s1) = G_FREEZE %23 + %24:_(s32) = G_CONSTANT i32 1 + %12:_(s32) = G_ADD %11, %24 + %25:_(s1) = G_ICMP intpred(slt), %11(s32), %0 + %10:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %25(s1), %9(s32) + SI_LOOP %10(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.4 + + bb.4: + %26:_(s1) = G_PHI %14(s1), %bb.3 + %27:_(s32) = G_PHI %10(s32), %bb.3 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %27(s32) + %28:_(s32) = G_FCONSTANT float 0.000000e+00 + %29:_(s32) = G_FCONSTANT float 1.000000e+00 + %30:_(s32) = G_SELECT %26(s1), %29, %28 + G_STORE %30(s32), %6(p0) :: (store (s32)) + S_ENDPGM 0 +... + +--- +name: loop_with_1break +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: loop_with_1break + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) + ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4 + ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5 + ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.5, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %14(s32), %bb.5 + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32) + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32) + ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64) + ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]] + ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.4(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 + ; GFX10-NEXT: G_STORE [[C4]](s32), [[MV2]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: G_BR %bb.4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.5(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 false + ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C6]](s32) + ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64) + ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C7]] + ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C7]] + ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 100 + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI1]](s32), [[C8]] + ; GFX10-NEXT: G_BR %bb.5 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32) + ; GFX10-NEXT: S_ENDPGM 0 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.5: + ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.3, [[DEF]](s32), %bb.1 + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C5]](s1), %bb.3, [[C1]](s1), %bb.1 + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s1) = G_PHI [[ICMP1]](s1), %bb.3, [[C1]](s1), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32) + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI4]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.6 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.6: + ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_PHI [[PHI3]](s1), %bb.5 + ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.5 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI6]](s32) + ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[PHI5]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $vgpr2 + %4:_(s32) = COPY $vgpr3 + %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32) + %6:_(s32) = COPY $vgpr4 + %7:_(s32) = COPY $vgpr5 + %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32) + %9:_(s32) = G_CONSTANT i32 0 + %10:_(s32) = G_IMPLICIT_DEF + + bb.1: + successors: %bb.3(0x40000000), %bb.5(0x40000000) + + %11:_(s32) = G_PHI %12(s32), %bb.5, %9(s32), %bb.0 + %13:_(s32) = G_PHI %9(s32), %bb.0, %14(s32), %bb.5 + %15:_(s1) = G_CONSTANT i1 true + %16:_(s64) = G_SEXT %13(s32) + %17:_(s32) = G_CONSTANT i32 2 + %18:_(s64) = G_SHL %16, %17(s32) + %19:_(p1) = G_PTR_ADD %5, %18(s64) + %20:_(s32) = G_LOAD %19(p1) :: (load (s32), addrspace 1) + %21:_(s32) = G_CONSTANT i32 0 + %22:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %20(s32), %21 + %23:sreg_32_xm0_xexec(s32) = SI_IF %22(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.3 + + bb.2: + successors: %bb.4(0x80000000) + + %24:_(s32) = G_CONSTANT i32 10 + G_STORE %24(s32), %8(p1) :: (store (s32), addrspace 1) + G_BR %bb.4 + + bb.3: + successors: %bb.5(0x80000000) + + %25:_(s1) = G_CONSTANT i1 false + %26:_(s32) = G_CONSTANT i32 2 + %27:_(s64) = G_SHL %16, %26(s32) + %28:_(p1) = G_PTR_ADD %2, %27(s64) + %29:_(s32) = G_LOAD %28(p1) :: (load (s32), addrspace 1) + %30:_(s32) = G_CONSTANT i32 1 + %31:_(s32) = G_ADD %29, %30 + G_STORE %31(s32), %28(p1) :: (store (s32), addrspace 1) + %32:_(s32) = G_ADD %13, %30 + %33:_(s32) = G_CONSTANT i32 100 + %34:_(s1) = G_ICMP intpred(ult), %13(s32), %33 + G_BR %bb.5 + + bb.4: + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32) + S_ENDPGM 0 + + bb.5: + successors: %bb.6(0x04000000), %bb.1(0x7c000000) + + %14:_(s32) = G_PHI %32(s32), %bb.3, %10(s32), %bb.1 + %36:_(s1) = G_PHI %25(s1), %bb.3, %15(s1), %bb.1 + %37:_(s1) = G_PHI %34(s1), %bb.3, %15(s1), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %23(s32) + %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %37(s1), %11(s32) + SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.6 + + bb.6: + successors: %bb.2(0x40000000), %bb.4(0x40000000) + + %38:sreg_32_xm0_xexec(s1) = G_PHI %36(s1), %bb.5 + %39:_(s32) = G_PHI %12(s32), %bb.5 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %39(s32) + %35:sreg_32_xm0_xexec(s32) = SI_IF %38(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll new file mode 100644 index 000000000000..afd271c99577 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll @@ -0,0 +1,461 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -amdgpu-global-isel-risky-select -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s + +; Simples case, if - then, that requires lane mask merging, +; %phi lane mask will hold %val_A at %A. Lanes that are active in %B +; will overwrite its own lane bit in lane mask with val_B +define amdgpu_ps void @divergent_i1_phi_if_then(ptr addrspace(1) %out, i32 %tid, i32 %cond) { +; GFX10-LABEL: divergent_i1_phi_if_then: +; GFX10: ; %bb.0: ; %A +; GFX10-NEXT: v_cmp_le_u32_e64 s0, 6, v2 +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v3 +; GFX10-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX10-NEXT: ; %bb.1: ; %B +; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 1, v2 +; GFX10-NEXT: ; %bb.2: ; %exit +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 2, 1, s0 +; GFX10-NEXT: global_store_dword v[0:1], v2, off +; GFX10-NEXT: s_endpgm +A: + %val_A = icmp uge i32 %tid, 6 + %cmp = icmp eq i32 %cond, 0 + br i1 %cmp, label %B, label %exit + +B: + %val_B = icmp ult i32 %tid, 1 + br label %exit + +exit: + %phi = phi i1 [ %val_A, %A ], [ %val_B, %B ] + %sel = select i1 %phi, i32 1, i32 2 + store i32 %sel, ptr addrspace(1) %out + ret void +} + +; if - else +define amdgpu_ps void @divergent_i1_phi_if_else(ptr addrspace(1) %out, i32 %tid, i32 %cond) { +; GFX10-LABEL: divergent_i1_phi_if_else: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_and_b32 s0, 1, s0 +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v3 +; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 +; GFX10-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX10-NEXT: s_xor_b32 s1, exec_lo, s1 +; GFX10-NEXT: ; %bb.1: ; %B +; GFX10-NEXT: v_cmp_gt_u32_e64 s0, 2, v2 +; GFX10-NEXT: ; implicit-def: $vgpr2 +; GFX10-NEXT: ; %bb.2: ; %Flow +; GFX10-NEXT: s_andn2_saveexec_b32 s1, s1 +; GFX10-NEXT: ; %bb.3: ; %A +; GFX10-NEXT: v_cmp_le_u32_e64 s0, 1, v2 +; GFX10-NEXT: ; %bb.4: ; %exit +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX10-NEXT: v_cndmask_b32_e64 v2, 2, 1, s0 +; GFX10-NEXT: global_store_dword v[0:1], v2, off +; GFX10-NEXT: s_endpgm +entry: + %cmp = icmp eq i32 %cond, 0 + br i1 %cmp, label %A, label %B + +A: + %val_A = icmp uge i32 %tid, 1 + br label %exit + +B: + %val_B = icmp ult i32 %tid, 2 + br label %exit + +exit: + %phi = phi i1 [ %val_A, %A ], [ %val_B, %B ] + %sel = select i1 %phi, i32 1, i32 2 + store i32 %sel, ptr addrspace(1) %out + ret void +} + +; if - break; + +; counter = 0; +; do { +; if (a[counter] == 0) +; break; +; if (b[counter] == 0) +; break; +; if (c[counter] == 0) +; break; +; x[counter++]+=1; +; } while (counter<100); + +; Tests with multiple break conditions. Divergent phis will be used to track +; if any of the break conditions was reached. We only need to do simple lane +; mask merging (for current loop iteration only). There is an intrinsic, +; if_break, that will merge lane masks across all iterations of the loop. + +define amdgpu_cs void @loop_with_1break(ptr addrspace(1) %x, ptr addrspace(1) %a) { +; GFX10-LABEL: loop_with_1break: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, 0 +; GFX10-NEXT: v_mov_b32_e32 v4, s0 +; GFX10-NEXT: s_branch .LBB2_2 +; GFX10-NEXT: .LBB2_1: ; %Flow +; GFX10-NEXT: ; in Loop: Header=BB2_2 Depth=1 +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX10-NEXT: s_and_b32 s1, exec_lo, s2 +; GFX10-NEXT: s_or_b32 s0, s1, s0 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s0 +; GFX10-NEXT: s_cbranch_execz .LBB2_4 +; GFX10-NEXT: .LBB2_2: ; %A +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_ashrrev_i32_e32 v5, 31, v4 +; GFX10-NEXT: s_mov_b32 s2, -1 +; GFX10-NEXT: v_lshlrev_b64 v[5:6], 2, v[4:5] +; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v2, v5 +; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, v3, v6, vcc_lo +; GFX10-NEXT: global_load_dword v7, v[7:8], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v7 +; GFX10-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB2_1 +; GFX10-NEXT: ; %bb.3: ; %loop.body +; GFX10-NEXT: ; in Loop: Header=BB2_2 Depth=1 +; GFX10-NEXT: v_add_co_u32 v5, vcc_lo, v0, v5 +; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, v1, v6, vcc_lo +; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v4 +; GFX10-NEXT: v_cmp_gt_u32_e64 s2, 0x64, v4 +; GFX10-NEXT: global_load_dword v7, v[5:6], off +; GFX10-NEXT: v_mov_b32_e32 v4, v8 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_add_nc_u32_e32 v7, 1, v7 +; GFX10-NEXT: global_store_dword v[5:6], v7, off +; GFX10-NEXT: s_branch .LBB2_1 +; GFX10-NEXT: .LBB2_4: ; %exit +; GFX10-NEXT: s_endpgm +entry: + br label %A + +A: + %counter = phi i32 [ %counter.plus.1, %loop.body ], [ 0, %entry ] + %a.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %a, i32 %counter + %a.val = load i32, ptr addrspace(1) %a.plus.counter + %a.cond = icmp eq i32 %a.val, 0 + br i1 %a.cond, label %exit, label %loop.body + +loop.body: + %x.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %x, i32 %counter + %x.val = load i32, ptr addrspace(1) %x.plus.counter + %x.val.plus.1 = add i32 %x.val, 1 + store i32 %x.val.plus.1, ptr addrspace(1) %x.plus.counter + %counter.plus.1 = add i32 %counter, 1 + %x.cond = icmp ult i32 %counter, 100 + br i1 %x.cond, label %exit, label %A + +exit: + ret void +} + +define amdgpu_cs void @loop_with_2breaks(ptr addrspace(1) %x, ptr addrspace(1) %a, ptr addrspace(1) %b) { +; GFX10-LABEL: loop_with_2breaks: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, 0 +; GFX10-NEXT: v_mov_b32_e32 v6, s0 +; GFX10-NEXT: s_branch .LBB3_3 +; GFX10-NEXT: .LBB3_1: ; %Flow3 +; GFX10-NEXT: ; in Loop: Header=BB3_3 Depth=1 +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s3 +; GFX10-NEXT: .LBB3_2: ; %Flow +; GFX10-NEXT: ; in Loop: Header=BB3_3 Depth=1 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX10-NEXT: s_and_b32 s1, exec_lo, s2 +; GFX10-NEXT: s_or_b32 s0, s1, s0 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s0 +; GFX10-NEXT: s_cbranch_execz .LBB3_6 +; GFX10-NEXT: .LBB3_3: ; %A +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_ashrrev_i32_e32 v7, 31, v6 +; GFX10-NEXT: s_mov_b32 s2, -1 +; GFX10-NEXT: v_lshlrev_b64 v[7:8], 2, v[6:7] +; GFX10-NEXT: v_add_co_u32 v9, vcc_lo, v2, v7 +; GFX10-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, v3, v8, vcc_lo +; GFX10-NEXT: global_load_dword v9, v[9:10], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9 +; GFX10-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB3_2 +; GFX10-NEXT: ; %bb.4: ; %B +; GFX10-NEXT: ; in Loop: Header=BB3_3 Depth=1 +; GFX10-NEXT: v_add_co_u32 v9, vcc_lo, v4, v7 +; GFX10-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, v5, v8, vcc_lo +; GFX10-NEXT: global_load_dword v9, v[9:10], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9 +; GFX10-NEXT: s_and_saveexec_b32 s3, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB3_1 +; GFX10-NEXT: ; %bb.5: ; %loop.body +; GFX10-NEXT: ; in Loop: Header=BB3_3 Depth=1 +; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v0, v7 +; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, v1, v8, vcc_lo +; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v6 +; GFX10-NEXT: v_cmp_gt_u32_e64 s2, 0x64, v6 +; GFX10-NEXT: global_load_dword v9, v[7:8], off +; GFX10-NEXT: v_mov_b32_e32 v6, v10 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v9 +; GFX10-NEXT: global_store_dword v[7:8], v9, off +; GFX10-NEXT: s_branch .LBB3_1 +; GFX10-NEXT: .LBB3_6: ; %exit +; GFX10-NEXT: s_endpgm +entry: + br label %A + +A: + %counter = phi i32 [ %counter.plus.1, %loop.body ], [ 0, %entry ] + %a.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %a, i32 %counter + %a.val = load i32, ptr addrspace(1) %a.plus.counter + %a.cond = icmp eq i32 %a.val, 0 + br i1 %a.cond, label %exit, label %B + +B: + %b.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %b, i32 %counter + %b.val = load i32, ptr addrspace(1) %b.plus.counter + %b.cond = icmp eq i32 %b.val, 0 + br i1 %b.cond, label %exit, label %loop.body + +loop.body: + %x.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %x, i32 %counter + %x.val = load i32, ptr addrspace(1) %x.plus.counter + %x.val.plus.1 = add i32 %x.val, 1 + store i32 %x.val.plus.1, ptr addrspace(1) %x.plus.counter + %counter.plus.1 = add i32 %counter, 1 + %x.cond = icmp ult i32 %counter, 100 + br i1 %x.cond, label %exit, label %A + +exit: + ret void +} + +define amdgpu_cs void @loop_with_3breaks(ptr addrspace(1) %x, ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c) { +; GFX10-LABEL: loop_with_3breaks: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, 0 +; GFX10-NEXT: v_mov_b32_e32 v8, s0 +; GFX10-NEXT: s_branch .LBB4_4 +; GFX10-NEXT: .LBB4_1: ; %Flow5 +; GFX10-NEXT: ; in Loop: Header=BB4_4 Depth=1 +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: .LBB4_2: ; %Flow4 +; GFX10-NEXT: ; in Loop: Header=BB4_4 Depth=1 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s3 +; GFX10-NEXT: .LBB4_3: ; %Flow +; GFX10-NEXT: ; in Loop: Header=BB4_4 Depth=1 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX10-NEXT: s_and_b32 s1, exec_lo, s2 +; GFX10-NEXT: s_or_b32 s0, s1, s0 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s0 +; GFX10-NEXT: s_cbranch_execz .LBB4_8 +; GFX10-NEXT: .LBB4_4: ; %A +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_ashrrev_i32_e32 v9, 31, v8 +; GFX10-NEXT: s_mov_b32 s2, -1 +; GFX10-NEXT: v_lshlrev_b64 v[9:10], 2, v[8:9] +; GFX10-NEXT: v_add_co_u32 v11, vcc_lo, v2, v9 +; GFX10-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, v3, v10, vcc_lo +; GFX10-NEXT: global_load_dword v11, v[11:12], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11 +; GFX10-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB4_3 +; GFX10-NEXT: ; %bb.5: ; %B +; GFX10-NEXT: ; in Loop: Header=BB4_4 Depth=1 +; GFX10-NEXT: v_add_co_u32 v11, vcc_lo, v4, v9 +; GFX10-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, v5, v10, vcc_lo +; GFX10-NEXT: global_load_dword v11, v[11:12], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11 +; GFX10-NEXT: s_and_saveexec_b32 s3, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB4_2 +; GFX10-NEXT: ; %bb.6: ; %C +; GFX10-NEXT: ; in Loop: Header=BB4_4 Depth=1 +; GFX10-NEXT: v_add_co_u32 v11, vcc_lo, v6, v9 +; GFX10-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, v7, v10, vcc_lo +; GFX10-NEXT: global_load_dword v11, v[11:12], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11 +; GFX10-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB4_1 +; GFX10-NEXT: ; %bb.7: ; %loop.body +; GFX10-NEXT: ; in Loop: Header=BB4_4 Depth=1 +; GFX10-NEXT: v_add_co_u32 v9, vcc_lo, v0, v9 +; GFX10-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, v1, v10, vcc_lo +; GFX10-NEXT: v_add_nc_u32_e32 v12, 1, v8 +; GFX10-NEXT: v_cmp_gt_u32_e64 s2, 0x64, v8 +; GFX10-NEXT: global_load_dword v11, v[9:10], off +; GFX10-NEXT: v_mov_b32_e32 v8, v12 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_add_nc_u32_e32 v11, 1, v11 +; GFX10-NEXT: global_store_dword v[9:10], v11, off +; GFX10-NEXT: s_branch .LBB4_1 +; GFX10-NEXT: .LBB4_8: ; %exit +; GFX10-NEXT: s_endpgm +entry: + br label %A + +A: + %counter = phi i32 [ %counter.plus.1, %loop.body ], [ 0, %entry ] + %a.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %a, i32 %counter + %a.val = load i32, ptr addrspace(1) %a.plus.counter + %a.cond = icmp eq i32 %a.val, 0 + br i1 %a.cond, label %exit, label %B + +B: + %b.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %b, i32 %counter + %b.val = load i32, ptr addrspace(1) %b.plus.counter + %b.cond = icmp eq i32 %b.val, 0 + br i1 %b.cond, label %exit, label %C + +C: + %c.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %c, i32 %counter + %c.val = load i32, ptr addrspace(1) %c.plus.counter + %c.cond = icmp eq i32 %c.val, 0 + br i1 %c.cond, label %exit, label %loop.body + +loop.body: + %x.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %x, i32 %counter + %x.val = load i32, ptr addrspace(1) %x.plus.counter + %x.val.plus.1 = add i32 %x.val, 1 + store i32 %x.val.plus.1, ptr addrspace(1) %x.plus.counter + %counter.plus.1 = add i32 %counter, 1 + %x.cond = icmp ult i32 %counter, 100 + br i1 %x.cond, label %exit, label %A + +exit: + ret void +} + +; Divergent condition if with body, ending with break. This is loop with two +; exits but structurizer will create phi that will track exit from break +; and move break.body after the loop. Loop will then have one exit and phi +; used outside of the loop by condition used to enter the break.body. +define amdgpu_cs void @loop_with_div_break_with_body(ptr addrspace(1) %x, ptr addrspace(1) %a, ptr addrspace(1) %a.break) { +; GFX10-LABEL: loop_with_div_break_with_body: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, 0 +; GFX10-NEXT: v_mov_b32_e32 v6, s0 +; GFX10-NEXT: s_branch .LBB5_2 +; GFX10-NEXT: .LBB5_1: ; %Flow +; GFX10-NEXT: ; in Loop: Header=BB5_2 Depth=1 +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX10-NEXT: s_and_b32 s1, exec_lo, s2 +; GFX10-NEXT: s_or_b32 s0, s1, s0 +; GFX10-NEXT: s_and_b32 s1, 1, s3 +; GFX10-NEXT: v_cmp_ne_u32_e64 s1, 0, s1 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s0 +; GFX10-NEXT: s_cbranch_execz .LBB5_4 +; GFX10-NEXT: .LBB5_2: ; %A +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_ashrrev_i32_e32 v7, 31, v6 +; GFX10-NEXT: s_mov_b32 s2, -1 +; GFX10-NEXT: s_mov_b32 s3, 1 +; GFX10-NEXT: v_lshlrev_b64 v[7:8], 2, v[6:7] +; GFX10-NEXT: v_add_co_u32 v9, vcc_lo, v2, v7 +; GFX10-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, v3, v8, vcc_lo +; GFX10-NEXT: global_load_dword v9, v[9:10], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9 +; GFX10-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB5_1 +; GFX10-NEXT: ; %bb.3: ; %loop.body +; GFX10-NEXT: ; in Loop: Header=BB5_2 Depth=1 +; GFX10-NEXT: v_add_co_u32 v7, vcc_lo, v0, v7 +; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, v1, v8, vcc_lo +; GFX10-NEXT: v_add_nc_u32_e32 v10, 1, v6 +; GFX10-NEXT: v_cmp_gt_u32_e64 s2, 0x64, v6 +; GFX10-NEXT: s_mov_b32 s3, 0 +; GFX10-NEXT: global_load_dword v9, v[7:8], off +; GFX10-NEXT: v_mov_b32_e32 v6, v10 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v9 +; GFX10-NEXT: global_store_dword v[7:8], v9, off +; GFX10-NEXT: s_branch .LBB5_1 +; GFX10-NEXT: .LBB5_4: ; %loop.exit.guard +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX10-NEXT: s_and_saveexec_b32 s0, s1 +; GFX10-NEXT: s_xor_b32 s0, exec_lo, s0 +; GFX10-NEXT: s_cbranch_execz .LBB5_6 +; GFX10-NEXT: ; %bb.5: ; %break.body +; GFX10-NEXT: v_mov_b32_e32 v0, 10 +; GFX10-NEXT: global_store_dword v[4:5], v0, off +; GFX10-NEXT: .LBB5_6: ; %exit +; GFX10-NEXT: s_endpgm +entry: + br label %A + +A: + %counter = phi i32 [ %counter.plus.1, %loop.body ], [ 0, %entry ] + %a.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %a, i32 %counter + %a.val = load i32, ptr addrspace(1) %a.plus.counter + %a.cond = icmp eq i32 %a.val, 0 + br i1 %a.cond, label %break.body, label %loop.body + +break.body: + store i32 10, ptr addrspace(1) %a.break + br label %exit + + +loop.body: + %x.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %x, i32 %counter + %x.val = load i32, ptr addrspace(1) %x.plus.counter + %x.val.plus.1 = add i32 %x.val, 1 + store i32 %x.val.plus.1, ptr addrspace(1) %x.plus.counter + %counter.plus.1 = add i32 %counter, 1 + %x.cond = icmp ult i32 %counter, 100 + br i1 %x.cond, label %exit, label %A + +exit: + ret void +} + +; Snippet from test generated by the GraphicsFuzz tool, frontend generates ir +; with irreducible control flow graph. FixIrreducible converts it into natural +; loop and in the process creates i1 phi with three incoming values. + +; int loop(int x, int y, int a0, int a1, int a2, int a3, int a4) { +; do { +; if (y < a2) { +; do { +; } while (x < a2); +; } +; if (x < a3) { +; return a1; +; } +; } while (y < a2); +; return a0; +; } + +; This test is also interesting because it has phi with three incomings +;define amdgpu_ps i32 @irreducible_cfg(i32 %x, i32 %y, i32 %a0, i32 %a1, i32 %a2, i32 %a3) { +;.entry: +; %.y_lt_a2 = icmp sgt i32 %a2, %y +; %.x_lt_a2 = icmp sgt i32 %a2, %x +; %.x_lt_a3 = icmp sgt i32 %a3, %x +; br i1 %.y_lt_a2, label %.preheader, label %.loopexit ; first iteration, jump to inner loop if 'y < a2' or start with 'if (x < a3)' +; +;.preheader: ; if (y < a2), +; br label %.inner_loop +; +;.inner_loop: ; do while x < a2 +; br i1 %.x_lt_a2, label %.inner_loop, label %.loopexit +; +;.loopexit: ; if x < a3 +; %not.inner_loop = xor i1 %.y_lt_a2, true +; %brmerge = select i1 %.x_lt_a3, i1 true, i1 %not.inner_loop ; exit loop if 'x < a3' or 'loop ends since !(y < a2)' +; %.ret = select i1 %.x_lt_a3, i32 %a1, i32 %a0 ; select retrun value a1 'x < a3' or a0 'loop ends' +; br i1 %brmerge, label %.exit, label %.preheader +; +;.exit: +; ret i32 %.ret +;} + diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir new file mode 100644 index 000000000000..9461d558684e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir @@ -0,0 +1,1004 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering %s -o - | FileCheck -check-prefix=GFX10 %s + +--- +name: divergent_i1_phi_if_then +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: divergent_i1_phi_if_then + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C]] + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C1]] + ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.1 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C2]] + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32) + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI]](s1), [[C4]], [[C3]] + ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $vgpr2 + %4:_(s32) = COPY $vgpr3 + %5:_(s32) = G_CONSTANT i32 6 + %6:_(s1) = G_ICMP intpred(uge), %3(s32), %5 + %7:_(s32) = G_CONSTANT i32 0 + %8:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), %4(s32), %7 + %9:sreg_32_xm0_xexec(s32) = SI_IF %8(s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.1 + + bb.1: + successors: %bb.2(0x80000000) + + %10:_(s32) = G_CONSTANT i32 1 + %11:_(s1) = G_ICMP intpred(ult), %3(s32), %10 + + bb.2: + %12:_(s1) = G_PHI %6(s1), %bb.0, %11(s1), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %9(s32) + %13:_(s32) = G_CONSTANT i32 2 + %14:_(s32) = G_CONSTANT i32 1 + %15:_(s32) = G_SELECT %12(s1), %14, %13 + G_STORE %15(s32), %2(p1) :: (store (s32), addrspace 1) + S_ENDPGM 0 +... + +--- +name: divergent_i1_phi_if_else +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: divergent_i1_phi_if_else + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[COPY3]](s32), [[C]] + ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s1) = G_PHI %10(s1), %bb.3, [[DEF]](s1), %bb.0 + ; GFX10-NEXT: [[SI_ELSE:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_ELSE [[SI_IF]](s32), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.4(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C1]] + ; GFX10-NEXT: G_BR %bb.4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C2]] + ; GFX10-NEXT: G_BR %bb.1 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s1) = G_PHI [[PHI]](s1), %bb.1, [[ICMP1]](s1), %bb.2 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_ELSE]](s32) + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI1]](s1), [[C3]], [[C4]] + ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.3(0x40000000), %bb.1(0x40000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $vgpr2 + %4:_(s32) = COPY $vgpr3 + %5:_(s1) = G_IMPLICIT_DEF + %6:_(s32) = G_CONSTANT i32 0 + %7:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %4(s32), %6 + %8:sreg_32_xm0_xexec(s32) = SI_IF %7(s1), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.3 + + bb.1: + successors: %bb.2(0x40000000), %bb.4(0x40000000) + + %9:_(s1) = G_PHI %10(s1), %bb.3, %5(s1), %bb.0 + %11:sreg_32_xm0_xexec(s32) = SI_ELSE %8(s32), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 + + bb.2: + successors: %bb.4(0x80000000) + + %12:_(s32) = G_CONSTANT i32 1 + %13:_(s1) = G_ICMP intpred(uge), %3(s32), %12 + G_BR %bb.4 + + bb.3: + successors: %bb.1(0x80000000) + + %14:_(s32) = G_CONSTANT i32 2 + %10:_(s1) = G_ICMP intpred(ult), %3(s32), %14 + G_BR %bb.1 + + bb.4: + %15:_(s1) = G_PHI %9(s1), %bb.1, %13(s1), %bb.2 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %11(s32) + %16:_(s32) = G_CONSTANT i32 1 + %17:_(s32) = G_CONSTANT i32 2 + %18:_(s32) = G_SELECT %15(s1), %16, %17 + G_STORE %18(s32), %2(p1) :: (store (s32), addrspace 1) + S_ENDPGM 0 +... + +--- +name: loop_with_1break +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: loop_with_1break + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %9(s32), %bb.3, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %11(s32), %bb.3 + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32) + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32) + ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64) + ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]] + ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.3(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C4]](s32) + ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64) + ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C5]] + ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C5]] + ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 100 + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI1]](s32), [[C6]] + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.2, [[DEF]](s32), %bb.1 + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[ICMP1]](s1), %bb.2, [[C1]](s1), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32) + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI3]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.3 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32) + ; GFX10-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $vgpr2 + %4:_(s32) = COPY $vgpr3 + %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32) + %6:_(s32) = G_CONSTANT i32 0 + %7:_(s32) = G_IMPLICIT_DEF + + bb.1: + successors: %bb.2(0x40000000), %bb.3(0x40000000) + + %8:_(s32) = G_PHI %9(s32), %bb.3, %6(s32), %bb.0 + %10:_(s32) = G_PHI %6(s32), %bb.0, %11(s32), %bb.3 + %12:_(s1) = G_CONSTANT i1 true + %13:_(s64) = G_SEXT %10(s32) + %14:_(s32) = G_CONSTANT i32 2 + %15:_(s64) = G_SHL %13, %14(s32) + %16:_(p1) = G_PTR_ADD %5, %15(s64) + %17:_(s32) = G_LOAD %16(p1) :: (load (s32), addrspace 1) + %18:_(s32) = G_CONSTANT i32 0 + %19:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %17(s32), %18 + %20:sreg_32_xm0_xexec(s32) = SI_IF %19(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 + + bb.2: + successors: %bb.3(0x80000000) + + %21:_(s32) = G_CONSTANT i32 2 + %22:_(s64) = G_SHL %13, %21(s32) + %23:_(p1) = G_PTR_ADD %2, %22(s64) + %24:_(s32) = G_LOAD %23(p1) :: (load (s32), addrspace 1) + %25:_(s32) = G_CONSTANT i32 1 + %26:_(s32) = G_ADD %24, %25 + G_STORE %26(s32), %23(p1) :: (store (s32), addrspace 1) + %27:_(s32) = G_ADD %10, %25 + %28:_(s32) = G_CONSTANT i32 100 + %29:_(s1) = G_ICMP intpred(ult), %10(s32), %28 + + bb.3: + successors: %bb.4(0x04000000), %bb.1(0x7c000000) + + %11:_(s32) = G_PHI %27(s32), %bb.2, %7(s32), %bb.1 + %30:_(s1) = G_PHI %29(s1), %bb.2, %12(s1), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %20(s32) + %9:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %30(s1), %8(s32) + SI_LOOP %9(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.4 + + bb.4: + %31:_(s32) = G_PHI %9(s32), %bb.3 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %31(s32) + S_ENDPGM 0 +... + +--- +name: loop_with_2breaks +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: loop_with_2breaks + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) + ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4 + ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5 + ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.3, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %14(s32), %bb.3 + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32) + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32) + ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64) + ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]] + ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C5]](s32) + ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV2]], [[SHL1]](s64) + ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD1]](s32), [[C6]] + ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %32(s32), %bb.5, [[DEF]](s32), %bb.1 + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI %34(s1), %bb.5, [[C1]](s1), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32) + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI3]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.6 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: successors: %bb.5(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C7]](s32) + ; GFX10-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL2]](s64) + ; GFX10-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[C8]] + ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD2]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C8]] + ; GFX10-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 100 + ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI1]](s32), [[C9]] + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.5: + ; GFX10-NEXT: successors: %bb.3(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.4, [[DEF]](s32), %bb.2 + ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s1) = G_PHI [[ICMP2]](s1), %bb.4, [[C4]](s1), %bb.2 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32) + ; GFX10-NEXT: G_BR %bb.3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.6: + ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.3 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI6]](s32) + ; GFX10-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $vgpr2 + %4:_(s32) = COPY $vgpr3 + %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32) + %6:_(s32) = COPY $vgpr4 + %7:_(s32) = COPY $vgpr5 + %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32) + %9:_(s32) = G_CONSTANT i32 0 + %10:_(s32) = G_IMPLICIT_DEF + + bb.1: + successors: %bb.2(0x40000000), %bb.3(0x40000000) + + %11:_(s32) = G_PHI %12(s32), %bb.3, %9(s32), %bb.0 + %13:_(s32) = G_PHI %9(s32), %bb.0, %14(s32), %bb.3 + %15:_(s1) = G_CONSTANT i1 true + %16:_(s64) = G_SEXT %13(s32) + %17:_(s32) = G_CONSTANT i32 2 + %18:_(s64) = G_SHL %16, %17(s32) + %19:_(p1) = G_PTR_ADD %5, %18(s64) + %20:_(s32) = G_LOAD %19(p1) :: (load (s32), addrspace 1) + %21:_(s32) = G_CONSTANT i32 0 + %22:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %20(s32), %21 + %23:sreg_32_xm0_xexec(s32) = SI_IF %22(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 + + bb.2: + successors: %bb.4(0x40000000), %bb.5(0x40000000) + + %24:_(s1) = G_CONSTANT i1 true + %25:_(s32) = G_CONSTANT i32 2 + %26:_(s64) = G_SHL %16, %25(s32) + %27:_(p1) = G_PTR_ADD %8, %26(s64) + %28:_(s32) = G_LOAD %27(p1) :: (load (s32), addrspace 1) + %29:_(s32) = G_CONSTANT i32 0 + %30:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %28(s32), %29 + %31:sreg_32_xm0_xexec(s32) = SI_IF %30(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.4 + + bb.3: + successors: %bb.6(0x04000000), %bb.1(0x7c000000) + + %14:_(s32) = G_PHI %32(s32), %bb.5, %10(s32), %bb.1 + %33:_(s1) = G_PHI %34(s1), %bb.5, %15(s1), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %23(s32) + %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %33(s1), %11(s32) + SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.6 + + bb.4: + successors: %bb.5(0x80000000) + + %35:_(s32) = G_CONSTANT i32 2 + %36:_(s64) = G_SHL %16, %35(s32) + %37:_(p1) = G_PTR_ADD %2, %36(s64) + %38:_(s32) = G_LOAD %37(p1) :: (load (s32), addrspace 1) + %39:_(s32) = G_CONSTANT i32 1 + %40:_(s32) = G_ADD %38, %39 + G_STORE %40(s32), %37(p1) :: (store (s32), addrspace 1) + %41:_(s32) = G_ADD %13, %39 + %42:_(s32) = G_CONSTANT i32 100 + %43:_(s1) = G_ICMP intpred(ult), %13(s32), %42 + + bb.5: + successors: %bb.3(0x80000000) + + %32:_(s32) = G_PHI %41(s32), %bb.4, %10(s32), %bb.2 + %34:_(s1) = G_PHI %43(s1), %bb.4, %24(s1), %bb.2 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %31(s32) + G_BR %bb.3 + + bb.6: + %44:_(s32) = G_PHI %12(s32), %bb.3 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %44(s32) + S_ENDPGM 0 +... + +--- +name: loop_with_3breaks +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: loop_with_3breaks + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) + ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4 + ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5 + ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32) + ; GFX10-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6 + ; GFX10-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7 + ; GFX10-NEXT: [[MV3:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %15(s32), %bb.3, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %17(s32), %bb.3 + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32) + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32) + ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64) + ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]] + ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C5]](s32) + ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV2]], [[SHL1]](s64) + ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD1]](s32), [[C6]] + ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP1]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.8(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %35(s32), %bb.5, [[DEF]](s32), %bb.1 + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI %37(s1), %bb.5, [[C1]](s1), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32) + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI3]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.8 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: successors: %bb.6(0x40000000), %bb.7(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C8]](s32) + ; GFX10-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV3]], [[SHL2]](s64) + ; GFX10-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD2]](s32), [[C9]] + ; GFX10-NEXT: [[SI_IF2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP2]](s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.6 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.5: + ; GFX10-NEXT: successors: %bb.3(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI %46(s32), %bb.7, [[DEF]](s32), %bb.2 + ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s1) = G_PHI %47(s1), %bb.7, [[C4]](s1), %bb.2 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF1]](s32) + ; GFX10-NEXT: G_BR %bb.3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.6: + ; GFX10-NEXT: successors: %bb.7(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C10]](s32) + ; GFX10-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL3]](s64) + ; GFX10-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[C11]] + ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD3]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C11]] + ; GFX10-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 100 + ; GFX10-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI1]](s32), [[C12]] + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.7: + ; GFX10-NEXT: successors: %bb.5(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.6, [[DEF]](s32), %bb.4 + ; GFX10-NEXT: [[PHI7:%[0-9]+]]:_(s1) = G_PHI [[ICMP3]](s1), %bb.6, [[C7]](s1), %bb.4 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF2]](s32) + ; GFX10-NEXT: G_BR %bb.5 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.8: + ; GFX10-NEXT: [[PHI8:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.3 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI8]](s32) + ; GFX10-NEXT: S_ENDPGM 0 + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $vgpr2 + %4:_(s32) = COPY $vgpr3 + %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32) + %6:_(s32) = COPY $vgpr4 + %7:_(s32) = COPY $vgpr5 + %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32) + %9:_(s32) = COPY $vgpr6 + %10:_(s32) = COPY $vgpr7 + %11:_(p1) = G_MERGE_VALUES %9(s32), %10(s32) + %12:_(s32) = G_CONSTANT i32 0 + %13:_(s32) = G_IMPLICIT_DEF + + bb.1: + successors: %bb.2(0x40000000), %bb.3(0x40000000) + + %14:_(s32) = G_PHI %15(s32), %bb.3, %12(s32), %bb.0 + %16:_(s32) = G_PHI %12(s32), %bb.0, %17(s32), %bb.3 + %18:_(s1) = G_CONSTANT i1 true + %19:_(s64) = G_SEXT %16(s32) + %20:_(s32) = G_CONSTANT i32 2 + %21:_(s64) = G_SHL %19, %20(s32) + %22:_(p1) = G_PTR_ADD %5, %21(s64) + %23:_(s32) = G_LOAD %22(p1) :: (load (s32), addrspace 1) + %24:_(s32) = G_CONSTANT i32 0 + %25:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %23(s32), %24 + %26:sreg_32_xm0_xexec(s32) = SI_IF %25(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 + + bb.2: + successors: %bb.4(0x40000000), %bb.5(0x40000000) + + %27:_(s1) = G_CONSTANT i1 true + %28:_(s32) = G_CONSTANT i32 2 + %29:_(s64) = G_SHL %19, %28(s32) + %30:_(p1) = G_PTR_ADD %8, %29(s64) + %31:_(s32) = G_LOAD %30(p1) :: (load (s32), addrspace 1) + %32:_(s32) = G_CONSTANT i32 0 + %33:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %31(s32), %32 + %34:sreg_32_xm0_xexec(s32) = SI_IF %33(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.4 + + bb.3: + successors: %bb.8(0x04000000), %bb.1(0x7c000000) + + %17:_(s32) = G_PHI %35(s32), %bb.5, %13(s32), %bb.1 + %36:_(s1) = G_PHI %37(s1), %bb.5, %18(s1), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %26(s32) + %15:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %36(s1), %14(s32) + SI_LOOP %15(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.8 + + bb.4: + successors: %bb.6(0x40000000), %bb.7(0x40000000) + + %38:_(s1) = G_CONSTANT i1 true + %39:_(s32) = G_CONSTANT i32 2 + %40:_(s64) = G_SHL %19, %39(s32) + %41:_(p1) = G_PTR_ADD %11, %40(s64) + %42:_(s32) = G_LOAD %41(p1) :: (load (s32), addrspace 1) + %43:_(s32) = G_CONSTANT i32 0 + %44:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %42(s32), %43 + %45:sreg_32_xm0_xexec(s32) = SI_IF %44(s1), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.6 + + bb.5: + successors: %bb.3(0x80000000) + + %35:_(s32) = G_PHI %46(s32), %bb.7, %13(s32), %bb.2 + %37:_(s1) = G_PHI %47(s1), %bb.7, %27(s1), %bb.2 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %34(s32) + G_BR %bb.3 + + bb.6: + successors: %bb.7(0x80000000) + + %48:_(s32) = G_CONSTANT i32 2 + %49:_(s64) = G_SHL %19, %48(s32) + %50:_(p1) = G_PTR_ADD %2, %49(s64) + %51:_(s32) = G_LOAD %50(p1) :: (load (s32), addrspace 1) + %52:_(s32) = G_CONSTANT i32 1 + %53:_(s32) = G_ADD %51, %52 + G_STORE %53(s32), %50(p1) :: (store (s32), addrspace 1) + %54:_(s32) = G_ADD %16, %52 + %55:_(s32) = G_CONSTANT i32 100 + %56:_(s1) = G_ICMP intpred(ult), %16(s32), %55 + + bb.7: + successors: %bb.5(0x80000000) + + %46:_(s32) = G_PHI %54(s32), %bb.6, %13(s32), %bb.4 + %47:_(s1) = G_PHI %56(s1), %bb.6, %38(s1), %bb.4 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %45(s32) + G_BR %bb.5 + + bb.8: + %57:_(s32) = G_PHI %15(s32), %bb.3 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %57(s32) + S_ENDPGM 0 +... + +--- +name: loop_with_div_break_with_body +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: loop_with_div_break_with_body + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) + ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4 + ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5 + ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %12(s32), %bb.5, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %14(s32), %bb.5 + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32) + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32) + ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64) + ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]] + ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[ICMP]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.4(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 + ; GFX10-NEXT: G_STORE [[C4]](s32), [[MV2]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: G_BR %bb.4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.5(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 false + ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C6]](s32) + ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64) + ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C7]] + ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C7]] + ; GFX10-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 100 + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI1]](s32), [[C8]] + ; GFX10-NEXT: G_BR %bb.5 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32) + ; GFX10-NEXT: S_ENDPGM 0 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.5: + ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.3, [[DEF]](s32), %bb.1 + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C5]](s1), %bb.3, [[C1]](s1), %bb.1 + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s1) = G_PHI [[ICMP1]](s1), %bb.3, [[C1]](s1), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[SI_IF]](s32) + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI4]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.6 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.6: + ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_PHI [[PHI3]](s1), %bb.5 + ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.5 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI6]](s32) + ; GFX10-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[PHI5]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $vgpr2 + %4:_(s32) = COPY $vgpr3 + %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32) + %6:_(s32) = COPY $vgpr4 + %7:_(s32) = COPY $vgpr5 + %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32) + %9:_(s32) = G_CONSTANT i32 0 + %10:_(s32) = G_IMPLICIT_DEF + + bb.1: + successors: %bb.3(0x40000000), %bb.5(0x40000000) + + %11:_(s32) = G_PHI %12(s32), %bb.5, %9(s32), %bb.0 + %13:_(s32) = G_PHI %9(s32), %bb.0, %14(s32), %bb.5 + %15:_(s1) = G_CONSTANT i1 true + %16:_(s64) = G_SEXT %13(s32) + %17:_(s32) = G_CONSTANT i32 2 + %18:_(s64) = G_SHL %16, %17(s32) + %19:_(p1) = G_PTR_ADD %5, %18(s64) + %20:_(s32) = G_LOAD %19(p1) :: (load (s32), addrspace 1) + %21:_(s32) = G_CONSTANT i32 0 + %22:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %20(s32), %21 + %23:sreg_32_xm0_xexec(s32) = SI_IF %22(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.3 + + bb.2: + successors: %bb.4(0x80000000) + + %24:_(s32) = G_CONSTANT i32 10 + G_STORE %24(s32), %8(p1) :: (store (s32), addrspace 1) + G_BR %bb.4 + + bb.3: + successors: %bb.5(0x80000000) + + %25:_(s1) = G_CONSTANT i1 false + %26:_(s32) = G_CONSTANT i32 2 + %27:_(s64) = G_SHL %16, %26(s32) + %28:_(p1) = G_PTR_ADD %2, %27(s64) + %29:_(s32) = G_LOAD %28(p1) :: (load (s32), addrspace 1) + %30:_(s32) = G_CONSTANT i32 1 + %31:_(s32) = G_ADD %29, %30 + G_STORE %31(s32), %28(p1) :: (store (s32), addrspace 1) + %32:_(s32) = G_ADD %13, %30 + %33:_(s32) = G_CONSTANT i32 100 + %34:_(s1) = G_ICMP intpred(ult), %13(s32), %33 + G_BR %bb.5 + + bb.4: + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %35(s32) + S_ENDPGM 0 + + bb.5: + successors: %bb.6(0x04000000), %bb.1(0x7c000000) + + %14:_(s32) = G_PHI %32(s32), %bb.3, %10(s32), %bb.1 + %36:_(s1) = G_PHI %25(s1), %bb.3, %15(s1), %bb.1 + %37:_(s1) = G_PHI %34(s1), %bb.3, %15(s1), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %23(s32) + %12:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %37(s1), %11(s32) + SI_LOOP %12(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.6 + + bb.6: + successors: %bb.2(0x40000000), %bb.4(0x40000000) + + %38:sreg_32_xm0_xexec(s1) = G_PHI %36(s1), %bb.5 + %39:_(s32) = G_PHI %12(s32), %bb.5 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %39(s32) + %35:sreg_32_xm0_xexec(s32) = SI_IF %38(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 +... + +--- +name: irreducible_cfg +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: irreducible_cfg + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.7(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 + ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4 + ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5 + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY4]](s32), [[COPY1]] + ; GFX10-NEXT: G_BR %bb.7 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.3(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[COPY4]](s32), [[COPY]] + ; GFX10-NEXT: G_BR %bb.3 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.7(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s1) = G_PHI %12(s1), %bb.6, [[DEF]](s1), %bb.7 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s1) = G_PHI %12(s1), %bb.6, %14(s1), %bb.7 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32) + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI1]](s1), %17(s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.3(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.1, %19(s32), %bb.3 + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[ICMP1]](s1), [[PHI2]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT1]](s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.6 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: successors: %bb.5(0x04000000), %bb.7(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INTRINSIC_CONVERGENT]](s32) + ; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY5]](s32), [[COPY]] + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP]], [[C2]] + ; GFX10-NEXT: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP2]], [[XOR]] + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[OR]](s1), %25(s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT2]](s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.5 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.5: + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[ICMP2]](s1), %bb.4 + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT2]](s32), %bb.4 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32) + ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI3]](s1), [[COPY3]], [[COPY2]] + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[SELECT]](s32) + ; GFX10-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT3]](s32) + ; GFX10-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.6: + ; GFX10-NEXT: successors: %bb.2(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT1]](s32), %bb.3 + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 false + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI5]](s32) + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.7: + ; GFX10-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT2]](s32), %bb.4, [[PHI6]](s32), %bb.2, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI7:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.4, [[INTRINSIC_CONVERGENT]](s32), %bb.2, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI8:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_PHI [[ICMP]](s1), %bb.0, [[PHI]](s1), %bb.2, [[C2]](s1), %bb.4 + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[PHI8]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.1 + bb.0: + successors: %bb.7(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s32) = COPY $vgpr2 + %3:_(s32) = COPY $vgpr3 + %4:_(s32) = COPY $vgpr4 + %5:_(s32) = COPY $vgpr5 + %6:_(s32) = G_CONSTANT i32 0 + %7:_(s1) = G_IMPLICIT_DEF + %8:_(s1) = G_ICMP intpred(sgt), %4(s32), %1 + G_BR %bb.7 + + bb.1: + successors: %bb.3(0x80000000) + + %9:_(s32) = G_CONSTANT i32 0 + %10:_(s1) = G_ICMP intpred(sle), %4(s32), %0 + G_BR %bb.3 + + bb.2: + successors: %bb.4(0x40000000), %bb.7(0x40000000) + + %11:_(s1) = G_PHI %12(s1), %bb.6, %7(s1), %bb.7 + %13:_(s1) = G_PHI %12(s1), %bb.6, %14(s1), %bb.7 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32) + %16:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %13(s1), %17(s32) + SI_LOOP %16(s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.4 + + bb.3: + successors: %bb.6(0x04000000), %bb.3(0x7c000000) + + %18:_(s32) = G_PHI %9(s32), %bb.1, %19(s32), %bb.3 + %19:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %10(s1), %18(s32) + SI_LOOP %19(s32), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.6 + + bb.4: + successors: %bb.5(0x04000000), %bb.7(0x7c000000) + + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %16(s32) + %20:_(s1) = G_ICMP intpred(sgt), %5(s32), %0 + %21:_(s1) = G_CONSTANT i1 true + %22:_(s1) = G_XOR %8, %21 + %23:_(s1) = G_OR %20, %22 + %24:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %23(s1), %25(s32) + SI_LOOP %24(s32), %bb.7, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.5 + + bb.5: + %26:_(s1) = G_PHI %20(s1), %bb.4 + %27:_(s32) = G_PHI %24(s32), %bb.4 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %27(s32) + %28:_(s32) = G_SELECT %26(s1), %3, %2 + %29:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %28(s32) + $sgpr0 = COPY %29(s32) + SI_RETURN_TO_EPILOG implicit $sgpr0 + + bb.6: + successors: %bb.2(0x80000000) + + %30:_(s32) = G_PHI %19(s32), %bb.3 + %12:_(s1) = G_CONSTANT i1 false + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %30(s32) + G_BR %bb.2 + + bb.7: + successors: %bb.1(0x40000000), %bb.2(0x40000000) + + %25:_(s32) = G_PHI %24(s32), %bb.4, %25(s32), %bb.2, %6(s32), %bb.0 + %17:_(s32) = G_PHI %6(s32), %bb.4, %16(s32), %bb.2, %6(s32), %bb.0 + %31:sreg_32_xm0_xexec(s1) = G_PHI %8(s1), %bb.0, %11(s1), %bb.2, %21(s1), %bb.4 + %14:_(s1) = G_CONSTANT i1 true + %15:sreg_32_xm0_xexec(s32) = SI_IF %31(s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.1 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll new file mode 100644 index 000000000000..54881f59096c --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll @@ -0,0 +1,171 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc -global-isel -amdgpu-global-isel-risky-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s + +define void @temporal_divergent_i1_phi(float %val, ptr %addr) { +; GFX10-LABEL: temporal_divergent_i1_phi: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_mov_b32 s4, 0 +; GFX10-NEXT: v_mov_b32_e32 v4, 1 +; GFX10-NEXT: v_mov_b32_e32 v3, s4 +; GFX10-NEXT: .LBB0_1: ; %loop +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_cvt_f32_u32_e32 v6, v3 +; GFX10-NEXT: v_mov_b32_e32 v5, v4 +; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v3 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v0 +; GFX10-NEXT: v_xor_b32_e32 v4, 1, v5 +; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_cbranch_execnz .LBB0_1 +; GFX10-NEXT: ; %bb.2: ; %exit +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: v_and_b32_e32 v0, 1, v5 +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo +; GFX10-NEXT: flat_store_dword v[1:2], v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_setpc_b64 s[30:31] +entry: + br label %loop + +loop: + %counter = phi i32 [ 0, %entry ], [ %counterPlus1, %loop ] + %bool_counter = phi i1 [ true, %entry ], [ %neg_bool_counter, %loop ] + %neg_bool_counter = xor i1 %bool_counter, true + %fcounter = uitofp i32 %counter to float + %cond = fcmp ogt float %fcounter, %val + %counterPlus1 = add i32 %counter, 1 + br i1 %cond, label %exit, label %loop + +exit: + %select = select i1 %bool_counter, float 1.000000e+00, float 0.000000e+00 + store float %select, ptr %addr + ret void +} + +define void @temporal_divergent_i1_non_phi(float %val, ptr %addr) { +; GFX10-LABEL: temporal_divergent_i1_non_phi: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_mov_b32 s4, 0 +; GFX10-NEXT: v_mov_b32_e32 v3, 1 +; GFX10-NEXT: v_mov_b32_e32 v4, s4 +; GFX10-NEXT: .LBB1_1: ; %loop +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_cvt_f32_u32_e32 v5, v4 +; GFX10-NEXT: v_xor_b32_e32 v3, 1, v3 +; GFX10-NEXT: v_add_nc_u32_e32 v4, 1, v4 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v0 +; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_cbranch_execnz .LBB1_1 +; GFX10-NEXT: ; %bb.2: ; %exit +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: v_and_b32_e32 v0, 1, v3 +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo +; GFX10-NEXT: flat_store_dword v[1:2], v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_setpc_b64 s[30:31] +entry: + br label %loop + +loop: + %counter = phi i32 [ 0, %entry ], [ %counterPlus1, %loop ] + %bool_counter = phi i1 [ true, %entry ], [ %neg_bool_counter, %loop ] + %neg_bool_counter = xor i1 %bool_counter, true + %fcounter = uitofp i32 %counter to float + %cond = fcmp ogt float %fcounter, %val + %counterPlus1 = add i32 %counter, 1 + br i1 %cond, label %exit, label %loop + +exit: + %select = select i1 %neg_bool_counter, float 1.000000e+00, float 0.000000e+00 + store float %select, ptr %addr + ret void +} + +; This is temporal divergent uniform i1 structurize-cfg phi. +; Loop has uniform condition if with body with break at the end. +define amdgpu_cs void @loop_with_1break(ptr addrspace(1) %x, i32 %x.size, ptr addrspace(1) inreg %a, ptr addrspace(1) inreg %a.break) { +; GFX10-LABEL: loop_with_1break: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s4, 0 +; GFX10-NEXT: v_mov_b32_e32 v4, s1 +; GFX10-NEXT: v_mov_b32_e32 v3, s0 +; GFX10-NEXT: v_mov_b32_e32 v5, s4 +; GFX10-NEXT: s_branch .LBB2_3 +; GFX10-NEXT: .LBB2_1: ; %loop.body +; GFX10-NEXT: ; in Loop: Header=BB2_3 Depth=1 +; GFX10-NEXT: v_add_co_u32 v6, vcc_lo, v0, v6 +; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v1, v7, vcc_lo +; GFX10-NEXT: v_add_nc_u32_e32 v9, 1, v5 +; GFX10-NEXT: v_cmp_lt_u32_e64 s0, v5, v2 +; GFX10-NEXT: s_mov_b32 s1, 0 +; GFX10-NEXT: global_load_dword v8, v[6:7], off +; GFX10-NEXT: v_mov_b32_e32 v5, v9 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_add_nc_u32_e32 v8, 1, v8 +; GFX10-NEXT: global_store_dword v[6:7], v8, off +; GFX10-NEXT: .LBB2_2: ; %Flow +; GFX10-NEXT: ; in Loop: Header=BB2_3 Depth=1 +; GFX10-NEXT: s_and_b32 s0, exec_lo, s0 +; GFX10-NEXT: s_or_b32 s4, s0, s4 +; GFX10-NEXT: s_and_b32 s0, 1, s1 +; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_cbranch_execz .LBB2_5 +; GFX10-NEXT: .LBB2_3: ; %A +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5 +; GFX10-NEXT: v_lshlrev_b64 v[6:7], 2, v[5:6] +; GFX10-NEXT: v_add_co_u32 v8, vcc_lo, v3, v6 +; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v4, v7, vcc_lo +; GFX10-NEXT: global_load_dword v8, v[8:9], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 +; GFX10-NEXT: s_cbranch_vccnz .LBB2_1 +; GFX10-NEXT: ; %bb.4: ; in Loop: Header=BB2_3 Depth=1 +; GFX10-NEXT: s_mov_b32 s0, -1 +; GFX10-NEXT: s_mov_b32 s1, 1 +; GFX10-NEXT: ; implicit-def: $vgpr5 +; GFX10-NEXT: s_branch .LBB2_2 +; GFX10-NEXT: .LBB2_5: ; %loop.exit.guard +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_and_saveexec_b32 s1, s0 +; GFX10-NEXT: s_xor_b32 s1, exec_lo, s1 +; GFX10-NEXT: s_cbranch_execz .LBB2_7 +; GFX10-NEXT: ; %bb.6: ; %break.body +; GFX10-NEXT: v_mov_b32_e32 v0, 10 +; GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GFX10-NEXT: .LBB2_7: ; %exit +; GFX10-NEXT: s_endpgm +entry: + br label %A + +A: + %counter = phi i32 [ %counter.plus.1, %loop.body ], [ 0, %entry ] + %a.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %a, i32 %counter + %a.val = load i32, ptr addrspace(1) %a.plus.counter + %a.cond = icmp eq i32 %a.val, 0 + br i1 %a.cond, label %break.body, label %loop.body + +break.body: + store i32 10, ptr addrspace(1) %a.break + br label %exit + +loop.body: + %x.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %x, i32 %counter + %x.val = load i32, ptr addrspace(1) %x.plus.counter + %x.val.plus.1 = add i32 %x.val, 1 + store i32 %x.val.plus.1, ptr addrspace(1) %x.plus.counter + %counter.plus.1 = add i32 %counter, 1 + %x.cond = icmp ult i32 %counter, %x.size + br i1 %x.cond, label %exit, label %A + +exit: + ret void +} + diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir new file mode 100644 index 000000000000..9c2d083d0aa1 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir @@ -0,0 +1,324 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering %s -o - | FileCheck -check-prefix=GFX10 %s + +--- +name: temporal_divergent_i1_phi +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: temporal_divergent_i1_phi + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C1]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %9(s32), %bb.1 + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s1) = G_PHI [[C]](s1), %bb.0, %11(s1), %bb.1 + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI2]], [[C2]] + ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI1]](s32) + ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]] + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C3]] + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[PHI2]](s1), %bb.1 + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32) + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI3]](s1), [[C5]], [[C4]] + ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32)) + ; GFX10-NEXT: SI_RETURN + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s32) = COPY $vgpr2 + %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32) + %4:_(s1) = G_CONSTANT i1 true + %5:_(s32) = G_CONSTANT i32 0 + + bb.1: + successors: %bb.2(0x04000000), %bb.1(0x7c000000) + + %6:_(s32) = G_PHI %7(s32), %bb.1, %5(s32), %bb.0 + %8:_(s32) = G_PHI %5(s32), %bb.0, %9(s32), %bb.1 + %10:_(s1) = G_PHI %4(s1), %bb.0, %11(s1), %bb.1 + %12:_(s1) = G_CONSTANT i1 true + %11:_(s1) = G_XOR %10, %12 + %13:_(s32) = G_UITOFP %8(s32) + %14:_(s1) = G_FCMP floatpred(ogt), %13(s32), %0 + %15:_(s32) = G_CONSTANT i32 1 + %9:_(s32) = G_ADD %8, %15 + %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %14(s1), %6(s32) + SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 + + bb.2: + %16:_(s1) = G_PHI %10(s1), %bb.1 + %17:_(s32) = G_PHI %7(s32), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %17(s32) + %18:_(s32) = G_FCONSTANT float 0.000000e+00 + %19:_(s32) = G_FCONSTANT float 1.000000e+00 + %20:_(s32) = G_SELECT %16(s1), %19, %18 + G_STORE %20(s32), %3(p0) :: (store (s32)) + SI_RETURN +... + +--- +name: temporal_divergent_i1_non_phi +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: temporal_divergent_i1_non_phi + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C1]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %9(s32), %bb.1 + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s1) = G_PHI [[C]](s1), %bb.0, %11(s1), %bb.1 + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI2]], [[C2]] + ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI1]](s32) + ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]] + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C3]] + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[XOR]](s1), %bb.1 + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI4]](s32) + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 + ; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[PHI3]](s1), [[C5]], [[C4]] + ; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32)) + ; GFX10-NEXT: SI_RETURN + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s32) = COPY $vgpr2 + %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32) + %4:_(s1) = G_CONSTANT i1 true + %5:_(s32) = G_CONSTANT i32 0 + + bb.1: + successors: %bb.2(0x04000000), %bb.1(0x7c000000) + + %6:_(s32) = G_PHI %7(s32), %bb.1, %5(s32), %bb.0 + %8:_(s32) = G_PHI %5(s32), %bb.0, %9(s32), %bb.1 + %10:_(s1) = G_PHI %4(s1), %bb.0, %11(s1), %bb.1 + %12:_(s1) = G_CONSTANT i1 true + %11:_(s1) = G_XOR %10, %12 + %13:_(s32) = G_UITOFP %8(s32) + %14:_(s1) = G_FCMP floatpred(ogt), %13(s32), %0 + %15:_(s32) = G_CONSTANT i32 1 + %9:_(s32) = G_ADD %8, %15 + %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %14(s1), %6(s32) + SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 + + bb.2: + %16:_(s1) = G_PHI %11(s1), %bb.1 + %17:_(s32) = G_PHI %7(s32), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %17(s32) + %18:_(s32) = G_FCONSTANT float 0.000000e+00 + %19:_(s32) = G_FCONSTANT float 1.000000e+00 + %20:_(s32) = G_SELECT %16(s1), %19, %18 + G_STORE %20(s32), %3(p0) :: (store (s32)) + SI_RETURN +... + +--- +name: loop_with_1break +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: loop_with_1break + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr0 + ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr1 + ; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32) + ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr2 + ; GFX10-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr3 + ; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY5]](s32), [[COPY6]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.3(0x50000000), %bb.5(0x30000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %13(s32), %bb.5, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %15(s32), %bb.5 + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[PHI1]](s32) + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C2]](s32) + ; GFX10-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64) + ; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C3]] + ; GFX10-NEXT: G_BRCOND [[ICMP]](s1), %bb.3 + ; GFX10-NEXT: G_BR %bb.5 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: successors: %bb.4(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 + ; GFX10-NEXT: G_STORE [[C4]](s32), [[MV2]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: G_BR %bb.4 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.3: + ; GFX10-NEXT: successors: %bb.5(0x80000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 false + ; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C6]](s32) + ; GFX10-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[MV]], [[SHL1]](s64) + ; GFX10-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1) + ; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[C7]] + ; GFX10-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD1]](p1) :: (store (s32), addrspace 1) + ; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C7]] + ; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[PHI1]](s32), [[COPY2]] + ; GFX10-NEXT: G_BR %bb.5 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.4: + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %34(s32) + ; GFX10-NEXT: S_ENDPGM 0 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.5: + ; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ADD1]](s32), %bb.3, [[DEF]](s32), %bb.1 + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C5]](s1), %bb.3, [[C1]](s1), %bb.1 + ; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s1) = G_PHI [[ICMP1]](s1), %bb.3, [[C1]](s1), %bb.1 + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[PHI4]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.6 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.6: + ; GFX10-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI5:%[0-9]+]]:sreg_32_xm0_xexec(s1) = G_PHI [[PHI3]](s1), %bb.5 + ; GFX10-NEXT: [[PHI6:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.5 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI6]](s32) + ; GFX10-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[PHI5]](s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + bb.0: + successors: %bb.1(0x80000000) + liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32) + %3:_(s32) = COPY $vgpr2 + %4:_(s32) = COPY $sgpr0 + %5:_(s32) = COPY $sgpr1 + %6:_(p1) = G_MERGE_VALUES %4(s32), %5(s32) + %7:_(s32) = COPY $sgpr2 + %8:_(s32) = COPY $sgpr3 + %9:_(p1) = G_MERGE_VALUES %7(s32), %8(s32) + %10:_(s32) = G_CONSTANT i32 0 + %11:_(s32) = G_IMPLICIT_DEF + + bb.1: + successors: %bb.3(0x50000000), %bb.5(0x30000000) + + %12:_(s32) = G_PHI %13(s32), %bb.5, %10(s32), %bb.0 + %14:_(s32) = G_PHI %10(s32), %bb.0, %15(s32), %bb.5 + %16:_(s1) = G_CONSTANT i1 true + %17:_(s64) = G_SEXT %14(s32) + %18:_(s32) = G_CONSTANT i32 2 + %19:_(s64) = G_SHL %17, %18(s32) + %20:_(p1) = G_PTR_ADD %6, %19(s64) + %21:_(s32) = G_LOAD %20(p1) :: (load (s32), addrspace 1) + %22:_(s32) = G_CONSTANT i32 0 + %23:_(s1) = G_ICMP intpred(ne), %21(s32), %22 + G_BRCOND %23(s1), %bb.3 + G_BR %bb.5 + + bb.2: + successors: %bb.4(0x80000000) + + %24:_(s32) = G_CONSTANT i32 10 + G_STORE %24(s32), %9(p1) :: (store (s32), addrspace 1) + G_BR %bb.4 + + bb.3: + successors: %bb.5(0x80000000) + + %25:_(s1) = G_CONSTANT i1 false + %26:_(s32) = G_CONSTANT i32 2 + %27:_(s64) = G_SHL %17, %26(s32) + %28:_(p1) = G_PTR_ADD %2, %27(s64) + %29:_(s32) = G_LOAD %28(p1) :: (load (s32), addrspace 1) + %30:_(s32) = G_CONSTANT i32 1 + %31:_(s32) = G_ADD %29, %30 + G_STORE %31(s32), %28(p1) :: (store (s32), addrspace 1) + %32:_(s32) = G_ADD %14, %30 + %33:_(s1) = G_ICMP intpred(ult), %14(s32), %3 + G_BR %bb.5 + + bb.4: + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %34(s32) + S_ENDPGM 0 + + bb.5: + successors: %bb.6(0x04000000), %bb.1(0x7c000000) + + %15:_(s32) = G_PHI %32(s32), %bb.3, %11(s32), %bb.1 + %35:_(s1) = G_PHI %25(s1), %bb.3, %16(s1), %bb.1 + %36:_(s1) = G_PHI %33(s1), %bb.3, %16(s1), %bb.1 + %13:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %36(s1), %12(s32) + SI_LOOP %13(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.6 + + bb.6: + successors: %bb.2(0x40000000), %bb.4(0x40000000) + + %37:sreg_32_xm0_xexec(s1) = G_PHI %35(s1), %bb.5 + %38:_(s32) = G_PHI %13(s32), %bb.5 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %38(s32) + %34:sreg_32_xm0_xexec(s32) = SI_IF %37(s1), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll new file mode 100644 index 000000000000..d065f228a4e4 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll @@ -0,0 +1,37 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 +; RUN: llc -global-isel -amdgpu-global-isel-risky-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s + +define void @temporal_divergent_i32(float %val, ptr %addr) { +; GFX10-LABEL: temporal_divergent_i32: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_mov_b32 s4, -1 +; GFX10-NEXT: v_mov_b32_e32 v3, s4 +; GFX10-NEXT: s_mov_b32 s4, 0 +; GFX10-NEXT: .LBB0_1: ; %loop +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_add_nc_u32_e32 v3, 1, v3 +; GFX10-NEXT: v_cvt_f32_u32_e32 v4, v3 +; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v0 +; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_cbranch_execnz .LBB0_1 +; GFX10-NEXT: ; %bb.2: ; %exit +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: flat_store_dword v[1:2], v3 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_setpc_b64 s[30:31] +entry: + br label %loop + +loop: + %counter = phi i32 [ 0, %entry ], [ %counter.plus.1, %loop ] + %f.counter = uitofp i32 %counter to float + %cond = fcmp ogt float %f.counter, %val + %counter.plus.1 = add i32 %counter, 1 + br i1 %cond, label %exit, label %loop + +exit: + store i32 %counter, ptr %addr + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir new file mode 100644 index 000000000000..4cc68029489e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir @@ -0,0 +1,70 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -global-isel -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering %s -o - | FileCheck -check-prefix=GFX10 %s + +--- +name: temporal_divergent_i32 +legalized: true +tracksRegLiveness: true +body: | + ; GFX10-LABEL: name: temporal_divergent_i32 + ; GFX10: bb.0: + ; GFX10-NEXT: successors: %bb.1(0x80000000) + ; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 + ; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) + ; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.1: + ; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[PHI:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C]](s32), %bb.0 + ; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %9(s32), %bb.1 + ; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI1]], [[C2]] + ; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[ADD]](s32) + ; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]] + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI]](s32) + ; GFX10-NEXT: SI_LOOP [[INTRINSIC_CONVERGENT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + ; GFX10-NEXT: G_BR %bb.2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: bb.2: + ; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ADD]](s32), %bb.1 + ; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[INTRINSIC_CONVERGENT]](s32), %bb.1 + ; GFX10-NEXT: G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s32) + ; GFX10-NEXT: G_STORE [[PHI2]](s32), [[MV]](p0) :: (store (s32)) + ; GFX10-NEXT: SI_RETURN + bb.0: + successors: %bb.1(0x80000000) + liveins: $vgpr0, $vgpr1, $vgpr2 + + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(s32) = COPY $vgpr2 + %3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32) + %4:_(s32) = G_CONSTANT i32 0 + %5:_(s32) = G_CONSTANT i32 -1 + + bb.1: + successors: %bb.2(0x04000000), %bb.1(0x7c000000) + + %6:_(s32) = G_PHI %7(s32), %bb.1, %4(s32), %bb.0 + %8:_(s32) = G_PHI %5(s32), %bb.0, %9(s32), %bb.1 + %10:_(s32) = G_CONSTANT i32 1 + %9:_(s32) = G_ADD %8, %10 + %11:_(s32) = G_UITOFP %9(s32) + %12:_(s1) = G_FCMP floatpred(ogt), %11(s32), %0 + %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.if.break), %12(s1), %6(s32) + SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec + G_BR %bb.2 + + bb.2: + %13:_(s32) = G_PHI %9(s32), %bb.1 + %14:_(s32) = G_PHI %7(s32), %bb.1 + G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %14(s32) + G_STORE %13(s32), %3(p0) :: (store (s32)) + SI_RETURN +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll index d6d36fe1acf3..096ca5bc8705 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s define float @test_min_max_ValK0_K1_f32(float %a) #0 { ; GFX10-LABEL: test_min_max_ValK0_K1_f32: @@ -14,6 +15,12 @@ define float @test_min_max_ValK0_K1_f32(float %a) #0 { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_med3_f32 v0, v0, 2.0, 4.0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_ValK0_K1_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_med3_num_f32 v0, v0, 2.0, 4.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %maxnum = call nnan float @llvm.maxnum.f32(float %a, float 2.0) %fmed = call nnan float @llvm.minnum.f32(float %maxnum, float 4.0) ret float %fmed @@ -31,6 +38,12 @@ define float @test_min_max_K0Val_K1_f32(float %a) #1 { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_med3_f32 v0, v0, 2.0, 4.0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_K0Val_K1_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_med3_num_f32 v0, v0, 2.0, 4.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %maxnum = call nnan float @llvm.maxnum.f32(float 2.0, float %a) %fmed = call nnan float @llvm.minnum.f32(float %maxnum, float 4.0) ret float %fmed @@ -53,6 +66,14 @@ define half @test_min_K1max_ValK0_f16(half %a) #0 { ; GFX8-NEXT: v_max_f16_e32 v0, 2.0, v0 ; GFX8-NEXT: v_min_f16_e32 v0, 4.0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_K1max_ValK0_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_max_num_f16_e32 v0, v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_med3_num_f16 v0, v0, 2.0, 4.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %maxnum = call half @llvm.maxnum.f16(half %a, half 2.0) %fmed = call half @llvm.minnum.f16(half 4.0, half %maxnum) ret half %fmed @@ -71,6 +92,12 @@ define half @test_min_K1max_K0Val_f16(half %a) #1 { ; GFX8-NEXT: v_max_f16_e32 v0, 2.0, v0 ; GFX8-NEXT: v_min_f16_e32 v0, 4.0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_K1max_K0Val_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_med3_num_f16 v0, v0, 2.0, 4.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %maxnum = call nnan half @llvm.maxnum.f16(half 2.0, half %a) %fmed = call nnan half @llvm.minnum.f16(half 4.0, half %maxnum) ret half %fmed @@ -89,6 +116,12 @@ define float @test_max_min_ValK1_K0_f32(float %a) #0 { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_med3_f32 v0, v0, 2.0, 4.0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_min_ValK1_K0_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_med3_num_f32 v0, v0, 2.0, 4.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %minnum = call nnan float @llvm.minnum.f32(float %a, float 4.0) %fmed = call nnan float @llvm.maxnum.f32(float %minnum, float 2.0) ret float %fmed @@ -106,6 +139,12 @@ define float @test_max_min_K1Val_K0_f32(float %a) #1 { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_med3_f32 v0, v0, 2.0, 4.0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_min_K1Val_K0_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_med3_num_f32 v0, v0, 2.0, 4.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %minnum = call nnan float @llvm.minnum.f32(float 4.0, float %a) %fmed = call nnan float @llvm.maxnum.f32(float %minnum, float 2.0) ret float %fmed @@ -124,6 +163,12 @@ define half @test_max_K0min_ValK1_f16(half %a) #0 { ; GFX8-NEXT: v_min_f16_e32 v0, 4.0, v0 ; GFX8-NEXT: v_max_f16_e32 v0, 2.0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_K0min_ValK1_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_med3_num_f16 v0, v0, 2.0, 4.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %minnum = call nnan half @llvm.minnum.f16(half %a, half 4.0) %fmed = call nnan half @llvm.maxnum.f16(half 2.0, half %minnum) ret half %fmed @@ -142,6 +187,12 @@ define half @test_max_K0min_K1Val_f16(half %a) #1 { ; GFX8-NEXT: v_min_f16_e32 v0, 4.0, v0 ; GFX8-NEXT: v_max_f16_e32 v0, 2.0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_K0min_K1Val_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_med3_num_f16 v0, v0, 2.0, 4.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %minnum = call nnan half @llvm.minnum.f16(half 4.0, half %a) %fmed = call nnan half @llvm.maxnum.f16(half 2.0, half %minnum) ret half %fmed @@ -161,6 +212,12 @@ define float @test_min_max_global_nnan(float %a) #2 { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_med3_f32 v0, v0, 2.0, 4.0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_global_nnan: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_med3_num_f32 v0, v0, 2.0, 4.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %maxnum = call float @llvm.maxnum.f32(float %a, float 2.0) %fmed = call float @llvm.minnum.f32(float %maxnum, float 4.0) ret float %fmed @@ -178,6 +235,12 @@ define float @test_max_min_global_nnan(float %a) #2 { ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: v_med3_f32 v0, v0, 2.0, 4.0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_min_global_nnan: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_med3_num_f32 v0, v0, 2.0, 4.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %minnum = call float @llvm.minnum.f32(float %a, float 4.0) %fmed = call float @llvm.maxnum.f32(float %minnum, float 2.0) ret float %fmed @@ -202,6 +265,12 @@ define float @test_min_max_K0_gt_K1(float %a) #0 { ; GFX8-NEXT: v_max_f32_e32 v0, 4.0, v0 ; GFX8-NEXT: v_min_f32_e32 v0, 2.0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_K0_gt_K1: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_maxmin_num_f32 v0, v0, 4.0, 2.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %maxnum = call nnan float @llvm.maxnum.f32(float %a, float 4.0) %fmed = call nnan float @llvm.minnum.f32(float %maxnum, float 2.0) ret float %fmed @@ -222,6 +291,12 @@ define float @test_max_min_K0_gt_K1(float %a) #0 { ; GFX8-NEXT: v_min_f32_e32 v0, 2.0, v0 ; GFX8-NEXT: v_max_f32_e32 v0, 4.0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_min_K0_gt_K1: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_minmax_num_f32 v0, v0, 2.0, 4.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %minnum = call nnan float @llvm.minnum.f32(float %a, float 2.0) %fmed = call nnan float @llvm.maxnum.f32(float %minnum, float 4.0) ret float %fmed @@ -242,6 +317,12 @@ define float @test_min_max_non_inline_const(float %a) #0 { ; GFX8-NEXT: v_max_f32_e32 v0, 2.0, v0 ; GFX8-NEXT: v_min_f32_e32 v0, 0x41000000, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_non_inline_const: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_maxmin_num_f32 v0, v0, 2.0, 0x41000000 +; GFX12-NEXT: s_setpc_b64 s[30:31] %maxnum = call nnan float @llvm.maxnum.f32(float %a, float 2.0) %fmed = call nnan float @llvm.minnum.f32(float %maxnum, float 8.0) ret float %fmed @@ -263,6 +344,14 @@ define double @test_min_max_f64(double %a) #0 { ; GFX8-NEXT: v_max_f64 v[0:1], v[0:1], 2.0 ; GFX8-NEXT: v_min_f64 v[0:1], v[0:1], 4.0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_max_num_f64_e32 v[0:1], 2.0, v[0:1] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_min_num_f64_e32 v[0:1], 4.0, v[0:1] +; GFX12-NEXT: s_setpc_b64 s[30:31] %maxnum = call nnan double @llvm.maxnum.f64(double %a, double 2.0) %fmed = call nnan double @llvm.minnum.f64(double %maxnum, double 4.0) ret double %fmed @@ -287,6 +376,14 @@ define <2 x half> @test_min_max_v2f16(<2 x half> %a) #0 { ; GFX8-NEXT: v_min_f16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; GFX8-NEXT: v_or_b32_e32 v0, v1, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_v2f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_pk_max_num_f16 v0, v0, 2.0 op_sel_hi:[1,0] +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_pk_min_num_f16 v0, v0, 4.0 op_sel_hi:[1,0] +; GFX12-NEXT: s_setpc_b64 s[30:31] %maxnum = call nnan <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> <half 2.0, half 2.0>) %fmed = call nnan <2 x half> @llvm.minnum.v2f16(<2 x half> %maxnum, <2 x half> <half 4.0, half 4.0>) ret <2 x half> %fmed @@ -309,6 +406,14 @@ define float @test_min_max_maybe_NaN_input_ieee_false(float %a) #1 { ; GFX8-NEXT: v_max_f32_e32 v0, 2.0, v0 ; GFX8-NEXT: v_min_f32_e32 v0, 4.0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_min_max_maybe_NaN_input_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_med3_num_f32 v0, v0, 2.0, 4.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %maxnum = call float @llvm.maxnum.f32(float %a, float 2.0) %fmed = call float @llvm.minnum.f32(float %maxnum, float 4.0) ret float %fmed @@ -330,6 +435,14 @@ define float @test_max_min_maybe_NaN_input_ieee_false(float %a) #1 { ; GFX8-NEXT: v_min_f32_e32 v0, 4.0, v0 ; GFX8-NEXT: v_max_f32_e32 v0, 2.0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_min_maybe_NaN_input_ieee_false: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_minmax_num_f32 v0, v0, 4.0, 2.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %minnum = call float @llvm.minnum.f32(float %a, float 4.0) %fmed = call float @llvm.maxnum.f32(float %minnum, float 2.0) ret float %fmed @@ -352,6 +465,14 @@ define float @test_max_min_maybe_NaN_input_ieee_true(float %a) #0 { ; GFX8-NEXT: v_min_f32_e32 v0, 4.0, v0 ; GFX8-NEXT: v_max_f32_e32 v0, 2.0, v0 ; GFX8-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: test_max_min_maybe_NaN_input_ieee_true: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_max_num_f32_e32 v0, v0, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_minmax_num_f32 v0, v0, 4.0, 2.0 +; GFX12-NEXT: s_setpc_b64 s[30:31] %minnum = call float @llvm.minnum.f32(float %a, float 4.0) %fmed = call float @llvm.maxnum.f32(float %minnum, float 2.0) ret float %fmed diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll index bd570df3d83b..ed298796937c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 %s define float @v_rsq_clamp_f32(float %src) #0 { ; SI-LABEL: v_rsq_clamp_f32: @@ -16,6 +17,15 @@ define float @v_rsq_clamp_f32(float %src) #0 { ; VI-NEXT: v_min_f32_e32 v0, 0x7f7fffff, v0 ; VI-NEXT: v_max_f32_e32 v0, 0xff7fffff, v0 ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_rsq_clamp_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_rsq_f32_e32 v0, v0 +; GFX12-NEXT: v_mov_b32_e32 v1, 0xff7fffff +; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_minmax_num_f32 v0, v0, 0x7f7fffff, v1 +; GFX12-NEXT: s_setpc_b64 s[30:31] %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float %src) ret float %rsq_clamp } @@ -34,6 +44,15 @@ define float @v_rsq_clamp_fabs_f32(float %src) #0 { ; VI-NEXT: v_min_f32_e32 v0, 0x7f7fffff, v0 ; VI-NEXT: v_max_f32_e32 v0, 0xff7fffff, v0 ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_rsq_clamp_fabs_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_rsq_f32_e64 v0, |v0| +; GFX12-NEXT: v_mov_b32_e32 v1, 0xff7fffff +; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_minmax_num_f32 v0, v0, 0x7f7fffff, v1 +; GFX12-NEXT: s_setpc_b64 s[30:31] %fabs.src = call float @llvm.fabs.f32(float %src) %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float %fabs.src) ret float %rsq_clamp @@ -56,6 +75,19 @@ define double @v_rsq_clamp_f64(double %src) #0 { ; VI-NEXT: s_mov_b32 s5, 0xffefffff ; VI-NEXT: v_max_f64 v[0:1], v[0:1], s[4:5] ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_rsq_clamp_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_rsq_f64_e32 v[0:1], v[0:1] +; GFX12-NEXT: s_mov_b32 s0, -1 +; GFX12-NEXT: s_mov_b32 s1, 0x7fefffff +; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: v_min_num_f64_e32 v[0:1], s[0:1], v[0:1] +; GFX12-NEXT: s_mov_b32 s1, 0xffefffff +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: v_max_num_f64_e32 v[0:1], s[0:1], v[0:1] +; GFX12-NEXT: s_setpc_b64 s[30:31] %rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src) ret double %rsq_clamp } @@ -77,6 +109,19 @@ define double @v_rsq_clamp_fabs_f64(double %src) #0 { ; VI-NEXT: s_mov_b32 s5, 0xffefffff ; VI-NEXT: v_max_f64 v[0:1], v[0:1], s[4:5] ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_rsq_clamp_fabs_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_rsq_f64_e64 v[0:1], |v[0:1]| +; GFX12-NEXT: s_mov_b32 s0, -1 +; GFX12-NEXT: s_mov_b32 s1, 0x7fefffff +; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: v_min_num_f64_e32 v[0:1], s[0:1], v[0:1] +; GFX12-NEXT: s_mov_b32 s1, 0xffefffff +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: v_max_num_f64_e32 v[0:1], s[0:1], v[0:1] +; GFX12-NEXT: s_setpc_b64 s[30:31] %fabs.src = call double @llvm.fabs.f64(double %src) %rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %fabs.src) ret double %rsq_clamp @@ -96,6 +141,15 @@ define float @v_rsq_clamp_undef_f32() #0 { ; VI-NEXT: v_min_f32_e32 v0, 0x7f7fffff, v0 ; VI-NEXT: v_max_f32_e32 v0, 0xff7fffff, v0 ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_rsq_clamp_undef_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_rsq_f32_e32 v0, s0 +; GFX12-NEXT: v_mov_b32_e32 v1, 0xff7fffff +; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_minmax_num_f32 v0, v0, 0x7f7fffff, v1 +; GFX12-NEXT: s_setpc_b64 s[30:31] %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float undef) ret float %rsq_clamp } @@ -117,6 +171,19 @@ define double @v_rsq_clamp_undef_f64() #0 { ; VI-NEXT: s_mov_b32 s5, 0xffefffff ; VI-NEXT: v_max_f64 v[0:1], v[0:1], s[4:5] ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_rsq_clamp_undef_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_rsq_f64_e32 v[0:1], s[0:1] +; GFX12-NEXT: s_mov_b32 s0, -1 +; GFX12-NEXT: s_mov_b32 s1, 0x7fefffff +; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: v_min_num_f64_e32 v[0:1], s[0:1], v[0:1] +; GFX12-NEXT: s_mov_b32 s1, 0xffefffff +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: v_max_num_f64_e32 v[0:1], s[0:1], v[0:1] +; GFX12-NEXT: s_setpc_b64 s[30:31] %rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double undef) ret double %rsq_clamp } @@ -135,6 +202,15 @@ define float @v_rsq_clamp_f32_non_ieee(float %src) #2 { ; VI-NEXT: v_min_f32_e32 v0, 0x7f7fffff, v0 ; VI-NEXT: v_max_f32_e32 v0, 0xff7fffff, v0 ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_rsq_clamp_f32_non_ieee: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_rsq_f32_e32 v0, v0 +; GFX12-NEXT: v_mov_b32_e32 v1, 0xff7fffff +; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_minmax_num_f32 v0, v0, 0x7f7fffff, v1 +; GFX12-NEXT: s_setpc_b64 s[30:31] %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float %src) ret float %rsq_clamp } @@ -156,6 +232,19 @@ define double @v_rsq_clamp_f64_non_ieee(double %src) #2 { ; VI-NEXT: s_mov_b32 s5, 0xffefffff ; VI-NEXT: v_max_f64 v[0:1], v[0:1], s[4:5] ; VI-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: v_rsq_clamp_f64_non_ieee: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX12-NEXT: v_rsq_f64_e32 v[0:1], v[0:1] +; GFX12-NEXT: s_mov_b32 s0, -1 +; GFX12-NEXT: s_mov_b32 s1, 0x7fefffff +; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: v_min_num_f64_e32 v[0:1], s[0:1], v[0:1] +; GFX12-NEXT: s_mov_b32 s1, 0xffefffff +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: v_max_num_f64_e32 v[0:1], s[0:1], v[0:1] +; GFX12-NEXT: s_setpc_b64 s[30:31] %rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src) ret double %rsq_clamp } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir index 95f55a6d800e..a97d905f2a97 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankcombiner-clamp-fmed3-const.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=GFX12 --- name: test_fmed3_f32_known_nnan_ieee_true legalized: true @@ -22,6 +23,16 @@ body: | ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]] ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_CLAMP [[FMUL]] ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32) + ; + ; GFX12-LABEL: name: test_fmed3_f32_known_nnan_ieee_true + ; GFX12: liveins: $vgpr0 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GFX12-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]] + ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_CLAMP [[FMUL]] + ; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32) %0:vgpr(s32) = COPY $vgpr0 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 %8:vgpr(s32) = COPY %2(s32) @@ -58,6 +69,18 @@ body: | ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_CLAMP [[FMUL]] ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_CLAMP]](s16) ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) + ; + ; GFX12-LABEL: name: test_fmed3_f16_known_nnan_ieee_false + ; GFX12: liveins: $vgpr0 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32) + ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16) + ; GFX12-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]] + ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_CLAMP [[FMUL]] + ; GFX12-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_CLAMP]](s16) + ; GFX12-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) %2:vgpr(s32) = COPY $vgpr0 %0:vgpr(s16) = G_TRUNC %2(s32) %3:sgpr(s16) = G_FCONSTANT half 0xH4000 @@ -95,6 +118,17 @@ body: | ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]] ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMINNUM_IEEE]] ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32) + ; + ; GFX12-LABEL: name: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_true + ; GFX12: liveins: $vgpr0 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+01 + ; GFX12-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY]] + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GFX12-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]] + ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMINNUM_IEEE]] + ; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32) %0:vgpr(s32) = COPY $vgpr0 %2:sgpr(s32) = G_FCONSTANT float 1.000000e+01 %8:vgpr(s32) = G_FCANONICALIZE %0 @@ -130,6 +164,16 @@ body: | ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]] ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMUL]] ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32) + ; + ; GFX12-LABEL: name: test_fmed3_maybe_SNaN_input_zero_third_operand_ieee_true_dx10clamp_true + ; GFX12: liveins: $vgpr0 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GFX12-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]] + ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMUL]] + ; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32) %0:vgpr(s32) = COPY $vgpr0 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 %8:vgpr(s32) = COPY %2(s32) @@ -170,6 +214,16 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FMED3 [[FMUL]], [[COPY2]], [[COPY3]] ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32) + ; + ; GFX12-LABEL: name: test_fmed3_f32_maybe_NaN_ieee_false + ; GFX12: liveins: $vgpr0 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GFX12-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]] + ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMUL]] + ; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32) %0:vgpr(s32) = COPY $vgpr0 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 %8:vgpr(s32) = COPY %2(s32) @@ -209,6 +263,17 @@ body: | ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32) ; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FMED3 [[FMINNUM_IEEE]], [[COPY2]], [[COPY3]] ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32) + ; + ; GFX12-LABEL: name: test_fmed3_non_SNaN_input_ieee_true_dx10clamp_false + ; GFX12: liveins: $vgpr0 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+01 + ; GFX12-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[COPY]] + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GFX12-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY1]] + ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMINNUM_IEEE]] + ; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32) %0:vgpr(s32) = COPY $vgpr0 %2:sgpr(s32) = G_FCONSTANT float 1.000000e+01 %8:vgpr(s32) = G_FCANONICALIZE %0 @@ -244,6 +309,16 @@ body: | ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]] ; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMUL]] ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32) + ; + ; GFX12-LABEL: name: test_fmed3_maybe_SNaN_input_ieee_true_dx10clamp_true + ; GFX12: liveins: $vgpr0 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GFX12-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GFX12-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]] + ; GFX12-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = G_AMDGPU_CLAMP [[FMUL]] + ; GFX12-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32) %0:vgpr(s32) = COPY $vgpr0 %2:sgpr(s32) = G_FCONSTANT float 2.000000e+00 %8:vgpr(s32) = COPY %2(s32) diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll index 4da9080e2c69..95d533544c30 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll @@ -1,11 +1,13 @@ ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -enable-var-scope %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 -enable-var-scope %s ; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata ; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf0000{{$}} ; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf02c0{{$}} ; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf0000{{$}} +; GFX12-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x600f0000{{$}} define amdgpu_cs half @cs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add @@ -15,6 +17,7 @@ define amdgpu_cs half @cs_amdpal(half %arg0) #0 { ; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xaf0000{{$}} ; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xaf02c0{{$}} ; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xaf0000{{$}} +; GFX12-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xf0000{{$}} define amdgpu_es half @es_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add @@ -24,6 +27,7 @@ define amdgpu_es half @es_amdpal(half %arg0) #0 { ; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xaf0000{{$}} ; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xaf02c0{{$}} ; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xaf0000{{$}} +; GFX12-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xa0f0000{{$}} define amdgpu_gs half @gs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add @@ -33,6 +37,7 @@ define amdgpu_gs half @gs_amdpal(half %arg0) #0 { ; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xaf0000{{$}} ; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xaf02c0{{$}} ; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xaf0000{{$}} +; GFX12-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x50f0000{{$}} define amdgpu_hs half @hs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add @@ -42,6 +47,7 @@ define amdgpu_hs half @hs_amdpal(half %arg0) #0 { ; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xaf0000{{$}} ; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xaf02c0{{$}} ; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xaf0000{{$}} +; GFX12-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xf0000{{$}} define amdgpu_ls half @ls_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add @@ -52,6 +58,7 @@ define amdgpu_ls half @ls_amdpal(half %arg0) #0 { ; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xaf0000{{$}} ; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xaf02c0{{$}} ; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xaf0000{{$}} +; GFX12-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x20f0000{{$}} define amdgpu_ps half @ps_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add @@ -61,6 +68,7 @@ define amdgpu_ps half @ps_amdpal(half %arg0) #0 { ; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xaf0000{{$}} ; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xaf02c0{{$}} ; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xaf0000{{$}} +; GFX12-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x80f0000{{$}} define amdgpu_vs half @vs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add diff --git a/llvm/test/CodeGen/AMDGPU/clamp.ll b/llvm/test/CodeGen/AMDGPU/clamp.ll index 20b248875487..3c0b8f7712e1 100644 --- a/llvm/test/CodeGen/AMDGPU/clamp.ll +++ b/llvm/test/CodeGen/AMDGPU/clamp.ll @@ -3,6 +3,7 @@ ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX8 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s +; RUN: llc -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s define amdgpu_kernel void @v_clamp_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 { ; GFX6-LABEL: v_clamp_f32: @@ -61,6 +62,19 @@ define amdgpu_kernel void @v_clamp_f32(ptr addrspace(1) %out, ptr addrspace(1) % ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -129,6 +143,19 @@ define amdgpu_kernel void @v_clamp_neg_f32(ptr addrspace(1) %out, ptr addrspace( ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_neg_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, -v1, -v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -198,6 +225,19 @@ define amdgpu_kernel void @v_clamp_negabs_f32(ptr addrspace(1) %out, ptr addrspa ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_negabs_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, -|v1|, -|v1| clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -277,6 +317,21 @@ define amdgpu_kernel void @v_clamp_negzero_f32(ptr addrspace(1) %out, ptr addrsp ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_negzero_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_add_f32_e32 v1, 0.5, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_maxmin_num_f32 v1, v1, 0x80000000, 1.0 +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -356,6 +411,21 @@ define amdgpu_kernel void @v_clamp_negzero_maybe_snan_f32(ptr addrspace(1) %out, ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_negzero_maybe_snan_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_maxmin_num_f32 v1, v1, 0x80000000, 1.0 +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -442,6 +512,24 @@ define amdgpu_kernel void @v_clamp_multi_use_max_f32(ptr addrspace(1) %out, ptr ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_multi_use_max_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e32 v1, v1, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_max_num_f32_e32 v1, 0, v1 +; GFX12-NEXT: v_min_num_f32_e32 v2, 1.0, v1 +; GFX12-NEXT: global_store_b32 v0, v2, s[0:1] +; GFX12-NEXT: global_store_b32 v[0:1], v1, off th:TH_STORE_NT_RT +; GFX12-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -512,6 +600,19 @@ define amdgpu_kernel void @v_clamp_f16(ptr addrspace(1) %out, ptr addrspace(1) % ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 1, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_u16 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f16_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid @@ -581,6 +682,19 @@ define amdgpu_kernel void @v_clamp_neg_f16(ptr addrspace(1) %out, ptr addrspace( ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_neg_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 1, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_u16 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f16_e64 v1, -v1, -v1 clamp +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid @@ -651,6 +765,19 @@ define amdgpu_kernel void @v_clamp_negabs_f16(ptr addrspace(1) %out, ptr addrspa ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_negabs_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 1, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_u16 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f16_e64 v1, -|v1|, -|v1| clamp +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr half, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid @@ -722,6 +849,19 @@ define amdgpu_kernel void @v_clamp_f64(ptr addrspace(1) %out, ptr addrspace(1) % ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b64 v[0:1], v2, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_f64 v[0:1], v[0:1], v[0:1] clamp +; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr double, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr double, ptr addrspace(1) %out, i32 %tid @@ -790,6 +930,19 @@ define amdgpu_kernel void @v_clamp_neg_f64(ptr addrspace(1) %out, ptr addrspace( ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_neg_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b64 v[0:1], v2, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_f64 v[0:1], -v[0:1], -v[0:1] clamp +; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr double, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr double, ptr addrspace(1) %out, i32 %tid @@ -859,6 +1012,19 @@ define amdgpu_kernel void @v_clamp_negabs_f64(ptr addrspace(1) %out, ptr addrspa ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_negabs_f64: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b64 v[0:1], v2, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_f64 v[0:1], -|v[0:1]|, -|v[0:1]| clamp +; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr double, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr double, ptr addrspace(1) %out, i32 %tid @@ -933,6 +1099,19 @@ define amdgpu_kernel void @v_clamp_med3_aby_negzero_f32(ptr addrspace(1) %out, p ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_med3_aby_negzero_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_med3_num_f32 v1, 0x80000000, 1.0, v1 +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -999,6 +1178,19 @@ define amdgpu_kernel void @v_clamp_med3_aby_f32(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_med3_aby_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -1065,6 +1257,19 @@ define amdgpu_kernel void @v_clamp_med3_bay_f32(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_med3_bay_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -1131,6 +1336,19 @@ define amdgpu_kernel void @v_clamp_med3_yab_f32(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_med3_yab_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -1197,6 +1415,19 @@ define amdgpu_kernel void @v_clamp_med3_yba_f32(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_med3_yba_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -1263,6 +1494,19 @@ define amdgpu_kernel void @v_clamp_med3_ayb_f32(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_med3_ayb_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -1329,6 +1573,19 @@ define amdgpu_kernel void @v_clamp_med3_bya_f32(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_med3_bya_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -1381,6 +1638,16 @@ define amdgpu_kernel void @v_clamp_constants_to_one_f32(ptr addrspace(1) %out) # ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_constants_to_one_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12-NEXT: v_dual_mov_b32 v1, 1.0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid %med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float 4.0) @@ -1430,6 +1697,16 @@ define amdgpu_kernel void @v_clamp_constants_to_zero_f32(ptr addrspace(1) %out) ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_constants_to_zero_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid %med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float -4.0) @@ -1480,6 +1757,16 @@ define amdgpu_kernel void @v_clamp_constant_preserve_f32(ptr addrspace(1) %out) ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_constant_preserve_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12-NEXT: v_dual_mov_b32 v1, 0.5 :: v_dual_lshlrev_b32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid %med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float 0.5) @@ -1530,6 +1817,16 @@ define amdgpu_kernel void @v_clamp_constant_preserve_denorm_f32(ptr addrspace(1) ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_constant_preserve_denorm_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12-NEXT: v_dual_mov_b32 v1, 0x7fffff :: v_dual_lshlrev_b32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid %med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float bitcast (i32 8388607 to float)) @@ -1579,6 +1876,16 @@ define amdgpu_kernel void @v_clamp_constant_qnan_f32(ptr addrspace(1) %out) #0 { ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_constant_qnan_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid %med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float 0x7FF8000000000000) @@ -1628,6 +1935,16 @@ define amdgpu_kernel void @v_clamp_constant_snan_f32(ptr addrspace(1) %out) #0 { ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_constant_snan_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid %med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float bitcast (i32 2139095041 to float)) @@ -1701,6 +2018,19 @@ define amdgpu_kernel void @v_clamp_f32_no_dx10_clamp(ptr addrspace(1) %out, ptr ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_f32_no_dx10_clamp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_add_f32_e64 v1, v1, 0.5 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -1770,6 +2100,19 @@ define amdgpu_kernel void @v_clamp_f32_snan_dx10clamp(ptr addrspace(1) %out, ptr ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_f32_snan_dx10clamp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_add_f32_e64 v1, v1, 0.5 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -1844,6 +2187,19 @@ define amdgpu_kernel void @v_clamp_f32_snan_no_dx10clamp(ptr addrspace(1) %out, ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_f32_snan_no_dx10clamp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -1917,6 +2273,19 @@ define amdgpu_kernel void @v_clamp_f32_snan_no_dx10clamp_nnan_src(ptr addrspace( ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_f32_snan_no_dx10clamp_nnan_src: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_add_f32_e64 v1, v1, 1.0 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -1986,6 +2355,19 @@ define amdgpu_kernel void @v_clamp_med3_aby_f32_no_dx10_clamp(ptr addrspace(1) % ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_med3_aby_f32_no_dx10_clamp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -2052,6 +2434,19 @@ define amdgpu_kernel void @v_clamp_med3_bay_f32_no_dx10_clamp(ptr addrspace(1) % ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_med3_bay_f32_no_dx10_clamp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -2118,6 +2513,19 @@ define amdgpu_kernel void @v_clamp_med3_yab_f32_no_dx10_clamp(ptr addrspace(1) % ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_med3_yab_f32_no_dx10_clamp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -2184,6 +2592,19 @@ define amdgpu_kernel void @v_clamp_med3_yba_f32_no_dx10_clamp(ptr addrspace(1) % ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_med3_yba_f32_no_dx10_clamp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -2250,6 +2671,19 @@ define amdgpu_kernel void @v_clamp_med3_ayb_f32_no_dx10_clamp(ptr addrspace(1) % ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_med3_ayb_f32_no_dx10_clamp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -2316,6 +2750,19 @@ define amdgpu_kernel void @v_clamp_med3_bya_f32_no_dx10_clamp(ptr addrspace(1) % ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_med3_bya_f32_no_dx10_clamp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_max_num_f32_e64 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid @@ -2368,6 +2815,16 @@ define amdgpu_kernel void @v_clamp_constant_qnan_f32_no_dx10_clamp(ptr addrspace ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_constant_qnan_f32_no_dx10_clamp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid %med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float 0x7FF8000000000000) @@ -2418,6 +2875,16 @@ define amdgpu_kernel void @v_clamp_constant_snan_f32_no_dx10_clamp(ptr addrspace ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_constant_snan_f32_no_dx10_clamp: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid %med = call float @llvm.amdgcn.fmed3.f32(float 0.0, float 1.0, float bitcast (i32 2139095041 to float)) @@ -2490,6 +2957,19 @@ define amdgpu_kernel void @v_clamp_v2f16(ptr addrspace(1) %out, ptr addrspace(1) ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_v2f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -2577,6 +3057,19 @@ define amdgpu_kernel void @v_clamp_v2f16_undef_elt(ptr addrspace(1) %out, ptr ad ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_v2f16_undef_elt: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -2663,6 +3156,22 @@ define amdgpu_kernel void @v_clamp_v2f16_not_zero(ptr addrspace(1) %out, ptr add ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_v2f16_not_zero: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_pk_max_num_f16 v1, v1, 2.0 +; GFX12-NEXT: v_pk_min_num_f16 v1, v1, 1.0 op_sel_hi:[1,0] +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -2748,6 +3257,22 @@ define amdgpu_kernel void @v_clamp_v2f16_not_one(ptr addrspace(1) %out, ptr addr ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_v2f16_not_one: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_pk_max_num_f16 v1, v1, 0 +; GFX12-NEXT: v_pk_min_num_f16 v1, v1, 1.0 op_sel:[0,1] op_sel_hi:[1,0] +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -2825,6 +3350,19 @@ define amdgpu_kernel void @v_clamp_neg_v2f16(ptr addrspace(1) %out, ptr addrspac ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_neg_v2f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 neg_lo:[1,1] neg_hi:[1,1] clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -2906,6 +3444,21 @@ define amdgpu_kernel void @v_clamp_negabs_v2f16(ptr addrspace(1) %out, ptr addrs ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_negabs_v2f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 neg_lo:[1,1] neg_hi:[1,1] clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -2986,6 +3539,19 @@ define amdgpu_kernel void @v_clamp_neglo_v2f16(ptr addrspace(1) %out, ptr addrsp ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_neglo_v2f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 neg_lo:[1,1] clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -3065,6 +3631,19 @@ define amdgpu_kernel void @v_clamp_neghi_v2f16(ptr addrspace(1) %out, ptr addrsp ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_neghi_v2f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 neg_hi:[1,1] clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -3144,6 +3723,19 @@ define amdgpu_kernel void @v_clamp_v2f16_shuffle(ptr addrspace(1) %out, ptr addr ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_v2f16_shuffle: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 op_sel:[1,1] op_sel_hi:[0,0] clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -3232,6 +3824,19 @@ define amdgpu_kernel void @v_clamp_v2f16_undef_limit_elts0(ptr addrspace(1) %out ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_v2f16_undef_limit_elts0: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -3319,6 +3924,19 @@ define amdgpu_kernel void @v_clamp_v2f16_undef_limit_elts1(ptr addrspace(1) %out ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_v2f16_undef_limit_elts1: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: global_load_b32 v1, v0, s[2:3] +; GFX12-NEXT: s_waitcnt vmcnt(0) +; GFX12-NEXT: v_pk_max_num_f16 v1, v1, v1 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm %tid = call i32 @llvm.amdgcn.workitem.id.x() %gep0 = getelementptr <2 x half>, ptr addrspace(1) %aptr, i32 %tid %out.gep = getelementptr <2 x half>, ptr addrspace(1) %out, i32 %tid @@ -3400,6 +4018,25 @@ define amdgpu_kernel void @v_clamp_diff_source_f32(ptr addrspace(1) %out, ptr ad ; GFX11-NEXT: s_nop 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: v_clamp_diff_source_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: v_mov_b32_e32 v0, 0 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_clause 0x1 +; GFX12-NEXT: s_load_b64 s[4:5], s[2:3], 0x0 +; GFX12-NEXT: s_load_b32 s2, s[2:3], 0x8 +; GFX12-NEXT: s_waitcnt lgkmcnt(0) +; GFX12-NEXT: s_add_f32 s3, s4, s5 +; GFX12-NEXT: s_add_f32 s2, s4, s2 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3) +; GFX12-NEXT: s_max_num_f32 s2, s3, s2 +; GFX12-NEXT: v_max_num_f32_e64 v1, s2, s2 clamp +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] offset:12 +; GFX12-NEXT: s_nop 0 +; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX12-NEXT: s_endpgm { %gep1 = getelementptr float, ptr addrspace(1) %aptr, i32 1 %gep2 = getelementptr float, ptr addrspace(1) %aptr, i32 2 diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum.ll b/llvm/test/CodeGen/AMDGPU/fmaximum.ll new file mode 100644 index 000000000000..4fe2a4ad2a2f --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/fmaximum.ll @@ -0,0 +1,311 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-SDAG %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-GISEL %s + +define amdgpu_ps float @test_fmaximum_f32_vv(float %a, float %b) { +; GCN-LABEL: test_fmaximum_f32_vv: +; GCN: ; %bb.0: +; GCN-NEXT: v_maximum_f32 v0, v0, v1 +; GCN-NEXT: ; return to shader part epilog + %val = call float @llvm.maximum.f32(float %a, float %b) + ret float %val +} + +define amdgpu_ps float @test_fmaximum_f32_ss(float inreg %a, float inreg %b) { +; GCN-LABEL: test_fmaximum_f32_ss: +; GCN: ; %bb.0: +; GCN-NEXT: s_maximum_f32 s0, s0, s1 +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: ; return to shader part epilog + %val = call float @llvm.maximum.f32(float %a, float %b) + ret float %val +} + +define amdgpu_ps float @test_fmaximum_f32_vs(float %a, float inreg %b) { +; GCN-LABEL: test_fmaximum_f32_vs: +; GCN: ; %bb.0: +; GCN-NEXT: v_maximum_f32 v0, v0, s0 +; GCN-NEXT: ; return to shader part epilog + %val = call float @llvm.maximum.f32(float %a, float %b) + ret float %val +} + +define amdgpu_ps float @test_fmaximum_nnan_f32(float %a, float %b) { +; GCN-LABEL: test_fmaximum_nnan_f32: +; GCN: ; %bb.0: +; GCN-NEXT: v_maximum_f32 v0, v0, v1 +; GCN-NEXT: ; return to shader part epilog + %val = call nnan float @llvm.maximum.f32(float %a, float %b) + ret float %val +} + +define amdgpu_ps <2 x float> @test_fmaximum_v2f32(<2 x float> %a, <2 x float> %b) { +; GCN-LABEL: test_fmaximum_v2f32: +; GCN: ; %bb.0: +; GCN-NEXT: v_maximum_f32 v0, v0, v2 +; GCN-NEXT: v_maximum_f32 v1, v1, v3 +; GCN-NEXT: ; return to shader part epilog + %val = call <2 x float> @llvm.maximum.v2f32(<2 x float> %a, <2 x float> %b) + ret <2 x float> %val +} + +define amdgpu_ps <2 x float> @test_fmaximum_v2f32_ss(<2 x float> inreg %a, <2 x float> inreg %b) { +; GCN-LABEL: test_fmaximum_v2f32_ss: +; GCN: ; %bb.0: +; GCN-NEXT: s_maximum_f32 s0, s0, s2 +; GCN-NEXT: s_maximum_f32 s1, s1, s3 +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GCN-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GCN-NEXT: ; return to shader part epilog + %val = call <2 x float> @llvm.maximum.v2f32(<2 x float> %a, <2 x float> %b) + ret <2 x float> %val +} + +define amdgpu_ps <3 x float> @test_fmaximum_v3f32(<3 x float> %a, <3 x float> %b) { +; GCN-LABEL: test_fmaximum_v3f32: +; GCN: ; %bb.0: +; GCN-NEXT: v_maximum_f32 v0, v0, v3 +; GCN-NEXT: v_maximum_f32 v1, v1, v4 +; GCN-NEXT: v_maximum_f32 v2, v2, v5 +; GCN-NEXT: ; return to shader part epilog + %val = call <3 x float> @llvm.maximum.v3f32(<3 x float> %a, <3 x float> %b) + ret <3 x float> %val +} + +define amdgpu_ps <4 x float> @test_fmaximum_v4f32(<4 x float> %a, <4 x float> %b) { +; GCN-LABEL: test_fmaximum_v4f32: +; GCN: ; %bb.0: +; GCN-NEXT: v_maximum_f32 v0, v0, v4 +; GCN-NEXT: v_maximum_f32 v1, v1, v5 +; GCN-NEXT: v_maximum_f32 v2, v2, v6 +; GCN-NEXT: v_maximum_f32 v3, v3, v7 +; GCN-NEXT: ; return to shader part epilog + %val = call <4 x float> @llvm.maximum.v4f32(<4 x float> %a, <4 x float> %b) + ret <4 x float> %val +} + +define amdgpu_ps <16 x float> @test_fmaximum_v16f32(<16 x float> %a, <16 x float> %b) { +; GCN-LABEL: test_fmaximum_v16f32: +; GCN: ; %bb.0: +; GCN-NEXT: v_maximum_f32 v0, v0, v16 +; GCN-NEXT: v_maximum_f32 v1, v1, v17 +; GCN-NEXT: v_maximum_f32 v2, v2, v18 +; GCN-NEXT: v_maximum_f32 v3, v3, v19 +; GCN-NEXT: v_maximum_f32 v4, v4, v20 +; GCN-NEXT: v_maximum_f32 v5, v5, v21 +; GCN-NEXT: v_maximum_f32 v6, v6, v22 +; GCN-NEXT: v_maximum_f32 v7, v7, v23 +; GCN-NEXT: v_maximum_f32 v8, v8, v24 +; GCN-NEXT: v_maximum_f32 v9, v9, v25 +; GCN-NEXT: v_maximum_f32 v10, v10, v26 +; GCN-NEXT: v_maximum_f32 v11, v11, v27 +; GCN-NEXT: v_maximum_f32 v12, v12, v28 +; GCN-NEXT: v_maximum_f32 v13, v13, v29 +; GCN-NEXT: v_maximum_f32 v14, v14, v30 +; GCN-NEXT: v_maximum_f32 v15, v15, v31 +; GCN-NEXT: ; return to shader part epilog + %val = call <16 x float> @llvm.maximum.v16f32(<16 x float> %a, <16 x float> %b) + ret <16 x float> %val +} + +define amdgpu_ps half @test_fmaximum_f16_vv(half %a, half %b) { +; GCN-LABEL: test_fmaximum_f16_vv: +; GCN: ; %bb.0: +; GCN-NEXT: v_maximum_f16 v0, v0, v1 +; GCN-NEXT: ; return to shader part epilog + %val = call half @llvm.maximum.f16(half %a, half %b) + ret half %val +} + +define amdgpu_ps half @test_fmaximum_f16_ss(half inreg %a, half inreg %b) { +; GCN-LABEL: test_fmaximum_f16_ss: +; GCN: ; %bb.0: +; GCN-NEXT: s_maximum_f16 s0, s0, s1 +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: ; return to shader part epilog + %val = call half @llvm.maximum.f16(half %a, half %b) + ret half %val +} + +define amdgpu_ps <2 x half> @test_fmaximum_v2f16_vv(<2 x half> %a, <2 x half> %b) { +; GCN-LABEL: test_fmaximum_v2f16_vv: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_maximum_f16 v0, v0, v1 +; GCN-NEXT: ; return to shader part epilog + %val = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b) + ret <2 x half> %val +} + +define amdgpu_ps <2 x half> @test_fmaximum_v2f16_ss(<2 x half> inreg %a, <2 x half> inreg %b) { +; GCN-LABEL: test_fmaximum_v2f16_ss: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_maximum_f16 v0, s0, s1 +; GCN-NEXT: ; return to shader part epilog + %val = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b) + ret <2 x half> %val +} + +define amdgpu_ps <3 x half> @test_fmaximum_v3f16_vv(<3 x half> %a, <3 x half> %b) { +; GCN-LABEL: test_fmaximum_v3f16_vv: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_maximum_f16 v0, v0, v2 +; GCN-NEXT: v_maximum_f16 v1, v1, v3 +; GCN-NEXT: ; return to shader part epilog + %val = call <3 x half> @llvm.maximum.v3f16(<3 x half> %a, <3 x half> %b) + ret <3 x half> %val +} + +define amdgpu_ps <3 x half> @test_fmaximum_v3f16_ss(<3 x half> inreg %a, <3 x half> inreg %b) { +; GCN-LABEL: test_fmaximum_v3f16_ss: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_maximum_f16 v0, s0, s2 +; GCN-NEXT: s_maximum_f16 s0, s1, s3 +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: ; return to shader part epilog + %val = call <3 x half> @llvm.maximum.v3f16(<3 x half> %a, <3 x half> %b) + ret <3 x half> %val +} + +define amdgpu_ps <4 x half> @test_fmaximum_v4f16(<4 x half> %a, <4 x half> %b) { +; GCN-LABEL: test_fmaximum_v4f16: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_maximum_f16 v0, v0, v2 +; GCN-NEXT: v_pk_maximum_f16 v1, v1, v3 +; GCN-NEXT: ; return to shader part epilog + %val = call <4 x half> @llvm.maximum.v4f16(<4 x half> %a, <4 x half> %b) + ret <4 x half> %val +} + +define amdgpu_ps <4 x half> @test_fmaximum_v4f16_ss(<4 x half> inreg %a, <4 x half> inreg %b) { +; GCN-LABEL: test_fmaximum_v4f16_ss: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_maximum_f16 v0, s0, s2 +; GCN-NEXT: v_pk_maximum_f16 v1, s1, s3 +; GCN-NEXT: ; return to shader part epilog + %val = call <4 x half> @llvm.maximum.v4f16(<4 x half> %a, <4 x half> %b) + ret <4 x half> %val +} + +define amdgpu_ps <2 x float> @test_fmaximum_f64_vv(double %a, double %b) { +; GCN-LABEL: test_fmaximum_f64_vv: +; GCN: ; %bb.0: +; GCN-NEXT: v_maximum_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: ; return to shader part epilog + %val = call double @llvm.maximum.f64(double %a, double %b) + %ret = bitcast double %val to <2 x float> + ret <2 x float> %ret +} + +define amdgpu_ps <2 x float> @test_fmaximum_f64_ss(double inreg %a, double inreg %b) { +; GCN-LABEL: test_fmaximum_f64_ss: +; GCN: ; %bb.0: +; GCN-NEXT: v_maximum_f64 v[0:1], s[0:1], s[2:3] +; GCN-NEXT: ; return to shader part epilog + %val = call double @llvm.maximum.f64(double %a, double %b) + %ret = bitcast double %val to <2 x float> + ret <2 x float> %ret +} + +define amdgpu_ps <4 x float> @test_fmaximum_v2f64_ss(<2 x double> inreg %a, <2 x double> inreg %b) { +; GCN-LABEL: test_fmaximum_v2f64_ss: +; GCN: ; %bb.0: +; GCN-NEXT: v_maximum_f64 v[0:1], s[0:1], s[4:5] +; GCN-NEXT: v_maximum_f64 v[2:3], s[2:3], s[6:7] +; GCN-NEXT: ; return to shader part epilog + %val = call <2 x double> @llvm.maximum.v2f64(<2 x double> %a, <2 x double> %b) + %ret = bitcast <2 x double> %val to <4 x float> + ret <4 x float> %ret +} + +define amdgpu_ps <8 x float> @test_fmaximum_v4f64(<4 x double> %a, <4 x double> %b) { +; GCN-LABEL: test_fmaximum_v4f64: +; GCN: ; %bb.0: +; GCN-NEXT: v_maximum_f64 v[0:1], v[0:1], v[8:9] +; GCN-NEXT: v_maximum_f64 v[2:3], v[2:3], v[10:11] +; GCN-NEXT: v_maximum_f64 v[4:5], v[4:5], v[12:13] +; GCN-NEXT: v_maximum_f64 v[6:7], v[6:7], v[14:15] +; GCN-NEXT: ; return to shader part epilog + %val = call <4 x double> @llvm.maximum.v4f64(<4 x double> %a, <4 x double> %b) + %ret = bitcast <4 x double> %val to <8 x float> + ret <8 x float> %ret +} + +define amdgpu_ps <8 x float> @test_fmaximum_v4f64_ss(<4 x double> inreg %a, <4 x double> inreg %b) { +; GCN-LABEL: test_fmaximum_v4f64_ss: +; GCN: ; %bb.0: +; GCN-NEXT: v_maximum_f64 v[0:1], s[0:1], s[8:9] +; GCN-NEXT: v_maximum_f64 v[2:3], s[2:3], s[10:11] +; GCN-NEXT: v_maximum_f64 v[4:5], s[4:5], s[12:13] +; GCN-NEXT: v_maximum_f64 v[6:7], s[6:7], s[14:15] +; GCN-NEXT: ; return to shader part epilog + %val = call <4 x double> @llvm.maximum.v4f64(<4 x double> %a, <4 x double> %b) + %ret = bitcast <4 x double> %val to <8 x float> + ret <8 x float> %ret +} + +define amdgpu_kernel void @fmaximumi_f32_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GCN-LABEL: fmaximumi_f32_move_to_valu: +; GCN: ; %bb.0: +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_load_b32 v1, v0, s[6:7] th:TH_LOAD_RT_NT +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: global_load_b32 v2, v0, s[0:1] th:TH_LOAD_RT_NT +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_maximum_f32 v1, v1, v2 +; GCN-NEXT: global_store_b32 v0, v1, s[4:5] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm + %a = load volatile float, ptr addrspace(1) %aptr, align 4 + %b = load volatile float, ptr addrspace(1) %bptr, align 4 + %v = call float @llvm.maximum.f32(float %a, float %b) + store float %v, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GCN-LABEL: fmaximum_f16_move_to_valu: +; GCN: ; %bb.0: +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_load_u16 v1, v0, s[6:7] th:TH_LOAD_RT_NT +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: global_load_u16 v2, v0, s[0:1] th:TH_LOAD_RT_NT +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_maximum_f16 v1, v1, v2 +; GCN-NEXT: global_store_b16 v0, v1, s[4:5] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm + %a = load volatile half, ptr addrspace(1) %aptr, align 4 + %b = load volatile half, ptr addrspace(1) %bptr, align 4 + %v = call half @llvm.maximum.f16(half %a, half %b) + store half %v, ptr addrspace(1) %out, align 4 + ret void +} + +declare float @llvm.maximum.f32(float, float) +declare <2 x float> @llvm.maximum.v2f32(<2 x float>, <2 x float>) +declare <3 x float> @llvm.maximum.v3f32(<3 x float>, <3 x float>) +declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>) +declare <16 x float> @llvm.maximum.v16f32(<16 x float>, <16 x float>) +declare half @llvm.maximum.f16(half, half) +declare <2 x half> @llvm.maximum.v2f16(<2 x half>, <2 x half>) +declare <3 x half> @llvm.maximum.v3f16(<3 x half>, <3 x half>) +declare <4 x half> @llvm.maximum.v4f16(<4 x half>, <4 x half>) +declare double @llvm.maximum.f64(double, double) +declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>) +declare <4 x double> @llvm.maximum.v4f64(<4 x double>, <4 x double>) +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX12-GISEL: {{.*}} +; GFX12-SDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll new file mode 100644 index 000000000000..2d057e6feac4 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll @@ -0,0 +1,98 @@ +; RUN: llc -march=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s + +; GCN-LABEL: {{^}}test_fmaximum3_olt_0_f32: +; GCN: buffer_load_b32 [[REGC:v[0-9]+]] +; GCN: buffer_load_b32 [[REGB:v[0-9]+]] +; GCN: buffer_load_b32 [[REGA:v[0-9]+]] +; GCN: v_maximum3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]] +; GCN: buffer_store_b32 [[RESULT]], +define amdgpu_kernel void @test_fmaximum3_olt_0_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) { + %a = load volatile float, ptr addrspace(1) %aptr, align 4 + %b = load volatile float, ptr addrspace(1) %bptr, align 4 + %c = load volatile float, ptr addrspace(1) %cptr, align 4 + %f0 = call float @llvm.maximum.f32(float %a, float %b) + %f1 = call float @llvm.maximum.f32(float %f0, float %c) + store float %f1, ptr addrspace(1) %out, align 4 + ret void +} + +; Commute operand of second fmaximum +; GCN-LABEL: {{^}}test_fmaximum3_olt_1_f32: +; GCN: buffer_load_b32 [[REGB:v[0-9]+]] +; GCN: buffer_load_b32 [[REGA:v[0-9]+]] +; GCN: buffer_load_b32 [[REGC:v[0-9]+]] +; GCN: v_maximum3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]] +; GCN: buffer_store_b32 [[RESULT]], +define amdgpu_kernel void @test_fmaximum3_olt_1_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) { + %a = load volatile float, ptr addrspace(1) %aptr, align 4 + %b = load volatile float, ptr addrspace(1) %bptr, align 4 + %c = load volatile float, ptr addrspace(1) %cptr, align 4 + %f0 = call float @llvm.maximum.f32(float %a, float %b) + %f1 = call float @llvm.maximum.f32(float %c, float %f0) + store float %f1, ptr addrspace(1) %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}test_fmaximum3_olt_0_f16: +; GCN: buffer_load_u16 [[REGC:v[0-9]+]] +; GCN: buffer_load_u16 [[REGB:v[0-9]+]] +; GCN: buffer_load_u16 [[REGA:v[0-9]+]] +; GCN: v_maximum3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]] +; GCN: buffer_store_b16 [[RESULT]], +define amdgpu_kernel void @test_fmaximum3_olt_0_f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) { + %a = load volatile half, ptr addrspace(1) %aptr, align 2 + %b = load volatile half, ptr addrspace(1) %bptr, align 2 + %c = load volatile half, ptr addrspace(1) %cptr, align 2 + %f0 = call half @llvm.maximum.f16(half %a, half %b) + %f1 = call half @llvm.maximum.f16(half %f0, half %c) + store half %f1, ptr addrspace(1) %out, align 2 + ret void +} + +; GCN-LABEL: {{^}}test_fmaximum3_olt_1_f16: +; GCN: buffer_load_u16 [[REGA:v[0-9]+]] +; GCN: buffer_load_u16 [[REGB:v[0-9]+]] +; GCN: buffer_load_u16 [[REGC:v[0-9]+]] +; GCN: v_maximum3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGA]], [[REGB]] +; GCN: buffer_store_b16 [[RESULT]], +define amdgpu_kernel void @test_fmaximum3_olt_1_f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) { + %a = load volatile half, ptr addrspace(1) %aptr, align 2 + %b = load volatile half, ptr addrspace(1) %bptr, align 2 + %c = load volatile half, ptr addrspace(1) %cptr, align 2 + %f0 = call half @llvm.maximum.f16(half %a, half %b) + %f1 = call half @llvm.maximum.f16(half %c, half %f0) + store half %f1, ptr addrspace(1) %out, align 2 + ret void +} + +; Checks whether the test passes; performMinMaxCombine() should not optimize vector patterns of maximum3 +; since there are no pack instructions for fmaximum3. +; GCN-LABEL: {{^}}no_fmaximum3_v2f16: +; GCN: v_pk_maximum_f16 v0, v0, v1 +; GCN: v_pk_maximum_f16 v0, v2, v0 +; GCN: v_pk_maximum_f16 v0, v0, v3 +; GCN-NEXT: s_setpc_b64 +define <2 x half> @no_fmaximum3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) { +entry: + %max = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %b) + %max1 = call <2 x half> @llvm.maximum.v2f16(<2 x half> %c, <2 x half> %max) + %res = call <2 x half> @llvm.maximum.v2f16(<2 x half> %max1, <2 x half> %d) + ret <2 x half> %res +} + +; GCN-LABEL: {{^}}no_fmaximum3_olt_0_f64: +; GCN-COUNT-2: v_maximum_f64 +define amdgpu_kernel void @no_fmaximum3_olt_0_f64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) { + %a = load volatile double, ptr addrspace(1) %aptr, align 4 + %b = load volatile double, ptr addrspace(1) %bptr, align 4 + %c = load volatile double, ptr addrspace(1) %cptr, align 4 + %f0 = call double @llvm.maximum.f64(double %a, double %b) + %f1 = call double @llvm.maximum.f64(double %f0, double %c) + store double %f1, ptr addrspace(1) %out, align 4 + ret void +} + +declare double @llvm.maximum.f64(double, double) +declare float @llvm.maximum.f32(float, float) +declare half @llvm.maximum.f16(half, half) +declare <2 x half> @llvm.maximum.v2f16(<2 x half>, <2 x half>) diff --git a/llvm/test/CodeGen/AMDGPU/fminimum.ll b/llvm/test/CodeGen/AMDGPU/fminimum.ll new file mode 100644 index 000000000000..b63a4fa40b59 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/fminimum.ll @@ -0,0 +1,311 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-SDAG %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX12-GISEL %s + +define amdgpu_ps float @test_fminimum_f32_vv(float %a, float %b) { +; GCN-LABEL: test_fminimum_f32_vv: +; GCN: ; %bb.0: +; GCN-NEXT: v_minimum_f32 v0, v0, v1 +; GCN-NEXT: ; return to shader part epilog + %val = call float @llvm.minimum.f32(float %a, float %b) + ret float %val +} + +define amdgpu_ps float @test_fminimum_f32_ss(float inreg %a, float inreg %b) { +; GCN-LABEL: test_fminimum_f32_ss: +; GCN: ; %bb.0: +; GCN-NEXT: s_minimum_f32 s0, s0, s1 +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: ; return to shader part epilog + %val = call float @llvm.minimum.f32(float %a, float %b) + ret float %val +} + +define amdgpu_ps float @test_fminimum_f32_vs(float %a, float inreg %b) { +; GCN-LABEL: test_fminimum_f32_vs: +; GCN: ; %bb.0: +; GCN-NEXT: v_minimum_f32 v0, v0, s0 +; GCN-NEXT: ; return to shader part epilog + %val = call float @llvm.minimum.f32(float %a, float %b) + ret float %val +} + +define amdgpu_ps float @test_fminimum_nnan_f32(float %a, float %b) { +; GCN-LABEL: test_fminimum_nnan_f32: +; GCN: ; %bb.0: +; GCN-NEXT: v_minimum_f32 v0, v0, v1 +; GCN-NEXT: ; return to shader part epilog + %val = call nnan float @llvm.minimum.f32(float %a, float %b) + ret float %val +} + +define amdgpu_ps <2 x float> @test_fminimum_v2f32(<2 x float> %a, <2 x float> %b) { +; GCN-LABEL: test_fminimum_v2f32: +; GCN: ; %bb.0: +; GCN-NEXT: v_minimum_f32 v0, v0, v2 +; GCN-NEXT: v_minimum_f32 v1, v1, v3 +; GCN-NEXT: ; return to shader part epilog + %val = call <2 x float> @llvm.minimum.v2f32(<2 x float> %a, <2 x float> %b) + ret <2 x float> %val +} + +define amdgpu_ps <2 x float> @test_fminimum_v2f32_ss(<2 x float> inreg %a, <2 x float> inreg %b) { +; GCN-LABEL: test_fminimum_v2f32_ss: +; GCN: ; %bb.0: +; GCN-NEXT: s_minimum_f32 s0, s0, s2 +; GCN-NEXT: s_minimum_f32 s1, s1, s3 +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GCN-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GCN-NEXT: ; return to shader part epilog + %val = call <2 x float> @llvm.minimum.v2f32(<2 x float> %a, <2 x float> %b) + ret <2 x float> %val +} + +define amdgpu_ps <3 x float> @test_fminimum_v3f32(<3 x float> %a, <3 x float> %b) { +; GCN-LABEL: test_fminimum_v3f32: +; GCN: ; %bb.0: +; GCN-NEXT: v_minimum_f32 v0, v0, v3 +; GCN-NEXT: v_minimum_f32 v1, v1, v4 +; GCN-NEXT: v_minimum_f32 v2, v2, v5 +; GCN-NEXT: ; return to shader part epilog + %val = call <3 x float> @llvm.minimum.v3f32(<3 x float> %a, <3 x float> %b) + ret <3 x float> %val +} + +define amdgpu_ps <4 x float> @test_fminimum_v4f32(<4 x float> %a, <4 x float> %b) { +; GCN-LABEL: test_fminimum_v4f32: +; GCN: ; %bb.0: +; GCN-NEXT: v_minimum_f32 v0, v0, v4 +; GCN-NEXT: v_minimum_f32 v1, v1, v5 +; GCN-NEXT: v_minimum_f32 v2, v2, v6 +; GCN-NEXT: v_minimum_f32 v3, v3, v7 +; GCN-NEXT: ; return to shader part epilog + %val = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> %b) + ret <4 x float> %val +} + +define amdgpu_ps <16 x float> @test_fminimum_v16f32(<16 x float> %a, <16 x float> %b) { +; GCN-LABEL: test_fminimum_v16f32: +; GCN: ; %bb.0: +; GCN-NEXT: v_minimum_f32 v0, v0, v16 +; GCN-NEXT: v_minimum_f32 v1, v1, v17 +; GCN-NEXT: v_minimum_f32 v2, v2, v18 +; GCN-NEXT: v_minimum_f32 v3, v3, v19 +; GCN-NEXT: v_minimum_f32 v4, v4, v20 +; GCN-NEXT: v_minimum_f32 v5, v5, v21 +; GCN-NEXT: v_minimum_f32 v6, v6, v22 +; GCN-NEXT: v_minimum_f32 v7, v7, v23 +; GCN-NEXT: v_minimum_f32 v8, v8, v24 +; GCN-NEXT: v_minimum_f32 v9, v9, v25 +; GCN-NEXT: v_minimum_f32 v10, v10, v26 +; GCN-NEXT: v_minimum_f32 v11, v11, v27 +; GCN-NEXT: v_minimum_f32 v12, v12, v28 +; GCN-NEXT: v_minimum_f32 v13, v13, v29 +; GCN-NEXT: v_minimum_f32 v14, v14, v30 +; GCN-NEXT: v_minimum_f32 v15, v15, v31 +; GCN-NEXT: ; return to shader part epilog + %val = call <16 x float> @llvm.minimum.v16f32(<16 x float> %a, <16 x float> %b) + ret <16 x float> %val +} + +define amdgpu_ps half @test_fminimum_f16_vv(half %a, half %b) { +; GCN-LABEL: test_fminimum_f16_vv: +; GCN: ; %bb.0: +; GCN-NEXT: v_minimum_f16 v0, v0, v1 +; GCN-NEXT: ; return to shader part epilog + %val = call half @llvm.minimum.f16(half %a, half %b) + ret half %val +} + +define amdgpu_ps half @test_fminimum_f16_ss(half inreg %a, half inreg %b) { +; GCN-LABEL: test_fminimum_f16_ss: +; GCN: ; %bb.0: +; GCN-NEXT: s_minimum_f16 s0, s0, s1 +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: ; return to shader part epilog + %val = call half @llvm.minimum.f16(half %a, half %b) + ret half %val +} + +define amdgpu_ps <2 x half> @test_fminimum_v2f16_vv(<2 x half> %a, <2 x half> %b) { +; GCN-LABEL: test_fminimum_v2f16_vv: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_minimum_f16 v0, v0, v1 +; GCN-NEXT: ; return to shader part epilog + %val = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %b) + ret <2 x half> %val +} + +define amdgpu_ps <2 x half> @test_fminimum_v2f16_ss(<2 x half> inreg %a, <2 x half> inreg %b) { +; GCN-LABEL: test_fminimum_v2f16_ss: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_minimum_f16 v0, s0, s1 +; GCN-NEXT: ; return to shader part epilog + %val = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %b) + ret <2 x half> %val +} + +define amdgpu_ps <3 x half> @test_fminimum_v3f16_vv(<3 x half> %a, <3 x half> %b) { +; GCN-LABEL: test_fminimum_v3f16_vv: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_minimum_f16 v0, v0, v2 +; GCN-NEXT: v_minimum_f16 v1, v1, v3 +; GCN-NEXT: ; return to shader part epilog + %val = call <3 x half> @llvm.minimum.v3f16(<3 x half> %a, <3 x half> %b) + ret <3 x half> %val +} + +define amdgpu_ps <3 x half> @test_fminimum_v3f16_ss(<3 x half> inreg %a, <3 x half> inreg %b) { +; GCN-LABEL: test_fminimum_v3f16_ss: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_minimum_f16 v0, s0, s2 +; GCN-NEXT: s_minimum_f16 s0, s1, s3 +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: ; return to shader part epilog + %val = call <3 x half> @llvm.minimum.v3f16(<3 x half> %a, <3 x half> %b) + ret <3 x half> %val +} + +define amdgpu_ps <4 x half> @test_fminimum_v4f16(<4 x half> %a, <4 x half> %b) { +; GCN-LABEL: test_fminimum_v4f16: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_minimum_f16 v0, v0, v2 +; GCN-NEXT: v_pk_minimum_f16 v1, v1, v3 +; GCN-NEXT: ; return to shader part epilog + %val = call <4 x half> @llvm.minimum.v4f16(<4 x half> %a, <4 x half> %b) + ret <4 x half> %val +} + +define amdgpu_ps <4 x half> @test_fminimum_v4f16_ss(<4 x half> inreg %a, <4 x half> inreg %b) { +; GCN-LABEL: test_fminimum_v4f16_ss: +; GCN: ; %bb.0: +; GCN-NEXT: v_pk_minimum_f16 v0, s0, s2 +; GCN-NEXT: v_pk_minimum_f16 v1, s1, s3 +; GCN-NEXT: ; return to shader part epilog + %val = call <4 x half> @llvm.minimum.v4f16(<4 x half> %a, <4 x half> %b) + ret <4 x half> %val +} + +define amdgpu_ps <2 x float> @test_fminimum_f64_vv(double %a, double %b) { +; GCN-LABEL: test_fminimum_f64_vv: +; GCN: ; %bb.0: +; GCN-NEXT: v_minimum_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: ; return to shader part epilog + %val = call double @llvm.minimum.f64(double %a, double %b) + %ret = bitcast double %val to <2 x float> + ret <2 x float> %ret +} + +define amdgpu_ps <2 x float> @test_fminimum_f64_ss(double inreg %a, double inreg %b) { +; GCN-LABEL: test_fminimum_f64_ss: +; GCN: ; %bb.0: +; GCN-NEXT: v_minimum_f64 v[0:1], s[0:1], s[2:3] +; GCN-NEXT: ; return to shader part epilog + %val = call double @llvm.minimum.f64(double %a, double %b) + %ret = bitcast double %val to <2 x float> + ret <2 x float> %ret +} + +define amdgpu_ps <4 x float> @test_fminimum_v2f64_ss(<2 x double> inreg %a, <2 x double> inreg %b) { +; GCN-LABEL: test_fminimum_v2f64_ss: +; GCN: ; %bb.0: +; GCN-NEXT: v_minimum_f64 v[0:1], s[0:1], s[4:5] +; GCN-NEXT: v_minimum_f64 v[2:3], s[2:3], s[6:7] +; GCN-NEXT: ; return to shader part epilog + %val = call <2 x double> @llvm.minimum.v2f64(<2 x double> %a, <2 x double> %b) + %ret = bitcast <2 x double> %val to <4 x float> + ret <4 x float> %ret +} + +define amdgpu_ps <8 x float> @test_fminimum_v4f64(<4 x double> %a, <4 x double> %b) { +; GCN-LABEL: test_fminimum_v4f64: +; GCN: ; %bb.0: +; GCN-NEXT: v_minimum_f64 v[0:1], v[0:1], v[8:9] +; GCN-NEXT: v_minimum_f64 v[2:3], v[2:3], v[10:11] +; GCN-NEXT: v_minimum_f64 v[4:5], v[4:5], v[12:13] +; GCN-NEXT: v_minimum_f64 v[6:7], v[6:7], v[14:15] +; GCN-NEXT: ; return to shader part epilog + %val = call <4 x double> @llvm.minimum.v4f64(<4 x double> %a, <4 x double> %b) + %ret = bitcast <4 x double> %val to <8 x float> + ret <8 x float> %ret +} + +define amdgpu_ps <8 x float> @test_fminimum_v4f64_ss(<4 x double> inreg %a, <4 x double> inreg %b) { +; GCN-LABEL: test_fminimum_v4f64_ss: +; GCN: ; %bb.0: +; GCN-NEXT: v_minimum_f64 v[0:1], s[0:1], s[8:9] +; GCN-NEXT: v_minimum_f64 v[2:3], s[2:3], s[10:11] +; GCN-NEXT: v_minimum_f64 v[4:5], s[4:5], s[12:13] +; GCN-NEXT: v_minimum_f64 v[6:7], s[6:7], s[14:15] +; GCN-NEXT: ; return to shader part epilog + %val = call <4 x double> @llvm.minimum.v4f64(<4 x double> %a, <4 x double> %b) + %ret = bitcast <4 x double> %val to <8 x float> + ret <8 x float> %ret +} + +define amdgpu_kernel void @fminimumi_f32_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GCN-LABEL: fminimumi_f32_move_to_valu: +; GCN: ; %bb.0: +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_load_b32 v1, v0, s[6:7] th:TH_LOAD_RT_NT +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: global_load_b32 v2, v0, s[0:1] th:TH_LOAD_RT_NT +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_minimum_f32 v1, v1, v2 +; GCN-NEXT: global_store_b32 v0, v1, s[4:5] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm + %a = load volatile float, ptr addrspace(1) %aptr, align 4 + %b = load volatile float, ptr addrspace(1) %bptr, align 4 + %v = call float @llvm.minimum.f32(float %a, float %b) + store float %v, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_kernel void @fminimum_f16_move_to_valu(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr) { +; GCN-LABEL: fminimum_f16_move_to_valu: +; GCN: ; %bb.0: +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_load_u16 v1, v0, s[6:7] th:TH_LOAD_RT_NT +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: global_load_u16 v2, v0, s[0:1] th:TH_LOAD_RT_NT +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_minimum_f16 v1, v1, v2 +; GCN-NEXT: global_store_b16 v0, v1, s[4:5] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm + %a = load volatile half, ptr addrspace(1) %aptr, align 4 + %b = load volatile half, ptr addrspace(1) %bptr, align 4 + %v = call half @llvm.minimum.f16(half %a, half %b) + store half %v, ptr addrspace(1) %out, align 4 + ret void +} + +declare float @llvm.minimum.f32(float, float) +declare <2 x float> @llvm.minimum.v2f32(<2 x float>, <2 x float>) +declare <3 x float> @llvm.minimum.v3f32(<3 x float>, <3 x float>) +declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>) +declare <16 x float> @llvm.minimum.v16f32(<16 x float>, <16 x float>) +declare half @llvm.minimum.f16(half, half) +declare <2 x half> @llvm.minimum.v2f16(<2 x half>, <2 x half>) +declare <3 x half> @llvm.minimum.v3f16(<3 x half>, <3 x half>) +declare <4 x half> @llvm.minimum.v4f16(<4 x half>, <4 x half>) +declare double @llvm.minimum.f64(double, double) +declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>) +declare <4 x double> @llvm.minimum.v4f64(<4 x double>, <4 x double>) +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX12-GISEL: {{.*}} +; GFX12-SDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/fminimum3.ll b/llvm/test/CodeGen/AMDGPU/fminimum3.ll new file mode 100644 index 000000000000..e28b32403215 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/fminimum3.ll @@ -0,0 +1,98 @@ +; RUN: llc -march=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN %s + +; GCN-LABEL: {{^}}test_fminimum3_olt_0_f32: +; GCN: buffer_load_b32 [[REGC:v[0-9]+]] +; GCN: buffer_load_b32 [[REGB:v[0-9]+]] +; GCN: buffer_load_b32 [[REGA:v[0-9]+]] +; GCN: v_minimum3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]] +; GCN: buffer_store_b32 [[RESULT]], +define amdgpu_kernel void @test_fminimum3_olt_0_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) { + %a = load volatile float, ptr addrspace(1) %aptr, align 4 + %b = load volatile float, ptr addrspace(1) %bptr, align 4 + %c = load volatile float, ptr addrspace(1) %cptr, align 4 + %f0 = call float @llvm.minimum.f32(float %a, float %b) + %f1 = call float @llvm.minimum.f32(float %f0, float %c) + store float %f1, ptr addrspace(1) %out, align 4 + ret void +} + +; Commute operand of second fminimum +; GCN-LABEL: {{^}}test_fminimum3_olt_1_f32: +; GCN: buffer_load_b32 [[REGB:v[0-9]+]] +; GCN: buffer_load_b32 [[REGA:v[0-9]+]] +; GCN: buffer_load_b32 [[REGC:v[0-9]+]] +; GCN: v_minimum3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]] +; GCN: buffer_store_b32 [[RESULT]], +define amdgpu_kernel void @test_fminimum3_olt_1_f32(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) { + %a = load volatile float, ptr addrspace(1) %aptr, align 4 + %b = load volatile float, ptr addrspace(1) %bptr, align 4 + %c = load volatile float, ptr addrspace(1) %cptr, align 4 + %f0 = call float @llvm.minimum.f32(float %a, float %b) + %f1 = call float @llvm.minimum.f32(float %c, float %f0) + store float %f1, ptr addrspace(1) %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}test_fminimum3_olt_0_f16: +; GCN: buffer_load_u16 [[REGC:v[0-9]+]] +; GCN: buffer_load_u16 [[REGB:v[0-9]+]] +; GCN: buffer_load_u16 [[REGA:v[0-9]+]] +; GCN: v_minimum3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]] +; GCN: buffer_store_b16 [[RESULT]], +define amdgpu_kernel void @test_fminimum3_olt_0_f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) { + %a = load volatile half, ptr addrspace(1) %aptr, align 2 + %b = load volatile half, ptr addrspace(1) %bptr, align 2 + %c = load volatile half, ptr addrspace(1) %cptr, align 2 + %f0 = call half @llvm.minimum.f16(half %a, half %b) + %f1 = call half @llvm.minimum.f16(half %f0, half %c) + store half %f1, ptr addrspace(1) %out, align 2 + ret void +} + +; GCN-LABEL: {{^}}test_fminimum3_olt_1_f16: +; GCN: buffer_load_u16 [[REGA:v[0-9]+]] +; GCN: buffer_load_u16 [[REGB:v[0-9]+]] +; GCN: buffer_load_u16 [[REGC:v[0-9]+]] +; GCN: v_minimum3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGA]], [[REGB]] +; GCN: buffer_store_b16 [[RESULT]], +define amdgpu_kernel void @test_fminimum3_olt_1_f16(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) { + %a = load volatile half, ptr addrspace(1) %aptr, align 2 + %b = load volatile half, ptr addrspace(1) %bptr, align 2 + %c = load volatile half, ptr addrspace(1) %cptr, align 2 + %f0 = call half @llvm.minimum.f16(half %a, half %b) + %f1 = call half @llvm.minimum.f16(half %c, half %f0) + store half %f1, ptr addrspace(1) %out, align 2 + ret void +} + +; Checks whether the test passes; performMinMaxCombine() should not optimize vector patterns of minimum3 +; since there are no pack instructions for fminimum3. +; GCN-LABEL: {{^}}no_fminimum3_v2f16: +; GCN: v_pk_minimum_f16 v0, v0, v1 +; GCN: v_pk_minimum_f16 v0, v2, v0 +; GCN: v_pk_minimum_f16 v0, v0, v3 +; GCN-NEXT: s_setpc_b64 +define <2 x half> @no_fminimum3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) { +entry: + %min = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %b) + %min1 = call <2 x half> @llvm.minimum.v2f16(<2 x half> %c, <2 x half> %min) + %res = call <2 x half> @llvm.minimum.v2f16(<2 x half> %min1, <2 x half> %d) + ret <2 x half> %res +} + +; GCN-LABEL: {{^}}no_fminimum3_olt_0_f64: +; GCN-COUNT-2: v_minimum_f64 +define amdgpu_kernel void @no_fminimum3_olt_0_f64(ptr addrspace(1) %out, ptr addrspace(1) %aptr, ptr addrspace(1) %bptr, ptr addrspace(1) %cptr) { + %a = load volatile double, ptr addrspace(1) %aptr, align 4 + %b = load volatile double, ptr addrspace(1) %bptr, align 4 + %c = load volatile double, ptr addrspace(1) %cptr, align 4 + %f0 = call double @llvm.minimum.f64(double %a, double %b) + %f1 = call double @llvm.minimum.f64(double %f0, double %c) + store double %f1, ptr addrspace(1) %out, align 4 + ret void +} + +declare double @llvm.minimum.f64(double, double) +declare float @llvm.minimum.f32(float, float) +declare half @llvm.minimum.f16(half, half) +declare <2 x half> @llvm.minimum.v2f16(<2 x half>, <2 x half>) diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll new file mode 100644 index 000000000000..368503725f68 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/fneg-combines-gfx1200.ll @@ -0,0 +1,270 @@ +; RUN: llc -march=amdgcn -mcpu=gfx1200 -start-before=amdgpu-unify-divergent-exit-nodes --verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-SDAG %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1200 -start-before=amdgpu-unify-divergent-exit-nodes --verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-GISEL %s + +; -------------------------------------------------------------------------------- +; fminimum tests +; -------------------------------------------------------------------------------- + +; GCN-LABEL: {{^}}v_fneg_minimum_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: global_load_b32 [[B:v[0-9]+]] +; GCN: v_maximum_f32 [[RESULT:v[0-9]+]], -[[A]], -[[B]] +; GCN: global_store_b32 v[{{[0-9:]+}}], [[RESULT]] +define void @v_fneg_minimum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %b = load volatile float, ptr addrspace(1) %b.gep + %min = call float @llvm.minimum.f32(float %a, float %b) + %fneg = fneg float %min + store float %fneg, ptr addrspace(1) %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_fneg_self_minimum_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: v_maximum_f32 [[RESULT:v[0-9]+]], -[[A]], -[[A]] +; GCN: global_store_b32 v[{{[0-9:]+}}], [[RESULT]] +define void @v_fneg_self_minimum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %min = call float @llvm.minimum.f32(float %a, float %a) + %min.fneg = fneg float %min + store float %min.fneg, ptr addrspace(1) %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_fneg_posk_minimum_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: v_maximum_f32 [[RESULT:v[0-9]+]], -[[A]], -4.0 +; GCN: global_store_b32 v[{{[0-9:]+}}], [[RESULT]] +define void @v_fneg_posk_minimum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %min = call float @llvm.minimum.f32(float %a, float 4.0) + %fneg = fneg float %min + store float %fneg, ptr addrspace(1) %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_fneg_negk_minimum_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: v_maximum_f32 [[RESULT:v[0-9]+]], -[[A]], 4.0 +; GCN: global_store_b32 v[{{[0-9:]+}}], [[RESULT]] +define void @v_fneg_negk_minimum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %min = call float @llvm.minimum.f32(float %a, float -4.0) + %fneg = fneg float %min + store float %fneg, ptr addrspace(1) %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_fneg_0_minimum_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: v_minimum_f32 [[RESULT:v[0-9]+]], [[A]], 0 +; GCN: global_store_b32 v[{{[0-9:]+}}], [[RESULT]] +define void @v_fneg_0_minimum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %min = call float @llvm.minimum.f32(float %a, float 0.0) + %fneg = fneg float %min + store float %fneg, ptr addrspace(1) %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_fneg_0_minimum_foldable_use_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: global_load_b32 [[B:v[0-9]+]] +; GCN: v_minimum_f32 [[MIN:v[0-9]+]], [[A]], 0 +; GCN: v_mul_f32_e64 [[RESULT:v[0-9]+]], -[[MIN]], [[B]] +; GCN: global_store_b32 v[{{[0-9:]+}}], [[RESULT]] +define void @v_fneg_0_minimum_foldable_use_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %b = load volatile float, ptr addrspace(1) %b.gep + %min = call float @llvm.minimum.f32(float %a, float 0.0) + %fneg = fneg float %min + %mul = fmul float %fneg, %b + store float %mul, ptr addrspace(1) %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_fneg_minimum_multi_use_minimum_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: global_load_b32 [[B:v[0-9]+]] +; GCN: v_maximum_f32 [[MAX0:v[0-9]+]], -[[A]], -[[B]] +; GCN-SDAG: v_mul_f32_e32 [[MUL1:v[0-9]+]], -4.0, [[MAX0]] +; GCN-GISEL: v_mul_f32_e64 [[MUL1:v[0-9]+]], -[[MAX0]], 4.0 +; GCN: global_store_b32 v[{{[0-9:]+}}], [[MAX0]] +; GCN: global_store_b32 v[{{[0-9:]+}}], [[MUL1]] +define void @v_fneg_minimum_multi_use_minimum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %b = load volatile float, ptr addrspace(1) %b.gep + %min = call float @llvm.minimum.f32(float %a, float %b) + %fneg = fneg float %min + %use1 = fmul float %min, 4.0 + store volatile float %fneg, ptr addrspace(1) %out + store volatile float %use1, ptr addrspace(1) %out + ret void +} + +; -------------------------------------------------------------------------------- +; fmaximum tests +; -------------------------------------------------------------------------------- + +; GCN-LABEL: {{^}}v_fneg_maximum_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: global_load_b32 [[B:v[0-9]+]] +; GCN: v_minimum_f32 [[RESULT:v[0-9]+]], -[[A]], -[[B]] +; GCN: global_store_b32 v[{{[0-9:]+}}], [[RESULT]] +define void @v_fneg_maximum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %b = load volatile float, ptr addrspace(1) %b.gep + %min = call float @llvm.maximum.f32(float %a, float %b) + %fneg = fneg float %min + store float %fneg, ptr addrspace(1) %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_fneg_self_maximum_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: v_minimum_f32 [[RESULT:v[0-9]+]], -[[A]], -[[A]] +; GCN: global_store_b32 v[{{[0-9:]+}}], [[RESULT]] +define void @v_fneg_self_maximum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %min = call float @llvm.maximum.f32(float %a, float %a) + %min.fneg = fneg float %min + store float %min.fneg, ptr addrspace(1) %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_fneg_posk_maximum_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: v_minimum_f32 [[RESULT:v[0-9]+]], -[[A]], -4.0 +; GCN: global_store_b32 v[{{[0-9:]+}}], [[RESULT]] +define void @v_fneg_posk_maximum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %min = call float @llvm.maximum.f32(float %a, float 4.0) + %fneg = fneg float %min + store float %fneg, ptr addrspace(1) %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_fneg_negk_maximum_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: v_minimum_f32 [[RESULT:v[0-9]+]], -[[A]], 4.0 +; GCN: global_store_b32 v[{{[0-9:]+}}], [[RESULT]] +define void @v_fneg_negk_maximum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %min = call float @llvm.maximum.f32(float %a, float -4.0) + %fneg = fneg float %min + store float %fneg, ptr addrspace(1) %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_fneg_0_maximum_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: v_maximum_f32 [[RESULT:v[0-9]+]], [[A]], 0 +; GCN: global_store_b32 v[{{[0-9:]+}}], [[RESULT]] +define void @v_fneg_0_maximum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %max = call float @llvm.maximum.f32(float %a, float 0.0) + %fneg = fneg float %max + store float %fneg, ptr addrspace(1) %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_fneg_0_maximum_foldable_use_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: global_load_b32 [[B:v[0-9]+]] +; GCN: v_maximum_f32 [[MAX:v[0-9]+]], [[A]], 0 +; GCN: v_mul_f32_e64 [[RESULT:v[0-9]+]], -[[MAX]], [[B]] +; GCN: global_store_b32 v[{{[0-9:]+}}], [[RESULT]] +define void @v_fneg_0_maximum_foldable_use_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %b = load volatile float, ptr addrspace(1) %b.gep + %max = call float @llvm.maximum.f32(float %a, float 0.0) + %fneg = fneg float %max + %mul = fmul float %fneg, %b + store float %mul, ptr addrspace(1) %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_fneg_maximum_multi_use_maximum_f32: +; GCN: global_load_b32 [[A:v[0-9]+]] +; GCN: global_load_b32 [[B:v[0-9]+]] +; GCN: v_minimum_f32 [[MAX0:v[0-9]+]], -[[A]], -[[B]] +; GCN-SDAG: v_mul_f32_e32 [[MUL1:v[0-9]+]], -4.0, [[MAX0]] +; GCN-GISEL: v_mul_f32_e64 [[MUL1:v[0-9]+]], -[[MAX0]], 4.0 +; GCN: global_store_b32 v[{{[0-9:]+}}], [[MAX0]] +; GCN: global_store_b32 v[{{[0-9:]+}}], [[MUL1]] +define void @v_fneg_maximum_multi_use_maximum_f32(ptr addrspace(1) %out, ptr addrspace(1) %a.ptr, ptr addrspace(1) %b.ptr) { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %tid.ext = sext i32 %tid to i64 + %a.gep = getelementptr inbounds float, ptr addrspace(1) %a.ptr, i64 %tid.ext + %b.gep = getelementptr inbounds float, ptr addrspace(1) %b.ptr, i64 %tid.ext + %out.gep = getelementptr inbounds float, ptr addrspace(1) %out, i64 %tid.ext + %a = load volatile float, ptr addrspace(1) %a.gep + %b = load volatile float, ptr addrspace(1) %b.gep + %min = call float @llvm.maximum.f32(float %a, float %b) + %fneg = fneg float %min + %use1 = fmul float %min, 4.0 + store volatile float %fneg, ptr addrspace(1) %out + store volatile float %use1, ptr addrspace(1) %out + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() +declare float @llvm.minimum.f32(float, float) +declare float @llvm.maximum.f32(float, float) diff --git a/llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll b/llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll index 688f0314f7d8..58c6406fac7a 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll @@ -9,15 +9,10 @@ declare void @llvm.amdgcn.global.load.lds(ptr addrspace(1) nocapture %gptr, ptr ; FIXME: vmcnt(0) is too strong, it shall use vmcnt(2) before the first ; ds_read_b32 and vmcnt(0) before the second. -; FIXME: GFX10 does not get a waitcount at all. ; GCN-LABEL: {{^}}buffer_load_lds_dword_2_arrays: ; GCN-COUNT-4: buffer_load_dword -; GFX9: s_waitcnt vmcnt(0) - -; FIXME: -; GFX10-NOT: s_waitcnt - +; GCN: s_waitcnt vmcnt(0) ; GCN: ds_read_b32 ; FIXME: @@ -49,9 +44,9 @@ main_body: ; GFX9: s_waitcnt vmcnt(0) ; GFX9-COUNT-2: ds_read_b32 -; FIXME: -; GFX10-NOT: s_waitcnt +; FIXME: can be vmcnt(2) +; GFX10: s_waitcnt vmcnt(0) ; GFX10: ds_read_b32 ; FIXME: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll index 48c4e0276edd..4e65b3763394 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll @@ -3,6 +3,9 @@ ; RUN: llc -march=amdgcn -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck --check-prefix=VARIANT1 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=VARIANT2 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck --check-prefix=VARIANT3 %s +; RUN: llc -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck --check-prefix=VARIANT4 %s +; RUN: llc -march=amdgcn -mcpu=gfx1200 -mattr=+auto-waitcnt-before-barrier -verify-machineinstrs < %s | FileCheck --check-prefix=VARIANT5 %s +; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck --check-prefix=VARIANT6 %s define amdgpu_kernel void @test_barrier(ptr addrspace(1) %out, i32 %size) #0 { ; VARIANT0-LABEL: test_barrier: @@ -85,6 +88,80 @@ define amdgpu_kernel void @test_barrier(ptr addrspace(1) %out, i32 %size) #0 { ; VARIANT3-NEXT: s_waitcnt vmcnt(0) ; VARIANT3-NEXT: global_store_dword v2, v0, s[2:3] ; VARIANT3-NEXT: s_endpgm +; +; VARIANT4-LABEL: test_barrier: +; VARIANT4: ; %bb.0: ; %entry +; VARIANT4-NEXT: s_clause 0x1 +; VARIANT4-NEXT: s_load_b32 s2, s[0:1], 0x2c +; VARIANT4-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; VARIANT4-NEXT: v_lshlrev_b32_e32 v3, 2, v0 +; VARIANT4-NEXT: s_waitcnt lgkmcnt(0) +; VARIANT4-NEXT: v_xad_u32 v1, v0, -1, s2 +; VARIANT4-NEXT: global_store_b32 v3, v0, s[0:1] +; VARIANT4-NEXT: s_barrier_signal -1 +; VARIANT4-NEXT: s_barrier_wait -1 +; VARIANT4-NEXT: v_ashrrev_i32_e32 v2, 31, v1 +; VARIANT4-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; VARIANT4-NEXT: v_lshlrev_b64_e32 v[1:2], 2, v[1:2] +; VARIANT4-NEXT: v_add_co_u32 v1, vcc_lo, s0, v1 +; VARIANT4-NEXT: s_delay_alu instid0(VALU_DEP_2) +; VARIANT4-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo +; VARIANT4-NEXT: global_load_b32 v0, v[1:2], off +; VARIANT4-NEXT: s_waitcnt vmcnt(0) +; VARIANT4-NEXT: global_store_b32 v3, v0, s[0:1] +; VARIANT4-NEXT: s_nop 0 +; VARIANT4-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; VARIANT4-NEXT: s_endpgm +; +; VARIANT5-LABEL: test_barrier: +; VARIANT5: ; %bb.0: ; %entry +; VARIANT5-NEXT: s_clause 0x1 +; VARIANT5-NEXT: s_load_b32 s2, s[0:1], 0x2c +; VARIANT5-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; VARIANT5-NEXT: v_lshlrev_b32_e32 v3, 2, v0 +; VARIANT5-NEXT: s_waitcnt lgkmcnt(0) +; VARIANT5-NEXT: v_xad_u32 v1, v0, -1, s2 +; VARIANT5-NEXT: global_store_b32 v3, v0, s[0:1] +; VARIANT5-NEXT: s_barrier_signal -1 +; VARIANT5-NEXT: s_barrier_wait -1 +; VARIANT5-NEXT: v_ashrrev_i32_e32 v2, 31, v1 +; VARIANT5-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; VARIANT5-NEXT: v_lshlrev_b64_e32 v[1:2], 2, v[1:2] +; VARIANT5-NEXT: v_add_co_u32 v1, vcc_lo, s0, v1 +; VARIANT5-NEXT: s_delay_alu instid0(VALU_DEP_2) +; VARIANT5-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo +; VARIANT5-NEXT: global_load_b32 v0, v[1:2], off +; VARIANT5-NEXT: s_waitcnt vmcnt(0) +; VARIANT5-NEXT: global_store_b32 v3, v0, s[0:1] +; VARIANT5-NEXT: s_nop 0 +; VARIANT5-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; VARIANT5-NEXT: s_endpgm +; +; VARIANT6-LABEL: test_barrier: +; VARIANT6: ; %bb.0: ; %entry +; VARIANT6-NEXT: s_clause 0x1 +; VARIANT6-NEXT: s_load_b32 s2, s[0:1], 0x2c +; VARIANT6-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; VARIANT6-NEXT: v_lshlrev_b32_e32 v5, 2, v0 +; VARIANT6-NEXT: s_waitcnt lgkmcnt(0) +; VARIANT6-NEXT: s_sub_co_i32 s2, s2, 1 +; VARIANT6-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0 +; VARIANT6-NEXT: v_sub_nc_u32_e32 v1, s2, v0 +; VARIANT6-NEXT: global_store_b32 v5, v0, s[0:1] +; VARIANT6-NEXT: s_barrier_signal -1 +; VARIANT6-NEXT: s_barrier_wait -1 +; VARIANT6-NEXT: v_ashrrev_i32_e32 v2, 31, v1 +; VARIANT6-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; VARIANT6-NEXT: v_lshlrev_b64_e32 v[1:2], 2, v[1:2] +; VARIANT6-NEXT: v_add_co_u32 v1, vcc_lo, v3, v1 +; VARIANT6-NEXT: s_delay_alu instid0(VALU_DEP_2) +; VARIANT6-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo +; VARIANT6-NEXT: global_load_b32 v0, v[1:2], off +; VARIANT6-NEXT: s_waitcnt vmcnt(0) +; VARIANT6-NEXT: global_store_b32 v5, v0, s[0:1] +; VARIANT6-NEXT: s_nop 0 +; VARIANT6-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; VARIANT6-NEXT: s_endpgm entry: %tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll new file mode 100644 index 000000000000..1ad3e58ce7fc --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll @@ -0,0 +1,1366 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s +; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GLOBAL-ISEL %s + +define amdgpu_kernel void @test1_s_barrier_signal(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test1_s_barrier_signal: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v3, v2, s[0:1] +; GCN-NEXT: s_barrier_signal -1 +; GCN-NEXT: s_barrier_wait -1 +; GCN-NEXT: global_store_b32 v3, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test1_s_barrier_signal: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_barrier_signal -1 +; GLOBAL-ISEL-NEXT: s_barrier_wait -1 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.barrier.signal(i32 -1) + call void @llvm.amdgcn.s.barrier.wait(i16 -1) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test2_s_barrier_signal(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test2_s_barrier_signal: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v3, v2, s[0:1] +; GCN-NEXT: s_barrier_signal 1 +; GCN-NEXT: s_barrier_wait 1 +; GCN-NEXT: global_store_b32 v3, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test2_s_barrier_signal: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_barrier_signal 1 +; GLOBAL-ISEL-NEXT: s_barrier_wait 1 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.barrier.signal(i32 1) + call void @llvm.amdgcn.s.barrier.wait(i16 1) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test3_s_barrier_signal(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test3_s_barrier_signal: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v3, v2, s[0:1] +; GCN-NEXT: s_barrier_signal 0 +; GCN-NEXT: s_barrier_wait 0 +; GCN-NEXT: global_store_b32 v3, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test3_s_barrier_signal: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_barrier_signal 0 +; GLOBAL-ISEL-NEXT: s_barrier_wait 0 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.barrier.signal(i32 0) + call void @llvm.amdgcn.s.barrier.wait(i16 0) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test1_s_barrier_signal_var(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test1_s_barrier_signal_var: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v2, v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 2, v0 +; GCN-NEXT: s_mov_b32 m0, 1 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v2, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v3, v1, s[0:1] +; GCN-NEXT: s_barrier_signal m0 +; GCN-NEXT: s_barrier_wait 1 +; GCN-NEXT: global_store_b32 v3, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test1_s_barrier_signal_var: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_mov_b32 m0, 1 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_barrier_signal m0 +; GLOBAL-ISEL-NEXT: s_barrier_wait 1 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.barrier.signal.var(i32 1) + call void @llvm.amdgcn.s.barrier.wait(i16 1) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define void @test2_s_barrier_signal_var(i32 %arg) { +; GCN-LABEL: test2_s_barrier_signal_var: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GCN-NEXT: s_mov_b32 m0, s0 +; GCN-NEXT: s_barrier_signal m0 +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; GLOBAL-ISEL-LABEL: test2_s_barrier_signal_var: +; GLOBAL-ISEL: ; %bb.0: +; GLOBAL-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 m0, v0 +; GLOBAL-ISEL-NEXT: s_barrier_signal m0 +; GLOBAL-ISEL-NEXT: s_setpc_b64 s[30:31] + call void @llvm.amdgcn.s.barrier.signal.var(i32 %arg) + ret void +} + +define amdgpu_kernel void @test1_s_barrier_signal_isfirst(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(1) %out) #0 { +; GCN-LABEL: test1_s_barrier_signal_isfirst: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v0, v1, s[6:7] +; GCN-NEXT: s_barrier_signal_isfirst -1 +; GCN-NEXT: s_cselect_b32 s3, s3, s5 +; GCN-NEXT: s_cselect_b32 s2, s2, s4 +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: global_load_b32 v2, v1, s[0:1] +; GCN-NEXT: global_load_b32 v1, v1, s[2:3] +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_lo_u32 v1, v1, v2 +; GCN-NEXT: global_store_b32 v0, v1, s[6:7] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test1_s_barrier_signal_isfirst: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7] +; GLOBAL-ISEL-NEXT: s_barrier_signal_isfirst -1 +; GLOBAL-ISEL-NEXT: s_cselect_b32 s8, 1, 0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GLOBAL-ISEL-NEXT: s_and_b32 s8, s8, 1 +; GLOBAL-ISEL-NEXT: s_cmp_lg_u32 s8, 0 +; GLOBAL-ISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] +; GLOBAL-ISEL-NEXT: s_clause 0x1 +; GLOBAL-ISEL-NEXT: global_load_b32 v2, v1, s[0:1] +; GLOBAL-ISEL-NEXT: global_load_b32 v1, v1, s[2:3] +; GLOBAL-ISEL-NEXT: s_waitcnt vmcnt(0) +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v1, v2 +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + %isfirst = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1) + %0 = load i32, ptr addrspace(1) %a, align 4 + %b.c = select i1 %isfirst, ptr addrspace(1) %b, ptr addrspace(1) %c + %1 = load i32, ptr addrspace(1) %b.c, align 4 + %mul1 = mul nsw i32 %1, %0 + store i32 %mul1, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test2_s_barrier_signal_isfirst(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(1) %out) #0 { +; GCN-LABEL: test2_s_barrier_signal_isfirst: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v0, v1, s[6:7] +; GCN-NEXT: s_barrier_signal_isfirst 1 +; GCN-NEXT: s_cselect_b32 s3, s3, s5 +; GCN-NEXT: s_cselect_b32 s2, s2, s4 +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: global_load_b32 v2, v1, s[0:1] +; GCN-NEXT: global_load_b32 v1, v1, s[2:3] +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_lo_u32 v1, v1, v2 +; GCN-NEXT: global_store_b32 v0, v1, s[6:7] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test2_s_barrier_signal_isfirst: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7] +; GLOBAL-ISEL-NEXT: s_barrier_signal_isfirst 1 +; GLOBAL-ISEL-NEXT: s_cselect_b32 s8, 1, 0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GLOBAL-ISEL-NEXT: s_and_b32 s8, s8, 1 +; GLOBAL-ISEL-NEXT: s_cmp_lg_u32 s8, 0 +; GLOBAL-ISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] +; GLOBAL-ISEL-NEXT: s_clause 0x1 +; GLOBAL-ISEL-NEXT: global_load_b32 v2, v1, s[0:1] +; GLOBAL-ISEL-NEXT: global_load_b32 v1, v1, s[2:3] +; GLOBAL-ISEL-NEXT: s_waitcnt vmcnt(0) +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v1, v2 +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + %isfirst = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 1) + %0 = load i32, ptr addrspace(1) %a, align 4 + %b.c = select i1 %isfirst, ptr addrspace(1) %b, ptr addrspace(1) %c + %1 = load i32, ptr addrspace(1) %b.c, align 4 + %mul1 = mul nsw i32 %1, %0 + store i32 %mul1, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test3_s_barrier_signal_isfirst(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(1) %out) #0 { +; GCN-LABEL: test3_s_barrier_signal_isfirst: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v0, v1, s[6:7] +; GCN-NEXT: s_barrier_signal_isfirst 1 +; GCN-NEXT: s_cselect_b32 s3, s3, s5 +; GCN-NEXT: s_cselect_b32 s2, s2, s4 +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: global_load_b32 v2, v1, s[0:1] +; GCN-NEXT: global_load_b32 v1, v1, s[2:3] +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_lo_u32 v1, v1, v2 +; GCN-NEXT: global_store_b32 v0, v1, s[6:7] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test3_s_barrier_signal_isfirst: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7] +; GLOBAL-ISEL-NEXT: s_barrier_signal_isfirst 1 +; GLOBAL-ISEL-NEXT: s_cselect_b32 s8, 1, 0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GLOBAL-ISEL-NEXT: s_and_b32 s8, s8, 1 +; GLOBAL-ISEL-NEXT: s_cmp_lg_u32 s8, 0 +; GLOBAL-ISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] +; GLOBAL-ISEL-NEXT: s_clause 0x1 +; GLOBAL-ISEL-NEXT: global_load_b32 v2, v1, s[0:1] +; GLOBAL-ISEL-NEXT: global_load_b32 v1, v1, s[2:3] +; GLOBAL-ISEL-NEXT: s_waitcnt vmcnt(0) +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v1, v2 +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + %isfirst = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 1) + %0 = load i32, ptr addrspace(1) %a, align 4 + %b.c = select i1 %isfirst, ptr addrspace(1) %b, ptr addrspace(1) %c + %1 = load i32, ptr addrspace(1) %b.c, align 4 + %mul1 = mul nsw i32 %1, %0 + store i32 %mul1, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test1_s_barrier_signal_isfirst_var(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(1) %out) #0 { +; GCN-LABEL: test1_s_barrier_signal_isfirst_var: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GCN-NEXT: s_mov_b32 m0, 1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v0, v1, s[6:7] +; GCN-NEXT: s_barrier_signal_isfirst m0 +; GCN-NEXT: s_cselect_b32 s3, s3, s5 +; GCN-NEXT: s_cselect_b32 s2, s2, s4 +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: global_load_b32 v2, v1, s[0:1] +; GCN-NEXT: global_load_b32 v1, v1, s[2:3] +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_lo_u32 v1, v1, v2 +; GCN-NEXT: global_store_b32 v0, v1, s[6:7] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test1_s_barrier_signal_isfirst_var: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GLOBAL-ISEL-NEXT: s_mov_b32 m0, 1 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7] +; GLOBAL-ISEL-NEXT: s_barrier_signal_isfirst m0 +; GLOBAL-ISEL-NEXT: s_cselect_b32 s8, 1, 0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GLOBAL-ISEL-NEXT: s_and_b32 s8, s8, 1 +; GLOBAL-ISEL-NEXT: s_cmp_lg_u32 s8, 0 +; GLOBAL-ISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] +; GLOBAL-ISEL-NEXT: s_clause 0x1 +; GLOBAL-ISEL-NEXT: global_load_b32 v2, v1, s[0:1] +; GLOBAL-ISEL-NEXT: global_load_b32 v1, v1, s[2:3] +; GLOBAL-ISEL-NEXT: s_waitcnt vmcnt(0) +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v1, v2 +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + %isfirst = call i1 @llvm.amdgcn.s.barrier.signal.isfirst.var(i32 1) + %0 = load i32, ptr addrspace(1) %a, align 4 + %b.c = select i1 %isfirst, ptr addrspace(1) %b, ptr addrspace(1) %c + %1 = load i32, ptr addrspace(1) %b.c, align 4 + %mul1 = mul nsw i32 %1, %0 + store i32 %mul1, ptr addrspace(1) %tmp1 + ret void +} + +define void @test2_s_barrier_signal_isfirst_var(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, i32 %arg, ptr addrspace(1) %out) { +; GCN-LABEL: test2_s_barrier_signal_isfirst_var: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_and_b32 v9, 0x3ff, v31 +; GCN-NEXT: v_readfirstlane_b32 s0, v6 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GCN-NEXT: v_lshlrev_b32_e32 v9, 2, v9 +; GCN-NEXT: s_mov_b32 m0, s0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GCN-NEXT: v_add_co_u32 v7, vcc_lo, v7, v9 +; GCN-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo +; GCN-NEXT: global_store_b32 v[7:8], v10, off +; GCN-NEXT: s_barrier_signal_isfirst m0 +; GCN-NEXT: s_cselect_b32 vcc_lo, -1, 0 +; GCN-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v3, v5, v3 +; GCN-NEXT: global_load_b32 v0, v[0:1], off +; GCN-NEXT: global_load_b32 v1, v[2:3], off +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_lo_u32 v0, v1, v0 +; GCN-NEXT: global_store_b32 v[7:8], v0, off +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; GLOBAL-ISEL-LABEL: test2_s_barrier_signal_isfirst_var: +; GLOBAL-ISEL: ; %bb.0: +; GLOBAL-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GLOBAL-ISEL-NEXT: v_and_b32_e32 v9, 0x3ff, v31 +; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 m0, v6 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) +; GLOBAL-ISEL-NEXT: v_lshlrev_b32_e32 v9, 2, v9 +; GLOBAL-ISEL-NEXT: v_add_co_u32 v7, vcc_lo, v7, v9 +; GLOBAL-ISEL-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo +; GLOBAL-ISEL-NEXT: v_mov_b32_e32 v9, 0 +; GLOBAL-ISEL-NEXT: global_store_b32 v[7:8], v9, off +; GLOBAL-ISEL-NEXT: s_barrier_signal_isfirst m0 +; GLOBAL-ISEL-NEXT: s_cselect_b32 s0, 1, 0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GLOBAL-ISEL-NEXT: s_and_b32 s0, 1, s0 +; GLOBAL-ISEL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 +; GLOBAL-ISEL-NEXT: v_dual_cndmask_b32 v2, v4, v2 :: v_dual_cndmask_b32 v3, v5, v3 +; GLOBAL-ISEL-NEXT: global_load_b32 v0, v[0:1], off +; GLOBAL-ISEL-NEXT: global_load_b32 v1, v[2:3], off +; GLOBAL-ISEL-NEXT: s_waitcnt vmcnt(0) +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: global_store_b32 v[7:8], v0, off +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: s_setpc_b64 s[30:31] + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + %isfirst = call i1 @llvm.amdgcn.s.barrier.signal.isfirst.var(i32 %arg) + %1 = load i32, ptr addrspace(1) %a, align 4 + %b.c = select i1 %isfirst, ptr addrspace(1) %b, ptr addrspace(1) %c + %2 = load i32, ptr addrspace(1) %b.c, align 4 + %mul1 = mul nsw i32 %2, %1 + store i32 %mul1, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test1_s_barrier_init(ptr addrspace(1) %out, i32 %mbrCnt) #0 { +; GCN-LABEL: test1_s_barrier_init: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b32 s2, s2, 16 +; GCN-NEXT: global_store_b32 v3, v2, s[0:1] +; GCN-NEXT: s_mov_b32 m0, s2 +; GCN-NEXT: s_barrier_init -1 +; GCN-NEXT: global_store_b32 v3, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test1_s_barrier_init: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_clause 0x1 +; GLOBAL-ISEL-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: s_lshl_b32 m0, 16, s2 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_barrier_init -1 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.barrier.init(i32 -1, i32 %mbrCnt) + %tmp2 = mul i32 %tmp, %tmp + %tmp3 = sub i32 %tmp2, %tmp + store i32 %tmp3, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test2_s_barrier_init(ptr addrspace(1) %out, i32 %mbrCnt) #0 { +; GCN-LABEL: test2_s_barrier_init: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b32 s2, s2, 16 +; GCN-NEXT: global_store_b32 v3, v2, s[0:1] +; GCN-NEXT: s_mov_b32 m0, s2 +; GCN-NEXT: s_barrier_init 1 +; GCN-NEXT: global_store_b32 v3, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test2_s_barrier_init: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_clause 0x1 +; GLOBAL-ISEL-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: s_lshl_b32 m0, 16, s2 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_barrier_init 1 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.barrier.init(i32 1, i32 %mbrCnt) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test3_s_barrier_init(ptr addrspace(1) %out, i32 %mbrCnt) #0 { +; GCN-LABEL: test3_s_barrier_init: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b32 s2, s2, 16 +; GCN-NEXT: global_store_b32 v3, v2, s[0:1] +; GCN-NEXT: s_mov_b32 m0, s2 +; GCN-NEXT: s_barrier_init 0 +; GCN-NEXT: global_store_b32 v3, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test3_s_barrier_init: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_clause 0x1 +; GLOBAL-ISEL-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: s_lshl_b32 m0, 16, s2 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_barrier_init 0 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.barrier.init(i32 0, i32 %mbrCnt) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test4_s_barrier_init(ptr addrspace(1) %out, i32 %bar, i32 %mbrCnt) #0 { +; GCN-LABEL: test4_s_barrier_init: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b32 s3, s3, 16 +; GCN-NEXT: global_store_b32 v3, v2, s[0:1] +; GCN-NEXT: s_or_b32 s2, s2, s3 +; GCN-NEXT: s_mov_b32 m0, s2 +; GCN-NEXT: s_barrier_init m0 +; GCN-NEXT: global_store_b32 v3, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test4_s_barrier_init: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: s_lshl_b32 s3, 16, s3 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_or_b32 m0, s2, s3 +; GLOBAL-ISEL-NEXT: s_barrier_init m0 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.barrier.init(i32 %bar, i32 %mbrCnt) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define void @test5_s_barrier_init_m0(i32 %arg1 ,i32 %arg2) { +; GCN-LABEL: test5_s_barrier_init_m0: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GCN-NEXT: v_or_b32_e32 v0, v0, v1 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GCN-NEXT: s_mov_b32 m0, s0 +; GCN-NEXT: s_barrier_init m0 +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; GLOBAL-ISEL-LABEL: test5_s_barrier_init_m0: +; GLOBAL-ISEL: ; %bb.0: +; GLOBAL-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 s0, v1 +; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 s1, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: s_lshl_b32 s0, 16, s0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) +; GLOBAL-ISEL-NEXT: s_or_b32 m0, s1, s0 +; GLOBAL-ISEL-NEXT: s_barrier_init m0 +; GLOBAL-ISEL-NEXT: s_setpc_b64 s[30:31] + call void @llvm.amdgcn.s.barrier.init(i32 %arg1, i32 %arg2) + ret void +} + +define amdgpu_kernel void @test1_s_barrier_join(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test1_s_barrier_join: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GCN-NEXT: s_barrier_join -1 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v2, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test1_s_barrier_join: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_barrier_join -1 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.barrier.join(i32 -1) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test2_s_barrier_join(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test2_s_barrier_join: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GCN-NEXT: s_barrier_join 1 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v2, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test2_s_barrier_join: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_barrier_join 1 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.barrier.join(i32 1) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test3_s_barrier_join(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test3_s_barrier_join: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GCN-NEXT: s_barrier_join 0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v2, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test3_s_barrier_join: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_barrier_join 0 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.barrier.join(i32 0) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test4_s_barrier_join_m0(ptr addrspace(1) %out, i32 %bar) #0 { +; GCN-LABEL: test4_s_barrier_join_m0: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: s_load_b64 s[2:3], s[0:1], 0x24 +; GCN-NEXT: s_load_b32 s0, s[0:1], 0x2c +; GCN-NEXT: v_mul_u32_u24_e32 v2, v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 2, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v2, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v3, v1, s[2:3] +; GCN-NEXT: s_mov_b32 m0, s0 +; GCN-NEXT: s_barrier_join m0 +; GCN-NEXT: global_store_b32 v3, v0, s[2:3] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test4_s_barrier_join_m0: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_clause 0x1 +; GLOBAL-ISEL-NEXT: s_load_b64 s[2:3], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: s_load_b32 s0, s[0:1], 0x2c +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[2:3] +; GLOBAL-ISEL-NEXT: s_mov_b32 m0, s0 +; GLOBAL-ISEL-NEXT: s_barrier_join m0 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[2:3] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.barrier.join(i32 %bar) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define void @test5_s_barrier_join_m0(i32 %arg) { +; GCN-LABEL: test5_s_barrier_join_m0: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GCN-NEXT: s_mov_b32 m0, s0 +; GCN-NEXT: s_barrier_join m0 +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; GLOBAL-ISEL-LABEL: test5_s_barrier_join_m0: +; GLOBAL-ISEL: ; %bb.0: +; GLOBAL-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 m0, v0 +; GLOBAL-ISEL-NEXT: s_barrier_join m0 +; GLOBAL-ISEL-NEXT: s_setpc_b64 s[30:31] + call void @llvm.amdgcn.s.barrier.join(i32 %arg) + ret void +} + +define amdgpu_kernel void @test1_s_barrier_leave(ptr addrspace(1) %a, ptr addrspace(1) %b, ptr addrspace(1) %c, ptr addrspace(1) %out) #0 { +; GCN-LABEL: test1_s_barrier_leave: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v0, v1, s[6:7] +; GCN-NEXT: s_barrier_leave +; GCN-NEXT: s_cselect_b32 s3, s3, s5 +; GCN-NEXT: s_cselect_b32 s2, s2, s4 +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: global_load_b32 v2, v1, s[0:1] +; GCN-NEXT: global_load_b32 v1, v1, s[2:3] +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_mul_lo_u32 v1, v1, v2 +; GCN-NEXT: global_store_b32 v0, v1, s[6:7] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test1_s_barrier_leave: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b256 s[0:7], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7] +; GLOBAL-ISEL-NEXT: s_barrier_leave +; GLOBAL-ISEL-NEXT: s_cselect_b32 s8, 1, 0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GLOBAL-ISEL-NEXT: s_and_b32 s8, s8, 1 +; GLOBAL-ISEL-NEXT: s_cmp_lg_u32 s8, 0 +; GLOBAL-ISEL-NEXT: s_cselect_b64 s[2:3], s[2:3], s[4:5] +; GLOBAL-ISEL-NEXT: s_clause 0x1 +; GLOBAL-ISEL-NEXT: global_load_b32 v2, v1, s[0:1] +; GLOBAL-ISEL-NEXT: global_load_b32 v1, v1, s[2:3] +; GLOBAL-ISEL-NEXT: s_waitcnt vmcnt(0) +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v1, v2 +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[6:7] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + %0 = call i1 @llvm.amdgcn.s.barrier.leave() + %1 = load i32, ptr addrspace(1) %a, align 4 + %b.c = select i1 %0, ptr addrspace(1) %b, ptr addrspace(1) %c + %2 = load i32, ptr addrspace(1) %b.c, align 4 + %mul1 = mul nsw i32 %2, %1 + store i32 %mul1, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test1_s_wakeup_barrier(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test1_s_wakeup_barrier: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GCN-NEXT: s_wakeup_barrier -1 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v2, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test1_s_wakeup_barrier: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_wakeup_barrier -1 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.wakeup.barrier(i32 -1) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test2_s_wakeup_barrier(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test2_s_wakeup_barrier: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GCN-NEXT: s_wakeup_barrier 1 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v2, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test2_s_wakeup_barrier: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_wakeup_barrier 1 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.wakeup.barrier(i32 1) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test3_s_wakeup_barrier(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test3_s_wakeup_barrier: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0 +; GCN-NEXT: s_wakeup_barrier 0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v2, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test3_s_wakeup_barrier: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_wakeup_barrier 0 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.wakeup.barrier(i32 0) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test4_s_wakeup_barrier_m0(ptr addrspace(1) %out, i32 %bar) #0 { +; GCN-LABEL: test4_s_wakeup_barrier_m0: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: s_load_b64 s[2:3], s[0:1], 0x24 +; GCN-NEXT: s_load_b32 s0, s[0:1], 0x2c +; GCN-NEXT: v_mul_u32_u24_e32 v2, v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 2, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v2, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v3, v1, s[2:3] +; GCN-NEXT: s_mov_b32 m0, s0 +; GCN-NEXT: s_wakeup_barrier m0 +; GCN-NEXT: global_store_b32 v3, v0, s[2:3] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test4_s_wakeup_barrier_m0: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_clause 0x1 +; GLOBAL-ISEL-NEXT: s_load_b64 s[2:3], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: s_load_b32 s0, s[0:1], 0x2c +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[2:3] +; GLOBAL-ISEL-NEXT: s_mov_b32 m0, s0 +; GLOBAL-ISEL-NEXT: s_wakeup_barrier m0 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[2:3] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.wakeup.barrier(i32 %bar) + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} + +define void @test5_s_wakeup_barrier_m0(i32 %arg) { +; GCN-LABEL: test5_s_wakeup_barrier_m0: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GCN-NEXT: s_mov_b32 m0, s0 +; GCN-NEXT: s_wakeup_barrier m0 +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; GLOBAL-ISEL-LABEL: test5_s_wakeup_barrier_m0: +; GLOBAL-ISEL: ; %bb.0: +; GLOBAL-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 m0, v0 +; GLOBAL-ISEL-NEXT: s_wakeup_barrier m0 +; GLOBAL-ISEL-NEXT: s_setpc_b64 s[30:31] + call void @llvm.amdgcn.s.wakeup.barrier(i32 %arg) + ret void +} + +define amdgpu_kernel void @test1_s_get_barrier_state(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test1_s_get_barrier_state: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_get_barrier_state s2, -1 +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GCN-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_lshlrev_b32 v0, 2, v0 +; GCN-NEXT: global_store_b32 v0, v1, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test1_s_get_barrier_state: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1] +; GLOBAL-ISEL-NEXT: s_get_barrier_state s2, -1 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GLOBAL-ISEL-NEXT: v_mov_b32_e32 v1, s2 +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + %state = call i32 @llvm.amdgcn.s.get.barrier.state(i32 -1) + store i32 %state, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test2_s_get_barrier_state(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test2_s_get_barrier_state: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_get_barrier_state s2, 1 +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GCN-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_lshlrev_b32 v0, 2, v0 +; GCN-NEXT: global_store_b32 v0, v1, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test2_s_get_barrier_state: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1] +; GLOBAL-ISEL-NEXT: s_get_barrier_state s2, 1 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GLOBAL-ISEL-NEXT: v_mov_b32_e32 v1, s2 +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + %state = call i32 @llvm.amdgcn.s.get.barrier.state(i32 1) + store i32 %state, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test3_s_get_barrier_state(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test3_s_get_barrier_state: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_get_barrier_state s2, 0 +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GCN-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_lshlrev_b32 v0, 2, v0 +; GCN-NEXT: global_store_b32 v0, v1, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test3_s_get_barrier_state: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1] +; GLOBAL-ISEL-NEXT: s_get_barrier_state s2, 0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GLOBAL-ISEL-NEXT: v_mov_b32_e32 v1, s2 +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + %state = call i32 @llvm.amdgcn.s.get.barrier.state(i32 0) + store i32 %state, ptr addrspace(1) %tmp1 + ret void +} + +define amdgpu_kernel void @test4_s_get_barrier_state_m0(ptr addrspace(1) %out, i32 %bar) #0 { +; GCN-LABEL: test4_s_get_barrier_state_m0: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_clause 0x1 +; GCN-NEXT: s_load_b64 s[2:3], s[0:1], 0x24 +; GCN-NEXT: s_load_b32 s0, s[0:1], 0x2c +; GCN-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v0, v1, s[2:3] +; GCN-NEXT: s_mov_b32 m0, s0 +; GCN-NEXT: s_get_barrier_state s0, m0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: global_store_b32 v0, v1, s[2:3] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test4_s_get_barrier_state_m0: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_clause 0x1 +; GLOBAL-ISEL-NEXT: s_load_b64 s[2:3], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: s_load_b32 s0, s[0:1], 0x2c +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[2:3] +; GLOBAL-ISEL-NEXT: s_mov_b32 m0, s0 +; GLOBAL-ISEL-NEXT: s_get_barrier_state s0, m0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GLOBAL-ISEL-NEXT: v_mov_b32_e32 v1, s0 +; GLOBAL-ISEL-NEXT: global_store_b32 v0, v1, s[2:3] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + %state = call i32 @llvm.amdgcn.s.get.barrier.state(i32 %bar) + store i32 %state, ptr addrspace(1) %tmp1 + ret void +} + +define i32 @test5_s_get_barrier_state_m0(i32 %arg) { +; GCN-LABEL: test5_s_get_barrier_state_m0: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_2) +; GCN-NEXT: s_mov_b32 m0, s0 +; GCN-NEXT: s_get_barrier_state s0, m0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: s_setpc_b64 s[30:31] +; +; GLOBAL-ISEL-LABEL: test5_s_get_barrier_state_m0: +; GLOBAL-ISEL: ; %bb.0: +; GLOBAL-ISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GLOBAL-ISEL-NEXT: v_readfirstlane_b32 m0, v0 +; GLOBAL-ISEL-NEXT: s_get_barrier_state s0, m0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2) +; GLOBAL-ISEL-NEXT: v_mov_b32_e32 v0, s0 +; GLOBAL-ISEL-NEXT: s_setpc_b64 s[30:31] + %state = call i32 @llvm.amdgcn.s.get.barrier.state(i32 %arg) + ret i32 %state +} + +define amdgpu_kernel void @test_barrier_convert(ptr addrspace(1) %out) #0 { +; GCN-LABEL: test_barrier_convert: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GCN-NEXT: v_mul_u32_u24_e32 v1, v0, v0 +; GCN-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GCN-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: global_store_b32 v3, v2, s[0:1] +; GCN-NEXT: s_barrier_signal -1 +; GCN-NEXT: s_barrier_wait -1 +; GCN-NEXT: global_store_b32 v3, v0, s[0:1] +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GCN-NEXT: s_endpgm +; +; GLOBAL-ISEL-LABEL: test_barrier_convert: +; GLOBAL-ISEL: ; %bb.0: ; %entry +; GLOBAL-ISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GLOBAL-ISEL-NEXT: v_mul_lo_u32 v1, v0, v0 +; GLOBAL-ISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v3, 2, v0 +; GLOBAL-ISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GLOBAL-ISEL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 +; GLOBAL-ISEL-NEXT: s_waitcnt lgkmcnt(0) +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v2, s[0:1] +; GLOBAL-ISEL-NEXT: s_barrier_signal -1 +; GLOBAL-ISEL-NEXT: s_barrier_wait -1 +; GLOBAL-ISEL-NEXT: global_store_b32 v3, v0, s[0:1] +; GLOBAL-ISEL-NEXT: s_nop 0 +; GLOBAL-ISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GLOBAL-ISEL-NEXT: s_endpgm +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %tmp + store i32 0, ptr addrspace(1) %tmp1 + call void @llvm.amdgcn.s.barrier() + %tmp3 = mul i32 %tmp, %tmp + %tmp4 = sub i32 %tmp3, %tmp + store i32 %tmp4, ptr addrspace(1) %tmp1 + ret void +} +declare void @llvm.amdgcn.s.barrier() #1 +declare void @llvm.amdgcn.s.barrier.wait(i16) #1 +declare void @llvm.amdgcn.s.barrier.signal(i32) #1 +declare void @llvm.amdgcn.s.barrier.signal.var(i32) #1 +declare i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32) #1 +declare i1 @llvm.amdgcn.s.barrier.signal.isfirst.var(i32) #1 +declare void @llvm.amdgcn.s.barrier.init(i32, i32) #1 +declare void @llvm.amdgcn.s.barrier.join(i32) #1 +declare i1 @llvm.amdgcn.s.barrier.leave() #1 +declare void @llvm.amdgcn.s.wakeup.barrier(i32) #1 +declare i32 @llvm.amdgcn.s.get.barrier.state(i32) #1 +declare i32 @llvm.amdgcn.s.get.barrier.state.var(i32) #1 +declare i32 @llvm.amdgcn.workitem.id.x() #2 + +attributes #0 = { nounwind } +attributes #1 = { convergent nounwind } +attributes #2 = { nounwind readnone } diff --git a/llvm/test/CodeGen/AMDGPU/minimummaximum.ll b/llvm/test/CodeGen/AMDGPU/minimummaximum.ll new file mode 100644 index 000000000000..e73ce7a4826c --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/minimummaximum.ll @@ -0,0 +1,144 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,SDAG %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GISEL %s + +define amdgpu_ps float @test_minmax_f32(float %a, float %b, float %c) { +; GFX12-LABEL: test_minmax_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximumminimum_f32 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog + %max = call float @llvm.maximum.f32(float %a, float %b) + %minmax = call float @llvm.minimum.f32(float %max, float %c) + ret float %minmax +} + +define amdgpu_ps void @s_test_minmax_f32(float inreg %a, float inreg %b, float inreg %c, ptr addrspace(1) inreg %out) { +; SDAG-LABEL: s_test_minmax_f32: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_maximum_f32 s0, s0, s1 +; SDAG-NEXT: s_mov_b32 s5, s4 +; SDAG-NEXT: s_mov_b32 s4, s3 +; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3) +; SDAG-NEXT: s_minimum_f32 s0, s0, s2 +; SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 +; SDAG-NEXT: global_store_b32 v0, v1, s[4:5] +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-NEXT: s_endpgm +; +; GISEL-LABEL: s_test_minmax_f32: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_maximum_f32 s0, s0, s1 +; GISEL-NEXT: s_mov_b32 s6, s3 +; GISEL-NEXT: s_mov_b32 s7, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-NEXT: s_minimum_f32 s0, s0, s2 +; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-NEXT: global_store_b32 v1, v0, s[6:7] +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-NEXT: s_endpgm + %smax = call float @llvm.maximum.f32(float %a, float %b) + %sminmax = call float @llvm.minimum.f32(float %smax, float %c) + store float %sminmax, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps float @test_minmax_commuted_f32(float %a, float %b, float %c) { +; GFX12-LABEL: test_minmax_commuted_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximumminimum_f32 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog + %max = call float @llvm.maximum.f32(float %a, float %b) + %minmax = call float @llvm.minimum.f32(float %c, float %max) + ret float %minmax +} + +define amdgpu_ps float @test_maxmin_f32(float %a, float %b, float %c) { +; GFX12-LABEL: test_maxmin_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_minimummaximum_f32 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog + %min = call float @llvm.minimum.f32(float %a, float %b) + %maxmin = call float @llvm.maximum.f32(float %min, float %c) + ret float %maxmin +} + +define amdgpu_ps float @test_maxmin_commuted_f32(float %a, float %b, float %c) { +; GFX12-LABEL: test_maxmin_commuted_f32: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_minimummaximum_f32 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog + %min = call float @llvm.minimum.f32(float %a, float %b) + %maxmin = call float @llvm.maximum.f32(float %c, float %min) + ret float %maxmin +} + +define amdgpu_ps half @test_minmax_f16(half %a, half %b, half %c) { +; GFX12-LABEL: test_minmax_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximumminimum_f16 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog + %max = call half @llvm.maximum.f16(half %a, half %b) + %minmax = call half @llvm.minimum.f16(half %max, half %c) + ret half %minmax +} + +define amdgpu_ps half @test_minmax_commuted_f16(half %a, half %b, half %c) { +; GFX12-LABEL: test_minmax_commuted_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_maximumminimum_f16 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog + %max = call half @llvm.maximum.f16(half %a, half %b) + %minmax = call half @llvm.minimum.f16(half %c, half %max) + ret half %minmax +} + +define amdgpu_ps half @test_maxmin_commuted_f16(half %a, half %b, half %c) { +; GFX12-LABEL: test_maxmin_commuted_f16: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_minimummaximum_f16 v0, v0, v1, v2 +; GFX12-NEXT: ; return to shader part epilog + %min = call half @llvm.minimum.f16(half %a, half %b) + %maxmin = call half @llvm.maximum.f16(half %c, half %min) + ret half %maxmin +} + +define amdgpu_ps void @s_test_minmax_f16(half inreg %a, half inreg %b, half inreg %c, ptr addrspace(1) inreg %out) { +; SDAG-LABEL: s_test_minmax_f16: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_maximum_f16 s0, s0, s1 +; SDAG-NEXT: s_mov_b32 s5, s4 +; SDAG-NEXT: s_mov_b32 s4, s3 +; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3) +; SDAG-NEXT: s_minimum_f16 s0, s0, s2 +; SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 +; SDAG-NEXT: global_store_b16 v0, v1, s[4:5] +; SDAG-NEXT: s_nop 0 +; SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-NEXT: s_endpgm +; +; GISEL-LABEL: s_test_minmax_f16: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_maximum_f16 s0, s0, s1 +; GISEL-NEXT: s_mov_b32 s6, s3 +; GISEL-NEXT: s_mov_b32 s7, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-NEXT: s_minimum_f16 s0, s0, s2 +; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) +; GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-NEXT: global_store_b16 v1, v0, s[6:7] +; GISEL-NEXT: s_nop 0 +; GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-NEXT: s_endpgm + %smax = call half @llvm.maximum.f16(half %a, half %b) + %sminmax = call half @llvm.minimum.f16(half %smax, half %c) + store half %sminmax, ptr addrspace(1) %out + ret void +} + +declare half @llvm.minimum.f16(half, half) +declare half @llvm.maximum.f16(half, half) +declare float @llvm.minimum.f32(float, float) +declare float @llvm.maximum.f32(float, float) diff --git a/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll b/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll index b209d5809c57..29910646c893 100644 --- a/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll +++ b/llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux < %s | FileCheck %s -check-prefix=PPC64LE -; This tests interaction between MergeICmp and ExpandMemCmp. +; This tests interaction between MergeICmp and expand-memcmp. %"struct.std::pair" = type { i32, i32 } diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 030ae06af6d2..b34ccb3ff0f9 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -271,7 +271,7 @@ ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0" ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0" ; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0" -; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p2" +; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4" ; RV64M: .attribute 5, "rv64i2p1_m2p0" ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0" @@ -360,7 +360,7 @@ ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvl32b1p0" ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p8_zve32f1p0_zve32x1p0_zvfbfmin0p8_zvfbfwma0p8_zvl32b1p0" ; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0" -; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p2" +; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll index d9d3442043a9..aec27b58e1fc 100644 --- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll +++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll @@ -31,16 +31,17 @@ define i32 @main() nounwind { ; RV32IFD-NEXT: fld fa5, 0(sp) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IFD-NEXT: fld fa4, %lo(.LCPI1_0)(a0) -; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1) -; RV32IFD-NEXT: fld fa3, %lo(.LCPI1_1)(a0) ; RV32IFD-NEXT: flt.d a0, fa5, fa4 -; RV32IFD-NEXT: flt.d a1, fa3, fa5 -; RV32IFD-NEXT: or a0, a0, a1 -; RV32IFD-NEXT: beqz a0, .LBB1_2 -; RV32IFD-NEXT: # %bb.1: # %if.then -; RV32IFD-NEXT: call abort@plt -; RV32IFD-NEXT: .LBB1_2: # %if.end +; RV32IFD-NEXT: bnez a0, .LBB1_3 +; RV32IFD-NEXT: # %bb.1: # %entry +; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1) +; RV32IFD-NEXT: fld fa4, %lo(.LCPI1_1)(a0) +; RV32IFD-NEXT: flt.d a0, fa4, fa5 +; RV32IFD-NEXT: bnez a0, .LBB1_3 +; RV32IFD-NEXT: # %bb.2: # %if.end ; RV32IFD-NEXT: call exit@plt +; RV32IFD-NEXT: .LBB1_3: # %if.then +; RV32IFD-NEXT: call abort@plt ; ; RV32IZFINXZDINX-LABEL: main: ; RV32IZFINXZDINX: # %bb.0: # %entry @@ -56,17 +57,18 @@ define i32 @main() nounwind { ; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0) ; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_0+4)(a2) ; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a2) -; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI1_1) -; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI1_1+4)(a4) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_1)(a4) ; RV32IZFINXZDINX-NEXT: flt.d a2, a0, a2 -; RV32IZFINXZDINX-NEXT: flt.d a0, a4, a0 -; RV32IZFINXZDINX-NEXT: or a0, a2, a0 -; RV32IZFINXZDINX-NEXT: beqz a0, .LBB1_2 -; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.then -; RV32IZFINXZDINX-NEXT: call abort@plt -; RV32IZFINXZDINX-NEXT: .LBB1_2: # %if.end +; RV32IZFINXZDINX-NEXT: bnez a2, .LBB1_3 +; RV32IZFINXZDINX-NEXT: # %bb.1: # %entry +; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_1) +; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI1_1+4)(a2) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_1)(a2) +; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0 +; RV32IZFINXZDINX-NEXT: bnez a0, .LBB1_3 +; RV32IZFINXZDINX-NEXT: # %bb.2: # %if.end ; RV32IZFINXZDINX-NEXT: call exit@plt +; RV32IZFINXZDINX-NEXT: .LBB1_3: # %if.then +; RV32IZFINXZDINX-NEXT: call abort@plt entry: %call = call double @test(double 2.000000e+00) %cmp = fcmp olt double %call, 2.400000e-01 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll index ac3bf0d89b5e..a2f367abb9dd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll @@ -12432,7 +12432,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 1 @@ -12470,7 +12469,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v14 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v14, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 6, e8, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 5 @@ -12494,7 +12492,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v13 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v13, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 10, e8, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 9 @@ -12509,7 +12506,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v14, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 11, e8, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 10 @@ -12522,7 +12518,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 12, e8, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 11 @@ -12535,7 +12530,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v13 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v9, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 13, e8, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 12 @@ -12548,7 +12542,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v9, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 14, e8, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 13 @@ -12572,7 +12565,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 18, e8, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 17 @@ -12610,7 +12602,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 22, e8, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 21 @@ -12634,7 +12625,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 26, e8, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 25 @@ -12660,7 +12650,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 30, e8, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 29 @@ -12673,7 +12662,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 31, e8, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 30 @@ -12698,7 +12686,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v14, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 3, e8, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 2 @@ -12710,7 +12697,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3 @@ -12721,7 +12707,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v13 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v14, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 7, e8, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 6 @@ -12733,7 +12718,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v13 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v13, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v13, 7 @@ -12756,7 +12740,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 15, e8, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 14 @@ -12768,7 +12751,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v9, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v9, 15 @@ -12791,7 +12773,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v14, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 19, e8, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v14, 18 @@ -12803,7 +12784,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 20, e8, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 19 @@ -12814,7 +12794,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 23, e8, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 22 @@ -12826,7 +12805,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 24, e8, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 23 @@ -12849,7 +12827,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 27, e8, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 26 @@ -12861,7 +12838,6 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: li a3, 32 ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 28, e8, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 27 diff --git a/llvm/test/CodeGen/RISCV/select-and.ll b/llvm/test/CodeGen/RISCV/select-and.ll index 51f411bd9654..5ba489043f0b 100644 --- a/llvm/test/CodeGen/RISCV/select-and.ll +++ b/llvm/test/CodeGen/RISCV/select-and.ll @@ -40,14 +40,15 @@ define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: and a0, a0, a1 -; RV32I-NEXT: beqz a0, .LBB1_2 -; RV32I-NEXT: # %bb.1: # %if.then +; RV32I-NEXT: beqz a0, .LBB1_3 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: beqz a1, .LBB1_3 +; RV32I-NEXT: # %bb.2: # %if.then ; RV32I-NEXT: call both@plt -; RV32I-NEXT: j .LBB1_3 -; RV32I-NEXT: .LBB1_2: # %if.else +; RV32I-NEXT: j .LBB1_4 +; RV32I-NEXT: .LBB1_3: # %if.else ; RV32I-NEXT: call neither@plt -; RV32I-NEXT: .LBB1_3: # %if.end +; RV32I-NEXT: .LBB1_4: # %if.end ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -56,14 +57,15 @@ define signext i32 @if_of_and(i1 zeroext %a, i1 zeroext %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: and a0, a0, a1 -; RV64I-NEXT: beqz a0, .LBB1_2 -; RV64I-NEXT: # %bb.1: # %if.then +; RV64I-NEXT: beqz a0, .LBB1_3 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: beqz a1, .LBB1_3 +; RV64I-NEXT: # %bb.2: # %if.then ; RV64I-NEXT: call both@plt -; RV64I-NEXT: j .LBB1_3 -; RV64I-NEXT: .LBB1_2: # %if.else +; RV64I-NEXT: j .LBB1_4 +; RV64I-NEXT: .LBB1_3: # %if.else ; RV64I-NEXT: call neither@plt -; RV64I-NEXT: .LBB1_3: # %if.end +; RV64I-NEXT: .LBB1_4: # %if.end ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/select-or.ll b/llvm/test/CodeGen/RISCV/select-or.ll index 9ba284c611a6..d378bb4dd563 100644 --- a/llvm/test/CodeGen/RISCV/select-or.ll +++ b/llvm/test/CodeGen/RISCV/select-or.ll @@ -40,14 +40,15 @@ define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: beqz a0, .LBB1_2 -; RV32I-NEXT: # %bb.1: # %if.then -; RV32I-NEXT: call either@plt -; RV32I-NEXT: j .LBB1_3 -; RV32I-NEXT: .LBB1_2: # %if.else +; RV32I-NEXT: bnez a0, .LBB1_3 +; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: bnez a1, .LBB1_3 +; RV32I-NEXT: # %bb.2: # %if.else ; RV32I-NEXT: call neither@plt -; RV32I-NEXT: .LBB1_3: # %if.end +; RV32I-NEXT: j .LBB1_4 +; RV32I-NEXT: .LBB1_3: # %if.then +; RV32I-NEXT: call either@plt +; RV32I-NEXT: .LBB1_4: # %if.end ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -56,14 +57,15 @@ define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: beqz a0, .LBB1_2 -; RV64I-NEXT: # %bb.1: # %if.then -; RV64I-NEXT: call either@plt -; RV64I-NEXT: j .LBB1_3 -; RV64I-NEXT: .LBB1_2: # %if.else +; RV64I-NEXT: bnez a0, .LBB1_3 +; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: bnez a1, .LBB1_3 +; RV64I-NEXT: # %bb.2: # %if.else ; RV64I-NEXT: call neither@plt -; RV64I-NEXT: .LBB1_3: # %if.end +; RV64I-NEXT: j .LBB1_4 +; RV64I-NEXT: .LBB1_3: # %if.then +; RV64I-NEXT: call either@plt +; RV64I-NEXT: .LBB1_4: # %if.end ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/setcc-logic.ll b/llvm/test/CodeGen/RISCV/setcc-logic.ll index 6a6c1bcd8dec..14e76d1ff172 100644 --- a/llvm/test/CodeGen/RISCV/setcc-logic.ll +++ b/llvm/test/CodeGen/RISCV/setcc-logic.ll @@ -298,26 +298,22 @@ declare void @bar(...) define void @and_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_sge_eq: ; RV32I: # %bb.0: -; RV32I-NEXT: slt a0, a0, a1 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: snez a1, a2 -; RV32I-NEXT: or a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB13_2 +; RV32I-NEXT: blt a0, a1, .LBB13_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: bne a2, a3, .LBB13_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB13_2: +; RV32I-NEXT: .LBB13_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_sge_eq: ; RV64I: # %bb.0: -; RV64I-NEXT: slt a0, a0, a1 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: snez a1, a2 -; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB13_2 +; RV64I-NEXT: blt a0, a1, .LBB13_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: bne a2, a3, .LBB13_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB13_2: +; RV64I-NEXT: .LBB13_3: ; RV64I-NEXT: tail bar@plt %5 = icmp sge i32 %0, %1 %6 = icmp eq i32 %2, %3 @@ -335,26 +331,22 @@ define void @and_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_sle_eq: ; RV32I: # %bb.0: -; RV32I-NEXT: slt a0, a1, a0 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: snez a1, a2 -; RV32I-NEXT: or a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB14_2 +; RV32I-NEXT: blt a1, a0, .LBB14_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: bne a2, a3, .LBB14_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB14_2: +; RV32I-NEXT: .LBB14_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_sle_eq: ; RV64I: # %bb.0: -; RV64I-NEXT: slt a0, a1, a0 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: snez a1, a2 -; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB14_2 +; RV64I-NEXT: blt a1, a0, .LBB14_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: bne a2, a3, .LBB14_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB14_2: +; RV64I-NEXT: .LBB14_3: ; RV64I-NEXT: tail bar@plt %5 = icmp sle i32 %0, %1 %6 = icmp eq i32 %2, %3 @@ -372,26 +364,22 @@ define void @and_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_uge_eq: ; RV32I: # %bb.0: -; RV32I-NEXT: sltu a0, a0, a1 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: snez a1, a2 -; RV32I-NEXT: or a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB15_2 +; RV32I-NEXT: bltu a0, a1, .LBB15_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: bne a2, a3, .LBB15_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB15_2: +; RV32I-NEXT: .LBB15_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_uge_eq: ; RV64I: # %bb.0: -; RV64I-NEXT: sltu a0, a0, a1 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: snez a1, a2 -; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB15_2 +; RV64I-NEXT: bltu a0, a1, .LBB15_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: bne a2, a3, .LBB15_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB15_2: +; RV64I-NEXT: .LBB15_3: ; RV64I-NEXT: tail bar@plt %5 = icmp uge i32 %0, %1 %6 = icmp eq i32 %2, %3 @@ -409,26 +397,22 @@ define void @and_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_ule_eq: ; RV32I: # %bb.0: -; RV32I-NEXT: sltu a0, a1, a0 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: snez a1, a2 -; RV32I-NEXT: or a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB16_2 +; RV32I-NEXT: bltu a1, a0, .LBB16_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: bne a2, a3, .LBB16_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB16_2: +; RV32I-NEXT: .LBB16_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_ule_eq: ; RV64I: # %bb.0: -; RV64I-NEXT: sltu a0, a1, a0 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: snez a1, a2 -; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB16_2 +; RV64I-NEXT: bltu a1, a0, .LBB16_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: bne a2, a3, .LBB16_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB16_2: +; RV64I-NEXT: .LBB16_3: ; RV64I-NEXT: tail bar@plt %5 = icmp ule i32 %0, %1 %6 = icmp eq i32 %2, %3 @@ -446,26 +430,22 @@ define void @and_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_sge_ne: ; RV32I: # %bb.0: -; RV32I-NEXT: slt a0, a0, a1 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: seqz a1, a2 -; RV32I-NEXT: or a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB17_2 +; RV32I-NEXT: blt a0, a1, .LBB17_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: beq a2, a3, .LBB17_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB17_2: +; RV32I-NEXT: .LBB17_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_sge_ne: ; RV64I: # %bb.0: -; RV64I-NEXT: slt a0, a0, a1 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: seqz a1, a2 -; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB17_2 +; RV64I-NEXT: blt a0, a1, .LBB17_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: beq a2, a3, .LBB17_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB17_2: +; RV64I-NEXT: .LBB17_3: ; RV64I-NEXT: tail bar@plt %5 = icmp sge i32 %0, %1 %6 = icmp ne i32 %2, %3 @@ -483,26 +463,22 @@ define void @and_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_sle_ne: ; RV32I: # %bb.0: -; RV32I-NEXT: slt a0, a1, a0 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: seqz a1, a2 -; RV32I-NEXT: or a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB18_2 +; RV32I-NEXT: blt a1, a0, .LBB18_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: beq a2, a3, .LBB18_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB18_2: +; RV32I-NEXT: .LBB18_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_sle_ne: ; RV64I: # %bb.0: -; RV64I-NEXT: slt a0, a1, a0 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: seqz a1, a2 -; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB18_2 +; RV64I-NEXT: blt a1, a0, .LBB18_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: beq a2, a3, .LBB18_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB18_2: +; RV64I-NEXT: .LBB18_3: ; RV64I-NEXT: tail bar@plt %5 = icmp sle i32 %0, %1 %6 = icmp ne i32 %2, %3 @@ -520,26 +496,22 @@ define void @and_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_uge_ne: ; RV32I: # %bb.0: -; RV32I-NEXT: sltu a0, a0, a1 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: seqz a1, a2 -; RV32I-NEXT: or a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB19_2 +; RV32I-NEXT: bltu a0, a1, .LBB19_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: beq a2, a3, .LBB19_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB19_2: +; RV32I-NEXT: .LBB19_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_uge_ne: ; RV64I: # %bb.0: -; RV64I-NEXT: sltu a0, a0, a1 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: seqz a1, a2 -; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB19_2 +; RV64I-NEXT: bltu a0, a1, .LBB19_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: beq a2, a3, .LBB19_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB19_2: +; RV64I-NEXT: .LBB19_3: ; RV64I-NEXT: tail bar@plt %5 = icmp uge i32 %0, %1 %6 = icmp ne i32 %2, %3 @@ -557,26 +529,22 @@ define void @and_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_ule_ne: ; RV32I: # %bb.0: -; RV32I-NEXT: sltu a0, a1, a0 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: seqz a1, a2 -; RV32I-NEXT: or a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB20_2 +; RV32I-NEXT: bltu a1, a0, .LBB20_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: beq a2, a3, .LBB20_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB20_2: +; RV32I-NEXT: .LBB20_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_ule_ne: ; RV64I: # %bb.0: -; RV64I-NEXT: sltu a0, a1, a0 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: seqz a1, a2 -; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB20_2 +; RV64I-NEXT: bltu a1, a0, .LBB20_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: beq a2, a3, .LBB20_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB20_2: +; RV64I-NEXT: .LBB20_3: ; RV64I-NEXT: tail bar@plt %5 = icmp ule i32 %0, %1 %6 = icmp ne i32 %2, %3 @@ -594,27 +562,23 @@ define void @and_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @or_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_sge_eq: ; RV32I: # %bb.0: -; RV32I-NEXT: slt a0, a0, a1 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: snez a1, a2 -; RV32I-NEXT: and a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB21_2 +; RV32I-NEXT: bge a0, a1, .LBB21_3 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: ret -; RV32I-NEXT: .LBB21_2: +; RV32I-NEXT: beq a2, a3, .LBB21_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: tail bar@plt +; RV32I-NEXT: .LBB21_3: +; RV32I-NEXT: ret ; ; RV64I-LABEL: or_sge_eq: ; RV64I: # %bb.0: -; RV64I-NEXT: slt a0, a0, a1 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: snez a1, a2 -; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB21_2 +; RV64I-NEXT: bge a0, a1, .LBB21_3 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: ret -; RV64I-NEXT: .LBB21_2: +; RV64I-NEXT: beq a2, a3, .LBB21_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: tail bar@plt +; RV64I-NEXT: .LBB21_3: +; RV64I-NEXT: ret %5 = icmp sge i32 %0, %1 %6 = icmp eq i32 %2, %3 %7 = or i1 %5, %6 @@ -631,27 +595,23 @@ define void @or_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_sle_eq: ; RV32I: # %bb.0: -; RV32I-NEXT: slt a0, a1, a0 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: snez a1, a2 -; RV32I-NEXT: and a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB22_2 +; RV32I-NEXT: bge a1, a0, .LBB22_3 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: ret -; RV32I-NEXT: .LBB22_2: +; RV32I-NEXT: beq a2, a3, .LBB22_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: tail bar@plt +; RV32I-NEXT: .LBB22_3: +; RV32I-NEXT: ret ; ; RV64I-LABEL: or_sle_eq: ; RV64I: # %bb.0: -; RV64I-NEXT: slt a0, a1, a0 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: snez a1, a2 -; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB22_2 +; RV64I-NEXT: bge a1, a0, .LBB22_3 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: ret -; RV64I-NEXT: .LBB22_2: +; RV64I-NEXT: beq a2, a3, .LBB22_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: tail bar@plt +; RV64I-NEXT: .LBB22_3: +; RV64I-NEXT: ret %5 = icmp sle i32 %0, %1 %6 = icmp eq i32 %2, %3 %7 = or i1 %5, %6 @@ -668,27 +628,23 @@ define void @or_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_uge_eq: ; RV32I: # %bb.0: -; RV32I-NEXT: sltu a0, a0, a1 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: snez a1, a2 -; RV32I-NEXT: and a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB23_2 +; RV32I-NEXT: bgeu a0, a1, .LBB23_3 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: ret -; RV32I-NEXT: .LBB23_2: +; RV32I-NEXT: beq a2, a3, .LBB23_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: tail bar@plt +; RV32I-NEXT: .LBB23_3: +; RV32I-NEXT: ret ; ; RV64I-LABEL: or_uge_eq: ; RV64I: # %bb.0: -; RV64I-NEXT: sltu a0, a0, a1 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: snez a1, a2 -; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB23_2 +; RV64I-NEXT: bgeu a0, a1, .LBB23_3 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: ret -; RV64I-NEXT: .LBB23_2: +; RV64I-NEXT: beq a2, a3, .LBB23_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: tail bar@plt +; RV64I-NEXT: .LBB23_3: +; RV64I-NEXT: ret %5 = icmp uge i32 %0, %1 %6 = icmp eq i32 %2, %3 %7 = or i1 %5, %6 @@ -705,27 +661,23 @@ define void @or_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_ule_eq: ; RV32I: # %bb.0: -; RV32I-NEXT: sltu a0, a1, a0 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: snez a1, a2 -; RV32I-NEXT: and a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB24_2 +; RV32I-NEXT: bgeu a1, a0, .LBB24_3 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: ret -; RV32I-NEXT: .LBB24_2: +; RV32I-NEXT: beq a2, a3, .LBB24_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: tail bar@plt +; RV32I-NEXT: .LBB24_3: +; RV32I-NEXT: ret ; ; RV64I-LABEL: or_ule_eq: ; RV64I: # %bb.0: -; RV64I-NEXT: sltu a0, a1, a0 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: snez a1, a2 -; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB24_2 +; RV64I-NEXT: bgeu a1, a0, .LBB24_3 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: ret -; RV64I-NEXT: .LBB24_2: +; RV64I-NEXT: beq a2, a3, .LBB24_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: tail bar@plt +; RV64I-NEXT: .LBB24_3: +; RV64I-NEXT: ret %5 = icmp ule i32 %0, %1 %6 = icmp eq i32 %2, %3 %7 = or i1 %5, %6 @@ -742,27 +694,23 @@ define void @or_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_sge_ne: ; RV32I: # %bb.0: -; RV32I-NEXT: slt a0, a0, a1 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: seqz a1, a2 -; RV32I-NEXT: and a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB25_2 +; RV32I-NEXT: bge a0, a1, .LBB25_3 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: ret -; RV32I-NEXT: .LBB25_2: +; RV32I-NEXT: bne a2, a3, .LBB25_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: tail bar@plt +; RV32I-NEXT: .LBB25_3: +; RV32I-NEXT: ret ; ; RV64I-LABEL: or_sge_ne: ; RV64I: # %bb.0: -; RV64I-NEXT: slt a0, a0, a1 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: seqz a1, a2 -; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB25_2 +; RV64I-NEXT: bge a0, a1, .LBB25_3 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: ret -; RV64I-NEXT: .LBB25_2: +; RV64I-NEXT: bne a2, a3, .LBB25_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: tail bar@plt +; RV64I-NEXT: .LBB25_3: +; RV64I-NEXT: ret %5 = icmp sge i32 %0, %1 %6 = icmp ne i32 %2, %3 %7 = or i1 %5, %6 @@ -779,27 +727,23 @@ define void @or_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_sle_ne: ; RV32I: # %bb.0: -; RV32I-NEXT: slt a0, a1, a0 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: seqz a1, a2 -; RV32I-NEXT: and a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB26_2 +; RV32I-NEXT: bge a1, a0, .LBB26_3 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: ret -; RV32I-NEXT: .LBB26_2: +; RV32I-NEXT: bne a2, a3, .LBB26_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: tail bar@plt +; RV32I-NEXT: .LBB26_3: +; RV32I-NEXT: ret ; ; RV64I-LABEL: or_sle_ne: ; RV64I: # %bb.0: -; RV64I-NEXT: slt a0, a1, a0 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: seqz a1, a2 -; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB26_2 +; RV64I-NEXT: bge a1, a0, .LBB26_3 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: ret -; RV64I-NEXT: .LBB26_2: +; RV64I-NEXT: bne a2, a3, .LBB26_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: tail bar@plt +; RV64I-NEXT: .LBB26_3: +; RV64I-NEXT: ret %5 = icmp sle i32 %0, %1 %6 = icmp ne i32 %2, %3 %7 = or i1 %5, %6 @@ -816,27 +760,23 @@ define void @or_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_uge_ne: ; RV32I: # %bb.0: -; RV32I-NEXT: sltu a0, a0, a1 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: seqz a1, a2 -; RV32I-NEXT: and a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB27_2 +; RV32I-NEXT: bgeu a0, a1, .LBB27_3 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: ret -; RV32I-NEXT: .LBB27_2: +; RV32I-NEXT: bne a2, a3, .LBB27_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: tail bar@plt +; RV32I-NEXT: .LBB27_3: +; RV32I-NEXT: ret ; ; RV64I-LABEL: or_uge_ne: ; RV64I: # %bb.0: -; RV64I-NEXT: sltu a0, a0, a1 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: seqz a1, a2 -; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB27_2 +; RV64I-NEXT: bgeu a0, a1, .LBB27_3 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: ret -; RV64I-NEXT: .LBB27_2: +; RV64I-NEXT: bne a2, a3, .LBB27_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: tail bar@plt +; RV64I-NEXT: .LBB27_3: +; RV64I-NEXT: ret %5 = icmp uge i32 %0, %1 %6 = icmp ne i32 %2, %3 %7 = or i1 %5, %6 @@ -853,27 +793,23 @@ define void @or_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_ule_ne: ; RV32I: # %bb.0: -; RV32I-NEXT: sltu a0, a1, a0 -; RV32I-NEXT: xor a2, a2, a3 -; RV32I-NEXT: seqz a1, a2 -; RV32I-NEXT: and a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB28_2 +; RV32I-NEXT: bgeu a1, a0, .LBB28_3 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: ret -; RV32I-NEXT: .LBB28_2: +; RV32I-NEXT: bne a2, a3, .LBB28_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: tail bar@plt +; RV32I-NEXT: .LBB28_3: +; RV32I-NEXT: ret ; ; RV64I-LABEL: or_ule_ne: ; RV64I: # %bb.0: -; RV64I-NEXT: sltu a0, a1, a0 -; RV64I-NEXT: xor a2, a2, a3 -; RV64I-NEXT: seqz a1, a2 -; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB28_2 +; RV64I-NEXT: bgeu a1, a0, .LBB28_3 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: ret -; RV64I-NEXT: .LBB28_2: +; RV64I-NEXT: bne a2, a3, .LBB28_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: tail bar@plt +; RV64I-NEXT: .LBB28_3: +; RV64I-NEXT: ret %5 = icmp ule i32 %0, %1 %6 = icmp ne i32 %2, %3 %7 = or i1 %5, %6 @@ -890,26 +826,22 @@ define void @or_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @and_eq_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_eq_sge: ; RV32I: # %bb.0: -; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: snez a0, a0 -; RV32I-NEXT: slt a1, a2, a3 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: bnez a0, .LBB29_2 +; RV32I-NEXT: bne a0, a1, .LBB29_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: blt a2, a3, .LBB29_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB29_2: +; RV32I-NEXT: .LBB29_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_eq_sge: ; RV64I: # %bb.0: -; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: snez a0, a0 -; RV64I-NEXT: slt a1, a2, a3 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: bnez a0, .LBB29_2 +; RV64I-NEXT: bne a0, a1, .LBB29_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: blt a2, a3, .LBB29_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB29_2: +; RV64I-NEXT: .LBB29_3: ; RV64I-NEXT: tail bar@plt %5 = icmp eq i32 %0, %1 %6 = icmp sge i32 %2, %3 @@ -927,26 +859,22 @@ define void @and_eq_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_eq_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_eq_sle: ; RV32I: # %bb.0: -; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: snez a0, a0 -; RV32I-NEXT: slt a1, a3, a2 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: bnez a0, .LBB30_2 +; RV32I-NEXT: bne a0, a1, .LBB30_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: blt a3, a2, .LBB30_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB30_2: +; RV32I-NEXT: .LBB30_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_eq_sle: ; RV64I: # %bb.0: -; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: snez a0, a0 -; RV64I-NEXT: slt a1, a3, a2 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: bnez a0, .LBB30_2 +; RV64I-NEXT: bne a0, a1, .LBB30_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: blt a3, a2, .LBB30_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB30_2: +; RV64I-NEXT: .LBB30_3: ; RV64I-NEXT: tail bar@plt %5 = icmp eq i32 %0, %1 %6 = icmp sle i32 %2, %3 @@ -964,26 +892,22 @@ define void @and_eq_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_eq_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_eq_uge: ; RV32I: # %bb.0: -; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: snez a0, a0 -; RV32I-NEXT: sltu a1, a2, a3 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: bnez a0, .LBB31_2 +; RV32I-NEXT: bne a0, a1, .LBB31_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: bltu a2, a3, .LBB31_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB31_2: +; RV32I-NEXT: .LBB31_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_eq_uge: ; RV64I: # %bb.0: -; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: snez a0, a0 -; RV64I-NEXT: sltu a1, a2, a3 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: bnez a0, .LBB31_2 +; RV64I-NEXT: bne a0, a1, .LBB31_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: bltu a2, a3, .LBB31_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB31_2: +; RV64I-NEXT: .LBB31_3: ; RV64I-NEXT: tail bar@plt %5 = icmp eq i32 %0, %1 %6 = icmp uge i32 %2, %3 @@ -1001,26 +925,22 @@ define void @and_eq_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_eq_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_eq_ule: ; RV32I: # %bb.0: -; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: snez a0, a0 -; RV32I-NEXT: sltu a1, a3, a2 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: bnez a0, .LBB32_2 +; RV32I-NEXT: bne a0, a1, .LBB32_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: bltu a3, a2, .LBB32_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB32_2: +; RV32I-NEXT: .LBB32_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_eq_ule: ; RV64I: # %bb.0: -; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: snez a0, a0 -; RV64I-NEXT: sltu a1, a3, a2 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: bnez a0, .LBB32_2 +; RV64I-NEXT: bne a0, a1, .LBB32_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: bltu a3, a2, .LBB32_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB32_2: +; RV64I-NEXT: .LBB32_3: ; RV64I-NEXT: tail bar@plt %5 = icmp eq i32 %0, %1 %6 = icmp ule i32 %2, %3 @@ -1038,26 +958,22 @@ define void @and_eq_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_ne_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_ne_sge: ; RV32I: # %bb.0: -; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: seqz a0, a0 -; RV32I-NEXT: slt a1, a2, a3 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: bnez a0, .LBB33_2 +; RV32I-NEXT: beq a0, a1, .LBB33_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: blt a2, a3, .LBB33_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB33_2: +; RV32I-NEXT: .LBB33_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_ne_sge: ; RV64I: # %bb.0: -; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: seqz a0, a0 -; RV64I-NEXT: slt a1, a2, a3 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: bnez a0, .LBB33_2 +; RV64I-NEXT: beq a0, a1, .LBB33_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: blt a2, a3, .LBB33_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB33_2: +; RV64I-NEXT: .LBB33_3: ; RV64I-NEXT: tail bar@plt %5 = icmp ne i32 %0, %1 %6 = icmp sge i32 %2, %3 @@ -1075,26 +991,22 @@ define void @and_ne_sge(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_ne_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_ne_sle: ; RV32I: # %bb.0: -; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: seqz a0, a0 -; RV32I-NEXT: slt a1, a3, a2 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: bnez a0, .LBB34_2 +; RV32I-NEXT: beq a0, a1, .LBB34_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: blt a3, a2, .LBB34_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB34_2: +; RV32I-NEXT: .LBB34_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_ne_sle: ; RV64I: # %bb.0: -; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: seqz a0, a0 -; RV64I-NEXT: slt a1, a3, a2 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: bnez a0, .LBB34_2 +; RV64I-NEXT: beq a0, a1, .LBB34_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: blt a3, a2, .LBB34_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB34_2: +; RV64I-NEXT: .LBB34_3: ; RV64I-NEXT: tail bar@plt %5 = icmp ne i32 %0, %1 %6 = icmp sle i32 %2, %3 @@ -1112,26 +1024,22 @@ define void @and_ne_sle(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_ne_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_ne_uge: ; RV32I: # %bb.0: -; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: seqz a0, a0 -; RV32I-NEXT: sltu a1, a2, a3 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: bnez a0, .LBB35_2 +; RV32I-NEXT: beq a0, a1, .LBB35_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: bltu a2, a3, .LBB35_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB35_2: +; RV32I-NEXT: .LBB35_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_ne_uge: ; RV64I: # %bb.0: -; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: seqz a0, a0 -; RV64I-NEXT: sltu a1, a2, a3 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: bnez a0, .LBB35_2 +; RV64I-NEXT: beq a0, a1, .LBB35_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: bltu a2, a3, .LBB35_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB35_2: +; RV64I-NEXT: .LBB35_3: ; RV64I-NEXT: tail bar@plt %5 = icmp ne i32 %0, %1 %6 = icmp uge i32 %2, %3 @@ -1149,26 +1057,22 @@ define void @and_ne_uge(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_ne_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: and_ne_ule: ; RV32I: # %bb.0: -; RV32I-NEXT: xor a0, a0, a1 -; RV32I-NEXT: seqz a0, a0 -; RV32I-NEXT: sltu a1, a3, a2 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: bnez a0, .LBB36_2 +; RV32I-NEXT: beq a0, a1, .LBB36_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: bltu a3, a2, .LBB36_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB36_2: +; RV32I-NEXT: .LBB36_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_ne_ule: ; RV64I: # %bb.0: -; RV64I-NEXT: xor a0, a0, a1 -; RV64I-NEXT: seqz a0, a0 -; RV64I-NEXT: sltu a1, a3, a2 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: bnez a0, .LBB36_2 +; RV64I-NEXT: beq a0, a1, .LBB36_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: bltu a3, a2, .LBB36_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB36_2: +; RV64I-NEXT: .LBB36_3: ; RV64I-NEXT: tail bar@plt %5 = icmp ne i32 %0, %1 %6 = icmp ule i32 %2, %3 @@ -1186,24 +1090,22 @@ define void @and_ne_ule(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @and_sge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) { ; RV32I-LABEL: and_sge_gt0: ; RV32I: # %bb.0: -; RV32I-NEXT: slt a0, a0, a1 -; RV32I-NEXT: slti a1, a2, 1 -; RV32I-NEXT: or a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB37_2 +; RV32I-NEXT: blt a0, a1, .LBB37_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: blez a2, .LBB37_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB37_2: +; RV32I-NEXT: .LBB37_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_sge_gt0: ; RV64I: # %bb.0: -; RV64I-NEXT: slt a0, a0, a1 -; RV64I-NEXT: slti a1, a2, 1 -; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB37_2 +; RV64I-NEXT: blt a0, a1, .LBB37_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: blez a2, .LBB37_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB37_2: +; RV64I-NEXT: .LBB37_3: ; RV64I-NEXT: tail bar@plt %4 = icmp sge i32 %0, %1 %5 = icmp sgt i32 %2, 0 @@ -1221,24 +1123,22 @@ define void @and_sge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) { define void @and_sle_lt1(i32 signext %0, i32 signext %1, i32 signext %2) { ; RV32I-LABEL: and_sle_lt1: ; RV32I: # %bb.0: -; RV32I-NEXT: slt a0, a1, a0 -; RV32I-NEXT: sgtz a1, a2 -; RV32I-NEXT: or a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB38_2 +; RV32I-NEXT: blt a1, a0, .LBB38_3 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: bgtz a2, .LBB38_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: ret -; RV32I-NEXT: .LBB38_2: +; RV32I-NEXT: .LBB38_3: ; RV32I-NEXT: tail bar@plt ; ; RV64I-LABEL: and_sle_lt1: ; RV64I: # %bb.0: -; RV64I-NEXT: slt a0, a1, a0 -; RV64I-NEXT: sgtz a1, a2 -; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB38_2 +; RV64I-NEXT: blt a1, a0, .LBB38_3 ; RV64I-NEXT: # %bb.1: +; RV64I-NEXT: bgtz a2, .LBB38_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: ret -; RV64I-NEXT: .LBB38_2: +; RV64I-NEXT: .LBB38_3: ; RV64I-NEXT: tail bar@plt %4 = icmp sle i32 %0, %1 %5 = icmp slt i32 %2, 1 @@ -1256,25 +1156,23 @@ define void @and_sle_lt1(i32 signext %0, i32 signext %1, i32 signext %2) { define void @or_uge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) { ; RV32I-LABEL: or_uge_gt0: ; RV32I: # %bb.0: -; RV32I-NEXT: sltu a0, a0, a1 -; RV32I-NEXT: slti a1, a2, 1 -; RV32I-NEXT: and a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB39_2 +; RV32I-NEXT: bgeu a0, a1, .LBB39_3 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: ret -; RV32I-NEXT: .LBB39_2: +; RV32I-NEXT: bgtz a2, .LBB39_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: tail bar@plt +; RV32I-NEXT: .LBB39_3: +; RV32I-NEXT: ret ; ; RV64I-LABEL: or_uge_gt0: ; RV64I: # %bb.0: -; RV64I-NEXT: sltu a0, a0, a1 -; RV64I-NEXT: slti a1, a2, 1 -; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB39_2 +; RV64I-NEXT: bgeu a0, a1, .LBB39_3 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: ret -; RV64I-NEXT: .LBB39_2: +; RV64I-NEXT: bgtz a2, .LBB39_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: tail bar@plt +; RV64I-NEXT: .LBB39_3: +; RV64I-NEXT: ret %4 = icmp uge i32 %0, %1 %5 = icmp sgt i32 %2, 0 %6 = or i1 %4, %5 @@ -1291,25 +1189,23 @@ define void @or_uge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) { define void @or_ule_lt1(i32 signext %0, i32 signext %1, i32 signext %2) { ; RV32I-LABEL: or_ule_lt1: ; RV32I: # %bb.0: -; RV32I-NEXT: sltu a0, a1, a0 -; RV32I-NEXT: sgtz a1, a2 -; RV32I-NEXT: and a0, a1, a0 -; RV32I-NEXT: bnez a0, .LBB40_2 +; RV32I-NEXT: bgeu a1, a0, .LBB40_3 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: ret -; RV32I-NEXT: .LBB40_2: +; RV32I-NEXT: blez a2, .LBB40_3 +; RV32I-NEXT: # %bb.2: ; RV32I-NEXT: tail bar@plt +; RV32I-NEXT: .LBB40_3: +; RV32I-NEXT: ret ; ; RV64I-LABEL: or_ule_lt1: ; RV64I: # %bb.0: -; RV64I-NEXT: sltu a0, a1, a0 -; RV64I-NEXT: sgtz a1, a2 -; RV64I-NEXT: and a0, a1, a0 -; RV64I-NEXT: bnez a0, .LBB40_2 +; RV64I-NEXT: bgeu a1, a0, .LBB40_3 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: ret -; RV64I-NEXT: .LBB40_2: +; RV64I-NEXT: blez a2, .LBB40_3 +; RV64I-NEXT: # %bb.2: ; RV64I-NEXT: tail bar@plt +; RV64I-NEXT: .LBB40_3: +; RV64I-NEXT: ret %4 = icmp ule i32 %0, %1 %5 = icmp slt i32 %2, 1 %6 = or i1 %4, %5 diff --git a/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll b/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll index 07b921e3d90f..771a72f8d55f 100644 --- a/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll +++ b/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll @@ -10,16 +10,19 @@ define dso_local i32 @test_zext_i8() nounwind { ; RV32I-LABEL: test_zext_i8: ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: lui a0, %hi(bytes) -; RV32I-NEXT: addi a1, a0, %lo(bytes) -; RV32I-NEXT: lbu a0, %lo(bytes)(a0) -; RV32I-NEXT: lbu a1, 1(a1) -; RV32I-NEXT: xori a0, a0, 136 -; RV32I-NEXT: xori a1, a1, 7 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: beqz a0, .LBB0_2 -; RV32I-NEXT: # %bb.1: # %if.then +; RV32I-NEXT: lbu a1, %lo(bytes)(a0) +; RV32I-NEXT: li a2, 136 +; RV32I-NEXT: bne a1, a2, .LBB0_3 +; RV32I-NEXT: # %bb.1: # %entry +; RV32I-NEXT: addi a0, a0, %lo(bytes) +; RV32I-NEXT: lbu a0, 1(a0) +; RV32I-NEXT: li a1, 7 +; RV32I-NEXT: bne a0, a1, .LBB0_3 +; RV32I-NEXT: # %bb.2: # %if.end +; RV32I-NEXT: li a0, 0 +; RV32I-NEXT: ret +; RV32I-NEXT: .LBB0_3: # %if.then ; RV32I-NEXT: li a0, 1 -; RV32I-NEXT: .LBB0_2: # %if.end ; RV32I-NEXT: ret entry: %0 = load i8, ptr @bytes, align 1 @@ -42,18 +45,20 @@ define dso_local i32 @test_zext_i16() nounwind { ; RV32I-LABEL: test_zext_i16: ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: lui a0, %hi(shorts) -; RV32I-NEXT: addi a1, a0, %lo(shorts) -; RV32I-NEXT: lhu a0, %lo(shorts)(a0) -; RV32I-NEXT: lhu a1, 2(a1) +; RV32I-NEXT: lhu a1, %lo(shorts)(a0) ; RV32I-NEXT: lui a2, 16 ; RV32I-NEXT: addi a2, a2, -120 -; RV32I-NEXT: xor a0, a0, a2 -; RV32I-NEXT: xori a1, a1, 7 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: beqz a0, .LBB1_2 -; RV32I-NEXT: # %bb.1: # %if.then +; RV32I-NEXT: bne a1, a2, .LBB1_3 +; RV32I-NEXT: # %bb.1: # %entry +; RV32I-NEXT: addi a0, a0, %lo(shorts) +; RV32I-NEXT: lhu a0, 2(a0) +; RV32I-NEXT: li a1, 7 +; RV32I-NEXT: bne a0, a1, .LBB1_3 +; RV32I-NEXT: # %bb.2: # %if.end +; RV32I-NEXT: li a0, 0 +; RV32I-NEXT: ret +; RV32I-NEXT: .LBB1_3: # %if.then ; RV32I-NEXT: li a0, 1 -; RV32I-NEXT: .LBB1_2: # %if.end ; RV32I-NEXT: ret entry: %0 = load i16, ptr @shorts, align 2 diff --git a/llvm/test/CodeGen/X86/coalescer-dead-flag-verifier-error.ll b/llvm/test/CodeGen/X86/coalescer-dead-flag-verifier-error.ll new file mode 100644 index 000000000000..4a396599a444 --- /dev/null +++ b/llvm/test/CodeGen/X86/coalescer-dead-flag-verifier-error.ll @@ -0,0 +1,131 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=x86_64-pc-linux-gnu -verify-coalescing < %s | FileCheck %s + +%"class.llvm::APInt." = type <{ %union.anon., i32, [4 x i8] }> +%union.anon. = type { i64 } + +define void @_ZNK4llvm5APInt21multiplicativeInverseERKS0_(ptr %r) { +; CHECK-LABEL: _ZNK4llvm5APInt21multiplicativeInverseERKS0_: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: xorl %edx, %edx +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: .p2align 4, 0x90 +; CHECK-NEXT: .LBB0_4: # %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i +; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: movl %edx, %edx +; CHECK-NEXT: shlq $4, %rdx +; CHECK-NEXT: movl $0, (%rdi,%rdx) +; CHECK-NEXT: movl %ecx, %edx +; CHECK-NEXT: .LBB0_1: # %bb +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB0_3 Depth 2 +; CHECK-NEXT: xorl $1, %ecx +; CHECK-NEXT: xorl %esi, %esi +; CHECK-NEXT: movq %rcx, %r8 +; CHECK-NEXT: testb %al, %al +; CHECK-NEXT: jne .LBB0_4 +; CHECK-NEXT: .p2align 4, 0x90 +; CHECK-NEXT: .LBB0_3: # %for.body.i.i.i.i.i.3 +; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: orq $1, %r8 +; CHECK-NEXT: orq $1, %rsi +; CHECK-NEXT: testb %al, %al +; CHECK-NEXT: je .LBB0_3 +; CHECK-NEXT: jmp .LBB0_4 +entry: + br label %bb + +bb: ; preds = %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i, %entry + %i.0 = phi i32 [ 0, %entry ], [ %xor, %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i ] + %xor = xor i32 %i.0, 1 + %idxprom = zext nneg i32 %xor to i64 + br label %for.body.i.i.i.i.i + +for.body.i.i.i.i.i: ; preds = %for.body.i.i.i.i.i.3, %bb + %lsr.iv37 = phi i64 [ %lsr.iv.next38, %for.body.i.i.i.i.i.3 ], [ 0, %bb ] + %lsr.iv = phi i64 [ %lsr.iv.next, %for.body.i.i.i.i.i.3 ], [ %idxprom, %bb ] + %exitcond.not.i.i.i.i.i.2 = icmp eq i64 0, 1 + br i1 %exitcond.not.i.i.i.i.i.2, label %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i, label %for.body.i.i.i.i.i.3 + +for.body.i.i.i.i.i.3: ; preds = %for.body.i.i.i.i.i + %sunkaddr55 = mul i64 %lsr.iv37, 0 + %i = xor i64 %lsr.iv, 0 + %lsr.iv.next = or i64 %lsr.iv, 1 + %lsr.iv.next38 = or i64 %lsr.iv37, 1 + br label %for.body.i.i.i.i.i + +_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i: ; preds = %for.body.i.i.i.i.i + %idxprom12 = zext nneg i32 %i.0 to i64 + %arrayidx13 = getelementptr [2 x %"class.llvm::APInt."], ptr %r, i64 0, i64 %idxprom12 + store i32 0, ptr %arrayidx13, align 4 + br label %bb +} + +; This variant hit an assert and never reached the verifier error +define void @_ZNK4llvm5APInt21multiplicativeInverseERKS0__assert(ptr %r) { +; CHECK-LABEL: _ZNK4llvm5APInt21multiplicativeInverseERKS0__assert: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: xorl %edx, %edx +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: jmp .LBB1_1 +; CHECK-NEXT: .p2align 4, 0x90 +; CHECK-NEXT: .LBB1_4: # %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i +; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1 +; CHECK-NEXT: movl %edx, %edx +; CHECK-NEXT: shlq $4, %rdx +; CHECK-NEXT: movl $0, (%rdi,%rdx) +; CHECK-NEXT: movl %ecx, %edx +; CHECK-NEXT: .LBB1_1: # %bb +; CHECK-NEXT: # =>This Loop Header: Depth=1 +; CHECK-NEXT: # Child Loop BB1_3 Depth 2 +; CHECK-NEXT: xorl $1, %ecx +; CHECK-NEXT: movq %rcx, %rsi +; CHECK-NEXT: shlq $4, %rsi +; CHECK-NEXT: movq (%rsi), %rsi +; CHECK-NEXT: xorl %r8d, %r8d +; CHECK-NEXT: testb %al, %al +; CHECK-NEXT: jne .LBB1_4 +; CHECK-NEXT: .p2align 4, 0x90 +; CHECK-NEXT: .LBB1_3: # %for.body.i.i.i.i.i.3 +; CHECK-NEXT: # Parent Loop BB1_1 Depth=1 +; CHECK-NEXT: # => This Inner Loop Header: Depth=2 +; CHECK-NEXT: orq $1, %rsi +; CHECK-NEXT: orq $1, %r8 +; CHECK-NEXT: testb %al, %al +; CHECK-NEXT: je .LBB1_3 +; CHECK-NEXT: jmp .LBB1_4 +entry: + br label %bb + +bb: ; preds = %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i, %entry + %i.0 = phi i32 [ 0, %entry ], [ %xor, %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i ] + %xor = xor i32 %i.0, 1 + %idxprom = zext nneg i32 %xor to i64 + %arrayidx = getelementptr [2 x %"class.llvm::APInt."], ptr null, i64 0, i64 %idxprom + %i.i.i.i.i.i = load ptr, ptr %arrayidx, align 16 + %i.i.i.i.i.i36 = ptrtoint ptr %i.i.i.i.i.i to i64 + br label %for.body.i.i.i.i.i + +for.body.i.i.i.i.i: ; preds = %for.body.i.i.i.i.i.3, %bb + %lsr.iv37 = phi i64 [ %lsr.iv.next38, %for.body.i.i.i.i.i.3 ], [ 0, %bb ] + %lsr.iv = phi i64 [ %lsr.iv.next, %for.body.i.i.i.i.i.3 ], [ %i.i.i.i.i.i36, %bb ] + %exitcond.not.i.i.i.i.i.2 = icmp eq i64 0, 1 + br i1 %exitcond.not.i.i.i.i.i.2, label %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i, label %for.body.i.i.i.i.i.3 + +for.body.i.i.i.i.i.3: ; preds = %for.body.i.i.i.i.i + %sunkaddr55 = mul i64 %lsr.iv37, 0 + %i = xor i64 %lsr.iv, 0 + %lsr.iv.next = or i64 %lsr.iv, 1 + %lsr.iv.next38 = or i64 %lsr.iv37, 1 + br label %for.body.i.i.i.i.i + +_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i: ; preds = %for.body.i.i.i.i.i + %idxprom12 = zext nneg i32 %i.0 to i64 + %arrayidx13 = getelementptr [2 x %"class.llvm::APInt."], ptr %r, i64 0, i64 %idxprom12 + store i32 0, ptr %arrayidx13, align 4 + br label %bb +} diff --git a/llvm/test/CodeGen/X86/coalescer-partial-redundancy-clear-dead-flag-undef-copy.mir b/llvm/test/CodeGen/X86/coalescer-partial-redundancy-clear-dead-flag-undef-copy.mir new file mode 100644 index 000000000000..5f33be0bc155 --- /dev/null +++ b/llvm/test/CodeGen/X86/coalescer-partial-redundancy-clear-dead-flag-undef-copy.mir @@ -0,0 +1,47 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=x86_64-pc-linux-gnu -run-pass=register-coalescer -verify-coalescing -o - %s | FileCheck %s + +# Check for "Live range continues after dead def flag". + +# There are 2 copies of undef, but the registers also appear to be +# live due to block live outs, and thus were not deleted as +# eliminateUndefCopy only considered the live range, and not the undef +# flag. +# +# removePartialRedundancy would move the COPY undef %0 in bb.1 to +# bb.0. The live range of %1 would then be extended to be live out of +# %bb.1 for the backedge phi. This would then fail the verifier, since +# the dead flag was no longer valid. This was fixed by directly +# considering the undef flag to avoid considering this special case. + +--- +name: partial_redundancy_coalesce_undef_copy_live_out +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: partial_redundancy_coalesce_undef_copy_live_out + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $rdi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $rdi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[XOR32ri:%[0-9]+]]:gr32 = XOR32ri undef [[XOR32ri]], 1, implicit-def dead $eflags + ; CHECK-NEXT: dead [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]] + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = IMPLICIT_DEF + ; CHECK-NEXT: JMP_1 %bb.1 + bb.0: + liveins: $rdi + + %0:gr32 = COPY $rdi + + bb.1: + %1:gr32 = COPY undef %0 + dead %1:gr32 = XOR32ri %1, 1, implicit-def dead $eflags + dead %2:gr32 = MOV32rr killed %0 + %0:gr32 = COPY killed undef %1 + JMP_1 %bb.1 + +... diff --git a/llvm/test/CodeGen/X86/coalescer-remat-with-undef-implicit-def-operand.mir b/llvm/test/CodeGen/X86/coalescer-remat-with-undef-implicit-def-operand.mir new file mode 100644 index 000000000000..42d17130412b --- /dev/null +++ b/llvm/test/CodeGen/X86/coalescer-remat-with-undef-implicit-def-operand.mir @@ -0,0 +1,123 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=x86_64-pc-linux-gnu -verify-coalescing -run-pass=register-coalescer -o - %s | FileCheck %s + +# The %1 = MOV32r0 is rematerialized as a subregister of %2. The +# implicit-def %1 operand needs to have an undef added, just like the +# main result operand. + +--- +name: remat_into_subregister_set_undef_implicit_operand_subregisters +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: remat_into_subregister_set_undef_implicit_operand_subregisters + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $rdi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_]] + ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_1]] + ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_2]].sub_32bit, implicit-def [[MOV32r0_2]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = XOR32ri [[MOV32r0_2]].sub_32bit, 1, implicit-def dead $eflags + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: JCC_1 %bb.4, 5, implicit killed undef $eflags + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[MOV32r0_1]] + ; CHECK-NEXT: dead [[SHL64ri:%[0-9]+]]:gr64_nosp = SHL64ri [[MOV32r0_]], 4, implicit-def dead $eflags + ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = COPY [[MOV32r0_2]].sub_32bit + ; CHECK-NEXT: JMP_1 %bb.1 + bb.0: + liveins: $rdi + + undef %0.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def %0 + %1:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def %1 + undef %2.sub_32bit:gr64_with_sub_8bit = COPY %1, implicit-def %2 + + bb.1: + %2.sub_32bit:gr64_with_sub_8bit = XOR32ri %2.sub_32bit, 1, implicit-def dead $eflags + + bb.2: + JCC_1 %bb.4, 5, implicit killed undef $eflags + + bb.3: + + bb.4: + dead %3:gr32 = MOV32rr %1 + dead %4:gr64_nosp = SHL64ri %0, 4, implicit-def dead $eflags + %1:gr32 = COPY %2.sub_32bit + JMP_1 %bb.1 + +... + +# Same, except the implicit-def on the original instruction already +# has a subregister index. + +--- +name: remat_into_subregister_set_undef_implicit_operand_subregisters_with_subreg +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: remat_into_subregister_set_undef_implicit_operand_subregisters_with_subreg + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $rdi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_]] + ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_1]].sub_8bit + ; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_2]].sub_8bit, implicit-def [[MOV32r0_2]] + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.2(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = XOR32ri [[MOV32r0_2]].sub_32bit, 1, implicit-def dead $eflags + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: JCC_1 %bb.4, 5, implicit killed undef $eflags + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3: + ; CHECK-NEXT: successors: %bb.4(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: dead [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[MOV32r0_1]] + ; CHECK-NEXT: dead [[SHL64ri:%[0-9]+]]:gr64_nosp = SHL64ri [[MOV32r0_]], 4, implicit-def dead $eflags + ; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = COPY [[MOV32r0_2]].sub_32bit + ; CHECK-NEXT: JMP_1 %bb.1 + bb.0: + liveins: $rdi + + undef %0.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def %0 + %1:gr32 = MOV32r0 implicit-def dead $eflags, undef implicit-def %1.sub_8bit + undef %2.sub_32bit:gr64_with_sub_8bit = COPY %1, implicit-def %2 + + bb.1: + %2.sub_32bit:gr64_with_sub_8bit = XOR32ri %2.sub_32bit, 1, implicit-def dead $eflags + + bb.2: + JCC_1 %bb.4, 5, implicit killed undef $eflags + + bb.3: + + bb.4: + dead %3:gr32 = MOV32rr %1 + dead %4:gr64_nosp = SHL64ri %0, 4, implicit-def dead $eflags + %1:gr32 = COPY %2.sub_32bit + JMP_1 %bb.1 + +... diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s index db166e8ffc10..8f2944586ed2 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sop1.s @@ -684,6 +684,51 @@ s_rndne_f16 s5, 0xfe0b s_rndne_f16 s5, 0x3456 // GFX12: encoding: [0xff,0x6e,0x85,0xbe,0x56,0x34,0x00,0x00] +s_barrier_signal -2 +// GFX12: encoding: [0xc2,0x4e,0x80,0xbe] + +s_barrier_signal -1 +// GFX12: encoding: [0xc1,0x4e,0x80,0xbe] + +s_barrier_signal m0 +// GFX12: encoding: [0x7d,0x4e,0x80,0xbe] + +s_barrier_signal_isfirst -2 +// GFX12: encoding: [0xc2,0x4f,0x80,0xbe] + +s_barrier_signal_isfirst -1 +// GFX12: encoding: [0xc1,0x4f,0x80,0xbe] + +s_barrier_signal_isfirst m0 +// GFX12: encoding: [0x7d,0x4f,0x80,0xbe] + +s_barrier_init -1 +// GFX12: encoding: [0xc1,0x51,0x80,0xbe] + +s_barrier_init -2 +// GFX12: encoding: [0xc2,0x51,0x80,0xbe] + +s_barrier_init m0 +// GFX12: encoding: [0x7d,0x51,0x80,0xbe] + +s_barrier_join -1 +// GFX12: encoding: [0xc1,0x52,0x80,0xbe] + +s_barrier_join -2 +// GFX12: encoding: [0xc2,0x52,0x80,0xbe] + +s_barrier_join m0 +// GFX12: encoding: [0x7d,0x52,0x80,0xbe] + +s_wakeup_barrier 1 +// GFX12: encoding: [0x81,0x57,0x80,0xbe] + +s_wakeup_barrier -1 +// GFX12: encoding: [0xc1,0x57,0x80,0xbe] + +s_wakeup_barrier m0 +// GFX12: encoding: [0x7d,0x57,0x80,0xbe] + s_mov_b32 s0, s1 // GFX12: encoding: [0x01,0x00,0x80,0xbe] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s b/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s index 1a898bebde57..d1d920872418 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sop2.s @@ -483,6 +483,108 @@ s_max_num_f32 s5, 0x3f717273, s2 s_max_num_f32 s5, s1, s105 // GFX12: encoding: [0x01,0x69,0x85,0xa1] +s_minimum_f32 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x85,0xa7] + +s_minimum_f32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0xa7] + +s_minimum_f32 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x85,0xa7] + +s_minimum_f32 s5, s103, s2 +// GFX12: encoding: [0x67,0x02,0x85,0xa7] + +s_minimum_f32 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x85,0xa7] + +s_minimum_f32 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x85,0xa7] + +s_minimum_f32 s5, ttmp11, s2 +// GFX12: encoding: [0x77,0x02,0x85,0xa7] + +s_minimum_f32 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x85,0xa7] + +s_minimum_f32 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x85,0xa7] + +s_minimum_f32 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x85,0xa7] + +s_minimum_f32 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x85,0xa7] + +s_minimum_f32 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x85,0xa7] + +s_minimum_f32 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x85,0xa7] + +s_minimum_f32 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x85,0xa7] + +s_minimum_f32 s5, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa7,0x56,0x34,0x12,0xaf] + +s_minimum_f32 s5, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa7,0x73,0x72,0x71,0x3f] + +s_minimum_f32 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x85,0xa7] + +s_maximum_f32 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x05,0xa8] + +s_maximum_f32 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0xa8] + +s_maximum_f32 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x05,0xa8] + +s_maximum_f32 s5, s103, s2 +// GFX12: encoding: [0x67,0x02,0x05,0xa8] + +s_maximum_f32 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x05,0xa8] + +s_maximum_f32 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x05,0xa8] + +s_maximum_f32 s5, ttmp11, s2 +// GFX12: encoding: [0x77,0x02,0x05,0xa8] + +s_maximum_f32 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x05,0xa8] + +s_maximum_f32 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x05,0xa8] + +s_maximum_f32 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x05,0xa8] + +s_maximum_f32 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x05,0xa8] + +s_maximum_f32 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x05,0xa8] + +s_maximum_f32 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x05,0xa8] + +s_maximum_f32 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x05,0xa8] + +s_maximum_f32 s5, 0xaf123456, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa8,0x56,0x34,0x12,0xaf] + +s_maximum_f32 s5, 0x3f717273, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa8,0x73,0x72,0x71,0x3f] + +s_maximum_f32 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x05,0xa8] + s_fmac_f32 s5, s1, s2 // GFX12: encoding: [0x01,0x02,0x85,0xa3] @@ -942,6 +1044,102 @@ s_min_num_f16 s5, 0x3456, s2 s_min_num_f16 s5, s1, s105 // GFX12: encoding: [0x01,0x69,0x85,0xa5] +s_maximum_f16 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x05,0xa9] + +s_maximum_f16 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0x69,0xa9] + +s_maximum_f16 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x05,0xa9] + +s_maximum_f16 s5, s101, s2 +// GFX12: encoding: [0x65,0x02,0x05,0xa9] + +s_maximum_f16 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x05,0xa9] + +s_maximum_f16 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x05,0xa9] + +s_maximum_f16 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x05,0xa9] + +s_maximum_f16 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x05,0xa9] + +s_maximum_f16 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x05,0xa9] + +s_maximum_f16 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x05,0xa9] + +s_maximum_f16 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x05,0xa9] + +s_maximum_f16 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x05,0xa9] + +s_maximum_f16 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x05,0xa9] + +s_maximum_f16 s5, 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa9,0x0b,0xfe,0x00,0x00] + +s_maximum_f16 s5, 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x05,0xa9,0x56,0x34,0x00,0x00] + +s_maximum_f16 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x05,0xa9] + +s_minimum_f16 s5, s1, s2 +// GFX12: encoding: [0x01,0x02,0x85,0xa8] + +s_minimum_f16 s105, s1, s2 +// GFX12: encoding: [0x01,0x02,0xe9,0xa8] + +s_minimum_f16 s5, s105, s2 +// GFX12: encoding: [0x69,0x02,0x85,0xa8] + +s_minimum_f16 s5, s101, s2 +// GFX12: encoding: [0x65,0x02,0x85,0xa8] + +s_minimum_f16 s5, vcc_lo, s2 +// GFX12: encoding: [0x6a,0x02,0x85,0xa8] + +s_minimum_f16 s5, vcc_hi, s2 +// GFX12: encoding: [0x6b,0x02,0x85,0xa8] + +s_minimum_f16 s5, m0, s2 +// GFX12: encoding: [0x7d,0x02,0x85,0xa8] + +s_minimum_f16 s5, exec_lo, s2 +// GFX12: encoding: [0x7e,0x02,0x85,0xa8] + +s_minimum_f16 s5, exec_hi, s2 +// GFX12: encoding: [0x7f,0x02,0x85,0xa8] + +s_minimum_f16 s5, 0, s2 +// GFX12: encoding: [0x80,0x02,0x85,0xa8] + +s_minimum_f16 s5, -1, s2 +// GFX12: encoding: [0xc1,0x02,0x85,0xa8] + +s_minimum_f16 s5, 0.5, s2 +// GFX12: encoding: [0xf0,0x02,0x85,0xa8] + +s_minimum_f16 s5, -4.0, s2 +// GFX12: encoding: [0xf7,0x02,0x85,0xa8] + +s_minimum_f16 s5, 0xfe0b, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa8,0x0b,0xfe,0x00,0x00] + +s_minimum_f16 s5, 0x3456, s2 +// GFX12: encoding: [0xff,0x02,0x85,0xa8,0x56,0x34,0x00,0x00] + +s_minimum_f16 s5, s1, s105 +// GFX12: encoding: [0x01,0x69,0x85,0xa8] + s_add_co_u32 s0, s1, s2 // GFX12: encoding: [0x01,0x02,0x00,0x80] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s index 2e9df11d6f5a..cf78b87a4761 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_sopp.s @@ -33,6 +33,15 @@ s_singleuse_vdst 0xffff s_singleuse_vdst 0x1234 // GFX12: encoding: [0x34,0x12,0x93,0xbf] +s_barrier_wait 0xffff +// GFX12: encoding: [0xff,0xff,0x94,0xbf] + +s_barrier_wait 1 +// GFX12: encoding: [0x01,0x00,0x94,0xbf] + +s_barrier_leave +// GFX12: encoding: [0x00,0x00,0x95,0xbf] + //===----------------------------------------------------------------------===// // s_waitcnt //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s index 71b2c442460f..e97e4b8c7241 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s @@ -5981,3 +5981,633 @@ v_xor_b16 v5, src_scc, vcc_lo v_xor_b16 v255, 0xfe0b, vcc_hi // GFX12: encoding: [0xff,0x00,0x64,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00] + +v_minimum_f32 v5, v1, v2 +// GFX12: encoding: [0x05,0x00,0x65,0xd7,0x01,0x05,0x02,0x00] + +v_minimum_f32 v5, v255, v255 +// GFX12: encoding: [0x05,0x00,0x65,0xd7,0xff,0xff,0x03,0x00] + +v_minimum_f32 v5, s1, s2 +// GFX12: encoding: [0x05,0x00,0x65,0xd7,0x01,0x04,0x00,0x00] + +v_minimum_f32 v5, s105, s105 +// GFX12: encoding: [0x05,0x00,0x65,0xd7,0x69,0xd2,0x00,0x00] + +v_minimum_f32 v5, vcc_lo, ttmp15 +// GFX12: encoding: [0x05,0x00,0x65,0xd7,0x6a,0xf6,0x00,0x00] + +v_minimum_f32 v5, vcc_hi, 0xaf123456 +// GFX12: encoding: [0x05,0x00,0x65,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf] + +v_minimum_f32 v5, ttmp15, src_scc +// GFX12: encoding: [0x05,0x00,0x65,0xd7,0x7b,0xfa,0x01,0x00] + +v_minimum_f32 v5, m0, 0.5 +// GFX12: encoding: [0x05,0x00,0x65,0xd7,0x7d,0xe0,0x01,0x00] + +v_minimum_f32 v5, exec_lo, -1 +// GFX12: encoding: [0x05,0x00,0x65,0xd7,0x7e,0x82,0x01,0x00] + +v_minimum_f32 v5, |exec_hi|, null +// GFX12: encoding: [0x05,0x01,0x65,0xd7,0x7f,0xf8,0x00,0x00] + +v_minimum_f32 v5, null, exec_lo +// GFX12: encoding: [0x05,0x00,0x65,0xd7,0x7c,0xfc,0x00,0x00] + +v_minimum_f32 v5, -1, exec_hi +// GFX12: encoding: [0x05,0x00,0x65,0xd7,0xc1,0xfe,0x00,0x00] + +v_minimum_f32 v5, 0.5, -m0 +// GFX12: encoding: [0x05,0x00,0x65,0xd7,0xf0,0xfa,0x00,0x40] + +v_minimum_f32 v5, -src_scc, |vcc_lo| +// GFX12: encoding: [0x05,0x02,0x65,0xd7,0xfd,0xd4,0x00,0x20] + +v_minimum_f32 v255, -|0xaf123456|, -|vcc_hi| +// GFX12: encoding: [0xff,0x03,0x65,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf] + +v_maximum_f32 v5, v1, v2 +// GFX12: encoding: [0x05,0x00,0x66,0xd7,0x01,0x05,0x02,0x00] + +v_maximum_f32 v5, v255, v255 +// GFX12: encoding: [0x05,0x00,0x66,0xd7,0xff,0xff,0x03,0x00] + +v_maximum_f32 v5, s1, s2 +// GFX12: encoding: [0x05,0x00,0x66,0xd7,0x01,0x04,0x00,0x00] + +v_maximum_f32 v5, s105, s105 +// GFX12: encoding: [0x05,0x00,0x66,0xd7,0x69,0xd2,0x00,0x00] + +v_maximum_f32 v5, vcc_lo, ttmp15 +// GFX12: encoding: [0x05,0x00,0x66,0xd7,0x6a,0xf6,0x00,0x00] + +v_maximum_f32 v5, vcc_hi, 0xaf123456 +// GFX12: encoding: [0x05,0x00,0x66,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf] + +v_maximum_f32 v5, ttmp15, src_scc +// GFX12: encoding: [0x05,0x00,0x66,0xd7,0x7b,0xfa,0x01,0x00] + +v_maximum_f32 v5, m0, 0.5 +// GFX12: encoding: [0x05,0x00,0x66,0xd7,0x7d,0xe0,0x01,0x00] + +v_maximum_f32 v5, exec_lo, -1 +// GFX12: encoding: [0x05,0x00,0x66,0xd7,0x7e,0x82,0x01,0x00] + +v_maximum_f32 v5, |exec_hi|, null +// GFX12: encoding: [0x05,0x01,0x66,0xd7,0x7f,0xf8,0x00,0x00] + +v_maximum_f32 v5, null, exec_lo +// GFX12: encoding: [0x05,0x00,0x66,0xd7,0x7c,0xfc,0x00,0x00] + +v_maximum_f32 v5, -1, exec_hi +// GFX12: encoding: [0x05,0x00,0x66,0xd7,0xc1,0xfe,0x00,0x00] + +v_maximum_f32 v5, 0.5, -m0 +// GFX12: encoding: [0x05,0x00,0x66,0xd7,0xf0,0xfa,0x00,0x40] + +v_maximum_f32 v5, -src_scc, |vcc_lo| +// GFX12: encoding: [0x05,0x02,0x66,0xd7,0xfd,0xd4,0x00,0x20] + +v_maximum_f32 v255, -|0xaf123456|, -|vcc_hi| +// GFX12: encoding: [0xff,0x03,0x66,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf] + +v_minimum_f16 v5, v1, v2 +// GFX12: encoding: [0x05,0x00,0x67,0xd7,0x01,0x05,0x02,0x00] + +v_minimum_f16 v5, v255, v255 +// GFX12: encoding: [0x05,0x00,0x67,0xd7,0xff,0xff,0x03,0x00] + +v_minimum_f16 v5, s1, s2 +// GFX12: encoding: [0x05,0x00,0x67,0xd7,0x01,0x04,0x00,0x00] + +v_minimum_f16 v5, s105, s105 +// GFX12: encoding: [0x05,0x00,0x67,0xd7,0x69,0xd2,0x00,0x00] + +v_minimum_f16 v5, vcc_lo, ttmp15 +// GFX12: encoding: [0x05,0x00,0x67,0xd7,0x6a,0xf6,0x00,0x00] + +v_minimum_f16 v5, vcc_hi, 0xaf12 +// GFX12: encoding: [0x05,0x00,0x67,0xd7,0x6b,0xfe,0x01,0x00,0x12,0xaf,0x00,0x00] + +v_minimum_f16 v5, ttmp15, src_scc +// GFX12: encoding: [0x05,0x00,0x67,0xd7,0x7b,0xfa,0x01,0x00] + +v_minimum_f16 v5, m0, 0.5 +// GFX12: encoding: [0x05,0x00,0x67,0xd7,0x7d,0xe0,0x01,0x00] + +v_minimum_f16 v5, exec_lo, -1 +// GFX12: encoding: [0x05,0x00,0x67,0xd7,0x7e,0x82,0x01,0x00] + +v_minimum_f16 v5, |exec_hi|, null +// GFX12: encoding: [0x05,0x01,0x67,0xd7,0x7f,0xf8,0x00,0x00] + +v_minimum_f16 v5, null, exec_lo +// GFX12: encoding: [0x05,0x00,0x67,0xd7,0x7c,0xfc,0x00,0x00] + +v_minimum_f16 v5, -1, exec_hi +// GFX12: encoding: [0x05,0x00,0x67,0xd7,0xc1,0xfe,0x00,0x00] + +v_minimum_f16 v5, 0.5, -m0 +// GFX12: encoding: [0x05,0x00,0x67,0xd7,0xf0,0xfa,0x00,0x40] + +v_minimum_f16 v5, -src_scc, |vcc_lo| +// GFX12: encoding: [0x05,0x02,0x67,0xd7,0xfd,0xd4,0x00,0x20] + +v_minimum_f16 v255, -|0xaf12|, -|vcc_hi| +// GFX12: encoding: [0xff,0x03,0x67,0xd7,0xff,0xd6,0x00,0x60,0x12,0xaf,0x00,0x00] + +v_minimum_f16 v205, v201, v200 +// GFX12: encoding: [0xcd,0x00,0x67,0xd7,0xc9,0x91,0x03,0x00] + +v_maximum_f16 v5, v1, v2 +// GFX12: encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x00] + +v_maximum_f16 v5, v255, v255 +// GFX12: encoding: [0x05,0x00,0x68,0xd7,0xff,0xff,0x03,0x00] + +v_maximum_f16 v5, s1, s2 +// GFX12: encoding: [0x05,0x00,0x68,0xd7,0x01,0x04,0x00,0x00] + +v_maximum_f16 v5, s105, s105 +// GFX12: encoding: [0x05,0x00,0x68,0xd7,0x69,0xd2,0x00,0x00] + +v_maximum_f16 v5, vcc_lo, ttmp15 +// GFX12: encoding: [0x05,0x00,0x68,0xd7,0x6a,0xf6,0x00,0x00] + +v_maximum_f16 v5, vcc_hi, 0xaf12 +// GFX12: encoding: [0x05,0x00,0x68,0xd7,0x6b,0xfe,0x01,0x00,0x12,0xaf,0x00,0x00] + +v_maximum_f16 v5, ttmp15, src_scc +// GFX12: encoding: [0x05,0x00,0x68,0xd7,0x7b,0xfa,0x01,0x00] + +v_maximum_f16 v5, m0, 0.5 +// GFX12: encoding: [0x05,0x00,0x68,0xd7,0x7d,0xe0,0x01,0x00] + +v_maximum_f16 v5, exec_lo, -1 +// GFX12: encoding: [0x05,0x00,0x68,0xd7,0x7e,0x82,0x01,0x00] + +v_maximum_f16 v5, |exec_hi|, null +// GFX12: encoding: [0x05,0x01,0x68,0xd7,0x7f,0xf8,0x00,0x00] + +v_maximum_f16 v5, null, exec_lo +// GFX12: encoding: [0x05,0x00,0x68,0xd7,0x7c,0xfc,0x00,0x00] + +v_maximum_f16 v5, -1, exec_hi +// GFX12: encoding: [0x05,0x00,0x68,0xd7,0xc1,0xfe,0x00,0x00] + +v_maximum_f16 v5, 0.5, -m0 +// GFX12: encoding: [0x05,0x00,0x68,0xd7,0xf0,0xfa,0x00,0x40] + +v_maximum_f16 v5, -src_scc, |vcc_lo| +// GFX12: encoding: [0x05,0x02,0x68,0xd7,0xfd,0xd4,0x00,0x20] + +v_maximum_f16 v255, -|0xaf12|, -|vcc_hi| +// GFX12: encoding: [0xff,0x03,0x68,0xd7,0xff,0xd6,0x00,0x60,0x12,0xaf,0x00,0x00] + +v_maximum_f16 v205, v201, v200 +// GFX12: encoding: [0xcd,0x00,0x68,0xd7,0xc9,0x91,0x03,0x00] + +v_minimum_f64 v[5:6], v[1:2], v[3:4] +// GFX12: encoding: [0x05,0x00,0x41,0xd7,0x01,0x07,0x02,0x00] + +v_minimum_f64 v[5:6], v[254:255], v[254:255] +// GFX12: encoding: [0x05,0x00,0x41,0xd7,0xfe,0xfd,0x03,0x00] + +v_minimum_f64 v[5:6], s[6:7], s[4:5] +// GFX12: encoding: [0x05,0x00,0x41,0xd7,0x06,0x08,0x00,0x00] + +v_minimum_f64 v[5:6], s[104:105], s[104:105] +// GFX12: encoding: [0x05,0x00,0x41,0xd7,0x68,0xd0,0x00,0x00] + +v_minimum_f64 v[5:6], vcc, ttmp[14:15] +// GFX12: encoding: [0x05,0x00,0x41,0xd7,0x6a,0xf4,0x00,0x00] + +v_minimum_f64 v[5:6], vcc, 0xaf121234 +// GFX12: encoding: [0x05,0x00,0x41,0xd7,0x6a,0xfe,0x01,0x00,0x34,0x12,0x12,0xaf] + +v_minimum_f64 v[5:6], ttmp[14:15], src_scc +// GFX12: encoding: [0x05,0x00,0x41,0xd7,0x7a,0xfa,0x01,0x00] + +v_minimum_f64 v[5:6], vcc, 0.5 +// GFX12: encoding: [0x05,0x00,0x41,0xd7,0x6a,0xe0,0x01,0x00] + +v_minimum_f64 v[5:6], exec, -1 +// GFX12: encoding: [0x05,0x00,0x41,0xd7,0x7e,0x82,0x01,0x00] + +v_minimum_f64 v[5:6], |exec|, null +// GFX12: encoding: [0x05,0x01,0x41,0xd7,0x7e,0xf8,0x00,0x00] + +v_minimum_f64 v[5:6], null, exec +// GFX12: encoding: [0x05,0x00,0x41,0xd7,0x7c,0xfc,0x00,0x00] + +v_minimum_f64 v[5:6], -1, exec +// GFX12: encoding: [0x05,0x00,0x41,0xd7,0xc1,0xfc,0x00,0x00] + +v_minimum_f64 v[5:6], 0.5, -vcc +// GFX12: encoding: [0x05,0x00,0x41,0xd7,0xf0,0xd4,0x00,0x40] + +v_minimum_f64 v[5:6], -src_scc, |vcc| +// GFX12: encoding: [0x05,0x02,0x41,0xd7,0xfd,0xd4,0x00,0x20] + +v_minimum_f64 v[254:255], -|2|, -|vcc| +// GFX12: encoding: [0xfe,0x03,0x41,0xd7,0x82,0xd4,0x00,0x60] + +v_maximum_f64 v[5:6], v[1:2], v[3:4] +// GFX12: encoding: [0x05,0x00,0x42,0xd7,0x01,0x07,0x02,0x00] + +v_maximum_f64 v[5:6], v[254:255], v[254:255] +// GFX12: encoding: [0x05,0x00,0x42,0xd7,0xfe,0xfd,0x03,0x00] + +v_maximum_f64 v[5:6], s[6:7], s[4:5] +// GFX12: encoding: [0x05,0x00,0x42,0xd7,0x06,0x08,0x00,0x00] + +v_maximum_f64 v[5:6], s[104:105], s[104:105] +// GFX12: encoding: [0x05,0x00,0x42,0xd7,0x68,0xd0,0x00,0x00] + +v_maximum_f64 v[5:6], vcc, ttmp[14:15] +// GFX12: encoding: [0x05,0x00,0x42,0xd7,0x6a,0xf4,0x00,0x00] + +v_maximum_f64 v[5:6], vcc, 0xaf121234 +// GFX12: encoding: [0x05,0x00,0x42,0xd7,0x6a,0xfe,0x01,0x00,0x34,0x12,0x12,0xaf] + +v_maximum_f64 v[5:6], ttmp[14:15], src_scc +// GFX12: encoding: [0x05,0x00,0x42,0xd7,0x7a,0xfa,0x01,0x00] + +v_maximum_f64 v[5:6], vcc, 0.5 +// GFX12: encoding: [0x05,0x00,0x42,0xd7,0x6a,0xe0,0x01,0x00] + +v_maximum_f64 v[5:6], exec, -1 +// GFX12: encoding: [0x05,0x00,0x42,0xd7,0x7e,0x82,0x01,0x00] + +v_maximum_f64 v[5:6], |exec|, null +// GFX12: encoding: [0x05,0x01,0x42,0xd7,0x7e,0xf8,0x00,0x00] + +v_maximum_f64 v[5:6], null, exec +// GFX12: encoding: [0x05,0x00,0x42,0xd7,0x7c,0xfc,0x00,0x00] + +v_maximum_f64 v[5:6], -1, exec +// GFX12: encoding: [0x05,0x00,0x42,0xd7,0xc1,0xfc,0x00,0x00] + +v_maximum_f64 v[5:6], 0.5, -vcc +// GFX12: encoding: [0x05,0x00,0x42,0xd7,0xf0,0xd4,0x00,0x40] + +v_maximum_f64 v[5:6], -src_scc, |vcc| +// GFX12: encoding: [0x05,0x02,0x42,0xd7,0xfd,0xd4,0x00,0x20] + +v_maximum_f64 v[254:255], -|2|, -|vcc| +// GFX12: encoding: [0xfe,0x03,0x42,0xd7,0x82,0xd4,0x00,0x60] + +v_minimum3_f32 v5, v1, v2, s3 +// GFX12: encoding: [0x05,0x00,0x2d,0xd6,0x01,0x05,0x0e,0x00] + +v_minimum3_f32 v5, v255, s2, s105 +// GFX12: encoding: [0x05,0x00,0x2d,0xd6,0xff,0x05,0xa4,0x01] + +v_minimum3_f32 v5, s1, v255, exec_hi +// GFX12: encoding: [0x05,0x00,0x2d,0xd6,0x01,0xfe,0xff,0x01] + +v_minimum3_f32 v5, s105, s105, exec_lo +// GFX12: encoding: [0x05,0x00,0x2d,0xd6,0x69,0xd2,0xf8,0x01] + +v_minimum3_f32 v5, vcc_lo, ttmp15, v3 +// GFX12: encoding: [0x05,0x00,0x2d,0xd6,0x6a,0xf6,0x0c,0x04] + +v_minimum3_f32 v5, vcc_hi, 0xaf123456, v255 +// GFX12: encoding: [0x05,0x00,0x2d,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf] + +v_minimum3_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| +// GFX12: encoding: [0x05,0x07,0x2d,0xd6,0x7b,0xfa,0xed,0xe1] + +v_minimum3_f32 v5, m0, 0.5, m0 +// GFX12: encoding: [0x05,0x00,0x2d,0xd6,0x7d,0xe0,0xf5,0x01] + +v_minimum3_f32 v5, |exec_lo|, -1, vcc_hi +// GFX12: encoding: [0x05,0x01,0x2d,0xd6,0x7e,0x82,0xad,0x01] + +v_minimum3_f32 v5, -|exec_hi|, null, -|vcc_lo| +// GFX12: encoding: [0x05,0x05,0x2d,0xd6,0x7f,0xf8,0xa8,0xa1] + +v_minimum3_f32 v5, null, exec_lo, -|0xaf123456| +// GFX12: encoding: [0x05,0x04,0x2d,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf] + +v_minimum3_f32 v5, -1, -|exec_hi|, -|src_scc| +// GFX12: encoding: [0x05,0x06,0x2d,0xd6,0xc1,0xfe,0xf4,0xc3] + +v_minimum3_f32 v5, 0.5, -m0, 0.5 mul:2 +// GFX12: encoding: [0x05,0x00,0x2d,0xd6,0xf0,0xfa,0xc0,0x4b] + +v_minimum3_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 +// GFX12: encoding: [0x05,0x02,0x2d,0xd6,0xfd,0xd4,0x04,0x33] + +v_minimum3_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 +// GFX12: encoding: [0xff,0x83,0x2d,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf] + +v_maximum3_f32 v5, v1, v2, s3 +// GFX12: encoding: [0x05,0x00,0x2e,0xd6,0x01,0x05,0x0e,0x00] + +v_maximum3_f32 v5, v255, s2, s105 +// GFX12: encoding: [0x05,0x00,0x2e,0xd6,0xff,0x05,0xa4,0x01] + +v_maximum3_f32 v5, s1, v255, exec_hi +// GFX12: encoding: [0x05,0x00,0x2e,0xd6,0x01,0xfe,0xff,0x01] + +v_maximum3_f32 v5, s105, s105, exec_lo +// GFX12: encoding: [0x05,0x00,0x2e,0xd6,0x69,0xd2,0xf8,0x01] + +v_maximum3_f32 v5, vcc_lo, ttmp15, v3 +// GFX12: encoding: [0x05,0x00,0x2e,0xd6,0x6a,0xf6,0x0c,0x04] + +v_maximum3_f32 v5, vcc_hi, 0xaf123456, v255 +// GFX12: encoding: [0x05,0x00,0x2e,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf] + +v_maximum3_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| +// GFX12: encoding: [0x05,0x07,0x2e,0xd6,0x7b,0xfa,0xed,0xe1] + +v_maximum3_f32 v5, m0, 0.5, m0 +// GFX12: encoding: [0x05,0x00,0x2e,0xd6,0x7d,0xe0,0xf5,0x01] + +v_maximum3_f32 v5, |exec_lo|, -1, vcc_hi +// GFX12: encoding: [0x05,0x01,0x2e,0xd6,0x7e,0x82,0xad,0x01] + +v_maximum3_f32 v5, -|exec_hi|, null, -|vcc_lo| +// GFX12: encoding: [0x05,0x05,0x2e,0xd6,0x7f,0xf8,0xa8,0xa1] + +v_maximum3_f32 v5, null, exec_lo, -|0xaf123456| +// GFX12: encoding: [0x05,0x04,0x2e,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf] + +v_maximum3_f32 v5, -1, -|exec_hi|, -|src_scc| +// GFX12: encoding: [0x05,0x06,0x2e,0xd6,0xc1,0xfe,0xf4,0xc3] + +v_maximum3_f32 v5, 0.5, -m0, 0.5 mul:2 +// GFX12: encoding: [0x05,0x00,0x2e,0xd6,0xf0,0xfa,0xc0,0x4b] + +v_maximum3_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 +// GFX12: encoding: [0x05,0x02,0x2e,0xd6,0xfd,0xd4,0x04,0x33] + +v_maximum3_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 +// GFX12: encoding: [0xff,0x83,0x2e,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf] + +v_minimum3_f16 v5, v1, v2, s3 +// GFX12: encoding: [0x05,0x00,0x2f,0xd6,0x01,0x05,0x0e,0x00] + +v_minimum3_f16 v5, v255, s2, s105 +// GFX12: encoding: [0x05,0x00,0x2f,0xd6,0xff,0x05,0xa4,0x01] + +v_minimum3_f16 v5, s1, v255, exec_hi +// GFX12: encoding: [0x05,0x00,0x2f,0xd6,0x01,0xfe,0xff,0x01] + +v_minimum3_f16 v5, s105, s105, exec_lo +// GFX12: encoding: [0x05,0x00,0x2f,0xd6,0x69,0xd2,0xf8,0x01] + +v_minimum3_f16 v5, vcc_lo, ttmp15, v3 +// GFX12: encoding: [0x05,0x00,0x2f,0xd6,0x6a,0xf6,0x0c,0x04] + +v_minimum3_f16 v5, vcc_hi, 0xaf12, v255 +// GFX12: encoding: [0x05,0x00,0x2f,0xd6,0x6b,0xfe,0xfd,0x07,0x12,0xaf,0x00,0x00] + +v_minimum3_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| +// GFX12: encoding: [0x05,0x07,0x2f,0xd6,0x7b,0xfa,0xed,0xe1] + +v_minimum3_f16 v5, m0, 0.5, m0 +// GFX12: encoding: [0x05,0x00,0x2f,0xd6,0x7d,0xe0,0xf5,0x01] + +v_minimum3_f16 v5, |exec_lo|, -1, vcc_hi +// GFX12: encoding: [0x05,0x01,0x2f,0xd6,0x7e,0x82,0xad,0x01] + +v_minimum3_f16 v5, -|exec_hi|, null, -|vcc_lo| +// GFX12: encoding: [0x05,0x05,0x2f,0xd6,0x7f,0xf8,0xa8,0xa1] + +v_minimum3_f16 v5, null, exec_lo, -|0xaf12| +// GFX12: encoding: [0x05,0x04,0x2f,0xd6,0x7c,0xfc,0xfc,0x83,0x12,0xaf,0x00,0x00] + +v_minimum3_f16 v5, -1, -|exec_hi|, -|src_scc| +// GFX12: encoding: [0x05,0x06,0x2f,0xd6,0xc1,0xfe,0xf4,0xc3] + +v_minimum3_f16 v5, 0.5, -m0, 0.5 +// GFX12: encoding: [0x05,0x00,0x2f,0xd6,0xf0,0xfa,0xc0,0x43] + +v_minimum3_f16 v5, -src_scc, |vcc_lo|, -1 +// GFX12: encoding: [0x05,0x02,0x2f,0xd6,0xfd,0xd4,0x04,0x23] + +v_minimum3_f16 v255, -|0xaf12|, -|vcc_hi|, null clamp +// GFX12: encoding: [0xff,0x83,0x2f,0xd6,0xff,0xd6,0xf0,0x61,0x12,0xaf,0x00,0x00] + +v_maximum3_f16 v5, v1, v2, s3 +// GFX12: encoding: [0x05,0x00,0x30,0xd6,0x01,0x05,0x0e,0x00] + +v_maximum3_f16 v5, v255, s2, s105 +// GFX12: encoding: [0x05,0x00,0x30,0xd6,0xff,0x05,0xa4,0x01] + +v_maximum3_f16 v5, s1, v255, exec_hi +// GFX12: encoding: [0x05,0x00,0x30,0xd6,0x01,0xfe,0xff,0x01] + +v_maximum3_f16 v5, s105, s105, exec_lo +// GFX12: encoding: [0x05,0x00,0x30,0xd6,0x69,0xd2,0xf8,0x01] + +v_maximum3_f16 v5, vcc_lo, ttmp15, v3 +// GFX12: encoding: [0x05,0x00,0x30,0xd6,0x6a,0xf6,0x0c,0x04] + +v_maximum3_f16 v5, vcc_hi, 0xaf12, v255 +// GFX12: encoding: [0x05,0x00,0x30,0xd6,0x6b,0xfe,0xfd,0x07,0x12,0xaf,0x00,0x00] + +v_maximum3_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| +// GFX12: encoding: [0x05,0x07,0x30,0xd6,0x7b,0xfa,0xed,0xe1] + +v_maximum3_f16 v5, m0, 0.5, m0 +// GFX12: encoding: [0x05,0x00,0x30,0xd6,0x7d,0xe0,0xf5,0x01] + +v_maximum3_f16 v5, |exec_lo|, -1, vcc_hi +// GFX12: encoding: [0x05,0x01,0x30,0xd6,0x7e,0x82,0xad,0x01] + +v_maximum3_f16 v5, -|exec_hi|, null, -|vcc_lo| +// GFX12: encoding: [0x05,0x05,0x30,0xd6,0x7f,0xf8,0xa8,0xa1] + +v_maximum3_f16 v5, null, exec_lo, -|0xaf12| +// GFX12: encoding: [0x05,0x04,0x30,0xd6,0x7c,0xfc,0xfc,0x83,0x12,0xaf,0x00,0x00] + +v_maximum3_f16 v5, -1, -|exec_hi|, -|src_scc| +// GFX12: encoding: [0x05,0x06,0x30,0xd6,0xc1,0xfe,0xf4,0xc3] + +v_maximum3_f16 v5, 0.5, -m0, 0.5 +// GFX12: encoding: [0x05,0x00,0x30,0xd6,0xf0,0xfa,0xc0,0x43] + +v_maximum3_f16 v5, -src_scc, |vcc_lo|, -1 +// GFX12: encoding: [0x05,0x02,0x30,0xd6,0xfd,0xd4,0x04,0x23] + +v_maximumminimum_f32 v5, v1, v2, s3 +// GFX12: encoding: [0x05,0x00,0x6d,0xd6,0x01,0x05,0x0e,0x00] + +v_maximumminimum_f32 v5, v255, s2, s105 +// GFX12: encoding: [0x05,0x00,0x6d,0xd6,0xff,0x05,0xa4,0x01] + +v_maximumminimum_f32 v5, s1, v255, exec_hi +// GFX12: encoding: [0x05,0x00,0x6d,0xd6,0x01,0xfe,0xff,0x01] + +v_maximumminimum_f32 v5, s105, s105, exec_lo +// GFX12: encoding: [0x05,0x00,0x6d,0xd6,0x69,0xd2,0xf8,0x01] + +v_maximumminimum_f32 v5, vcc_lo, ttmp15, v3 +// GFX12: encoding: [0x05,0x00,0x6d,0xd6,0x6a,0xf6,0x0c,0x04] + +v_maximumminimum_f32 v5, vcc_hi, 0xaf123456, v255 +// GFX12: encoding: [0x05,0x00,0x6d,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf] + +v_maximumminimum_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| +// GFX12: encoding: [0x05,0x07,0x6d,0xd6,0x7b,0xfa,0xed,0xe1] + +v_maximumminimum_f32 v5, m0, 0.5, m0 +// GFX12: encoding: [0x05,0x00,0x6d,0xd6,0x7d,0xe0,0xf5,0x01] + +v_maximumminimum_f32 v5, |exec_lo|, -1, vcc_hi +// GFX12: encoding: [0x05,0x01,0x6d,0xd6,0x7e,0x82,0xad,0x01] + +v_maximumminimum_f32 v5, -|exec_hi|, null, -|vcc_lo| +// GFX12: encoding: [0x05,0x05,0x6d,0xd6,0x7f,0xf8,0xa8,0xa1] + +v_maximumminimum_f32 v5, null, exec_lo, -|0xaf123456| +// GFX12: encoding: [0x05,0x04,0x6d,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf] + +v_maximumminimum_f32 v5, -1, -|exec_hi|, -|src_scc| +// GFX12: encoding: [0x05,0x06,0x6d,0xd6,0xc1,0xfe,0xf4,0xc3] + +v_maximumminimum_f32 v5, 0.5, -m0, 0.5 mul:2 +// GFX12: encoding: [0x05,0x00,0x6d,0xd6,0xf0,0xfa,0xc0,0x4b] + +v_maximumminimum_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 +// GFX12: encoding: [0x05,0x02,0x6d,0xd6,0xfd,0xd4,0x04,0x33] + +v_maximumminimum_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 +// GFX12: encoding: [0xff,0x83,0x6d,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf] + +v_minimummaximum_f32 v5, v1, v2, s3 +// GFX12: encoding: [0x05,0x00,0x6c,0xd6,0x01,0x05,0x0e,0x00] + +v_minimummaximum_f32 v5, v255, s2, s105 +// GFX12: encoding: [0x05,0x00,0x6c,0xd6,0xff,0x05,0xa4,0x01] + +v_minimummaximum_f32 v5, s1, v255, exec_hi +// GFX12: encoding: [0x05,0x00,0x6c,0xd6,0x01,0xfe,0xff,0x01] + +v_minimummaximum_f32 v5, s105, s105, exec_lo +// GFX12: encoding: [0x05,0x00,0x6c,0xd6,0x69,0xd2,0xf8,0x01] + +v_minimummaximum_f32 v5, vcc_lo, ttmp15, v3 +// GFX12: encoding: [0x05,0x00,0x6c,0xd6,0x6a,0xf6,0x0c,0x04] + +v_minimummaximum_f32 v5, vcc_hi, 0xaf123456, v255 +// GFX12: encoding: [0x05,0x00,0x6c,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf] + +v_minimummaximum_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| +// GFX12: encoding: [0x05,0x07,0x6c,0xd6,0x7b,0xfa,0xed,0xe1] + +v_minimummaximum_f32 v5, m0, 0.5, m0 +// GFX12: encoding: [0x05,0x00,0x6c,0xd6,0x7d,0xe0,0xf5,0x01] + +v_minimummaximum_f32 v5, |exec_lo|, -1, vcc_hi +// GFX12: encoding: [0x05,0x01,0x6c,0xd6,0x7e,0x82,0xad,0x01] + +v_minimummaximum_f32 v5, -|exec_hi|, null, -|vcc_lo| +// GFX12: encoding: [0x05,0x05,0x6c,0xd6,0x7f,0xf8,0xa8,0xa1] + +v_minimummaximum_f32 v5, null, exec_lo, -|0xaf123456| +// GFX12: encoding: [0x05,0x04,0x6c,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf] + +v_minimummaximum_f32 v5, -1, -|exec_hi|, -|src_scc| +// GFX12: encoding: [0x05,0x06,0x6c,0xd6,0xc1,0xfe,0xf4,0xc3] + +v_minimummaximum_f32 v5, 0.5, -m0, 0.5 mul:2 +// GFX12: encoding: [0x05,0x00,0x6c,0xd6,0xf0,0xfa,0xc0,0x4b] + +v_minimummaximum_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 +// GFX12: encoding: [0x05,0x02,0x6c,0xd6,0xfd,0xd4,0x04,0x33] + +v_minimummaximum_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 +// GFX12: encoding: [0xff,0x83,0x6c,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf] + +v_maximumminimum_f16 v5, v1, v2, s3 +// GFX12: encoding: [0x05,0x00,0x6f,0xd6,0x01,0x05,0x0e,0x00] + +v_maximumminimum_f16 v5, v255, s2, s105 +// GFX12: encoding: [0x05,0x00,0x6f,0xd6,0xff,0x05,0xa4,0x01] + +v_maximumminimum_f16 v5, s1, v255, exec_hi +// GFX12: encoding: [0x05,0x00,0x6f,0xd6,0x01,0xfe,0xff,0x01] + +v_maximumminimum_f16 v5, s105, s105, exec_lo +// GFX12: encoding: [0x05,0x00,0x6f,0xd6,0x69,0xd2,0xf8,0x01] + +v_maximumminimum_f16 v5, vcc_lo, ttmp15, v3 +// GFX12: encoding: [0x05,0x00,0x6f,0xd6,0x6a,0xf6,0x0c,0x04] + +v_maximumminimum_f16 v5, vcc_hi, 0xaf12, v255 +// GFX12: encoding: [0x05,0x00,0x6f,0xd6,0x6b,0xfe,0xfd,0x07,0x12,0xaf,0x00,0x00] + +v_maximumminimum_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| +// GFX12: encoding: [0x05,0x07,0x6f,0xd6,0x7b,0xfa,0xed,0xe1] + +v_maximumminimum_f16 v5, m0, 0.5, m0 +// GFX12: encoding: [0x05,0x00,0x6f,0xd6,0x7d,0xe0,0xf5,0x01] + +v_maximumminimum_f16 v5, |exec_lo|, -1, vcc_hi +// GFX12: encoding: [0x05,0x01,0x6f,0xd6,0x7e,0x82,0xad,0x01] + +v_maximumminimum_f16 v5, -|exec_hi|, null, -|vcc_lo| +// GFX12: encoding: [0x05,0x05,0x6f,0xd6,0x7f,0xf8,0xa8,0xa1] + +v_maximumminimum_f16 v5, null, exec_lo, -|0xaf12| +// GFX12: encoding: [0x05,0x04,0x6f,0xd6,0x7c,0xfc,0xfc,0x83,0x12,0xaf,0x00,0x00] + +v_maximumminimum_f16 v5, -1, -|exec_hi|, -|src_scc| +// GFX12: encoding: [0x05,0x06,0x6f,0xd6,0xc1,0xfe,0xf4,0xc3] + +v_maximumminimum_f16 v5, 0.5, -m0, 0.5 +// GFX12: encoding: [0x05,0x00,0x6f,0xd6,0xf0,0xfa,0xc0,0x43] + +v_maximumminimum_f16 v5, -src_scc, |vcc_lo|, -1 +// GFX12: encoding: [0x05,0x02,0x6f,0xd6,0xfd,0xd4,0x04,0x23] + +v_maximumminimum_f16 v255, -|0xaf12|, -|vcc_hi|, null clamp +// GFX12: encoding: [0xff,0x83,0x6f,0xd6,0xff,0xd6,0xf0,0x61,0x12,0xaf,0x00,0x00] + +v_minimummaximum_f16 v5, v1, v2, s3 +// GFX12: encoding: [0x05,0x00,0x6e,0xd6,0x01,0x05,0x0e,0x00] + +v_minimummaximum_f16 v5, v255, s2, s105 +// GFX12: encoding: [0x05,0x00,0x6e,0xd6,0xff,0x05,0xa4,0x01] + +v_minimummaximum_f16 v5, s1, v255, exec_hi +// GFX12: encoding: [0x05,0x00,0x6e,0xd6,0x01,0xfe,0xff,0x01] + +v_minimummaximum_f16 v5, s105, s105, exec_lo +// GFX12: encoding: [0x05,0x00,0x6e,0xd6,0x69,0xd2,0xf8,0x01] + +v_minimummaximum_f16 v5, vcc_lo, ttmp15, v3 +// GFX12: encoding: [0x05,0x00,0x6e,0xd6,0x6a,0xf6,0x0c,0x04] + +v_minimummaximum_f16 v5, vcc_hi, 0xaf12, v255 +// GFX12: encoding: [0x05,0x00,0x6e,0xd6,0x6b,0xfe,0xfd,0x07,0x12,0xaf,0x00,0x00] + +v_minimummaximum_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| +// GFX12: encoding: [0x05,0x07,0x6e,0xd6,0x7b,0xfa,0xed,0xe1] + +v_minimummaximum_f16 v5, m0, 0.5, m0 +// GFX12: encoding: [0x05,0x00,0x6e,0xd6,0x7d,0xe0,0xf5,0x01] + +v_minimummaximum_f16 v5, |exec_lo|, -1, vcc_hi +// GFX12: encoding: [0x05,0x01,0x6e,0xd6,0x7e,0x82,0xad,0x01] + +v_minimummaximum_f16 v5, -|exec_hi|, null, -|vcc_lo| +// GFX12: encoding: [0x05,0x05,0x6e,0xd6,0x7f,0xf8,0xa8,0xa1] + +v_minimummaximum_f16 v5, null, exec_lo, -|0xaf12| +// GFX12: encoding: [0x05,0x04,0x6e,0xd6,0x7c,0xfc,0xfc,0x83,0x12,0xaf,0x00,0x00] + +v_minimummaximum_f16 v5, -1, -|exec_hi|, -|src_scc| +// GFX12: encoding: [0x05,0x06,0x6e,0xd6,0xc1,0xfe,0xf4,0xc3] + +v_minimummaximum_f16 v5, 0.5, -m0, 0.5 +// GFX12: encoding: [0x05,0x00,0x6e,0xd6,0xf0,0xfa,0xc0,0x43] + +v_minimummaximum_f16 v5, -src_scc, |vcc_lo|, -1 +// GFX12: encoding: [0x05,0x02,0x6e,0xd6,0xfd,0xd4,0x04,0x23] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s index 63087442c464..26f63102df95 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s @@ -4693,3 +4693,504 @@ v_dot2_bf16_bf16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] quad_perm:[0,1,2, v_dot2_bf16_bf16_e64_dpp v5, v1, v2, 0 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf // GFX12: [0x05,0x00,0x67,0xd6,0xfa,0x04,0x02,0x02,0x01,0x1b,0x00,0xff] + +v_minimum_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] + +v_minimum_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] + +v_minimum_f32 v5, v1, v2 row_mirror +// GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] + +v_minimum_f32 v5, v1, v2 row_half_mirror +// GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] + +v_minimum_f32 v5, v1, v2 row_shl:1 +// GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] + +v_minimum_f32 v5, v1, v2 row_shl:15 +// GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] + +v_minimum_f32 v5, v1, v2 row_shr:1 +// GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] + +v_minimum_f32 v5, v1, v2 row_shr:15 +// GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] + +v_minimum_f32 v5, v1, v2 row_ror:1 +// GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] + +v_minimum_f32 v5, v1, v2 row_ror:15 +// GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] + +v_minimum_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] + +v_minimum_f32 v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: [0x05,0x01,0x65,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] + +v_minimum_f32 v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: [0x05,0x02,0x65,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] + +v_minimum_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: [0xff,0x03,0x65,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] + +v_maximum_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] + +v_maximum_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] + +v_maximum_f32 v5, v1, v2 row_mirror +// GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] + +v_maximum_f32 v5, v1, v2 row_half_mirror +// GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] + +v_maximum_f32 v5, v1, v2 row_shl:1 +// GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] + +v_maximum_f32 v5, v1, v2 row_shl:15 +// GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] + +v_maximum_f32 v5, v1, v2 row_shr:1 +// GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] + +v_maximum_f32 v5, v1, v2 row_shr:15 +// GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] + +v_maximum_f32 v5, v1, v2 row_ror:1 +// GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] + +v_maximum_f32 v5, v1, v2 row_ror:15 +// GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] + +v_maximum_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] + +v_maximum_f32 v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: [0x05,0x01,0x66,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] + +v_maximum_f32 v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: [0x05,0x02,0x66,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] + +v_maximum_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: [0xff,0x03,0x66,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] + +v_minimum_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] + +v_minimum_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] + +v_minimum_f16 v5, v1, v2 row_mirror +// GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] + +v_minimum_f16 v5, v1, v2 row_half_mirror +// GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] + +v_minimum_f16 v5, v1, v2 row_shl:1 +// GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] + +v_minimum_f16 v5, v1, v2 row_shl:15 +// GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] + +v_minimum_f16 v5, v1, v2 row_shr:1 +// GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] + +v_minimum_f16 v5, v1, v2 row_shr:15 +// GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] + +v_minimum_f16 v5, v1, v2 row_ror:1 +// GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] + +v_minimum_f16 v5, v1, v2 row_ror:15 +// GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] + +v_minimum_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] + +v_minimum_f16 v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: [0x05,0x01,0x67,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] + +v_minimum_f16 v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: [0x05,0x02,0x67,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] + +v_minimum_f16 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: [0xff,0x03,0x67,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] + +v_maximum_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] + +v_maximum_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] + +v_maximum_f16 v5, v1, v2 row_mirror +// GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] + +v_maximum_f16 v5, v1, v2 row_half_mirror +// GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] + +v_maximum_f16 v5, v1, v2 row_shl:1 +// GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] + +v_maximum_f16 v5, v1, v2 row_shl:15 +// GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] + +v_maximum_f16 v5, v1, v2 row_shr:1 +// GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] + +v_maximum_f16 v5, v1, v2 row_shr:15 +// GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] + +v_maximum_f16 v5, v1, v2 row_ror:1 +// GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] + +v_maximum_f16 v5, v1, v2 row_ror:15 +// GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] + +v_maximum_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] + +v_maximum_f16 v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: [0x05,0x01,0x68,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] + +v_maximum_f16 v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: [0x05,0x02,0x68,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] + +v_maximum_f16 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: [0xff,0x03,0x68,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30] + +v_minimum3_f32 v5, v1, v2, v3 quad_perm:[3,2,1,0] +// GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] + +v_minimum3_f32 v5, v1, v2, v3 quad_perm:[0,1,2,3] +// GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] + +v_minimum3_f32 v5, v1, v2, v3 row_mirror +// GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] + +v_minimum3_f32 v5, v1, v2, v255 row_half_mirror +// GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] + +v_minimum3_f32 v5, v1, v2, s105 row_shl:1 +// GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] + +v_minimum3_f32 v5, v1, v2, vcc_hi row_shl:15 +// GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] + +v_minimum3_f32 v5, v1, v2, vcc_lo row_shr:1 +// GFX12: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] + +v_minimum3_f32 v5, |v1|, v2, -ttmp15 row_shr:15 +// GFX12: [0x05,0x01,0x2d,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] + +v_minimum3_f32 v5, v1, -|v2|, exec_hi row_ror:1 +// GFX12: [0x05,0x02,0x2d,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] + +v_minimum3_f32 v5, -v1, v2, |exec_lo| row_ror:15 +// GFX12: [0x05,0x04,0x2d,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] + +v_minimum3_f32 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: [0x05,0x03,0x2d,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] + +v_minimum3_f32 v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: [0x05,0x05,0x2d,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] + +v_minimum3_f32 v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: [0x05,0x06,0x2d,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] + +v_minimum3_f32 v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: [0xff,0x87,0x2d,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] + +v_maximum3_f32 v5, v1, v2, v3 quad_perm:[3,2,1,0] +// GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] + +v_maximum3_f32 v5, v1, v2, v3 quad_perm:[0,1,2,3] +// GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] + +v_maximum3_f32 v5, v1, v2, v3 row_mirror +// GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] + +v_maximum3_f32 v5, v1, v2, v255 row_half_mirror +// GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] + +v_maximum3_f32 v5, v1, v2, s105 row_shl:1 +// GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] + +v_maximum3_f32 v5, v1, v2, vcc_hi row_shl:15 +// GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] + +v_maximum3_f32 v5, v1, v2, vcc_lo row_shr:1 +// GFX12: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] + +v_maximum3_f32 v5, |v1|, v2, -ttmp15 row_shr:15 +// GFX12: [0x05,0x01,0x2e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] + +v_maximum3_f32 v5, v1, -|v2|, exec_hi row_ror:1 +// GFX12: [0x05,0x02,0x2e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] + +v_maximum3_f32 v5, -v1, v2, |exec_lo| row_ror:15 +// GFX12: [0x05,0x04,0x2e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] + +v_maximum3_f32 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: [0x05,0x03,0x2e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] + +v_maximum3_f32 v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: [0x05,0x05,0x2e,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] + +v_maximum3_f32 v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: [0x05,0x06,0x2e,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] + +v_maximum3_f32 v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: [0xff,0x87,0x2e,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] + +v_minimum3_f16 v5, v1, v2, v3 quad_perm:[3,2,1,0] +// GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] + +v_minimum3_f16 v5, v1, v2, v3 quad_perm:[0,1,2,3] +// GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] + +v_minimum3_f16 v5, v1, v2, v3 row_mirror +// GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] + +v_minimum3_f16 v5, v1, v2, v255 row_half_mirror +// GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] + +v_minimum3_f16 v5, v1, v2, s105 row_shl:1 +// GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] + +v_minimum3_f16 v5, v1, v2, vcc_hi row_shl:15 +// GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] + +v_minimum3_f16 v5, v1, v2, vcc_lo row_shr:1 +// GFX12: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] + +v_minimum3_f16 v5, |v1|, v2, -ttmp15 row_shr:15 +// GFX12: [0x05,0x01,0x2f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] + +v_minimum3_f16 v5, v1, -|v2|, exec_hi row_ror:1 +// GFX12: [0x05,0x02,0x2f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] + +v_minimum3_f16 v5, -v1, v2, |exec_lo| row_ror:15 +// GFX12: [0x05,0x04,0x2f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] + +v_minimum3_f16 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: [0x05,0x03,0x2f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] + +v_minimum3_f16 v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: [0x05,0x05,0x2f,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] + +v_minimum3_f16 v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: [0x05,0x06,0x2f,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] + +v_minimum3_f16 v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: [0xff,0x87,0x2f,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30] + +v_maximum3_f16 v5, v1, v2, v3 quad_perm:[3,2,1,0] +// GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] + +v_maximum3_f16 v5, v1, v2, v3 quad_perm:[0,1,2,3] +// GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] + +v_maximum3_f16 v5, v1, v2, v3 row_mirror +// GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] + +v_maximum3_f16 v5, v1, v2, v255 row_half_mirror +// GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] + +v_maximum3_f16 v5, v1, v2, s105 row_shl:1 +// GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] + +v_maximum3_f16 v5, v1, v2, vcc_hi row_shl:15 +// GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] + +v_maximum3_f16 v5, v1, v2, vcc_lo row_shr:1 +// GFX12: [0x05,0x00,0x30,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] + +v_maximum3_f16 v5, |v1|, v2, -ttmp15 row_shr:15 +// GFX12: [0x05,0x01,0x30,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] + +v_maximum3_f16 v5, v1, -|v2|, exec_hi row_ror:1 +// GFX12: [0x05,0x02,0x30,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] + +v_maximum3_f16 v5, -v1, v2, |exec_lo| row_ror:15 +// GFX12: [0x05,0x04,0x30,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] + +v_maximum3_f16 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: [0x05,0x03,0x30,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] + +v_maximum3_f16 v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: [0x05,0x05,0x30,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] + +v_maximum3_f16 v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: [0x05,0x06,0x30,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] + +v_maximum3_f16 v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: [0xff,0x87,0x30,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30] + +v_maximumminimum_f32 v5, v1, v2, v3 quad_perm:[0,1,2,3] +// GFX12: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] + +v_maximumminimum_f32 v5, v1, v2, v3 row_mirror +// GFX12: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] + +v_maximumminimum_f32 v5, v1, v2, v255 row_half_mirror +// GFX12: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] + +v_maximumminimum_f32 v5, v1, v2, s105 row_shl:1 +// GFX12: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] + +v_maximumminimum_f32 v5, v1, v2, vcc_hi row_shl:15 +// GFX12: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] + +v_maximumminimum_f32 v5, v1, v2, vcc_lo row_shr:1 +// GFX12: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] + +v_maximumminimum_f32 v5, |v1|, v2, -ttmp15 row_shr:15 +// GFX12: [0x05,0x01,0x6d,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] + +v_maximumminimum_f32 v5, v1, -|v2|, exec_hi row_ror:1 +// GFX12: [0x05,0x02,0x6d,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] + +v_maximumminimum_f32 v5, -v1, v2, |exec_lo| row_ror:15 +// GFX12: [0x05,0x04,0x6d,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] + +v_maximumminimum_f32 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: [0x05,0x03,0x6d,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] + +v_maximumminimum_f32 v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: [0x05,0x05,0x6d,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] + +v_maximumminimum_f32 v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: [0x05,0x06,0x6d,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] + +v_maximumminimum_f32 v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: [0xff,0x87,0x6d,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] + +v_minimummaximum_f32 v5, v1, v2, v3 quad_perm:[3,2,1,0] +// GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] + +v_minimummaximum_f32 v5, v1, v2, v3 quad_perm:[0,1,2,3] +// GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] + +v_minimummaximum_f32 v5, v1, v2, v3 row_mirror +// GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] + +v_minimummaximum_f32 v5, v1, v2, v255 row_half_mirror +// GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] + +v_minimummaximum_f32 v5, v1, v2, s105 row_shl:1 +// GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] + +v_minimummaximum_f32 v5, v1, v2, vcc_hi row_shl:15 +// GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] + +v_minimummaximum_f32 v5, v1, v2, vcc_lo row_shr:1 +// GFX12: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] + +v_minimummaximum_f32 v5, |v1|, v2, -ttmp15 row_shr:15 +// GFX12: [0x05,0x01,0x6c,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] + +v_minimummaximum_f32 v5, v1, -|v2|, exec_hi row_ror:1 +// GFX12: [0x05,0x02,0x6c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] + +v_minimummaximum_f32 v5, -v1, v2, |exec_lo| row_ror:15 +// GFX12: [0x05,0x04,0x6c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] + +v_minimummaximum_f32 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: [0x05,0x03,0x6c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] + +v_minimummaximum_f32 v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: [0x05,0x05,0x6c,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] + +v_minimummaximum_f32 v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: [0x05,0x06,0x6c,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] + +v_minimummaximum_f32 v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: [0xff,0x87,0x6c,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30] + +v_maximumminimum_f16 v5, v1, v2, v3 quad_perm:[3,2,1,0] +// GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] + +v_maximumminimum_f16 v5, v1, v2, v3 quad_perm:[0,1,2,3] +// GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] + +v_maximumminimum_f16 v5, v1, v2, v3 row_mirror +// GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] + +v_maximumminimum_f16 v5, v1, v2, v255 row_half_mirror +// GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] + +v_maximumminimum_f16 v5, v1, v2, s105 row_shl:1 +// GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] + +v_maximumminimum_f16 v5, v1, v2, vcc_hi row_shl:15 +// GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] + +v_maximumminimum_f16 v5, v1, v2, vcc_lo row_shr:1 +// GFX12: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] + +v_maximumminimum_f16 v5, |v1|, v2, -ttmp15 row_shr:15 +// GFX12: [0x05,0x01,0x6f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] + +v_maximumminimum_f16 v5, v1, -|v2|, exec_hi row_ror:1 +// GFX12: [0x05,0x02,0x6f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] + +v_maximumminimum_f16 v5, -v1, v2, |exec_lo| row_ror:15 +// GFX12: [0x05,0x04,0x6f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] + +v_maximumminimum_f16 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: [0x05,0x03,0x6f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] + +v_maximumminimum_f16 v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: [0x05,0x05,0x6f,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] + +v_maximumminimum_f16 v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: [0x05,0x06,0x6f,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] + +v_maximumminimum_f16 v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: [0xff,0x87,0x6f,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30] + +v_minimummaximum_f16 v5, v1, v2, v3 quad_perm:[3,2,1,0] +// GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] + +v_minimummaximum_f16 v5, v1, v2, v3 quad_perm:[0,1,2,3] +// GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] + +v_minimummaximum_f16 v5, v1, v2, v3 row_mirror +// GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] + +v_minimummaximum_f16 v5, v1, v2, v255 row_half_mirror +// GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] + +v_minimummaximum_f16 v5, v1, v2, s105 row_shl:1 +// GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] + +v_minimummaximum_f16 v5, v1, v2, vcc_hi row_shl:15 +// GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] + +v_minimummaximum_f16 v5, v1, v2, vcc_lo row_shr:1 +// GFX12: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] + +v_minimummaximum_f16 v5, |v1|, v2, -ttmp15 row_shr:15 +// GFX12: [0x05,0x01,0x6e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] + +v_minimummaximum_f16 v5, v1, -|v2|, exec_hi row_ror:1 +// GFX12: [0x05,0x02,0x6e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] + +v_minimummaximum_f16 v5, -v1, v2, |exec_lo| row_ror:15 +// GFX12: [0x05,0x04,0x6e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] + +v_minimummaximum_f16 v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: [0x05,0x03,0x6e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] + +v_minimummaximum_f16 v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: [0x05,0x05,0x6e,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] + +v_minimummaximum_f16 v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: [0x05,0x06,0x6e,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] + +v_minimummaximum_f16 v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: [0xff,0x87,0x6e,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s index 82807aca0e7b..de294b1ff2a2 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s @@ -2966,3 +2966,339 @@ v_dot2_bf16_bf16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] dpp8:[0,1,2,3,4,4 v_dot2_bf16_bf16_e64_dpp v5, v1, v2, 0 dpp8:[7,6,5,4,3,2,1,0] // GFX12: [0x05,0x00,0x67,0xd6,0xe9,0x04,0x02,0x02,0x01,0x77,0x39,0x05] + +v_minimum_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x65,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_minimum_f32 v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x01,0x65,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] + +v_minimum_f32 v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: [0x05,0x02,0x65,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +v_minimum_f32 v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: [0xff,0x03,0x65,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +v_maximum_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x66,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_maximum_f32 v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x01,0x66,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] + +v_maximum_f32 v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: [0x05,0x02,0x66,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +v_maximum_f32 v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: [0xff,0x03,0x66,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +v_minimum_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x67,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_minimum_f16 v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x01,0x67,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] + +v_minimum_f16 v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: [0x05,0x02,0x67,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +v_minimum_f16 v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: [0xff,0x03,0x67,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +v_maximum_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x68,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_maximum_f16 v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x01,0x68,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] + +v_maximum_f16 v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: [0x05,0x02,0x68,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] + +v_maximum_f16 v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: [0xff,0x03,0x68,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] + +v_minimum3_f32 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] + +v_minimum3_f32 v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] + +v_minimum3_f32 v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] + +v_minimum3_f32 v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] + +v_minimum3_f32 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] + +v_minimum3_f32 v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x01,0x2d,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] + +v_minimum3_f32 v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x02,0x2d,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] + +v_minimum3_f32 v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x04,0x2d,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] + +v_minimum3_f32 v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x03,0x2d,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] + +v_minimum3_f32 v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x05,0x2d,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05] + +v_minimum3_f32 v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: [0x05,0x06,0x2d,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05] + +v_minimum3_f32 v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: [0xff,0x87,0x2d,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00] + +v_maximum3_f32 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] + +v_maximum3_f32 v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] + +v_maximum3_f32 v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] + +v_maximum3_f32 v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] + +v_maximum3_f32 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] + +v_maximum3_f32 v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x01,0x2e,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] + +v_maximum3_f32 v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x02,0x2e,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] + +v_maximum3_f32 v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x04,0x2e,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] + +v_maximum3_f32 v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x03,0x2e,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] + +v_maximum3_f32 v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x05,0x2e,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05] + +v_maximum3_f32 v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: [0x05,0x06,0x2e,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05] + +v_maximum3_f32 v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: [0xff,0x87,0x2e,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00] + +v_minimum3_f16 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2f,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] + +v_minimum3_f16 v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2f,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] + +v_minimum3_f16 v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2f,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] + +v_minimum3_f16 v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2f,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] + +v_minimum3_f16 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x2f,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] + +v_minimum3_f16 v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x01,0x2f,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] + +v_minimum3_f16 v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x02,0x2f,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] + +v_minimum3_f16 v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x04,0x2f,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] + +v_minimum3_f16 v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x03,0x2f,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] + +v_minimum3_f16 v5, -|v1|, v2, -|-1| dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x05,0x2f,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05] + +v_minimum3_f16 v5, v1, -|v2|, -|0.5| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: [0x05,0x06,0x2f,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05] + +v_minimum3_f16 v255, -|v255|, -|v255|, -|src_scc| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: [0xff,0x87,0x2f,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00] + +v_maximum3_f16 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x30,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] + +v_maximum3_f16 v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x30,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] + +v_maximum3_f16 v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x30,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] + +v_maximum3_f16 v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x30,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] + +v_maximum3_f16 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x30,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] + +v_maximum3_f16 v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x01,0x30,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] + +v_maximum3_f16 v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x02,0x30,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] + +v_maximum3_f16 v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x04,0x30,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] + +v_maximum3_f16 v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x03,0x30,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] + +v_maximum3_f16 v5, -|v1|, v2, -|-1| dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x05,0x30,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05] + +v_maximum3_f16 v5, v1, -|v2|, -|0.5| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: [0x05,0x06,0x30,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05] + +v_maximum3_f16 v255, -|v255|, -|v255|, -|src_scc| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: [0xff,0x87,0x30,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00] + +v_maximumminimum_f32 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] + +v_maximumminimum_f32 v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] + +v_maximumminimum_f32 v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] + +v_maximumminimum_f32 v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] + +v_maximumminimum_f32 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] + +v_maximumminimum_f32 v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x01,0x6d,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] + +v_maximumminimum_f32 v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x02,0x6d,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] + +v_maximumminimum_f32 v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x04,0x6d,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] + +v_maximumminimum_f32 v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x03,0x6d,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] + +v_maximumminimum_f32 v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x05,0x6d,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05] + +v_maximumminimum_f32 v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: [0x05,0x06,0x6d,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05] + +v_maximumminimum_f32 v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: [0xff,0x87,0x6d,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00] + +v_minimummaximum_f32 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6c,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] + +v_minimummaximum_f32 v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6c,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] + +v_minimummaximum_f32 v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6c,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] + +v_minimummaximum_f32 v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6c,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] + +v_minimummaximum_f32 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6c,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] + +v_minimummaximum_f32 v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x01,0x6c,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] + +v_minimummaximum_f32 v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x02,0x6c,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] + +v_minimummaximum_f32 v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x04,0x6c,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] + +v_minimummaximum_f32 v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x03,0x6c,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] + +v_minimummaximum_f32 v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x05,0x6c,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05] + +v_minimummaximum_f32 v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: [0x05,0x06,0x6c,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05] + +v_minimummaximum_f32 v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: [0xff,0x87,0x6c,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00] + +v_maximumminimum_f16 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6f,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] + +v_maximumminimum_f16 v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6f,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] + +v_maximumminimum_f16 v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6f,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] + +v_maximumminimum_f16 v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6f,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] + +v_maximumminimum_f16 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6f,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] + +v_maximumminimum_f16 v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x01,0x6f,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] + +v_maximumminimum_f16 v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x02,0x6f,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] + +v_maximumminimum_f16 v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x04,0x6f,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] + +v_maximumminimum_f16 v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x03,0x6f,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] + +v_maximumminimum_f16 v5, -|v1|, v2, -|-1| dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x05,0x6f,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05] + +v_maximumminimum_f16 v5, v1, -|v2|, -|0.5| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: [0x05,0x06,0x6f,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05] + +v_maximumminimum_f16 v255, -|v255|, -|v255|, -|src_scc| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: [0xff,0x87,0x6f,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00] + +v_minimummaximum_f16 v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] + +v_minimummaximum_f16 v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] + +v_minimummaximum_f16 v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] + +v_minimummaximum_f16 v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] + +v_minimummaximum_f16 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x00,0x6e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] + +v_minimummaximum_f16 v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x01,0x6e,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] + +v_minimummaximum_f16 v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x02,0x6e,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] + +v_minimummaximum_f16 v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x04,0x6e,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] + +v_minimummaximum_f16 v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x03,0x6e,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] + +v_minimummaximum_f16 v5, -|v1|, v2, -|-1| dpp8:[7,6,5,4,3,2,1,0] +// GFX12: [0x05,0x05,0x6e,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05] + +v_minimummaximum_f16 v5, v1, -|v2|, -|0.5| dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: [0x05,0x06,0x6e,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05] + +v_minimummaximum_f16 v255, -|v255|, -|v255|, -|src_scc| clamp dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: [0xff,0x87,0x6e,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s index 7a4687b34f8f..9a21f7a2eb56 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s @@ -1250,3 +1250,93 @@ v_pk_sub_u16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] v_pk_sub_u16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] clamp // GFX12: [0xff,0xd0,0x0b,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00] + +v_pk_minimum_f16 v5, v1, v2 +// GFX12: [0x05,0x40,0x1d,0xcc,0x01,0x05,0x02,0x18] + +v_pk_minimum_f16 v5, v255, v255 +// GFX12: [0x05,0x40,0x1d,0xcc,0xff,0xff,0x03,0x18] + +v_pk_minimum_f16 v5, s1, s2 +// GFX12: [0x05,0x40,0x1d,0xcc,0x01,0x04,0x00,0x18] + +v_pk_minimum_f16 v5, s105, s105 +// GFX12: [0x05,0x40,0x1d,0xcc,0x69,0xd2,0x00,0x18] + +v_pk_minimum_f16 v5, vcc_lo, ttmp15 +// GFX12: [0x05,0x40,0x1d,0xcc,0x6a,0xf6,0x00,0x18] + +v_pk_minimum_f16 v5, vcc_hi, 0xfe0b +// GFX12: [0x05,0x40,0x1d,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00] + +v_pk_minimum_f16 v5, ttmp15, src_scc +// GFX12: [0x05,0x40,0x1d,0xcc,0x7b,0xfa,0x01,0x18] + +v_pk_minimum_f16 v5, m0, 0.5 +// GFX12: [0x05,0x40,0x1d,0xcc,0x7d,0xe0,0x01,0x18] + +v_pk_minimum_f16 v5, exec_lo, -1 +// GFX12: [0x05,0x40,0x1d,0xcc,0x7e,0x82,0x01,0x18] + +v_pk_minimum_f16 v5, exec_hi, null +// GFX12: [0x05,0x40,0x1d,0xcc,0x7f,0xf8,0x00,0x18] + +v_pk_minimum_f16 v5, null, exec_lo +// GFX12: [0x05,0x40,0x1d,0xcc,0x7c,0xfc,0x00,0x18] + +v_pk_minimum_f16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0] neg_lo:[1,0] neg_hi:[1,0] +// GFX12: [0x05,0x59,0x1d,0xcc,0xc1,0xfe,0x00,0x20] + +v_pk_minimum_f16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1] neg_lo:[0,1] neg_hi:[0,1] +// GFX12: [0x05,0x42,0x1d,0xcc,0xf0,0xfa,0x00,0x58] + +v_pk_minimum_f16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] neg_lo:[0,0] neg_hi:[0,0] +// GFX12: [0x05,0x48,0x1d,0xcc,0xfd,0xd4,0x00,0x10] + +v_pk_minimum_f16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] neg_lo:[1,1] neg_hi:[1,1] clamp +// GFX12: [0xff,0xd3,0x1d,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00] + +v_pk_maximum_f16 v5, v1, v2 +// GFX12: [0x05,0x40,0x1e,0xcc,0x01,0x05,0x02,0x18] + +v_pk_maximum_f16 v5, v255, v255 +// GFX12: [0x05,0x40,0x1e,0xcc,0xff,0xff,0x03,0x18] + +v_pk_maximum_f16 v5, s1, s2 +// GFX12: [0x05,0x40,0x1e,0xcc,0x01,0x04,0x00,0x18] + +v_pk_maximum_f16 v5, s105, s105 +// GFX12: [0x05,0x40,0x1e,0xcc,0x69,0xd2,0x00,0x18] + +v_pk_maximum_f16 v5, vcc_lo, ttmp15 +// GFX12: [0x05,0x40,0x1e,0xcc,0x6a,0xf6,0x00,0x18] + +v_pk_maximum_f16 v5, vcc_hi, 0xfe0b +// GFX12: [0x05,0x40,0x1e,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00] + +v_pk_maximum_f16 v5, ttmp15, src_scc +// GFX12: [0x05,0x40,0x1e,0xcc,0x7b,0xfa,0x01,0x18] + +v_pk_maximum_f16 v5, m0, 0.5 +// GFX12: [0x05,0x40,0x1e,0xcc,0x7d,0xe0,0x01,0x18] + +v_pk_maximum_f16 v5, exec_lo, -1 +// GFX12: [0x05,0x40,0x1e,0xcc,0x7e,0x82,0x01,0x18] + +v_pk_maximum_f16 v5, exec_hi, null +// GFX12: [0x05,0x40,0x1e,0xcc,0x7f,0xf8,0x00,0x18] + +v_pk_maximum_f16 v5, null, exec_lo +// GFX12: [0x05,0x40,0x1e,0xcc,0x7c,0xfc,0x00,0x18] + +v_pk_maximum_f16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0] neg_lo:[1,0] neg_hi:[1,0] +// GFX12: [0x05,0x59,0x1e,0xcc,0xc1,0xfe,0x00,0x20] + +v_pk_maximum_f16 v5, 0.5, m0 op_sel:[0,0] op_sel_hi:[1,1] neg_lo:[0,1] neg_hi:[0,1] +// GFX12: [0x05,0x42,0x1e,0xcc,0xf0,0xfa,0x00,0x58] + +v_pk_maximum_f16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] neg_lo:[0,0] neg_hi:[0,0] +// GFX12: [0x05,0x48,0x1e,0xcc,0xfd,0xd4,0x00,0x10] + +v_pk_maximum_f16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] neg_lo:[1,1] neg_hi:[1,1] clamp +// GFX12: [0xff,0xd3,0x1e,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/hsa-gfx12-v4.s b/llvm/test/MC/AMDGPU/hsa-gfx12-v4.s new file mode 100644 index 000000000000..efbcec21f586 --- /dev/null +++ b/llvm/test/MC/AMDGPU/hsa-gfx12-v4.s @@ -0,0 +1,294 @@ +// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx1200 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefix=ASM %s +// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx1200 --amdhsa-code-object-version=4 -filetype=obj < %s > %t +// RUN: llvm-readelf -S -r -s %t | FileCheck --check-prefix=READOBJ %s +// RUN: llvm-objdump -s -j .rodata %t | FileCheck --check-prefix=OBJDUMP %s + +// READOBJ: Section Headers +// READOBJ: .text PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9]+}} AX {{[0-9]+}} {{[0-9]+}} 256 +// READOBJ: .rodata PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} 000100 {{[0-9]+}} A {{[0-9]+}} {{[0-9]+}} 64 + +// READOBJ: Relocation section '.rela.rodata' at offset +// READOBJ: 0000000000000010 {{[0-9a-f]+}}00000005 R_AMDGPU_REL64 0000000000000000 .text + 10 +// READOBJ: 0000000000000050 {{[0-9a-f]+}}00000005 R_AMDGPU_REL64 0000000000000000 .text + 110 +// READOBJ: 0000000000000090 {{[0-9a-f]+}}00000005 R_AMDGPU_REL64 0000000000000000 .text + 210 +// READOBJ: 00000000000000d0 {{[0-9a-f]+}}00000005 R_AMDGPU_REL64 0000000000000000 .text + 310 + +// READOBJ: Symbol table '.symtab' contains {{[0-9]+}} entries: +// READOBJ: 0000000000000000 0 FUNC LOCAL PROTECTED 2 minimal +// READOBJ-NEXT: 0000000000000100 0 FUNC LOCAL PROTECTED 2 complete +// READOBJ-NEXT: 0000000000000200 0 FUNC LOCAL PROTECTED 2 special_sgpr +// READOBJ-NEXT: 0000000000000300 0 FUNC LOCAL PROTECTED 2 disabled_user_sgpr +// READOBJ-NEXT: 0000000000000000 64 OBJECT LOCAL DEFAULT 3 minimal.kd +// READOBJ-NEXT: 0000000000000040 64 OBJECT LOCAL DEFAULT 3 complete.kd +// READOBJ-NEXT: 0000000000000080 64 OBJECT LOCAL DEFAULT 3 special_sgpr.kd +// READOBJ-NEXT: 00000000000000c0 64 OBJECT LOCAL DEFAULT 3 disabled_user_sgpr.kd + +// OBJDUMP: Contents of section .rodata +// Note, relocation for KERNEL_CODE_ENTRY_BYTE_OFFSET is not resolved here. +// minimal +// OBJDUMP-NEXT: 0000 00000000 00000000 00000000 00000000 +// OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000 +// OBJDUMP-NEXT: 0020 00000000 00000000 00000000 00000000 +// OBJDUMP-NEXT: 0030 00000c60 80000000 00000000 00000000 +// complete +// OBJDUMP-NEXT: 0040 01000000 01000000 08000000 00000000 +// OBJDUMP-NEXT: 0050 00000000 00000000 00000000 00000000 +// OBJDUMP-NEXT: 0060 00000000 00000000 00000000 00000000 +// OBJDUMP-NEXT: 0070 015021e4 1f0f007f 5e040000 00000000 +// special_sgpr +// OBJDUMP-NEXT: 0080 00000000 00000000 00000000 00000000 +// OBJDUMP-NEXT: 0090 00000000 00000000 00000000 00000000 +// OBJDUMP-NEXT: 00a0 00000000 00000000 00000000 00000000 +// OBJDUMP-NEXT: 00b0 00000060 80000000 00000000 00000000 +// disabled_user_sgpr +// OBJDUMP-NEXT: 00c0 00000000 00000000 00000000 00000000 +// OBJDUMP-NEXT: 00d0 00000000 00000000 00000000 00000000 +// OBJDUMP-NEXT: 00e0 00000000 00000000 00000000 00000000 +// OBJDUMP-NEXT: 00f0 00000c60 80000000 00000000 00000000 + +.text +// ASM: .text + +.amdgcn_target "amdgcn-amd-amdhsa--gfx1200" +// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx1200" + +.p2align 8 +.type minimal,@function +minimal: + s_endpgm + +.p2align 8 +.type complete,@function +complete: + s_endpgm + +.p2align 8 +.type special_sgpr,@function +special_sgpr: + s_endpgm + +.p2align 8 +.type disabled_user_sgpr,@function +disabled_user_sgpr: + s_endpgm + +.rodata +// ASM: .rodata + +// Test that only specifying required directives is allowed, and that defaulted +// values are omitted. +.p2align 6 +.amdhsa_kernel minimal + .amdhsa_next_free_vgpr 0 + .amdhsa_next_free_sgpr 0 +.end_amdhsa_kernel + +// ASM: .amdhsa_kernel minimal +// ASM: .amdhsa_next_free_vgpr 0 +// ASM-NEXT: .amdhsa_next_free_sgpr 0 +// ASM: .end_amdhsa_kernel + +// Test that we can specify all available directives with non-default values. +.p2align 6 +.amdhsa_kernel complete + .amdhsa_group_segment_fixed_size 1 + .amdhsa_private_segment_fixed_size 1 + .amdhsa_kernarg_size 8 + .amdhsa_user_sgpr_count 15 + .amdhsa_user_sgpr_dispatch_ptr 1 + .amdhsa_user_sgpr_queue_ptr 1 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 1 + .amdhsa_user_sgpr_private_segment_size 1 + .amdhsa_wavefront_size32 1 + .amdhsa_enable_private_segment 1 + .amdhsa_system_sgpr_workgroup_id_x 0 + .amdhsa_system_sgpr_workgroup_id_y 1 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 1 + .amdhsa_system_vgpr_workitem_id 1 + .amdhsa_next_free_vgpr 9 + .amdhsa_next_free_sgpr 27 + .amdhsa_reserve_vcc 0 + .amdhsa_float_round_mode_32 1 + .amdhsa_float_round_mode_16_64 1 + .amdhsa_float_denorm_mode_32 1 + .amdhsa_float_denorm_mode_16_64 0 + .amdhsa_fp16_overflow 1 + .amdhsa_workgroup_processor_mode 1 + .amdhsa_memory_ordered 1 + .amdhsa_forward_progress 1 + .amdhsa_shared_vgpr_count 0 + .amdhsa_round_robin_scheduling 1 + .amdhsa_exception_fp_ieee_invalid_op 1 + .amdhsa_exception_fp_denorm_src 1 + .amdhsa_exception_fp_ieee_div_zero 1 + .amdhsa_exception_fp_ieee_overflow 1 + .amdhsa_exception_fp_ieee_underflow 1 + .amdhsa_exception_fp_ieee_inexact 1 + .amdhsa_exception_int_div_zero 1 +.end_amdhsa_kernel + +// ASM: .amdhsa_kernel complete +// ASM-NEXT: .amdhsa_group_segment_fixed_size 1 +// ASM-NEXT: .amdhsa_private_segment_fixed_size 1 +// ASM-NEXT: .amdhsa_kernarg_size 8 +// ASM-NEXT: .amdhsa_user_sgpr_count 15 +// ASM-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1 +// ASM-NEXT: .amdhsa_user_sgpr_queue_ptr 1 +// ASM-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1 +// ASM-NEXT: .amdhsa_user_sgpr_dispatch_id 1 +// ASM-NEXT: .amdhsa_user_sgpr_private_segment_size 1 +// ASM-NEXT: .amdhsa_wavefront_size32 1 +// ASM-NEXT: .amdhsa_enable_private_segment 1 +// ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_x 0 +// ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1 +// ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1 +// ASM-NEXT: .amdhsa_system_sgpr_workgroup_info 1 +// ASM-NEXT: .amdhsa_system_vgpr_workitem_id 1 +// ASM-NEXT: .amdhsa_next_free_vgpr 9 +// ASM-NEXT: .amdhsa_next_free_sgpr 27 +// ASM-NEXT: .amdhsa_reserve_vcc 0 +// ASM-NEXT: .amdhsa_float_round_mode_32 1 +// ASM-NEXT: .amdhsa_float_round_mode_16_64 1 +// ASM-NEXT: .amdhsa_float_denorm_mode_32 1 +// ASM-NEXT: .amdhsa_float_denorm_mode_16_64 0 +// ASM-NEXT: .amdhsa_fp16_overflow 1 +// ASM-NEXT: .amdhsa_workgroup_processor_mode 1 +// ASM-NEXT: .amdhsa_memory_ordered 1 +// ASM-NEXT: .amdhsa_forward_progress 1 +// ASM-NEXT: .amdhsa_shared_vgpr_count 0 +// ASM-NEXT: .amdhsa_round_robin_scheduling 1 +// ASM-NEXT: .amdhsa_exception_fp_ieee_invalid_op 1 +// ASM-NEXT: .amdhsa_exception_fp_denorm_src 1 +// ASM-NEXT: .amdhsa_exception_fp_ieee_div_zero 1 +// ASM-NEXT: .amdhsa_exception_fp_ieee_overflow 1 +// ASM-NEXT: .amdhsa_exception_fp_ieee_underflow 1 +// ASM-NEXT: .amdhsa_exception_fp_ieee_inexact 1 +// ASM-NEXT: .amdhsa_exception_int_div_zero 1 +// ASM-NEXT: .end_amdhsa_kernel + +// Test that we are including special SGPR usage in the granulated count. +.p2align 6 +.amdhsa_kernel special_sgpr + .amdhsa_next_free_sgpr 27 + + .amdhsa_reserve_vcc 0 + + .amdhsa_float_denorm_mode_16_64 0 + .amdhsa_next_free_vgpr 0 +.end_amdhsa_kernel + +// ASM: .amdhsa_kernel special_sgpr +// ASM: .amdhsa_next_free_vgpr 0 +// ASM-NEXT: .amdhsa_next_free_sgpr 27 +// ASM-NEXT: .amdhsa_reserve_vcc 0 +// ASM: .amdhsa_float_denorm_mode_16_64 0 +// ASM: .end_amdhsa_kernel + +// Test that explicitly disabling user_sgpr's does not affect the user_sgpr +// count, i.e. this should produce the same descriptor as minimal. +.p2align 6 +.amdhsa_kernel disabled_user_sgpr + .amdhsa_next_free_vgpr 0 + .amdhsa_next_free_sgpr 0 +.end_amdhsa_kernel + +// ASM: .amdhsa_kernel disabled_user_sgpr +// ASM: .amdhsa_next_free_vgpr 0 +// ASM-NEXT: .amdhsa_next_free_sgpr 0 +// ASM: .end_amdhsa_kernel + +.section .foo + +.byte .amdgcn.gfx_generation_number +// ASM: .byte 12 + +.byte .amdgcn.gfx_generation_minor +// ASM: .byte 0 + +.byte .amdgcn.gfx_generation_stepping +// ASM: .byte 0 + +.byte .amdgcn.next_free_vgpr +// ASM: .byte 0 +.byte .amdgcn.next_free_sgpr +// ASM: .byte 0 + +v_mov_b32_e32 v7, s10 + +.byte .amdgcn.next_free_vgpr +// ASM: .byte 8 +.byte .amdgcn.next_free_sgpr +// ASM: .byte 11 + +.set .amdgcn.next_free_vgpr, 0 +.set .amdgcn.next_free_sgpr, 0 + +.byte .amdgcn.next_free_vgpr +// ASM: .byte 0 +.byte .amdgcn.next_free_sgpr +// ASM: .byte 0 + +v_mov_b32_e32 v16, s3 + +.byte .amdgcn.next_free_vgpr +// ASM: .byte 17 +.byte .amdgcn.next_free_sgpr +// ASM: .byte 4 + +// Metadata + +.amdgpu_metadata + amdhsa.version: + - 3 + - 0 + amdhsa.kernels: + - .name: amd_kernel_code_t_test_all + .symbol: amd_kernel_code_t_test_all@kd + .kernarg_segment_size: 8 + .group_segment_fixed_size: 16 + .private_segment_fixed_size: 32 + .kernarg_segment_align: 64 + .wavefront_size: 128 + .sgpr_count: 14 + .vgpr_count: 40 + .max_flat_workgroup_size: 256 + - .name: amd_kernel_code_t_minimal + .symbol: amd_kernel_code_t_minimal@kd + .kernarg_segment_size: 8 + .group_segment_fixed_size: 16 + .private_segment_fixed_size: 32 + .kernarg_segment_align: 64 + .wavefront_size: 128 + .sgpr_count: 14 + .vgpr_count: 40 + .max_flat_workgroup_size: 256 +.end_amdgpu_metadata + +// ASM: .amdgpu_metadata +// ASM: amdhsa.kernels: +// ASM: - .group_segment_fixed_size: 16 +// ASM: .kernarg_segment_align: 64 +// ASM: .kernarg_segment_size: 8 +// ASM: .max_flat_workgroup_size: 256 +// ASM: .name: amd_kernel_code_t_test_all +// ASM: .private_segment_fixed_size: 32 +// ASM: .sgpr_count: 14 +// ASM: .symbol: 'amd_kernel_code_t_test_all@kd' +// ASM: .vgpr_count: 40 +// ASM: .wavefront_size: 128 +// ASM: - .group_segment_fixed_size: 16 +// ASM: .kernarg_segment_align: 64 +// ASM: .kernarg_segment_size: 8 +// ASM: .max_flat_workgroup_size: 256 +// ASM: .name: amd_kernel_code_t_minimal +// ASM: .private_segment_fixed_size: 32 +// ASM: .sgpr_count: 14 +// ASM: .symbol: 'amd_kernel_code_t_minimal@kd' +// ASM: .vgpr_count: 40 +// ASM: .wavefront_size: 128 +// ASM: amdhsa.version: +// ASM-NEXT: - 3 +// ASM-NEXT: - 0 +// ASM: .end_amdgpu_metadata diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt index c061462339b6..1c31ee1e5dd7 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt @@ -684,6 +684,60 @@ # GFX12: s_rndne_f16 s5, 0x3456 ; encoding: [0xff,0x6e,0x85,0xbe,0x56,0x34,0x00,0x00] 0xff,0x6e,0x85,0xbe,0x56,0x34,0x00,0x00 +# GFX12: s_barrier_signal -2 ; encoding: [0xc2,0x4e,0x80,0xbe] +0xc2,0x4e,0x80,0xbe + +# GFX12: s_barrier_signal -1 ; encoding: [0xc1,0x4e,0x80,0xbe] +0xc1,0x4e,0x80,0xbe + +# GFX12: s_barrier_signal m0 ; encoding: [0x7d,0x4e,0x80,0xbe] +0x7d,0x4e,0x80,0xbe + +# GFX12: s_barrier_signal_isfirst -2 ; encoding: [0xc2,0x4f,0x80,0xbe] +0xc2,0x4f,0x80,0xbe + +# GFX12: s_barrier_signal_isfirst -1 ; encoding: [0xc1,0x4f,0x80,0xbe] +0xc1,0x4f,0x80,0xbe + +# GFX12: s_barrier_signal_isfirst m0 ; encoding: [0x7d,0x4f,0x80,0xbe] +0x7d,0x4f,0x80,0xbe + +# GFX12: s_barrier_init -1 ; encoding: [0xc1,0x51,0x80,0xbe] +0xc1,0x51,0x80,0xbe + +# GFX12: s_barrier_init -2 ; encoding: [0xc2,0x51,0x80,0xbe] +0xc2,0x51,0x80,0xbe + +# GFX12: s_barrier_init m0 ; encoding: [0x7d,0x51,0x80,0xbe] +0x7d,0x51,0x80,0xbe + +# GFX12: s_barrier_join -1 ; encoding: [0xc1,0x52,0x80,0xbe] +0xc1,0x52,0x80,0xbe + +# GFX12: s_barrier_join -2 ; encoding: [0xc2,0x52,0x80,0xbe] +0xc2,0x52,0x80,0xbe + +# GFX12: s_barrier_join m0 ; encoding: [0x7d,0x52,0x80,0xbe] +0x7d,0x52,0x80,0xbe + +# GFX12: s_wakeup_barrier 1 ; encoding: [0x81,0x57,0x80,0xbe] +0x81,0x57,0x80,0xbe + +# GFX12: s_wakeup_barrier -1 ; encoding: [0xc1,0x57,0x80,0xbe] +0xc1,0x57,0x80,0xbe + +# GFX12: s_wakeup_barrier m0 ; encoding: [0x7d,0x57,0x80,0xbe] +0x7d,0x57,0x80,0xbe + +# GFX12: s_get_barrier_state s3, -1 ; encoding: [0xc1,0x50,0x83,0xbe] +0xc1,0x50,0x83,0xbe + +# GFX12: s_get_barrier_state s3, -2 ; encoding: [0xc2,0x50,0x83,0xbe] +0xc2,0x50,0x83,0xbe + +# GFX12: s_get_barrier_state s3, m0 ; encoding: [0x7d,0x50,0x83,0xbe] +0x7d,0x50,0x83,0xbe + # GFX12: s_abs_i32 exec_hi, s1 ; encoding: [0x01,0x15,0xff,0xbe] 0x01,0x15,0xff,0xbe diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt index c177af7a6e50..297b6b083550 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop2.txt @@ -484,6 +484,108 @@ # GFX12: s_max_num_f32 s5, s1, s105 ; encoding: [0x01,0x69,0x85,0xa1] 0x01,0x69,0x85,0xa1 +# GFX12: s_minimum_f32 s5, s1, s2 ; encoding: [0x01,0x02,0x85,0xa7] +0x01,0x02,0x85,0xa7 + +# GFX12: s_minimum_f32 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0xa7] +0x01,0x02,0xe9,0xa7 + +# GFX12: s_minimum_f32 s5, s105, s2 ; encoding: [0x69,0x02,0x85,0xa7] +0x69,0x02,0x85,0xa7 + +# GFX12: s_minimum_f32 s5, s103, s2 ; encoding: [0x67,0x02,0x85,0xa7] +0x67,0x02,0x85,0xa7 + +# GFX12: s_minimum_f32 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x85,0xa7] +0x6a,0x02,0x85,0xa7 + +# GFX12: s_minimum_f32 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x85,0xa7] +0x6b,0x02,0x85,0xa7 + +# GFX12: s_minimum_f32 s5, ttmp11, s2 ; encoding: [0x77,0x02,0x85,0xa7] +0x77,0x02,0x85,0xa7 + +# GFX12: s_minimum_f32 s5, m0, s2 ; encoding: [0x7d,0x02,0x85,0xa7] +0x7d,0x02,0x85,0xa7 + +# GFX12: s_minimum_f32 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x85,0xa7] +0x7e,0x02,0x85,0xa7 + +# GFX12: s_minimum_f32 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x85,0xa7] +0x7f,0x02,0x85,0xa7 + +# GFX12: s_minimum_f32 s5, 0, s2 ; encoding: [0x80,0x02,0x85,0xa7] +0x80,0x02,0x85,0xa7 + +# GFX12: s_minimum_f32 s5, -1, s2 ; encoding: [0xc1,0x02,0x85,0xa7] +0xc1,0x02,0x85,0xa7 + +# GFX12: s_minimum_f32 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x85,0xa7] +0xf0,0x02,0x85,0xa7 + +# GFX12: s_minimum_f32 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x85,0xa7] +0xf7,0x02,0x85,0xa7 + +# GFX12: s_minimum_f32 s5, 0xaf123456, s2 ; encoding: [0xff,0x02,0x85,0xa7,0x56,0x34,0x12,0xaf] +0xff,0x02,0x85,0xa7,0x56,0x34,0x12,0xaf + +# GFX12: s_minimum_f32 s5, 0x3f717273, s2 ; encoding: [0xff,0x02,0x85,0xa7,0x73,0x72,0x71,0x3f] +0xff,0x02,0x85,0xa7,0x73,0x72,0x71,0x3f + +# GFX12: s_minimum_f32 s5, s1, s105 ; encoding: [0x01,0x69,0x85,0xa7] +0x01,0x69,0x85,0xa7 + +# GFX12: s_maximum_f32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0xa8] +0x01,0x02,0x05,0xa8 + +# GFX12: s_maximum_f32 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0xa8] +0x01,0x02,0x69,0xa8 + +# GFX12: s_maximum_f32 s5, s105, s2 ; encoding: [0x69,0x02,0x05,0xa8] +0x69,0x02,0x05,0xa8 + +# GFX12: s_maximum_f32 s5, s103, s2 ; encoding: [0x67,0x02,0x05,0xa8] +0x67,0x02,0x05,0xa8 + +# GFX12: s_maximum_f32 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x05,0xa8] +0x6a,0x02,0x05,0xa8 + +# GFX12: s_maximum_f32 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x05,0xa8] +0x6b,0x02,0x05,0xa8 + +# GFX12: s_maximum_f32 s5, ttmp11, s2 ; encoding: [0x77,0x02,0x05,0xa8] +0x77,0x02,0x05,0xa8 + +# GFX12: s_maximum_f32 s5, m0, s2 ; encoding: [0x7d,0x02,0x05,0xa8] +0x7d,0x02,0x05,0xa8 + +# GFX12: s_maximum_f32 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x05,0xa8] +0x7e,0x02,0x05,0xa8 + +# GFX12: s_maximum_f32 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x05,0xa8] +0x7f,0x02,0x05,0xa8 + +# GFX12: s_maximum_f32 s5, 0, s2 ; encoding: [0x80,0x02,0x05,0xa8] +0x80,0x02,0x05,0xa8 + +# GFX12: s_maximum_f32 s5, -1, s2 ; encoding: [0xc1,0x02,0x05,0xa8] +0xc1,0x02,0x05,0xa8 + +# GFX12: s_maximum_f32 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x05,0xa8] +0xf0,0x02,0x05,0xa8 + +# GFX12: s_maximum_f32 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x05,0xa8] +0xf7,0x02,0x05,0xa8 + +# GFX12: s_maximum_f32 s5, 0xaf123456, s2 ; encoding: [0xff,0x02,0x05,0xa8,0x56,0x34,0x12,0xaf] +0xff,0x02,0x05,0xa8,0x56,0x34,0x12,0xaf + +# GFX12: s_maximum_f32 s5, 0x3f717273, s2 ; encoding: [0xff,0x02,0x05,0xa8,0x73,0x72,0x71,0x3f] +0xff,0x02,0x05,0xa8,0x73,0x72,0x71,0x3f + +# GFX12: s_maximum_f32 s5, s1, s105 ; encoding: [0x01,0x69,0x05,0xa8] +0x01,0x69,0x05,0xa8 + # GFX12: s_fmac_f32 s5, s1, s2 ; encoding: [0x01,0x02,0x85,0xa3] 0x01,0x02,0x85,0xa3 @@ -943,6 +1045,102 @@ # GFX12: s_min_num_f16 s5, s1, s105 ; encoding: [0x01,0x69,0x85,0xa5] 0x01,0x69,0x85,0xa5 +# GFX12: s_maximum_f16 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0xa9] +0x01,0x02,0x05,0xa9 + +# GFX12: s_maximum_f16 s105, s1, s2 ; encoding: [0x01,0x02,0x69,0xa9] +0x01,0x02,0x69,0xa9 + +# GFX12: s_maximum_f16 s5, s105, s2 ; encoding: [0x69,0x02,0x05,0xa9] +0x69,0x02,0x05,0xa9 + +# GFX12: s_maximum_f16 s5, s101, s2 ; encoding: [0x65,0x02,0x05,0xa9] +0x65,0x02,0x05,0xa9 + +# GFX12: s_maximum_f16 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x05,0xa9] +0x6a,0x02,0x05,0xa9 + +# GFX12: s_maximum_f16 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x05,0xa9] +0x6b,0x02,0x05,0xa9 + +# GFX12: s_maximum_f16 s5, m0, s2 ; encoding: [0x7d,0x02,0x05,0xa9] +0x7d,0x02,0x05,0xa9 + +# GFX12: s_maximum_f16 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x05,0xa9] +0x7e,0x02,0x05,0xa9 + +# GFX12: s_maximum_f16 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x05,0xa9] +0x7f,0x02,0x05,0xa9 + +# GFX12: s_maximum_f16 s5, 0, s2 ; encoding: [0x80,0x02,0x05,0xa9] +0x80,0x02,0x05,0xa9 + +# GFX12: s_maximum_f16 s5, -1, s2 ; encoding: [0xc1,0x02,0x05,0xa9] +0xc1,0x02,0x05,0xa9 + +# GFX12: s_maximum_f16 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x05,0xa9] +0xf0,0x02,0x05,0xa9 + +# GFX12: s_maximum_f16 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x05,0xa9] +0xf7,0x02,0x05,0xa9 + +# GFX12: s_maximum_f16 s5, 0xfe0b, s2 ; encoding: [0xff,0x02,0x05,0xa9,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x05,0xa9,0x0b,0xfe,0x00,0x00 + +# GFX12: s_maximum_f16 s5, 0x3456, s2 ; encoding: [0xff,0x02,0x05,0xa9,0x56,0x34,0x00,0x00] +0xff,0x02,0x05,0xa9,0x56,0x34,0x00,0x00 + +# GFX12: s_maximum_f16 s5, s1, s105 ; encoding: [0x01,0x69,0x05,0xa9] +0x01,0x69,0x05,0xa9 + +# GFX12: s_minimum_f16 s5, s1, s2 ; encoding: [0x01,0x02,0x85,0xa8] +0x01,0x02,0x85,0xa8 + +# GFX12: s_minimum_f16 s105, s1, s2 ; encoding: [0x01,0x02,0xe9,0xa8] +0x01,0x02,0xe9,0xa8 + +# GFX12: s_minimum_f16 s5, s105, s2 ; encoding: [0x69,0x02,0x85,0xa8] +0x69,0x02,0x85,0xa8 + +# GFX12: s_minimum_f16 s5, s101, s2 ; encoding: [0x65,0x02,0x85,0xa8] +0x65,0x02,0x85,0xa8 + +# GFX12: s_minimum_f16 s5, vcc_lo, s2 ; encoding: [0x6a,0x02,0x85,0xa8] +0x6a,0x02,0x85,0xa8 + +# GFX12: s_minimum_f16 s5, vcc_hi, s2 ; encoding: [0x6b,0x02,0x85,0xa8] +0x6b,0x02,0x85,0xa8 + +# GFX12: s_minimum_f16 s5, m0, s2 ; encoding: [0x7d,0x02,0x85,0xa8] +0x7d,0x02,0x85,0xa8 + +# GFX12: s_minimum_f16 s5, exec_lo, s2 ; encoding: [0x7e,0x02,0x85,0xa8] +0x7e,0x02,0x85,0xa8 + +# GFX12: s_minimum_f16 s5, exec_hi, s2 ; encoding: [0x7f,0x02,0x85,0xa8] +0x7f,0x02,0x85,0xa8 + +# GFX12: s_minimum_f16 s5, 0, s2 ; encoding: [0x80,0x02,0x85,0xa8] +0x80,0x02,0x85,0xa8 + +# GFX12: s_minimum_f16 s5, -1, s2 ; encoding: [0xc1,0x02,0x85,0xa8] +0xc1,0x02,0x85,0xa8 + +# GFX12: s_minimum_f16 s5, 0.5, s2 ; encoding: [0xf0,0x02,0x85,0xa8] +0xf0,0x02,0x85,0xa8 + +# GFX12: s_minimum_f16 s5, -4.0, s2 ; encoding: [0xf7,0x02,0x85,0xa8] +0xf7,0x02,0x85,0xa8 + +# GFX12: s_minimum_f16 s5, 0xfe0b, s2 ; encoding: [0xff,0x02,0x85,0xa8,0x0b,0xfe,0x00,0x00] +0xff,0x02,0x85,0xa8,0x0b,0xfe,0x00,0x00 + +# GFX12: s_minimum_f16 s5, 0x3456, s2 ; encoding: [0xff,0x02,0x85,0xa8,0x56,0x34,0x00,0x00] +0xff,0x02,0x85,0xa8,0x56,0x34,0x00,0x00 + +# GFX12: s_minimum_f16 s5, s1, s105 ; encoding: [0x01,0x69,0x85,0xa8] +0x01,0x69,0x85,0xa8 + # GFX12: s_absdiff_i32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x83] 0x01,0x02,0x7f,0x83 diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt index fe74ff08a8e5..13ded15998fb 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sopp.txt @@ -15,6 +15,18 @@ # GFX12: s_singleuse_vdst 0x1234 ; encoding: [0x34,0x12,0x93,0xbf] 0x34,0x12,0x93,0xbf +# GFX12: s_barrier_wait 0xffff ; encoding: [0xff,0xff,0x94,0xbf] +0xff,0xff,0x94,0xbf + +# GFX12: s_barrier_wait 1 ; encoding: [0x01,0x00,0x94,0xbf] +0x01,0x00,0x94,0xbf + +# GFX12: s_barrier_leave ; encoding: [0x00,0x00,0x95,0xbf] +0x00,0x00,0x95,0xbf + +# GFX12: s_barrier ; encoding: [0x00,0x00,0xbd,0xbf] +0x00,0x00,0xbd,0xbf + # GFX12: s_branch 0 ; encoding: [0x00,0x00,0xa0,0xbf] 0x00,0x00,0xa0,0xbf diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt index 7f4f142d5bc1..8ff8c2c4c4f6 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt @@ -5495,3 +5495,632 @@ # GFX12: v_xor_b16 v255, 0xfe0b, vcc_hi ; encoding: [0xff,0x00,0x64,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00] 0xff,0x00,0x64,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00 +# GFX12: v_minimum_f32 v255, -|0xaf123456|, -|vcc_hi| ; encoding: [0xff,0x03,0x65,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf] +0xff,0x03,0x65,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf + +# GFX12: v_minimum_f32 v5, -1, exec_hi ; encoding: [0x05,0x00,0x65,0xd7,0xc1,0xfe,0x00,0x00] +0x05,0x00,0x65,0xd7,0xc1,0xfe,0x00,0x00 + +# GFX12: v_minimum_f32 v5, -src_scc, |vcc_lo| ; encoding: [0x05,0x02,0x65,0xd7,0xfd,0xd4,0x00,0x20] +0x05,0x02,0x65,0xd7,0xfd,0xd4,0x00,0x20 + +# GFX12: v_minimum_f32 v5, 0.5, -m0 ; encoding: [0x05,0x00,0x65,0xd7,0xf0,0xfa,0x00,0x40] +0x05,0x00,0x65,0xd7,0xf0,0xfa,0x00,0x40 + +# GFX12: v_minimum_f32 v5, exec_lo, -1 ; encoding: [0x05,0x00,0x65,0xd7,0x7e,0x82,0x01,0x00] +0x05,0x00,0x65,0xd7,0x7e,0x82,0x01,0x00 + +# GFX12: v_minimum_f32 v5, m0, 0.5 ; encoding: [0x05,0x00,0x65,0xd7,0x7d,0xe0,0x01,0x00] +0x05,0x00,0x65,0xd7,0x7d,0xe0,0x01,0x00 + +# GFX12: v_minimum_f32 v5, null, exec_lo ; encoding: [0x05,0x00,0x65,0xd7,0x7c,0xfc,0x00,0x00] +0x05,0x00,0x65,0xd7,0x7c,0xfc,0x00,0x00 + +# GFX12: v_minimum_f32 v5, s1, s2 ; encoding: [0x05,0x00,0x65,0xd7,0x01,0x04,0x00,0x00] +0x05,0x00,0x65,0xd7,0x01,0x04,0x00,0x00 + +# GFX12: v_minimum_f32 v5, s105, s105 ; encoding: [0x05,0x00,0x65,0xd7,0x69,0xd2,0x00,0x00] +0x05,0x00,0x65,0xd7,0x69,0xd2,0x00,0x00 + +# GFX12: v_minimum_f32 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x65,0xd7,0x7b,0xfa,0x01,0x00] +0x05,0x00,0x65,0xd7,0x7b,0xfa,0x01,0x00 + +# GFX12: v_minimum_f32 v5, v1, v2 ; encoding: [0x05,0x00,0x65,0xd7,0x01,0x05,0x02,0x00] +0x05,0x00,0x65,0xd7,0x01,0x05,0x02,0x00 + +# GFX12: v_minimum_f32 v5, v255, v255 ; encoding: [0x05,0x00,0x65,0xd7,0xff,0xff,0x03,0x00] +0x05,0x00,0x65,0xd7,0xff,0xff,0x03,0x00 + +# GFX12: v_minimum_f32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x65,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf] +0x05,0x00,0x65,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf + +# GFX12: v_minimum_f32 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x65,0xd7,0x6a,0xf6,0x00,0x00] +0x05,0x00,0x65,0xd7,0x6a,0xf6,0x00,0x00 + +# GFX12: v_minimum_f32 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x65,0xd7,0x7f,0xf8,0x00,0x00] +0x05,0x01,0x65,0xd7,0x7f,0xf8,0x00,0x00 + +# GFX12: v_maximum_f32 v255, -|0xaf123456|, -|vcc_hi| ; encoding: [0xff,0x03,0x66,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf] +0xff,0x03,0x66,0xd7,0xff,0xd6,0x00,0x60,0x56,0x34,0x12,0xaf + +# GFX12: v_maximum_f32 v5, -1, exec_hi ; encoding: [0x05,0x00,0x66,0xd7,0xc1,0xfe,0x00,0x00] +0x05,0x00,0x66,0xd7,0xc1,0xfe,0x00,0x00 + +# GFX12: v_maximum_f32 v5, -src_scc, |vcc_lo| ; encoding: [0x05,0x02,0x66,0xd7,0xfd,0xd4,0x00,0x20] +0x05,0x02,0x66,0xd7,0xfd,0xd4,0x00,0x20 + +# GFX12: v_maximum_f32 v5, 0.5, -m0 ; encoding: [0x05,0x00,0x66,0xd7,0xf0,0xfa,0x00,0x40] +0x05,0x00,0x66,0xd7,0xf0,0xfa,0x00,0x40 + +# GFX12: v_maximum_f32 v5, exec_lo, -1 ; encoding: [0x05,0x00,0x66,0xd7,0x7e,0x82,0x01,0x00] +0x05,0x00,0x66,0xd7,0x7e,0x82,0x01,0x00 + +# GFX12: v_maximum_f32 v5, m0, 0.5 ; encoding: [0x05,0x00,0x66,0xd7,0x7d,0xe0,0x01,0x00] +0x05,0x00,0x66,0xd7,0x7d,0xe0,0x01,0x00 + +# GFX12: v_maximum_f32 v5, null, exec_lo ; encoding: [0x05,0x00,0x66,0xd7,0x7c,0xfc,0x00,0x00] +0x05,0x00,0x66,0xd7,0x7c,0xfc,0x00,0x00 + +# GFX12: v_maximum_f32 v5, s1, s2 ; encoding: [0x05,0x00,0x66,0xd7,0x01,0x04,0x00,0x00] +0x05,0x00,0x66,0xd7,0x01,0x04,0x00,0x00 + +# GFX12: v_maximum_f32 v5, s105, s105 ; encoding: [0x05,0x00,0x66,0xd7,0x69,0xd2,0x00,0x00] +0x05,0x00,0x66,0xd7,0x69,0xd2,0x00,0x00 + +# GFX12: v_maximum_f32 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x66,0xd7,0x7b,0xfa,0x01,0x00] +0x05,0x00,0x66,0xd7,0x7b,0xfa,0x01,0x00 + +# GFX12: v_maximum_f32 v5, v1, v2 ; encoding: [0x05,0x00,0x66,0xd7,0x01,0x05,0x02,0x00] +0x05,0x00,0x66,0xd7,0x01,0x05,0x02,0x00 + +# GFX12: v_maximum_f32 v5, v255, v255 ; encoding: [0x05,0x00,0x66,0xd7,0xff,0xff,0x03,0x00] +0x05,0x00,0x66,0xd7,0xff,0xff,0x03,0x00 + +# GFX12: v_maximum_f32 v5, vcc_hi, 0xaf123456 ; encoding: [0x05,0x00,0x66,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf] +0x05,0x00,0x66,0xd7,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf + +# GFX12: v_maximum_f32 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x66,0xd7,0x6a,0xf6,0x00,0x00] +0x05,0x00,0x66,0xd7,0x6a,0xf6,0x00,0x00 + +# GFX12: v_maximum_f32 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x66,0xd7,0x7f,0xf8,0x00,0x00] +0x05,0x01,0x66,0xd7,0x7f,0xf8,0x00,0x00 + +# GFX12: v_minimum_f16 v205, v201, v200 ; encoding: [0xcd,0x00,0x67,0xd7,0xc9,0x91,0x03,0x00] +0xcd,0x00,0x67,0xd7,0xc9,0x91,0x03,0x00 + +# GFX12: v_minimum_f16 v255, -|0xaf12|, -|vcc_hi| ; encoding: [0xff,0x03,0x67,0xd7,0xff,0xd6,0x00,0x60,0x12,0xaf,0x00,0x00] +0xff,0x03,0x67,0xd7,0xff,0xd6,0x00,0x60,0x12,0xaf,0x00,0x00 + +# GFX12: v_minimum_f16 v5, -1, exec_hi ; encoding: [0x05,0x00,0x67,0xd7,0xc1,0xfe,0x00,0x00] +0x05,0x00,0x67,0xd7,0xc1,0xfe,0x00,0x00 + +# GFX12: v_minimum_f16 v5, -src_scc, |vcc_lo| ; encoding: [0x05,0x02,0x67,0xd7,0xfd,0xd4,0x00,0x20] +0x05,0x02,0x67,0xd7,0xfd,0xd4,0x00,0x20 + +# GFX12: v_minimum_f16 v5, 0.5, -m0 ; encoding: [0x05,0x00,0x67,0xd7,0xf0,0xfa,0x00,0x40] +0x05,0x00,0x67,0xd7,0xf0,0xfa,0x00,0x40 + +# GFX12: v_minimum_f16 v5, exec_lo, -1 ; encoding: [0x05,0x00,0x67,0xd7,0x7e,0x82,0x01,0x00] +0x05,0x00,0x67,0xd7,0x7e,0x82,0x01,0x00 + +# GFX12: v_minimum_f16 v5, m0, 0.5 ; encoding: [0x05,0x00,0x67,0xd7,0x7d,0xe0,0x01,0x00] +0x05,0x00,0x67,0xd7,0x7d,0xe0,0x01,0x00 + +# GFX12: v_minimum_f16 v5, null, exec_lo ; encoding: [0x05,0x00,0x67,0xd7,0x7c,0xfc,0x00,0x00] +0x05,0x00,0x67,0xd7,0x7c,0xfc,0x00,0x00 + +# GFX12: v_minimum_f16 v5, s1, s2 ; encoding: [0x05,0x00,0x67,0xd7,0x01,0x04,0x00,0x00] +0x05,0x00,0x67,0xd7,0x01,0x04,0x00,0x00 + +# GFX12: v_minimum_f16 v5, s105, s105 ; encoding: [0x05,0x00,0x67,0xd7,0x69,0xd2,0x00,0x00] +0x05,0x00,0x67,0xd7,0x69,0xd2,0x00,0x00 + +# GFX12: v_minimum_f16 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x67,0xd7,0x7b,0xfa,0x01,0x00] +0x05,0x00,0x67,0xd7,0x7b,0xfa,0x01,0x00 + +# GFX12: v_minimum_f16 v5, v1, v2 ; encoding: [0x05,0x00,0x67,0xd7,0x01,0x05,0x02,0x00] +0x05,0x00,0x67,0xd7,0x01,0x05,0x02,0x00 + +# GFX12: v_minimum_f16 v5, v255, v255 ; encoding: [0x05,0x00,0x67,0xd7,0xff,0xff,0x03,0x00] +0x05,0x00,0x67,0xd7,0xff,0xff,0x03,0x00 + +# GFX12: v_minimum_f16 v5, vcc_hi, 0xaf12 ; encoding: [0x05,0x00,0x67,0xd7,0x6b,0xfe,0x01,0x00,0x12,0xaf,0x00,0x00] +0x05,0x00,0x67,0xd7,0x6b,0xfe,0x01,0x00,0x12,0xaf,0x00,0x00 + +# GFX12: v_minimum_f16 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x67,0xd7,0x6a,0xf6,0x00,0x00] +0x05,0x00,0x67,0xd7,0x6a,0xf6,0x00,0x00 + +# GFX12: v_minimum_f16 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x67,0xd7,0x7f,0xf8,0x00,0x00] +0x05,0x01,0x67,0xd7,0x7f,0xf8,0x00,0x00 + +# GFX12: v_maximum_f16 v205, v201, v200 ; encoding: [0xcd,0x00,0x68,0xd7,0xc9,0x91,0x03,0x00] +0xcd,0x00,0x68,0xd7,0xc9,0x91,0x03,0x00 + +# GFX12: v_maximum_f16 v255, -|0xaf12|, -|vcc_hi| ; encoding: [0xff,0x03,0x68,0xd7,0xff,0xd6,0x00,0x60,0x12,0xaf,0x00,0x00] +0xff,0x03,0x68,0xd7,0xff,0xd6,0x00,0x60,0x12,0xaf,0x00,0x00 + +# GFX12: v_maximum_f16 v5, -1, exec_hi ; encoding: [0x05,0x00,0x68,0xd7,0xc1,0xfe,0x00,0x00] +0x05,0x00,0x68,0xd7,0xc1,0xfe,0x00,0x00 + +# GFX12: v_maximum_f16 v5, -src_scc, |vcc_lo| ; encoding: [0x05,0x02,0x68,0xd7,0xfd,0xd4,0x00,0x20] +0x05,0x02,0x68,0xd7,0xfd,0xd4,0x00,0x20 + +# GFX12: v_maximum_f16 v5, 0.5, -m0 ; encoding: [0x05,0x00,0x68,0xd7,0xf0,0xfa,0x00,0x40] +0x05,0x00,0x68,0xd7,0xf0,0xfa,0x00,0x40 + +# GFX12: v_maximum_f16 v5, exec_lo, -1 ; encoding: [0x05,0x00,0x68,0xd7,0x7e,0x82,0x01,0x00] +0x05,0x00,0x68,0xd7,0x7e,0x82,0x01,0x00 + +# GFX12: v_maximum_f16 v5, m0, 0.5 ; encoding: [0x05,0x00,0x68,0xd7,0x7d,0xe0,0x01,0x00] +0x05,0x00,0x68,0xd7,0x7d,0xe0,0x01,0x00 + +# GFX12: v_maximum_f16 v5, null, exec_lo ; encoding: [0x05,0x00,0x68,0xd7,0x7c,0xfc,0x00,0x00] +0x05,0x00,0x68,0xd7,0x7c,0xfc,0x00,0x00 + +# GFX12: v_maximum_f16 v5, s1, s2 ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x04,0x00,0x00] +0x05,0x00,0x68,0xd7,0x01,0x04,0x00,0x00 + +# GFX12: v_maximum_f16 v5, s105, s105 ; encoding: [0x05,0x00,0x68,0xd7,0x69,0xd2,0x00,0x00] +0x05,0x00,0x68,0xd7,0x69,0xd2,0x00,0x00 + +# GFX12: v_maximum_f16 v5, ttmp15, src_scc ; encoding: [0x05,0x00,0x68,0xd7,0x7b,0xfa,0x01,0x00] +0x05,0x00,0x68,0xd7,0x7b,0xfa,0x01,0x00 + +# GFX12: v_maximum_f16 v5, v1, v2 ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x00] +0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x00 + +# GFX12: v_maximum_f16 v5, v255, v255 ; encoding: [0x05,0x00,0x68,0xd7,0xff,0xff,0x03,0x00] +0x05,0x00,0x68,0xd7,0xff,0xff,0x03,0x00 + +# GFX12: v_maximum_f16 v5, vcc_hi, 0xaf12 ; encoding: [0x05,0x00,0x68,0xd7,0x6b,0xfe,0x01,0x00,0x12,0xaf,0x00,0x00] +0x05,0x00,0x68,0xd7,0x6b,0xfe,0x01,0x00,0x12,0xaf,0x00,0x00 + +# GFX12: v_maximum_f16 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x00,0x68,0xd7,0x6a,0xf6,0x00,0x00] +0x05,0x00,0x68,0xd7,0x6a,0xf6,0x00,0x00 + +# GFX12: v_maximum_f16 v5, |exec_hi|, null ; encoding: [0x05,0x01,0x68,0xd7,0x7f,0xf8,0x00,0x00] +0x05,0x01,0x68,0xd7,0x7f,0xf8,0x00,0x00 + +# GFX12: v_minimum_f64 v[254:255], -|2|, -|vcc| ; encoding: [0xfe,0x03,0x41,0xd7,0x82,0xd4,0x00,0x60] +0xfe,0x03,0x41,0xd7,0x82,0xd4,0x00,0x60 + +# GFX12: v_minimum_f64 v[5:6], -1, exec ; encoding: [0x05,0x00,0x41,0xd7,0xc1,0xfc,0x00,0x00] +0x05,0x00,0x41,0xd7,0xc1,0xfc,0x00,0x00 + +# GFX12: v_minimum_f64 v[5:6], -src_scc, |vcc| ; encoding: [0x05,0x02,0x41,0xd7,0xfd,0xd4,0x00,0x20] +0x05,0x02,0x41,0xd7,0xfd,0xd4,0x00,0x20 + +# GFX12: v_minimum_f64 v[5:6], 0.5, -vcc ; encoding: [0x05,0x00,0x41,0xd7,0xf0,0xd4,0x00,0x40] +0x05,0x00,0x41,0xd7,0xf0,0xd4,0x00,0x40 + +# GFX12: v_minimum_f64 v[5:6], exec, -1 ; encoding: [0x05,0x00,0x41,0xd7,0x7e,0x82,0x01,0x00] +0x05,0x00,0x41,0xd7,0x7e,0x82,0x01,0x00 + +# GFX12: v_minimum_f64 v[5:6], null, exec ; encoding: [0x05,0x00,0x41,0xd7,0x7c,0xfc,0x00,0x00] +0x05,0x00,0x41,0xd7,0x7c,0xfc,0x00,0x00 + +# GFX12: v_minimum_f64 v[5:6], s[104:105], s[104:105] ; encoding: [0x05,0x00,0x41,0xd7,0x68,0xd0,0x00,0x00] +0x05,0x00,0x41,0xd7,0x68,0xd0,0x00,0x00 + +# GFX12: v_minimum_f64 v[5:6], s[6:7], s[4:5] ; encoding: [0x05,0x00,0x41,0xd7,0x06,0x08,0x00,0x00] +0x05,0x00,0x41,0xd7,0x06,0x08,0x00,0x00 + +# GFX12: v_minimum_f64 v[5:6], ttmp[14:15], src_scc ; encoding: [0x05,0x00,0x41,0xd7,0x7a,0xfa,0x01,0x00] +0x05,0x00,0x41,0xd7,0x7a,0xfa,0x01,0x00 + +# GFX12: v_minimum_f64 v[5:6], v[1:2], v[3:4] ; encoding: [0x05,0x00,0x41,0xd7,0x01,0x07,0x02,0x00] +0x05,0x00,0x41,0xd7,0x01,0x07,0x02,0x00 + +# GFX12: v_minimum_f64 v[5:6], v[254:255], v[254:255] ; encoding: [0x05,0x00,0x41,0xd7,0xfe,0xfd,0x03,0x00] +0x05,0x00,0x41,0xd7,0xfe,0xfd,0x03,0x00 + +# GFX12: v_minimum_f64 v[5:6], vcc, 0.5 ; encoding: [0x05,0x00,0x41,0xd7,0x6a,0xe0,0x01,0x00] +0x05,0x00,0x41,0xd7,0x6a,0xe0,0x01,0x00 + +# GFX12: v_minimum_f64 v[5:6], vcc, 0xaf121234 ; encoding: [0x05,0x00,0x41,0xd7,0x6a,0xfe,0x01,0x00,0x34,0x12,0x12,0xaf] +0x05,0x00,0x41,0xd7,0x6a,0xfe,0x01,0x00,0x34,0x12,0x12,0xaf + +# GFX12: v_minimum_f64 v[5:6], vcc, ttmp[14:15] ; encoding: [0x05,0x00,0x41,0xd7,0x6a,0xf4,0x00,0x00] +0x05,0x00,0x41,0xd7,0x6a,0xf4,0x00,0x00 + +# GFX12: v_minimum_f64 v[5:6], |exec|, null ; encoding: [0x05,0x01,0x41,0xd7,0x7e,0xf8,0x00,0x00] +0x05,0x01,0x41,0xd7,0x7e,0xf8,0x00,0x00 + +# GFX12: v_maximum_f64 v[254:255], -|2|, -|vcc| ; encoding: [0xfe,0x03,0x42,0xd7,0x82,0xd4,0x00,0x60] +0xfe,0x03,0x42,0xd7,0x82,0xd4,0x00,0x60 + +# GFX12: v_maximum_f64 v[5:6], -1, exec ; encoding: [0x05,0x00,0x42,0xd7,0xc1,0xfc,0x00,0x00] +0x05,0x00,0x42,0xd7,0xc1,0xfc,0x00,0x00 + +# GFX12: v_maximum_f64 v[5:6], -src_scc, |vcc| ; encoding: [0x05,0x02,0x42,0xd7,0xfd,0xd4,0x00,0x20] +0x05,0x02,0x42,0xd7,0xfd,0xd4,0x00,0x20 + +# GFX12: v_maximum_f64 v[5:6], 0.5, -vcc ; encoding: [0x05,0x00,0x42,0xd7,0xf0,0xd4,0x00,0x40] +0x05,0x00,0x42,0xd7,0xf0,0xd4,0x00,0x40 + +# GFX12: v_maximum_f64 v[5:6], exec, -1 ; encoding: [0x05,0x00,0x42,0xd7,0x7e,0x82,0x01,0x00] +0x05,0x00,0x42,0xd7,0x7e,0x82,0x01,0x00 + +# GFX12: v_maximum_f64 v[5:6], null, exec ; encoding: [0x05,0x00,0x42,0xd7,0x7c,0xfc,0x00,0x00] +0x05,0x00,0x42,0xd7,0x7c,0xfc,0x00,0x00 + +# GFX12: v_maximum_f64 v[5:6], s[104:105], s[104:105] ; encoding: [0x05,0x00,0x42,0xd7,0x68,0xd0,0x00,0x00] +0x05,0x00,0x42,0xd7,0x68,0xd0,0x00,0x00 + +# GFX12: v_maximum_f64 v[5:6], s[6:7], s[4:5] ; encoding: [0x05,0x00,0x42,0xd7,0x06,0x08,0x00,0x00] +0x05,0x00,0x42,0xd7,0x06,0x08,0x00,0x00 + +# GFX12: v_maximum_f64 v[5:6], ttmp[14:15], src_scc ; encoding: [0x05,0x00,0x42,0xd7,0x7a,0xfa,0x01,0x00] +0x05,0x00,0x42,0xd7,0x7a,0xfa,0x01,0x00 + +# GFX12: v_maximum_f64 v[5:6], v[1:2], v[3:4] ; encoding: [0x05,0x00,0x42,0xd7,0x01,0x07,0x02,0x00] +0x05,0x00,0x42,0xd7,0x01,0x07,0x02,0x00 + +# GFX12: v_maximum_f64 v[5:6], v[254:255], v[254:255] ; encoding: [0x05,0x00,0x42,0xd7,0xfe,0xfd,0x03,0x00] +0x05,0x00,0x42,0xd7,0xfe,0xfd,0x03,0x00 + +# GFX12: v_maximum_f64 v[5:6], vcc, 0.5 ; encoding: [0x05,0x00,0x42,0xd7,0x6a,0xe0,0x01,0x00] +0x05,0x00,0x42,0xd7,0x6a,0xe0,0x01,0x00 + +# GFX12: v_maximum_f64 v[5:6], vcc, 0xaf121234 ; encoding: [0x05,0x00,0x42,0xd7,0x6a,0xfe,0x01,0x00,0x34,0x12,0x12,0xaf] +0x05,0x00,0x42,0xd7,0x6a,0xfe,0x01,0x00,0x34,0x12,0x12,0xaf + +# GFX12: v_maximum_f64 v[5:6], vcc, ttmp[14:15] ; encoding: [0x05,0x00,0x42,0xd7,0x6a,0xf4,0x00,0x00] +0x05,0x00,0x42,0xd7,0x6a,0xf4,0x00,0x00 + +# GFX12: v_maximum_f64 v[5:6], |exec|, null ; encoding: [0x05,0x01,0x42,0xd7,0x7e,0xf8,0x00,0x00] +0x05,0x01,0x42,0xd7,0x7e,0xf8,0x00,0x00 + +# GFX12: v_maximum3_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x2e,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf] +0xff,0x83,0x2e,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf + +# GFX12: v_maximum3_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x2e,0xd6,0xc1,0xfe,0xf4,0xc3] +0x05,0x06,0x2e,0xd6,0xc1,0xfe,0xf4,0xc3 + +# GFX12: v_maximum3_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x2e,0xd6,0xfd,0xd4,0x04,0x33] +0x05,0x02,0x2e,0xd6,0xfd,0xd4,0x04,0x33 + +# GFX12: v_maximum3_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x2e,0xd6,0x7f,0xf8,0xa8,0xa1] +0x05,0x05,0x2e,0xd6,0x7f,0xf8,0xa8,0xa1 + +# GFX12: v_maximum3_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x2e,0xd6,0x7b,0xfa,0xed,0xe1] +0x05,0x07,0x2e,0xd6,0x7b,0xfa,0xed,0xe1 + +# GFX12: v_maximum3_f32 v5, 0.5, -m0, 0.5 mul:2 ; encoding: [0x05,0x00,0x2e,0xd6,0xf0,0xfa,0xc0,0x4b] +0x05,0x00,0x2e,0xd6,0xf0,0xfa,0xc0,0x4b + +# GFX12: v_maximum3_f32 v5, m0, 0.5, m0 ; encoding: [0x05,0x00,0x2e,0xd6,0x7d,0xe0,0xf5,0x01] +0x05,0x00,0x2e,0xd6,0x7d,0xe0,0xf5,0x01 + +# GFX12: v_maximum3_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x2e,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf] +0x05,0x04,0x2e,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf + +# GFX12: v_maximum3_f32 v5, s1, v255, exec_hi ; encoding: [0x05,0x00,0x2e,0xd6,0x01,0xfe,0xff,0x01] +0x05,0x00,0x2e,0xd6,0x01,0xfe,0xff,0x01 + +# GFX12: v_maximum3_f32 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x2e,0xd6,0x69,0xd2,0xf8,0x01] +0x05,0x00,0x2e,0xd6,0x69,0xd2,0xf8,0x01 + +# GFX12: v_maximum3_f32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x2e,0xd6,0x01,0x05,0x0e,0x00] +0x05,0x00,0x2e,0xd6,0x01,0x05,0x0e,0x00 + +# GFX12: v_maximum3_f32 v5, v255, s2, s105 ; encoding: [0x05,0x00,0x2e,0xd6,0xff,0x05,0xa4,0x01] +0x05,0x00,0x2e,0xd6,0xff,0x05,0xa4,0x01 + +# GFX12: v_maximum3_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x2e,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf] +0x05,0x00,0x2e,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf + +# GFX12: v_maximum3_f32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x2e,0xd6,0x6a,0xf6,0x0c,0x04] +0x05,0x00,0x2e,0xd6,0x6a,0xf6,0x0c,0x04 + +# GFX12: v_maximum3_f32 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x2e,0xd6,0x7e,0x82,0xad,0x01] +0x05,0x01,0x2e,0xd6,0x7e,0x82,0xad,0x01 + +# GFX12: v_minimum3_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x2d,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf] +0xff,0x83,0x2d,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf + +# GFX12: v_minimum3_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x2d,0xd6,0xc1,0xfe,0xf4,0xc3] +0x05,0x06,0x2d,0xd6,0xc1,0xfe,0xf4,0xc3 + +# GFX12: v_minimum3_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x2d,0xd6,0xfd,0xd4,0x04,0x33] +0x05,0x02,0x2d,0xd6,0xfd,0xd4,0x04,0x33 + +# GFX12: v_minimum3_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x2d,0xd6,0x7f,0xf8,0xa8,0xa1] +0x05,0x05,0x2d,0xd6,0x7f,0xf8,0xa8,0xa1 + +# GFX12: v_minimum3_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x2d,0xd6,0x7b,0xfa,0xed,0xe1] +0x05,0x07,0x2d,0xd6,0x7b,0xfa,0xed,0xe1 + +# GFX12: v_minimum3_f32 v5, 0.5, -m0, 0.5 mul:2 ; encoding: [0x05,0x00,0x2d,0xd6,0xf0,0xfa,0xc0,0x4b] +0x05,0x00,0x2d,0xd6,0xf0,0xfa,0xc0,0x4b + +# GFX12: v_minimum3_f32 v5, m0, 0.5, m0 ; encoding: [0x05,0x00,0x2d,0xd6,0x7d,0xe0,0xf5,0x01] +0x05,0x00,0x2d,0xd6,0x7d,0xe0,0xf5,0x01 + +# GFX12: v_minimum3_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x2d,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf] +0x05,0x04,0x2d,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf + +# GFX12: v_minimum3_f32 v5, s1, v255, exec_hi ; encoding: [0x05,0x00,0x2d,0xd6,0x01,0xfe,0xff,0x01] +0x05,0x00,0x2d,0xd6,0x01,0xfe,0xff,0x01 + +# GFX12: v_minimum3_f32 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x2d,0xd6,0x69,0xd2,0xf8,0x01] +0x05,0x00,0x2d,0xd6,0x69,0xd2,0xf8,0x01 + +# GFX12: v_minimum3_f32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x2d,0xd6,0x01,0x05,0x0e,0x00] +0x05,0x00,0x2d,0xd6,0x01,0x05,0x0e,0x00 + +# GFX12: v_minimum3_f32 v5, v255, s2, s105 ; encoding: [0x05,0x00,0x2d,0xd6,0xff,0x05,0xa4,0x01] +0x05,0x00,0x2d,0xd6,0xff,0x05,0xa4,0x01 + +# GFX12: v_minimum3_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x2d,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf] +0x05,0x00,0x2d,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf + +# GFX12: v_minimum3_f32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x2d,0xd6,0x6a,0xf6,0x0c,0x04] +0x05,0x00,0x2d,0xd6,0x6a,0xf6,0x0c,0x04 + +# GFX12: v_minimum3_f32 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x2d,0xd6,0x7e,0x82,0xad,0x01] +0x05,0x01,0x2d,0xd6,0x7e,0x82,0xad,0x01 + +# GFX12: v_maximum3_f16 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x30,0xd6,0xc1,0xfe,0xf4,0xc3] +0x05,0x06,0x30,0xd6,0xc1,0xfe,0xf4,0xc3 + +# GFX12: v_maximum3_f16 v5, -src_scc, |vcc_lo|, -1 ; encoding: [0x05,0x02,0x30,0xd6,0xfd,0xd4,0x04,0x23] +0x05,0x02,0x30,0xd6,0xfd,0xd4,0x04,0x23 + +# GFX12: v_maximum3_f16 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x30,0xd6,0x7f,0xf8,0xa8,0xa1] +0x05,0x05,0x30,0xd6,0x7f,0xf8,0xa8,0xa1 + +# GFX12: v_maximum3_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x30,0xd6,0x7b,0xfa,0xed,0xe1] +0x05,0x07,0x30,0xd6,0x7b,0xfa,0xed,0xe1 + +# GFX12: v_maximum3_f16 v5, 0.5, -m0, 0.5 ; encoding: [0x05,0x00,0x30,0xd6,0xf0,0xfa,0xc0,0x43] +0x05,0x00,0x30,0xd6,0xf0,0xfa,0xc0,0x43 + +# GFX12: v_maximum3_f16 v5, m0, 0.5, m0 ; encoding: [0x05,0x00,0x30,0xd6,0x7d,0xe0,0xf5,0x01] +0x05,0x00,0x30,0xd6,0x7d,0xe0,0xf5,0x01 + +# GFX12: v_maximum3_f16 v5, null, exec_lo, -|0xaf12| ; encoding: [0x05,0x04,0x30,0xd6,0x7c,0xfc,0xfc,0x83,0x12,0xaf,0x00,0x00] +0x05,0x04,0x30,0xd6,0x7c,0xfc,0xfc,0x83,0x12,0xaf,0x00,0x00 + +# GFX12: v_maximum3_f16 v5, s1, v255, exec_hi ; encoding: [0x05,0x00,0x30,0xd6,0x01,0xfe,0xff,0x01] +0x05,0x00,0x30,0xd6,0x01,0xfe,0xff,0x01 + +# GFX12: v_maximum3_f16 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x30,0xd6,0x69,0xd2,0xf8,0x01] +0x05,0x00,0x30,0xd6,0x69,0xd2,0xf8,0x01 + +# GFX12: v_maximum3_f16 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x30,0xd6,0x01,0x05,0x0e,0x00] +0x05,0x00,0x30,0xd6,0x01,0x05,0x0e,0x00 + +# GFX12: v_maximum3_f16 v5, v255, s2, s105 ; encoding: [0x05,0x00,0x30,0xd6,0xff,0x05,0xa4,0x01] +0x05,0x00,0x30,0xd6,0xff,0x05,0xa4,0x01 + +# GFX12: v_maximum3_f16 v5, vcc_hi, 0xaf12, v255 ; encoding: [0x05,0x00,0x30,0xd6,0x6b,0xfe,0xfd,0x07,0x12,0xaf,0x00,0x00] +0x05,0x00,0x30,0xd6,0x6b,0xfe,0xfd,0x07,0x12,0xaf,0x00,0x00 + +# GFX12: v_maximum3_f16 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x30,0xd6,0x6a,0xf6,0x0c,0x04] +0x05,0x00,0x30,0xd6,0x6a,0xf6,0x0c,0x04 + +# GFX12: v_maximum3_f16 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x30,0xd6,0x7e,0x82,0xad,0x01] +0x05,0x01,0x30,0xd6,0x7e,0x82,0xad,0x01 + +# GFX12: v_minimum3_f16 v255, -|0xaf12|, -|vcc_hi|, null clamp ; encoding: [0xff,0x83,0x2f,0xd6,0xff,0xd6,0xf0,0x61,0x12,0xaf,0x00,0x00] +0xff,0x83,0x2f,0xd6,0xff,0xd6,0xf0,0x61,0x12,0xaf,0x00,0x00 + +# GFX12: v_minimum3_f16 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x2f,0xd6,0xc1,0xfe,0xf4,0xc3] +0x05,0x06,0x2f,0xd6,0xc1,0xfe,0xf4,0xc3 + +# GFX12: v_minimum3_f16 v5, -src_scc, |vcc_lo|, -1 ; encoding: [0x05,0x02,0x2f,0xd6,0xfd,0xd4,0x04,0x23] +0x05,0x02,0x2f,0xd6,0xfd,0xd4,0x04,0x23 + +# GFX12: v_minimum3_f16 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x2f,0xd6,0x7f,0xf8,0xa8,0xa1] +0x05,0x05,0x2f,0xd6,0x7f,0xf8,0xa8,0xa1 + +# GFX12: v_minimum3_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x2f,0xd6,0x7b,0xfa,0xed,0xe1] +0x05,0x07,0x2f,0xd6,0x7b,0xfa,0xed,0xe1 + +# GFX12: v_minimum3_f16 v5, 0.5, -m0, 0.5 ; encoding: [0x05,0x00,0x2f,0xd6,0xf0,0xfa,0xc0,0x43] +0x05,0x00,0x2f,0xd6,0xf0,0xfa,0xc0,0x43 + +# GFX12: v_minimum3_f16 v5, m0, 0.5, m0 ; encoding: [0x05,0x00,0x2f,0xd6,0x7d,0xe0,0xf5,0x01] +0x05,0x00,0x2f,0xd6,0x7d,0xe0,0xf5,0x01 + +# GFX12: v_minimum3_f16 v5, null, exec_lo, -|0xaf12| ; encoding: [0x05,0x04,0x2f,0xd6,0x7c,0xfc,0xfc,0x83,0x12,0xaf,0x00,0x00] +0x05,0x04,0x2f,0xd6,0x7c,0xfc,0xfc,0x83,0x12,0xaf,0x00,0x00 + +# GFX12: v_minimum3_f16 v5, s1, v255, exec_hi ; encoding: [0x05,0x00,0x2f,0xd6,0x01,0xfe,0xff,0x01] +0x05,0x00,0x2f,0xd6,0x01,0xfe,0xff,0x01 + +# GFX12: v_minimum3_f16 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x2f,0xd6,0x69,0xd2,0xf8,0x01] +0x05,0x00,0x2f,0xd6,0x69,0xd2,0xf8,0x01 + +# GFX12: v_minimum3_f16 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x2f,0xd6,0x01,0x05,0x0e,0x00] +0x05,0x00,0x2f,0xd6,0x01,0x05,0x0e,0x00 + +# GFX12: v_minimum3_f16 v5, v255, s2, s105 ; encoding: [0x05,0x00,0x2f,0xd6,0xff,0x05,0xa4,0x01] +0x05,0x00,0x2f,0xd6,0xff,0x05,0xa4,0x01 + +# GFX12: v_minimum3_f16 v5, vcc_hi, 0xaf12, v255 ; encoding: [0x05,0x00,0x2f,0xd6,0x6b,0xfe,0xfd,0x07,0x12,0xaf,0x00,0x00] +0x05,0x00,0x2f,0xd6,0x6b,0xfe,0xfd,0x07,0x12,0xaf,0x00,0x00 + +# GFX12: v_minimum3_f16 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x2f,0xd6,0x6a,0xf6,0x0c,0x04] +0x05,0x00,0x2f,0xd6,0x6a,0xf6,0x0c,0x04 + +# GFX12: v_minimum3_f16 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x2f,0xd6,0x7e,0x82,0xad,0x01] +0x05,0x01,0x2f,0xd6,0x7e,0x82,0xad,0x01 + +# GFX12: v_maximumminimum_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x6d,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf] +0xff,0x83,0x6d,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf + +# GFX12: v_maximumminimum_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x6d,0xd6,0xc1,0xfe,0xf4,0xc3] +0x05,0x06,0x6d,0xd6,0xc1,0xfe,0xf4,0xc3 + +# GFX12: v_maximumminimum_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x6d,0xd6,0xfd,0xd4,0x04,0x33] +0x05,0x02,0x6d,0xd6,0xfd,0xd4,0x04,0x33 + +# GFX12: v_maximumminimum_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x6d,0xd6,0x7f,0xf8,0xa8,0xa1] +0x05,0x05,0x6d,0xd6,0x7f,0xf8,0xa8,0xa1 + +# GFX12: v_maximumminimum_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x6d,0xd6,0x7b,0xfa,0xed,0xe1] +0x05,0x07,0x6d,0xd6,0x7b,0xfa,0xed,0xe1 + +# GFX12: v_maximumminimum_f32 v5, 0.5, -m0, 0.5 mul:2 ; encoding: [0x05,0x00,0x6d,0xd6,0xf0,0xfa,0xc0,0x4b] +0x05,0x00,0x6d,0xd6,0xf0,0xfa,0xc0,0x4b + +# GFX12: v_maximumminimum_f32 v5, m0, 0.5, m0 ; encoding: [0x05,0x00,0x6d,0xd6,0x7d,0xe0,0xf5,0x01] +0x05,0x00,0x6d,0xd6,0x7d,0xe0,0xf5,0x01 + +# GFX12: v_maximumminimum_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x6d,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf] +0x05,0x04,0x6d,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf + +# GFX12: v_maximumminimum_f32 v5, s1, v255, exec_hi ; encoding: [0x05,0x00,0x6d,0xd6,0x01,0xfe,0xff,0x01] +0x05,0x00,0x6d,0xd6,0x01,0xfe,0xff,0x01 + +# GFX12: v_maximumminimum_f32 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x6d,0xd6,0x69,0xd2,0xf8,0x01] +0x05,0x00,0x6d,0xd6,0x69,0xd2,0xf8,0x01 + +# GFX12: v_maximumminimum_f32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x6d,0xd6,0x01,0x05,0x0e,0x00] +0x05,0x00,0x6d,0xd6,0x01,0x05,0x0e,0x00 + +# GFX12: v_maximumminimum_f32 v5, v255, s2, s105 ; encoding: [0x05,0x00,0x6d,0xd6,0xff,0x05,0xa4,0x01] +0x05,0x00,0x6d,0xd6,0xff,0x05,0xa4,0x01 + +# GFX12: v_maximumminimum_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x6d,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf] +0x05,0x00,0x6d,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf + +# GFX12: v_maximumminimum_f32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x6d,0xd6,0x6a,0xf6,0x0c,0x04] +0x05,0x00,0x6d,0xd6,0x6a,0xf6,0x0c,0x04 + +# GFX12: v_maximumminimum_f32 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x6d,0xd6,0x7e,0x82,0xad,0x01] +0x05,0x01,0x6d,0xd6,0x7e,0x82,0xad,0x01 + +# GFX12: v_minimummaximum_f32 v255, -|0xaf123456|, -|vcc_hi|, null clamp div:2 ; encoding: [0xff,0x83,0x6c,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf] +0xff,0x83,0x6c,0xd6,0xff,0xd6,0xf0,0x79,0x56,0x34,0x12,0xaf + +# GFX12: v_minimummaximum_f32 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x6c,0xd6,0xc1,0xfe,0xf4,0xc3] +0x05,0x06,0x6c,0xd6,0xc1,0xfe,0xf4,0xc3 + +# GFX12: v_minimummaximum_f32 v5, -src_scc, |vcc_lo|, -1 mul:4 ; encoding: [0x05,0x02,0x6c,0xd6,0xfd,0xd4,0x04,0x33] +0x05,0x02,0x6c,0xd6,0xfd,0xd4,0x04,0x33 + +# GFX12: v_minimummaximum_f32 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x6c,0xd6,0x7f,0xf8,0xa8,0xa1] +0x05,0x05,0x6c,0xd6,0x7f,0xf8,0xa8,0xa1 + +# GFX12: v_minimummaximum_f32 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x6c,0xd6,0x7b,0xfa,0xed,0xe1] +0x05,0x07,0x6c,0xd6,0x7b,0xfa,0xed,0xe1 + +# GFX12: v_minimummaximum_f32 v5, 0.5, -m0, 0.5 mul:2 ; encoding: [0x05,0x00,0x6c,0xd6,0xf0,0xfa,0xc0,0x4b] +0x05,0x00,0x6c,0xd6,0xf0,0xfa,0xc0,0x4b + +# GFX12: v_minimummaximum_f32 v5, m0, 0.5, m0 ; encoding: [0x05,0x00,0x6c,0xd6,0x7d,0xe0,0xf5,0x01] +0x05,0x00,0x6c,0xd6,0x7d,0xe0,0xf5,0x01 + +# GFX12: v_minimummaximum_f32 v5, null, exec_lo, -|0xaf123456| ; encoding: [0x05,0x04,0x6c,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf] +0x05,0x04,0x6c,0xd6,0x7c,0xfc,0xfc,0x83,0x56,0x34,0x12,0xaf + +# GFX12: v_minimummaximum_f32 v5, s1, v255, exec_hi ; encoding: [0x05,0x00,0x6c,0xd6,0x01,0xfe,0xff,0x01] +0x05,0x00,0x6c,0xd6,0x01,0xfe,0xff,0x01 + +# GFX12: v_minimummaximum_f32 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x6c,0xd6,0x69,0xd2,0xf8,0x01] +0x05,0x00,0x6c,0xd6,0x69,0xd2,0xf8,0x01 + +# GFX12: v_minimummaximum_f32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x6c,0xd6,0x01,0x05,0x0e,0x00] +0x05,0x00,0x6c,0xd6,0x01,0x05,0x0e,0x00 + +# GFX12: v_minimummaximum_f32 v5, v255, s2, s105 ; encoding: [0x05,0x00,0x6c,0xd6,0xff,0x05,0xa4,0x01] +0x05,0x00,0x6c,0xd6,0xff,0x05,0xa4,0x01 + +# GFX12: v_minimummaximum_f32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x6c,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf] +0x05,0x00,0x6c,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf + +# GFX12: v_minimummaximum_f32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x6c,0xd6,0x6a,0xf6,0x0c,0x04] +0x05,0x00,0x6c,0xd6,0x6a,0xf6,0x0c,0x04 + +# GFX12: v_minimummaximum_f32 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x6c,0xd6,0x7e,0x82,0xad,0x01] +0x05,0x01,0x6c,0xd6,0x7e,0x82,0xad,0x01 + +# GFX12: v_maximumminimum_f16 v255, -|0xaf12|, -|vcc_hi|, null clamp ; encoding: [0xff,0x83,0x6f,0xd6,0xff,0xd6,0xf0,0x61,0x12,0xaf,0x00,0x00] +0xff,0x83,0x6f,0xd6,0xff,0xd6,0xf0,0x61,0x12,0xaf,0x00,0x00 + +# GFX12: v_maximumminimum_f16 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x6f,0xd6,0xc1,0xfe,0xf4,0xc3] +0x05,0x06,0x6f,0xd6,0xc1,0xfe,0xf4,0xc3 + +# GFX12: v_maximumminimum_f16 v5, -src_scc, |vcc_lo|, -1 ; encoding: [0x05,0x02,0x6f,0xd6,0xfd,0xd4,0x04,0x23] +0x05,0x02,0x6f,0xd6,0xfd,0xd4,0x04,0x23 + +# GFX12: v_maximumminimum_f16 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x6f,0xd6,0x7f,0xf8,0xa8,0xa1] +0x05,0x05,0x6f,0xd6,0x7f,0xf8,0xa8,0xa1 + +# GFX12: v_maximumminimum_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x6f,0xd6,0x7b,0xfa,0xed,0xe1] +0x05,0x07,0x6f,0xd6,0x7b,0xfa,0xed,0xe1 + +# GFX12: v_maximumminimum_f16 v5, 0.5, -m0, 0.5 ; encoding: [0x05,0x00,0x6f,0xd6,0xf0,0xfa,0xc0,0x43] +0x05,0x00,0x6f,0xd6,0xf0,0xfa,0xc0,0x43 + +# GFX12: v_maximumminimum_f16 v5, m0, 0.5, m0 ; encoding: [0x05,0x00,0x6f,0xd6,0x7d,0xe0,0xf5,0x01] +0x05,0x00,0x6f,0xd6,0x7d,0xe0,0xf5,0x01 + +# GFX12: v_maximumminimum_f16 v5, null, exec_lo, -|0xaf12| ; encoding: [0x05,0x04,0x6f,0xd6,0x7c,0xfc,0xfc,0x83,0x12,0xaf,0x00,0x00] +0x05,0x04,0x6f,0xd6,0x7c,0xfc,0xfc,0x83,0x12,0xaf,0x00,0x00 + +# GFX12: v_maximumminimum_f16 v5, s1, v255, exec_hi ; encoding: [0x05,0x00,0x6f,0xd6,0x01,0xfe,0xff,0x01] +0x05,0x00,0x6f,0xd6,0x01,0xfe,0xff,0x01 + +# GFX12: v_maximumminimum_f16 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x6f,0xd6,0x69,0xd2,0xf8,0x01] +0x05,0x00,0x6f,0xd6,0x69,0xd2,0xf8,0x01 + +# GFX12: v_maximumminimum_f16 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x6f,0xd6,0x01,0x05,0x0e,0x00] +0x05,0x00,0x6f,0xd6,0x01,0x05,0x0e,0x00 + +# GFX12: v_maximumminimum_f16 v5, v255, s2, s105 ; encoding: [0x05,0x00,0x6f,0xd6,0xff,0x05,0xa4,0x01] +0x05,0x00,0x6f,0xd6,0xff,0x05,0xa4,0x01 + +# GFX12: v_maximumminimum_f16 v5, vcc_hi, 0xaf12, v255 ; encoding: [0x05,0x00,0x6f,0xd6,0x6b,0xfe,0xfd,0x07,0x12,0xaf,0x00,0x00] +0x05,0x00,0x6f,0xd6,0x6b,0xfe,0xfd,0x07,0x12,0xaf,0x00,0x00 + +# GFX12: v_maximumminimum_f16 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x6f,0xd6,0x6a,0xf6,0x0c,0x04] +0x05,0x00,0x6f,0xd6,0x6a,0xf6,0x0c,0x04 + +# GFX12: v_maximumminimum_f16 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x6f,0xd6,0x7e,0x82,0xad,0x01] +0x05,0x01,0x6f,0xd6,0x7e,0x82,0xad,0x01 + +# GFX12: v_minimummaximum_f16 v5, -1, -|exec_hi|, -|src_scc| ; encoding: [0x05,0x06,0x6e,0xd6,0xc1,0xfe,0xf4,0xc3] +0x05,0x06,0x6e,0xd6,0xc1,0xfe,0xf4,0xc3 + +# GFX12: v_minimummaximum_f16 v5, -src_scc, |vcc_lo|, -1 ; encoding: [0x05,0x02,0x6e,0xd6,0xfd,0xd4,0x04,0x23] +0x05,0x02,0x6e,0xd6,0xfd,0xd4,0x04,0x23 + +# GFX12: v_minimummaximum_f16 v5, -|exec_hi|, null, -|vcc_lo| ; encoding: [0x05,0x05,0x6e,0xd6,0x7f,0xf8,0xa8,0xa1] +0x05,0x05,0x6e,0xd6,0x7f,0xf8,0xa8,0xa1 + +# GFX12: v_minimummaximum_f16 v5, -|ttmp15|, -|src_scc|, -|ttmp15| ; encoding: [0x05,0x07,0x6e,0xd6,0x7b,0xfa,0xed,0xe1] +0x05,0x07,0x6e,0xd6,0x7b,0xfa,0xed,0xe1 + +# GFX12: v_minimummaximum_f16 v5, 0.5, -m0, 0.5 ; encoding: [0x05,0x00,0x6e,0xd6,0xf0,0xfa,0xc0,0x43] +0x05,0x00,0x6e,0xd6,0xf0,0xfa,0xc0,0x43 + +# GFX12: v_minimummaximum_f16 v5, m0, 0.5, m0 ; encoding: [0x05,0x00,0x6e,0xd6,0x7d,0xe0,0xf5,0x01] +0x05,0x00,0x6e,0xd6,0x7d,0xe0,0xf5,0x01 + +# GFX12: v_minimummaximum_f16 v5, null, exec_lo, -|0xaf12| ; encoding: [0x05,0x04,0x6e,0xd6,0x7c,0xfc,0xfc,0x83,0x12,0xaf,0x00,0x00] +0x05,0x04,0x6e,0xd6,0x7c,0xfc,0xfc,0x83,0x12,0xaf,0x00,0x00 + +# GFX12: v_minimummaximum_f16 v5, s1, v255, exec_hi ; encoding: [0x05,0x00,0x6e,0xd6,0x01,0xfe,0xff,0x01] +0x05,0x00,0x6e,0xd6,0x01,0xfe,0xff,0x01 + +# GFX12: v_minimummaximum_f16 v5, s105, s105, exec_lo ; encoding: [0x05,0x00,0x6e,0xd6,0x69,0xd2,0xf8,0x01] +0x05,0x00,0x6e,0xd6,0x69,0xd2,0xf8,0x01 + +# GFX12: v_minimummaximum_f16 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x6e,0xd6,0x01,0x05,0x0e,0x00] +0x05,0x00,0x6e,0xd6,0x01,0x05,0x0e,0x00 + +# GFX12: v_minimummaximum_f16 v5, v255, s2, s105 ; encoding: [0x05,0x00,0x6e,0xd6,0xff,0x05,0xa4,0x01] +0x05,0x00,0x6e,0xd6,0xff,0x05,0xa4,0x01 + +# GFX12: v_minimummaximum_f16 v5, vcc_hi, 0xaf12, v255 ; encoding: [0x05,0x00,0x6e,0xd6,0x6b,0xfe,0xfd,0x07,0x12,0xaf,0x00,0x00] +0x05,0x00,0x6e,0xd6,0x6b,0xfe,0xfd,0x07,0x12,0xaf,0x00,0x00 + +# GFX12: v_minimummaximum_f16 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x6e,0xd6,0x6a,0xf6,0x0c,0x04] +0x05,0x00,0x6e,0xd6,0x6a,0xf6,0x0c,0x04 + +# GFX12: v_minimummaximum_f16 v5, |exec_lo|, -1, vcc_hi ; encoding: [0x05,0x01,0x6e,0xd6,0x7e,0x82,0xad,0x01] +0x05,0x01,0x6e,0xd6,0x7e,0x82,0xad,0x01 diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt index 40204c0dfdf4..69f61c7eb803 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt @@ -4110,3 +4110,507 @@ # GFX12: v_dot2_bf16_bf16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0x00,0x65,0x67,0xd6,0xfa,0x04,0x0e,0xc0,0x01,0xe4,0x04,0x00] 0x00,0x65,0x67,0xd6,0xfa,0x04,0x0e,0xc0,0x01,0xe4,0x04,0x00 + +# GFX12: v_minimum_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x03,0x65,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +0xff,0x03,0x65,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30 + +# GFX12: v_minimum_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x02,0x65,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] +0x05,0x02,0x65,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13 + +# GFX12: v_minimum_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff + +# GFX12: v_minimum_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff + +# GFX12: v_minimum_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff + +# GFX12: v_minimum_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff + +# GFX12: v_minimum_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff + +# GFX12: v_minimum_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff + +# GFX12: v_minimum_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff + +# GFX12: v_minimum_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff + +# GFX12: v_minimum_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff + +# GFX12: v_minimum_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff + +# GFX12: v_minimum_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +0x05,0x00,0x65,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff + +# GFX12: v_minimum_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x65,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +0x05,0x01,0x65,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01 + +# GFX12: v_maximum_f32_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x03,0x66,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +0xff,0x03,0x66,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30 + +# GFX12: v_maximum_f32_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x02,0x66,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] +0x05,0x02,0x66,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13 + +# GFX12: v_maximum_f32_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff + +# GFX12: v_maximum_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff + +# GFX12: v_maximum_f32_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff + +# GFX12: v_maximum_f32_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff + +# GFX12: v_maximum_f32_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff + +# GFX12: v_maximum_f32_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff + +# GFX12: v_maximum_f32_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff + +# GFX12: v_maximum_f32_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff + +# GFX12: v_maximum_f32_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff + +# GFX12: v_maximum_f32_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff + +# GFX12: v_maximum_f32_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +0x05,0x00,0x66,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff + +# GFX12: v_maximum_f32_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x66,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +0x05,0x01,0x66,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01 + +# GFX12: v_minimum_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x03,0x67,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +0xff,0x03,0x67,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30 + +# GFX12: v_minimum_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x02,0x67,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] +0x05,0x02,0x67,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13 + +# GFX12: v_minimum_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff + +# GFX12: v_minimum_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff + +# GFX12: v_minimum_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff + +# GFX12: v_minimum_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff + +# GFX12: v_minimum_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff + +# GFX12: v_minimum_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff + +# GFX12: v_minimum_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff + +# GFX12: v_minimum_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff + +# GFX12: v_minimum_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff + +# GFX12: v_minimum_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff + +# GFX12: v_minimum_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +0x05,0x00,0x67,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff + +# GFX12: v_minimum_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x67,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +0x05,0x01,0x67,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01 + +# GFX12: v_maximum_f16_e64_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x03,0x68,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30] +0xff,0x03,0x68,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30 + +# GFX12: v_maximum_f16_e64_dpp v5, -v1, |v2| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x02,0x68,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13] +0x05,0x02,0x68,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13 + +# GFX12: v_maximum_f16_e64_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff] +0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff + +# GFX12: v_maximum_f16_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] +0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff + +# GFX12: v_maximum_f16_e64_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff] +0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff + +# GFX12: v_maximum_f16_e64_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff] +0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff + +# GFX12: v_maximum_f16_e64_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff] +0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff + +# GFX12: v_maximum_f16_e64_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff] +0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff + +# GFX12: v_maximum_f16_e64_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff] +0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff + +# GFX12: v_maximum_f16_e64_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff] +0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff + +# GFX12: v_maximum_f16_e64_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff] +0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff + +# GFX12: v_maximum_f16_e64_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff] +0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff + +# GFX12: v_maximum_f16_e64_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff] +0x05,0x00,0x68,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff + +# GFX12: v_maximum_f16_e64_dpp v5, |v1|, -v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x01,0x68,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01] +0x05,0x01,0x68,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01 + +# GFX12: v_maximum3_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x2e,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30] +0xff,0x87,0x2e,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30 + +# GFX12: v_maximum3_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x2e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] +0x05,0x04,0x2e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff + +# GFX12: v_maximum3_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x2e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] +0x05,0x03,0x2e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff + +# GFX12: v_maximum3_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x2e,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] +0x05,0x05,0x2e,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01 + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x06,0x2e,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] +0x05,0x06,0x2e,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13 + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x2e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] +0x05,0x02,0x2e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] +0x05,0x00,0x2e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] +0x05,0x00,0x2e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] +0x05,0x00,0x2e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] +0x05,0x00,0x2e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] +0x05,0x00,0x2e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] +0x05,0x00,0x2e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] +0x05,0x00,0x2e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff + +# GFX12: v_maximum3_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x2e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] +0x05,0x01,0x2e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff + +# GFX12: v_minimum3_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x2d,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30] +0xff,0x87,0x2d,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30 + +# GFX12: v_minimum3_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x2d,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] +0x05,0x04,0x2d,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff + +# GFX12: v_minimum3_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x2d,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] +0x05,0x03,0x2d,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff + +# GFX12: v_minimum3_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x2d,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] +0x05,0x05,0x2d,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01 + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x06,0x2d,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] +0x05,0x06,0x2d,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13 + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x2d,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] +0x05,0x02,0x2d,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] +0x05,0x00,0x2d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] +0x05,0x00,0x2d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] +0x05,0x00,0x2d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] +0x05,0x00,0x2d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] +0x05,0x00,0x2d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] +0x05,0x00,0x2d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] +0x05,0x00,0x2d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff + +# GFX12: v_minimum3_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x2d,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] +0x05,0x01,0x2d,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff + +# GFX12: v_maximum3_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x30,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30] +0xff,0x87,0x30,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30 + +# GFX12: v_maximum3_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x30,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] +0x05,0x04,0x30,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff + +# GFX12: v_maximum3_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x30,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] +0x05,0x03,0x30,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff + +# GFX12: v_maximum3_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x30,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] +0x05,0x05,0x30,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01 + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x06,0x30,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] +0x05,0x06,0x30,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13 + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x30,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] +0x05,0x02,0x30,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] +0x05,0x00,0x30,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] +0x05,0x00,0x30,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] +0x05,0x00,0x30,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] +0x05,0x00,0x30,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] +0x05,0x00,0x30,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] +0x05,0x00,0x30,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] +0x05,0x00,0x30,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff + +# GFX12: v_maximum3_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x30,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] +0x05,0x01,0x30,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff + +# GFX12: v_minimum3_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x2f,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30] +0xff,0x87,0x2f,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30 + +# GFX12: v_minimum3_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x2f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] +0x05,0x04,0x2f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff + +# GFX12: v_minimum3_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x2f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] +0x05,0x03,0x2f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff + +# GFX12: v_minimum3_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x2f,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] +0x05,0x05,0x2f,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01 + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x06,0x2f,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] +0x05,0x06,0x2f,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13 + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x2f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] +0x05,0x02,0x2f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] +0x05,0x00,0x2f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] +0x05,0x00,0x2f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] +0x05,0x00,0x2f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] +0x05,0x00,0x2f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] +0x05,0x00,0x2f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] +0x05,0x00,0x2f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x2f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] +0x05,0x00,0x2f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff + +# GFX12: v_minimum3_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x2f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] +0x05,0x01,0x2f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff + +# GFX12: v_maximumminimum_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x6d,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30] +0xff,0x87,0x6d,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x6d,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] +0x05,0x04,0x6d,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff + +# GFX12: v_maximumminimum_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x6d,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] +0x05,0x03,0x6d,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff + +# GFX12: v_maximumminimum_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x6d,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] +0x05,0x05,0x6d,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x06,0x6d,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] +0x05,0x06,0x6d,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x6d,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] +0x05,0x02,0x6d,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] +0x05,0x00,0x6d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] +0x05,0x00,0x6d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] +0x05,0x00,0x6d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] +0x05,0x00,0x6d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] +0x05,0x00,0x6d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] +0x05,0x00,0x6d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] +0x05,0x00,0x6d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff + +# GFX12: v_maximumminimum_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x6d,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] +0x05,0x01,0x6d,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff + +# GFX12: v_minimummaximum_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x6c,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30] +0xff,0x87,0x6c,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x0d,0x30 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x6c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] +0x05,0x04,0x6c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff + +# GFX12: v_minimummaximum_f32_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x6c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] +0x05,0x03,0x6c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff + +# GFX12: v_minimummaximum_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x6c,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01] +0x05,0x05,0x6c,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x06,0x6c,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13] +0x05,0x06,0x6c,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x6c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] +0x05,0x02,0x6c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] +0x05,0x00,0x6c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] +0x05,0x00,0x6c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] +0x05,0x00,0x6c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] +0x05,0x00,0x6c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] +0x05,0x00,0x6c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] +0x05,0x00,0x6c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] +0x05,0x00,0x6c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff + +# GFX12: v_minimummaximum_f32_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x6c,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] +0x05,0x01,0x6c,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff + +# GFX12: v_maximumminimum_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x6f,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30] +0xff,0x87,0x6f,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x6f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] +0x05,0x04,0x6f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff + +# GFX12: v_maximumminimum_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x6f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] +0x05,0x03,0x6f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff + +# GFX12: v_maximumminimum_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x6f,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] +0x05,0x05,0x6f,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x06,0x6f,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] +0x05,0x06,0x6f,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x6f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] +0x05,0x02,0x6f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] +0x05,0x00,0x6f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] +0x05,0x00,0x6f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] +0x05,0x00,0x6f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] +0x05,0x00,0x6f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] +0x05,0x00,0x6f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] +0x05,0x00,0x6f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] +0x05,0x00,0x6f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff + +# GFX12: v_maximumminimum_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x6f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] +0x05,0x01,0x6f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff + +# GFX12: v_minimummaximum_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x87,0x6e,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30] +0xff,0x87,0x6e,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, -v1, v2, |exec_lo| row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x04,0x6e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff] +0x05,0x04,0x6e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff + +# GFX12: v_minimummaximum_f16_e64_dpp v5, -|v1|, -|v2|, null row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x03,0x6e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff] +0x05,0x03,0x6e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff + +# GFX12: v_minimummaximum_f16_e64_dpp v5, -|v1|, v2, -|-1| row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x05,0x6e,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01] +0x05,0x05,0x6e,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, -|v2|, -|0.5| row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0x05,0x06,0x6e,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13] +0x05,0x06,0x6e,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, -|v2|, exec_hi row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x02,0x6e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff] +0x05,0x02,0x6e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, v2, s105 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff] +0x05,0x00,0x6e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, v2, v255 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff] +0x05,0x00,0x6e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, v2, v3 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff] +0x05,0x00,0x6e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff] +0x05,0x00,0x6e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, v2, v3 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff] +0x05,0x00,0x6e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, v2, vcc_hi row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff] +0x05,0x00,0x6e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff] +0x05,0x00,0x6e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff + +# GFX12: v_minimummaximum_f16_e64_dpp v5, |v1|, v2, -ttmp15 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x01,0x6e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff] +0x05,0x01,0x6e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt index 904ec7c1347f..a7f018301614 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt @@ -2629,3 +2629,338 @@ # GFX12: v_dot2_bf16_bf16_e64_dpp v0, |v1|, -v2, -|s3| op_sel:[0,0,1,1] dpp8:[0,1,2,3,4,4,4,4] ; encoding: [0x00,0x65,0x67,0xd6,0xe9,0x04,0x0e,0xc0,0x01,0x88,0x46,0x92] 0x00,0x65,0x67,0xd6,0xe9,0x04,0x0e,0xc0,0x01,0x88,0x46,0x92 +# GFX12: v_maximum_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x03,0x66,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +0xff,0x03,0x66,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00 + +# GFX12: v_maximum_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x66,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +0x05,0x02,0x66,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x66,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +0x05,0x00,0x66,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x66,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +0x05,0x01,0x66,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum_f32_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x03,0x65,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +0xff,0x03,0x65,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00 + +# GFX12: v_minimum_f32_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x65,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +0x05,0x02,0x65,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x65,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +0x05,0x00,0x65,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum_f32_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x65,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +0x05,0x01,0x65,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum_f16_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x03,0x68,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +0xff,0x03,0x68,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00 + +# GFX12: v_maximum_f16_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x68,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +0x05,0x02,0x68,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x68,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +0x05,0x00,0x68,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x68,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +0x05,0x01,0x68,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum_f16_e64_dpp v255, -|v255|, -|v255| dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x03,0x67,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00] +0xff,0x03,0x67,0xd7,0xe9,0xfe,0x03,0x60,0xff,0x00,0x00,0x00 + +# GFX12: v_minimum_f16_e64_dpp v5, -v1, |v2| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x02,0x67,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05] +0x05,0x02,0x67,0xd7,0xea,0x04,0x02,0x20,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum_f16_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x67,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] +0x05,0x00,0x67,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum_f16_e64_dpp v5, |v1|, -v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x67,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05] +0x05,0x01,0x67,0xd7,0xe9,0x04,0x02,0x40,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x87,0x2e,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00] +0xff,0x87,0x2e,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00 + +# GFX12: v_maximum3_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x2e,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] +0x05,0x04,0x2e,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x2e,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] +0x05,0x03,0x2e,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x2e,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05] +0x05,0x05,0x2e,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x06,0x2e,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05] +0x05,0x06,0x2e,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x2e,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] +0x05,0x02,0x2e,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x2e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] +0x05,0x00,0x2e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] +0x05,0x00,0x2e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x2e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x2e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x2e,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] +0x05,0x01,0x2e,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x87,0x2d,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00] +0xff,0x87,0x2d,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00 + +# GFX12: v_minimum3_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x2d,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] +0x05,0x04,0x2d,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x2d,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] +0x05,0x03,0x2d,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x2d,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05] +0x05,0x05,0x2d,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x06,0x2d,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05] +0x05,0x06,0x2d,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x2d,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] +0x05,0x02,0x2d,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x2d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] +0x05,0x00,0x2d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] +0x05,0x00,0x2d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x2d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x2d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x2d,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] +0x05,0x01,0x2d,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x87,0x30,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00] +0xff,0x87,0x30,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00 + +# GFX12: v_maximum3_f16_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x30,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] +0x05,0x04,0x30,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f16_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x30,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] +0x05,0x03,0x30,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f16_e64_dpp v5, -|v1|, v2, -|-1| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x30,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05] +0x05,0x05,0x30,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, -|v2|, -|0.5| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x06,0x30,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05] +0x05,0x06,0x30,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x30,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] +0x05,0x02,0x30,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x30,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x30,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x30,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] +0x05,0x00,0x30,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x30,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] +0x05,0x00,0x30,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x30,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x30,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x30,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x30,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_maximum3_f16_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x30,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] +0x05,0x01,0x30,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x87,0x2f,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00] +0xff,0x87,0x2f,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00 + +# GFX12: v_minimum3_f16_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x2f,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] +0x05,0x04,0x2f,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f16_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x2f,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] +0x05,0x03,0x2f,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f16_e64_dpp v5, -|v1|, v2, -|-1| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x2f,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05] +0x05,0x05,0x2f,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, -|v2|, -|0.5| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x06,0x2f,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05] +0x05,0x06,0x2f,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x2f,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] +0x05,0x02,0x2f,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2f,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x2f,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2f,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] +0x05,0x00,0x2f,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2f,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] +0x05,0x00,0x2f,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2f,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x2f,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x2f,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x2f,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_minimum3_f16_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x2f,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] +0x05,0x01,0x2f,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x87,0x6d,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00] +0xff,0x87,0x6d,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x6d,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] +0x05,0x04,0x6d,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x6d,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] +0x05,0x03,0x6d,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x6d,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05] +0x05,0x05,0x6d,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x06,0x6d,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05] +0x05,0x06,0x6d,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x6d,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] +0x05,0x02,0x6d,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x6d,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] +0x05,0x00,0x6d,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] +0x05,0x00,0x6d,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x6d,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x6d,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6d,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] +0x05,0x01,0x6d,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f32_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp div:2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x87,0x6c,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00] +0xff,0x87,0x6c,0xd6,0xe9,0xfe,0xf7,0xfb,0xff,0x00,0x00,0x00 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x6c,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] +0x05,0x04,0x6c,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x6c,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] +0x05,0x03,0x6c,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, -|v1|, v2, -|-1| mul:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x6c,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05] +0x05,0x05,0x6c,0xd6,0xe9,0x04,0x06,0xab,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, -|v2|, -|0.5| mul:4 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x06,0x6c,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05] +0x05,0x06,0x6c,0xd6,0xea,0x04,0xc2,0xd3,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x6c,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] +0x05,0x02,0x6c,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6c,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x6c,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6c,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] +0x05,0x00,0x6c,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6c,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] +0x05,0x00,0x6c,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6c,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x6c,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6c,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x6c,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f32_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6c,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] +0x05,0x01,0x6c,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x87,0x6f,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00] +0xff,0x87,0x6f,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x6f,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] +0x05,0x04,0x6f,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x6f,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] +0x05,0x03,0x6f,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, -|v1|, v2, -|-1| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x6f,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05] +0x05,0x05,0x6f,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, -|v2|, -|0.5| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x06,0x6f,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05] +0x05,0x06,0x6f,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x6f,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] +0x05,0x02,0x6f,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6f,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x6f,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6f,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] +0x05,0x00,0x6f,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6f,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] +0x05,0x00,0x6f,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6f,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x6f,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6f,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x6f,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_maximumminimum_f16_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6f,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] +0x05,0x01,0x6f,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f16_e64_dpp v255, -|v255|, -|v255|, -|src_scc| clamp dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x87,0x6e,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00] +0xff,0x87,0x6e,0xd6,0xe9,0xfe,0xf7,0xe3,0xff,0x00,0x00,0x00 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, -v1, v2, |exec_lo| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x04,0x6e,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05] +0x05,0x04,0x6e,0xd6,0xe9,0x04,0xfa,0x21,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, -|v1|, -|v2|, null dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x03,0x6e,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05] +0x05,0x03,0x6e,0xd6,0xe9,0x04,0xf2,0x61,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, -|v1|, v2, -|-1| dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x05,0x6e,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05] +0x05,0x05,0x6e,0xd6,0xe9,0x04,0x06,0xa3,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, -|v2|, -|0.5| dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0x05,0x06,0x6e,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05] +0x05,0x06,0x6e,0xd6,0xea,0x04,0xc2,0xc3,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, -|v2|, exec_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x02,0x6e,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05] +0x05,0x02,0x6e,0xd6,0xe9,0x04,0xfe,0x41,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, v2, s105 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x6e,0xd6,0xe9,0x04,0xa6,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, v2, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05] +0x05,0x00,0x6e,0xd6,0xe9,0x04,0xfe,0x07,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05] +0x05,0x00,0x6e,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, v2, vcc_hi dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x6e,0xd6,0xe9,0x04,0xae,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05] +0x05,0x00,0x6e,0xd6,0xe9,0x04,0xaa,0x01,0x01,0x77,0x39,0x05 + +# GFX12: v_minimummaximum_f16_e64_dpp v5, |v1|, v2, -ttmp15 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x01,0x6e,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05] +0x05,0x01,0x6e,0xd6,0xe9,0x04,0xee,0x81,0x01,0x77,0x39,0x05 diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt index d07516b21cc6..373cd7126144 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt @@ -1251,3 +1251,93 @@ # GFX12: v_pk_sub_u16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] clamp ; encoding: [0xff,0xd0,0x0b,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00] 0xff,0xd0,0x0b,0xcc,0xff,0xd6,0x00,0x08,0x0b,0xfe,0x00,0x00 + +# GFX12: v_pk_maximum_f16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] neg_lo:[1,1] neg_hi:[1,1] clamp ; encoding: [0xff,0xd3,0x1e,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00] +0xff,0xd3,0x1e,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00 + +# GFX12: v_pk_maximum_f16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0] neg_lo:[1,0] neg_hi:[1,0] ; encoding: [0x05,0x59,0x1e,0xcc,0xc1,0xfe,0x00,0x20] +0x05,0x59,0x1e,0xcc,0xc1,0xfe,0x00,0x20 + +# GFX12: v_pk_maximum_f16 v5, 0.5, m0 neg_lo:[0,1] neg_hi:[0,1] ; encoding: [0x05,0x42,0x1e,0xcc,0xf0,0xfa,0x00,0x58] +0x05,0x42,0x1e,0xcc,0xf0,0xfa,0x00,0x58 + +# GFX12: v_pk_maximum_f16 v5, exec_hi, null ; encoding: [0x05,0x40,0x1e,0xcc,0x7f,0xf8,0x00,0x18] +0x05,0x40,0x1e,0xcc,0x7f,0xf8,0x00,0x18 + +# GFX12: v_pk_maximum_f16 v5, exec_lo, -1 ; encoding: [0x05,0x40,0x1e,0xcc,0x7e,0x82,0x01,0x18] +0x05,0x40,0x1e,0xcc,0x7e,0x82,0x01,0x18 + +# GFX12: v_pk_maximum_f16 v5, m0, 0.5 ; encoding: [0x05,0x40,0x1e,0xcc,0x7d,0xe0,0x01,0x18] +0x05,0x40,0x1e,0xcc,0x7d,0xe0,0x01,0x18 + +# GFX12: v_pk_maximum_f16 v5, null, exec_lo ; encoding: [0x05,0x40,0x1e,0xcc,0x7c,0xfc,0x00,0x18] +0x05,0x40,0x1e,0xcc,0x7c,0xfc,0x00,0x18 + +# GFX12: v_pk_maximum_f16 v5, s1, s2 ; encoding: [0x05,0x40,0x1e,0xcc,0x01,0x04,0x00,0x18] +0x05,0x40,0x1e,0xcc,0x01,0x04,0x00,0x18 + +# GFX12: v_pk_maximum_f16 v5, s105, s105 ; encoding: [0x05,0x40,0x1e,0xcc,0x69,0xd2,0x00,0x18] +0x05,0x40,0x1e,0xcc,0x69,0xd2,0x00,0x18 + +# GFX12: v_pk_maximum_f16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x1e,0xcc,0xfd,0xd4,0x00,0x10] +0x05,0x48,0x1e,0xcc,0xfd,0xd4,0x00,0x10 + +# GFX12: v_pk_maximum_f16 v5, ttmp15, src_scc ; encoding: [0x05,0x40,0x1e,0xcc,0x7b,0xfa,0x01,0x18] +0x05,0x40,0x1e,0xcc,0x7b,0xfa,0x01,0x18 + +# GFX12: v_pk_maximum_f16 v5, v1, v2 ; encoding: [0x05,0x40,0x1e,0xcc,0x01,0x05,0x02,0x18] +0x05,0x40,0x1e,0xcc,0x01,0x05,0x02,0x18 + +# GFX12: v_pk_maximum_f16 v5, v255, v255 ; encoding: [0x05,0x40,0x1e,0xcc,0xff,0xff,0x03,0x18] +0x05,0x40,0x1e,0xcc,0xff,0xff,0x03,0x18 + +# GFX12: v_pk_maximum_f16 v5, vcc_hi, 0xfe0b ; encoding: [0x05,0x40,0x1e,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00] +0x05,0x40,0x1e,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00 + +# GFX12: v_pk_maximum_f16 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x40,0x1e,0xcc,0x6a,0xf6,0x00,0x18] +0x05,0x40,0x1e,0xcc,0x6a,0xf6,0x00,0x18 + +# GFX12: v_pk_minimum_f16 v255, 0xfe0b, vcc_hi op_sel:[0,1] op_sel_hi:[1,0] neg_lo:[1,1] neg_hi:[1,1] clamp ; encoding: [0xff,0xd3,0x1d,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00] +0xff,0xd3,0x1d,0xcc,0xff,0xd6,0x00,0x68,0x0b,0xfe,0x00,0x00 + +# GFX12: v_pk_minimum_f16 v5, -1, exec_hi op_sel:[1,1] op_sel_hi:[0,0] neg_lo:[1,0] neg_hi:[1,0] ; encoding: [0x05,0x59,0x1d,0xcc,0xc1,0xfe,0x00,0x20] +0x05,0x59,0x1d,0xcc,0xc1,0xfe,0x00,0x20 + +# GFX12: v_pk_minimum_f16 v5, 0.5, m0 neg_lo:[0,1] neg_hi:[0,1] ; encoding: [0x05,0x42,0x1d,0xcc,0xf0,0xfa,0x00,0x58] +0x05,0x42,0x1d,0xcc,0xf0,0xfa,0x00,0x58 + +# GFX12: v_pk_minimum_f16 v5, exec_hi, null ; encoding: [0x05,0x40,0x1d,0xcc,0x7f,0xf8,0x00,0x18] +0x05,0x40,0x1d,0xcc,0x7f,0xf8,0x00,0x18 + +# GFX12: v_pk_minimum_f16 v5, exec_lo, -1 ; encoding: [0x05,0x40,0x1d,0xcc,0x7e,0x82,0x01,0x18] +0x05,0x40,0x1d,0xcc,0x7e,0x82,0x01,0x18 + +# GFX12: v_pk_minimum_f16 v5, m0, 0.5 ; encoding: [0x05,0x40,0x1d,0xcc,0x7d,0xe0,0x01,0x18] +0x05,0x40,0x1d,0xcc,0x7d,0xe0,0x01,0x18 + +# GFX12: v_pk_minimum_f16 v5, null, exec_lo ; encoding: [0x05,0x40,0x1d,0xcc,0x7c,0xfc,0x00,0x18] +0x05,0x40,0x1d,0xcc,0x7c,0xfc,0x00,0x18 + +# GFX12: v_pk_minimum_f16 v5, s1, s2 ; encoding: [0x05,0x40,0x1d,0xcc,0x01,0x04,0x00,0x18] +0x05,0x40,0x1d,0xcc,0x01,0x04,0x00,0x18 + +# GFX12: v_pk_minimum_f16 v5, s105, s105 ; encoding: [0x05,0x40,0x1d,0xcc,0x69,0xd2,0x00,0x18] +0x05,0x40,0x1d,0xcc,0x69,0xd2,0x00,0x18 + +# GFX12: v_pk_minimum_f16 v5, src_scc, vcc_lo op_sel:[1,0] op_sel_hi:[0,1] ; encoding: [0x05,0x48,0x1d,0xcc,0xfd,0xd4,0x00,0x10] +0x05,0x48,0x1d,0xcc,0xfd,0xd4,0x00,0x10 + +# GFX12: v_pk_minimum_f16 v5, ttmp15, src_scc ; encoding: [0x05,0x40,0x1d,0xcc,0x7b,0xfa,0x01,0x18] +0x05,0x40,0x1d,0xcc,0x7b,0xfa,0x01,0x18 + +# GFX12: v_pk_minimum_f16 v5, v1, v2 ; encoding: [0x05,0x40,0x1d,0xcc,0x01,0x05,0x02,0x18] +0x05,0x40,0x1d,0xcc,0x01,0x05,0x02,0x18 + +# GFX12: v_pk_minimum_f16 v5, v255, v255 ; encoding: [0x05,0x40,0x1d,0xcc,0xff,0xff,0x03,0x18] +0x05,0x40,0x1d,0xcc,0xff,0xff,0x03,0x18 + +# GFX12: v_pk_minimum_f16 v5, vcc_hi, 0xfe0b ; encoding: [0x05,0x40,0x1d,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00] +0x05,0x40,0x1d,0xcc,0x6b,0xfe,0x01,0x18,0x0b,0xfe,0x00,0x00 + +# GFX12: v_pk_minimum_f16 v5, vcc_lo, ttmp15 ; encoding: [0x05,0x40,0x1d,0xcc,0x6a,0xf6,0x00,0x18] +0x05,0x40,0x1d,0xcc,0x6a,0xf6,0x00,0x18 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt index 3fcba735584b..8d63b153b2d5 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-operands.txt @@ -81,7 +81,7 @@ # CHECK: b .+1024 0x48 0x00 0x04 0x00 -# CHECK: ba 1024 +# CHECK: ba 0x400 0x48 0x00 0x04 0x02 # FIXME: decode as beq 0, .+1024 @@ -89,6 +89,6 @@ 0x41 0x82 0x04 0x00 # FIXME: decode as beqa 0, 1024 -# CHECK: bta 2, 1024 +# CHECK: bta 2, 0x400 0x41 0x82 0x04 0x02 diff --git a/llvm/test/MC/Disassembler/X86/avx512_bf16-32.txt b/llvm/test/MC/Disassembler/X86/avx512_bf16-32.txt new file mode 100644 index 000000000000..42f0c75fe367 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/avx512_bf16-32.txt @@ -0,0 +1,90 @@ +# RUN: llvm-mc -triple i686-unknown-unknown -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple i686-unknown-unknown -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: vcvtne2ps2bf16 %zmm4, %zmm5, %zmm6 +# INTEL: vcvtne2ps2bf16 zmm6, zmm5, zmm4 +0x62,0xf2,0x57,0x48,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 %zmm4, %zmm5, %zmm6 {%k7} +# INTEL: vcvtne2ps2bf16 zmm6 {k7}, zmm5, zmm4 +0x62,0xf2,0x57,0x4f,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 %zmm4, %zmm5, %zmm6 {%k7} {z} +# INTEL: vcvtne2ps2bf16 zmm6 {k7} {z}, zmm5, zmm4 +0x62,0xf2,0x57,0xcf,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 (%ecx), %zmm5, %zmm6 +# INTEL: vcvtne2ps2bf16 zmm6, zmm5, zmmword ptr [ecx] +0x62,0xf2,0x57,0x48,0x72,0x31 + +# ATT: vcvtne2ps2bf16 291(%esp,%esi,8), %zmm5, %zmm6 +# INTEL: vcvtne2ps2bf16 zmm6, zmm5, zmmword ptr [esp + 8*esi + 291] +0x62,0xf2,0x57,0x48,0x72,0xb4,0xf4,0x23,0x01,0x00,0x00 + +# ATT: vcvtne2ps2bf16 268435456(%esp,%esi,8), %zmm5, %zmm6 +# INTEL: vcvtne2ps2bf16 zmm6, zmm5, zmmword ptr [esp + 8*esi + 268435456] +0x62,0xf2,0x57,0x48,0x72,0xb4,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vcvtne2ps2bf16 -64(%esp), %zmm5, %zmm6 +# INTEL: vcvtne2ps2bf16 zmm6, zmm5, zmmword ptr [esp - 64] +0x62,0xf2,0x57,0x48,0x72,0x74,0x24,0xff + +# ATT: vcvtne2ps2bf16 (%eax){1to16}, %zmm5, %zmm6 +# INTEL: vcvtne2ps2bf16 zmm6, zmm5, dword ptr [eax]{1to16} +0x62,0xf2,0x57,0x58,0x72,0x30 + +# ATT: vcvtne2ps2bf16 8128(%edx), %zmm5, %zmm6 +# INTEL: vcvtne2ps2bf16 zmm6, zmm5, zmmword ptr [edx + 8128] +0x62,0xf2,0x57,0x48,0x72,0x72,0x7f + +# ATT: vcvtne2ps2bf16 -8192(%edx), %zmm5, %zmm6 +# INTEL: vcvtne2ps2bf16 zmm6, zmm5, zmmword ptr [edx - 8192] +0x62,0xf2,0x57,0x48,0x72,0x72,0x80 + +# ATT: vcvtne2ps2bf16 508(%edx){1to16}, %zmm5, %zmm6 +# INTEL: vcvtne2ps2bf16 zmm6, zmm5, dword ptr [edx + 508]{1to16} +0x62,0xf2,0x57,0x58,0x72,0x72,0x7f + +# ATT: vcvtne2ps2bf16 -512(%edx){1to16}, %zmm5, %zmm6 +# INTEL: vcvtne2ps2bf16 zmm6, zmm5, dword ptr [edx - 512]{1to16} +0x62,0xf2,0x57,0x58,0x72,0x72,0x80 + +# ATT: vcvtneps2bf16 %zmm5, %ymm6 +# INTEL: vcvtneps2bf16 ymm6, zmm5 +0x62,0xf2,0x7e,0x48,0x72,0xf5 + +# ATT: vcvtneps2bf16 268435456(%esp,%esi,8), %ymm6 {%k7} +# INTEL: vcvtneps2bf16 ymm6 {k7}, zmmword ptr [esp + 8*esi + 268435456] +0x62,0xf2,0x7e,0x4f,0x72,0xb4,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vcvtneps2bf16 (%ecx){1to16}, %ymm6 +# INTEL: vcvtneps2bf16 ymm6, dword ptr [ecx]{1to16} +0x62,0xf2,0x7e,0x58,0x72,0x31 + +# ATT: vcvtneps2bf16 8128(%ecx), %ymm6 +# INTEL: vcvtneps2bf16 ymm6, zmmword ptr [ecx + 8128] +0x62,0xf2,0x7e,0x48,0x72,0x71,0x7f + +# ATT: vcvtneps2bf16 -512(%edx){1to16}, %ymm6 {%k7} {z} +# INTEL: vcvtneps2bf16 ymm6 {k7} {z}, dword ptr [edx - 512]{1to16} +0x62,0xf2,0x7e,0xdf,0x72,0x72,0x80 + +# ATT: vdpbf16ps %zmm4, %zmm5, %zmm6 +# INTEL: vdpbf16ps zmm6, zmm5, zmm4 +0x62,0xf2,0x56,0x48,0x52,0xf4 + +# ATT: vdpbf16ps 268435456(%esp,%esi,8), %zmm5, %zmm6 {%k7} +# INTEL: vdpbf16ps zmm6 {k7}, zmm5, zmmword ptr [esp + 8*esi + 268435456] +0x62,0xf2,0x56,0x4f,0x52,0xb4,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vdpbf16ps (%ecx){1to16}, %zmm5, %zmm6 +# INTEL: vdpbf16ps zmm6, zmm5, dword ptr [ecx]{1to16} +0x62,0xf2,0x56,0x58,0x52,0x31 + +# ATT: vdpbf16ps 8128(%ecx), %zmm5, %zmm6 +# INTEL: vdpbf16ps zmm6, zmm5, zmmword ptr [ecx + 8128] +0x62,0xf2,0x56,0x48,0x52,0x71,0x7f + +# ATT: vdpbf16ps -512(%edx){1to16}, %zmm5, %zmm6 {%k7} {z} +# INTEL: vdpbf16ps zmm6 {k7} {z}, zmm5, dword ptr [edx - 512]{1to16} +0x62,0xf2,0x56,0xdf,0x52,0x72,0x80 diff --git a/llvm/test/MC/Disassembler/X86/avx512_bf16-64.txt b/llvm/test/MC/Disassembler/X86/avx512_bf16-64.txt new file mode 100644 index 000000000000..7296bd4ed3d9 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/avx512_bf16-64.txt @@ -0,0 +1,90 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: vcvtne2ps2bf16 %zmm28, %zmm29, %zmm30 +# INTEL: vcvtne2ps2bf16 zmm30, zmm29, zmm28 +0x62,0x02,0x17,0x40,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 %zmm28, %zmm29, %zmm30 {%k7} +# INTEL: vcvtne2ps2bf16 zmm30 {k7}, zmm29, zmm28 +0x62,0x02,0x17,0x47,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 %zmm28, %zmm29, %zmm30 {%k7} {z} +# INTEL: vcvtne2ps2bf16 zmm30 {k7} {z}, zmm29, zmm28 +0x62,0x02,0x17,0xc7,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 (%rcx), %zmm29, %zmm30 +# INTEL: vcvtne2ps2bf16 zmm30, zmm29, zmmword ptr [rcx] +0x62,0x62,0x17,0x40,0x72,0x31 + +# ATT: vcvtne2ps2bf16 291(%rax,%r14,8), %zmm29, %zmm30 +# INTEL: vcvtne2ps2bf16 zmm30, zmm29, zmmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x17,0x40,0x72,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vcvtne2ps2bf16 268435456(%rax,%r14,8), %zmm29, %zmm30 +# INTEL: vcvtne2ps2bf16 zmm30, zmm29, zmmword ptr [rax + 8*r14 + 268435456] +0x62,0x22,0x17,0x40,0x72,0xb4,0xf0,0x00,0x00,0x00,0x10 + +# ATT: vcvtne2ps2bf16 -64(%rsp), %zmm29, %zmm30 +# INTEL: vcvtne2ps2bf16 zmm30, zmm29, zmmword ptr [rsp - 64] +0x62,0x62,0x17,0x40,0x72,0x74,0x24,0xff + +# ATT: vcvtne2ps2bf16 (%rcx){1to16}, %zmm29, %zmm30 +# INTEL: vcvtne2ps2bf16 zmm30, zmm29, dword ptr [rcx]{1to16} +0x62,0x62,0x17,0x50,0x72,0x31 + +# ATT: vcvtne2ps2bf16 8128(%rdx), %zmm29, %zmm30 +# INTEL: vcvtne2ps2bf16 zmm30, zmm29, zmmword ptr [rdx + 8128] +0x62,0x62,0x17,0x40,0x72,0x72,0x7f + +# ATT: vcvtne2ps2bf16 -8192(%rdx), %zmm29, %zmm30 +# INTEL: vcvtne2ps2bf16 zmm30, zmm29, zmmword ptr [rdx - 8192] +0x62,0x62,0x17,0x40,0x72,0x72,0x80 + +# ATT: vcvtne2ps2bf16 508(%rdx){1to16}, %zmm29, %zmm30 +# INTEL: vcvtne2ps2bf16 zmm30, zmm29, dword ptr [rdx + 508]{1to16} +0x62,0x62,0x17,0x50,0x72,0x72,0x7f + +# ATT: vcvtne2ps2bf16 -512(%rdx){1to16}, %zmm29, %zmm30 +# INTEL: vcvtne2ps2bf16 zmm30, zmm29, dword ptr [rdx - 512]{1to16} +0x62,0x62,0x17,0x50,0x72,0x72,0x80 + +# ATT: vcvtneps2bf16 %zmm29, %ymm30 +# INTEL: vcvtneps2bf16 ymm30, zmm29 +0x62,0x02,0x7e,0x48,0x72,0xf5 + +# ATT: vcvtneps2bf16 268435456(%rbp,%r14,8), %ymm30 {%k7} +# INTEL: vcvtneps2bf16 ymm30 {k7}, zmmword ptr [rbp + 8*r14 + 268435456] +0x62,0x22,0x7e,0x4f,0x72,0xb4,0xf5,0x00,0x00,0x00,0x10 + +# ATT: vcvtneps2bf16 (%r9){1to16}, %ymm30 +# INTEL: vcvtneps2bf16 ymm30, dword ptr [r9]{1to16} +0x62,0x42,0x7e,0x58,0x72,0x31 + +# ATT: vcvtneps2bf16 8128(%rcx), %ymm30 +# INTEL: vcvtneps2bf16 ymm30, zmmword ptr [rcx + 8128] +0x62,0x62,0x7e,0x48,0x72,0x71,0x7f + +# ATT: vcvtneps2bf16 -512(%rdx){1to16}, %ymm30 {%k7} {z} +# INTEL: vcvtneps2bf16 ymm30 {k7} {z}, dword ptr [rdx - 512]{1to16} +0x62,0x62,0x7e,0xdf,0x72,0x72,0x80 + +# ATT: vdpbf16ps %zmm28, %zmm29, %zmm30 +# INTEL: vdpbf16ps zmm30, zmm29, zmm28 +0x62,0x02,0x16,0x40,0x52,0xf4 + +# ATT: vdpbf16ps 268435456(%rbp,%r14,8), %zmm29, %zmm30 {%k7} +# INTEL: vdpbf16ps zmm30 {k7}, zmm29, zmmword ptr [rbp + 8*r14 + 268435456] +0x62,0x22,0x16,0x47,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10 + +# ATT: vdpbf16ps (%r9){1to16}, %zmm29, %zmm30 +# INTEL: vdpbf16ps zmm30, zmm29, dword ptr [r9]{1to16} +0x62,0x42,0x16,0x50,0x52,0x31 + +# ATT: vdpbf16ps 8128(%rcx), %zmm29, %zmm30 +# INTEL: vdpbf16ps zmm30, zmm29, zmmword ptr [rcx + 8128] +0x62,0x62,0x16,0x40,0x52,0x71,0x7f + +# ATT: vdpbf16ps -512(%rdx){1to16}, %zmm29, %zmm30 {%k7} {z} +# INTEL: vdpbf16ps zmm30 {k7} {z}, zmm29, dword ptr [rdx - 512]{1to16} +0x62,0x62,0x16,0xd7,0x52,0x72,0x80 diff --git a/llvm/test/MC/Disassembler/X86/avx512_bf16_vl-32.txt b/llvm/test/MC/Disassembler/X86/avx512_bf16_vl-32.txt new file mode 100644 index 000000000000..65ff8f73410f --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/avx512_bf16_vl-32.txt @@ -0,0 +1,170 @@ +# RUN: llvm-mc -triple i686-unknown-unknown -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple i686-unknown-unknown -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: vcvtne2ps2bf16 %xmm4, %xmm5, %xmm6 {%k7} +# INTEL: vcvtne2ps2bf16 xmm6 {k7}, xmm5, xmm4 +0x62,0xf2,0x57,0x0f,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 %xmm4, %xmm5, %xmm6 {%k7} {z} +# INTEL: vcvtne2ps2bf16 xmm6 {k7} {z}, xmm5, xmm4 +0x62,0xf2,0x57,0x8f,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 (%ecx), %xmm5, %xmm6 {%k7} +# INTEL: vcvtne2ps2bf16 xmm6 {k7}, xmm5, xmmword ptr [ecx] +0x62,0xf2,0x57,0x0f,0x72,0x31 + +# ATT: vcvtne2ps2bf16 291(%esp,%esi,8), %xmm5, %xmm6 {%k7} +# INTEL: vcvtne2ps2bf16 xmm6 {k7}, xmm5, xmmword ptr [esp + 8*esi + 291] +0x62,0xf2,0x57,0x0f,0x72,0xb4,0xf4,0x23,0x01,0x00,0x00 + +# ATT: vcvtne2ps2bf16 268435456(%esp,%esi,8), %xmm5, %xmm6 {%k7} +# INTEL: vcvtne2ps2bf16 xmm6 {k7}, xmm5, xmmword ptr [esp + 8*esi + 268435456] +0x62,0xf2,0x57,0x0f,0x72,0xb4,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vcvtne2ps2bf16 -16(%esp), %xmm5, %xmm6 {%k7} +# INTEL: vcvtne2ps2bf16 xmm6 {k7}, xmm5, xmmword ptr [esp - 16] +0x62,0xf2,0x57,0x0f,0x72,0x74,0x24,0xff + +# ATT: vcvtne2ps2bf16 (%eax){1to4}, %xmm5, %xmm6 {%k7} +# INTEL: vcvtne2ps2bf16 xmm6 {k7}, xmm5, dword ptr [eax]{1to4} +0x62,0xf2,0x57,0x1f,0x72,0x30 + +# ATT: vcvtne2ps2bf16 2032(%edx), %xmm5, %xmm6 {%k7} +# INTEL: vcvtne2ps2bf16 xmm6 {k7}, xmm5, xmmword ptr [edx + 2032] +0x62,0xf2,0x57,0x0f,0x72,0x72,0x7f + +# ATT: vcvtne2ps2bf16 -2048(%edx), %xmm5, %xmm6 {%k7} +# INTEL: vcvtne2ps2bf16 xmm6 {k7}, xmm5, xmmword ptr [edx - 2048] +0x62,0xf2,0x57,0x0f,0x72,0x72,0x80 + +# ATT: vcvtne2ps2bf16 508(%edx){1to4}, %xmm5, %xmm6 {%k7} +# INTEL: vcvtne2ps2bf16 xmm6 {k7}, xmm5, dword ptr [edx + 508]{1to4} +0x62,0xf2,0x57,0x1f,0x72,0x72,0x7f + +# ATT: vcvtne2ps2bf16 -512(%edx){1to4}, %xmm5, %xmm6 {%k7} +# INTEL: vcvtne2ps2bf16 xmm6 {k7}, xmm5, dword ptr [edx - 512]{1to4} +0x62,0xf2,0x57,0x1f,0x72,0x72,0x80 + +# ATT: vcvtne2ps2bf16 %ymm4, %ymm5, %ymm6 {%k7} +# INTEL: vcvtne2ps2bf16 ymm6 {k7}, ymm5, ymm4 +0x62,0xf2,0x57,0x2f,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 %ymm4, %ymm5, %ymm6 {%k7} {z} +# INTEL: vcvtne2ps2bf16 ymm6 {k7} {z}, ymm5, ymm4 +0x62,0xf2,0x57,0xaf,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 (%ecx), %ymm5, %ymm6 {%k7} +# INTEL: vcvtne2ps2bf16 ymm6 {k7}, ymm5, ymmword ptr [ecx] +0x62,0xf2,0x57,0x2f,0x72,0x31 + +# ATT: vcvtne2ps2bf16 291(%esp,%esi,8), %ymm5, %ymm6 {%k7} +# INTEL: vcvtne2ps2bf16 ymm6 {k7}, ymm5, ymmword ptr [esp + 8*esi + 291] +0x62,0xf2,0x57,0x2f,0x72,0xb4,0xf4,0x23,0x01,0x00,0x00 + +# ATT: vcvtne2ps2bf16 268435456(%esp,%esi,8), %ymm5, %ymm6 {%k7} +# INTEL: vcvtne2ps2bf16 ymm6 {k7}, ymm5, ymmword ptr [esp + 8*esi + 268435456] +0x62,0xf2,0x57,0x2f,0x72,0xb4,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vcvtne2ps2bf16 -32(%esp), %ymm5, %ymm6 {%k7} +# INTEL: vcvtne2ps2bf16 ymm6 {k7}, ymm5, ymmword ptr [esp - 32] +0x62,0xf2,0x57,0x2f,0x72,0x74,0x24,0xff + +# ATT: vcvtne2ps2bf16 (%eax){1to8}, %ymm5, %ymm6 {%k7} +# INTEL: vcvtne2ps2bf16 ymm6 {k7}, ymm5, dword ptr [eax]{1to8} +0x62,0xf2,0x57,0x3f,0x72,0x30 + +# ATT: vcvtne2ps2bf16 4064(%edx), %ymm5, %ymm6 {%k7} +# INTEL: vcvtne2ps2bf16 ymm6 {k7}, ymm5, ymmword ptr [edx + 4064] +0x62,0xf2,0x57,0x2f,0x72,0x72,0x7f + +# ATT: vcvtne2ps2bf16 -4096(%edx), %ymm5, %ymm6 {%k7} +# INTEL: vcvtne2ps2bf16 ymm6 {k7}, ymm5, ymmword ptr [edx - 4096] +0x62,0xf2,0x57,0x2f,0x72,0x72,0x80 + +# ATT: vcvtne2ps2bf16 508(%edx){1to8}, %ymm5, %ymm6 {%k7} +# INTEL: vcvtne2ps2bf16 ymm6 {k7}, ymm5, dword ptr [edx + 508]{1to8} +0x62,0xf2,0x57,0x3f,0x72,0x72,0x7f + +# ATT: vcvtne2ps2bf16 -512(%edx){1to8}, %ymm5, %ymm6 {%k7} +# INTEL: vcvtne2ps2bf16 ymm6 {k7}, ymm5, dword ptr [edx - 512]{1to8} +0x62,0xf2,0x57,0x3f,0x72,0x72,0x80 + +# ATT: vcvtneps2bf16 %xmm5, %xmm6 +# INTEL: vcvtneps2bf16 xmm6, xmm5 +0x62,0xf2,0x7e,0x08,0x72,0xf5 + +# ATT: vcvtneps2bf16x 268435456(%esp,%esi,8), %xmm6 {%k7} +# INTEL: vcvtneps2bf16 xmm6 {k7}, xmmword ptr [esp + 8*esi + 268435456] +0x62,0xf2,0x7e,0x0f,0x72,0xb4,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vcvtneps2bf16 (%ecx){1to4}, %xmm6 +# INTEL: vcvtneps2bf16 xmm6, dword ptr [ecx]{1to4} +0x62,0xf2,0x7e,0x18,0x72,0x31 + +# ATT: vcvtneps2bf16x 2032(%ecx), %xmm6 +# INTEL: vcvtneps2bf16 xmm6, xmmword ptr [ecx + 2032] +0x62,0xf2,0x7e,0x08,0x72,0x71,0x7f + +# ATT: vcvtneps2bf16 -512(%edx){1to4}, %xmm6 {%k7} {z} +# INTEL: vcvtneps2bf16 xmm6 {k7} {z}, dword ptr [edx - 512]{1to4} +0x62,0xf2,0x7e,0x9f,0x72,0x72,0x80 + +# ATT: vcvtneps2bf16 %ymm5, %xmm6 +# INTEL: vcvtneps2bf16 xmm6, ymm5 +0x62,0xf2,0x7e,0x28,0x72,0xf5 + +# ATT: vcvtneps2bf16y 268435456(%esp,%esi,8), %xmm6 {%k7} +# INTEL: vcvtneps2bf16 xmm6 {k7}, ymmword ptr [esp + 8*esi + 268435456] +0x62,0xf2,0x7e,0x2f,0x72,0xb4,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vcvtneps2bf16 (%ecx){1to8}, %xmm6 +# INTEL: vcvtneps2bf16 xmm6, dword ptr [ecx]{1to8} +0x62,0xf2,0x7e,0x38,0x72,0x31 + +# ATT: vcvtneps2bf16y 4064(%ecx), %xmm6 +# INTEL: vcvtneps2bf16 xmm6, ymmword ptr [ecx + 4064] +0x62,0xf2,0x7e,0x28,0x72,0x71,0x7f + +# ATT: vcvtneps2bf16 -512(%edx){1to8}, %xmm6 {%k7} {z} +# INTEL: vcvtneps2bf16 xmm6 {k7} {z}, dword ptr [edx - 512]{1to8} +0x62,0xf2,0x7e,0xbf,0x72,0x72,0x80 + +# ATT: vdpbf16ps %ymm4, %ymm5, %ymm6 +# INTEL: vdpbf16ps ymm6, ymm5, ymm4 +0x62,0xf2,0x56,0x28,0x52,0xf4 + +# ATT: vdpbf16ps 268435456(%esp,%esi,8), %ymm5, %ymm6 {%k7} +# INTEL: vdpbf16ps ymm6 {k7}, ymm5, ymmword ptr [esp + 8*esi + 268435456] +0x62,0xf2,0x56,0x2f,0x52,0xb4,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vdpbf16ps (%ecx){1to8}, %ymm5, %ymm6 +# INTEL: vdpbf16ps ymm6, ymm5, dword ptr [ecx]{1to8} +0x62,0xf2,0x56,0x38,0x52,0x31 + +# ATT: vdpbf16ps 4064(%ecx), %ymm5, %ymm6 +# INTEL: vdpbf16ps ymm6, ymm5, ymmword ptr [ecx + 4064] +0x62,0xf2,0x56,0x28,0x52,0x71,0x7f + +# ATT: vdpbf16ps -512(%edx){1to8}, %ymm5, %ymm6 {%k7} {z} +# INTEL: vdpbf16ps ymm6 {k7} {z}, ymm5, dword ptr [edx - 512]{1to8} +0x62,0xf2,0x56,0xbf,0x52,0x72,0x80 + +# ATT: vdpbf16ps %xmm4, %xmm5, %xmm6 +# INTEL: vdpbf16ps xmm6, xmm5, xmm4 +0x62,0xf2,0x56,0x08,0x52,0xf4 + +# ATT: vdpbf16ps 268435456(%esp,%esi,8), %xmm5, %xmm6 {%k7} +# INTEL: vdpbf16ps xmm6 {k7}, xmm5, xmmword ptr [esp + 8*esi + 268435456] +0x62,0xf2,0x56,0x0f,0x52,0xb4,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vdpbf16ps (%ecx){1to4}, %xmm5, %xmm6 +# INTEL: vdpbf16ps xmm6, xmm5, dword ptr [ecx]{1to4} +0x62,0xf2,0x56,0x18,0x52,0x31 + +# ATT: vdpbf16ps 2032(%ecx), %xmm5, %xmm6 +# INTEL: vdpbf16ps xmm6, xmm5, xmmword ptr [ecx + 2032] +0x62,0xf2,0x56,0x08,0x52,0x71,0x7f + +# ATT: vdpbf16ps -512(%edx){1to4}, %xmm5, %xmm6 {%k7} {z} +# INTEL: vdpbf16ps xmm6 {k7} {z}, xmm5, dword ptr [edx - 512]{1to4} +0x62,0xf2,0x56,0x9f,0x52,0x72,0x80 diff --git a/llvm/test/MC/Disassembler/X86/avx512_bf16_vl-64.txt b/llvm/test/MC/Disassembler/X86/avx512_bf16_vl-64.txt new file mode 100644 index 000000000000..d7fe10270cd3 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/avx512_bf16_vl-64.txt @@ -0,0 +1,178 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: vcvtne2ps2bf16 %xmm28, %xmm29, %xmm30 +# INTEL: vcvtne2ps2bf16 xmm30, xmm29, xmm28 +0x62,0x02,0x17,0x00,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 %xmm28, %xmm29, %xmm30 {%k7} +# INTEL: vcvtne2ps2bf16 xmm30 {k7}, xmm29, xmm28 +0x62,0x02,0x17,0x07,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 %xmm28, %xmm29, %xmm30 {%k7} {z} +# INTEL: vcvtne2ps2bf16 xmm30 {k7} {z}, xmm29, xmm28 +0x62,0x02,0x17,0x87,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 (%rcx), %xmm29, %xmm30 +# INTEL: vcvtne2ps2bf16 xmm30, xmm29, xmmword ptr [rcx] +0x62,0x62,0x17,0x00,0x72,0x31 + +# ATT: vcvtne2ps2bf16 291(%rax,%r14,8), %xmm29, %xmm30 +# INTEL: vcvtne2ps2bf16 xmm30, xmm29, xmmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x17,0x00,0x72,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vcvtne2ps2bf16 268435456(%rax,%r14,8), %xmm29, %xmm30 +# INTEL: vcvtne2ps2bf16 xmm30, xmm29, xmmword ptr [rax + 8*r14 + 268435456] +0x62,0x22,0x17,0x00,0x72,0xb4,0xf0,0x00,0x00,0x00,0x10 + +# ATT: vcvtne2ps2bf16 -16(%rsp), %xmm29, %xmm30 +# INTEL: vcvtne2ps2bf16 xmm30, xmm29, xmmword ptr [rsp - 16] +0x62,0x62,0x17,0x00,0x72,0x74,0x24,0xff + +# ATT: vcvtne2ps2bf16 (%rcx){1to4}, %xmm29, %xmm30 +# INTEL: vcvtne2ps2bf16 xmm30, xmm29, dword ptr [rcx]{1to4} +0x62,0x62,0x17,0x10,0x72,0x31 + +# ATT: vcvtne2ps2bf16 2032(%rdx), %xmm29, %xmm30 +# INTEL: vcvtne2ps2bf16 xmm30, xmm29, xmmword ptr [rdx + 2032] +0x62,0x62,0x17,0x00,0x72,0x72,0x7f + +# ATT: vcvtne2ps2bf16 -2048(%rdx), %xmm29, %xmm30 +# INTEL: vcvtne2ps2bf16 xmm30, xmm29, xmmword ptr [rdx - 2048] +0x62,0x62,0x17,0x00,0x72,0x72,0x80 + +# ATT: vcvtne2ps2bf16 508(%rdx){1to4}, %xmm29, %xmm30 +# INTEL: vcvtne2ps2bf16 xmm30, xmm29, dword ptr [rdx + 508]{1to4} +0x62,0x62,0x17,0x10,0x72,0x72,0x7f + +# ATT: vcvtne2ps2bf16 -512(%rdx){1to4}, %xmm29, %xmm30 +# INTEL: vcvtne2ps2bf16 xmm30, xmm29, dword ptr [rdx - 512]{1to4} +0x62,0x62,0x17,0x10,0x72,0x72,0x80 + +# ATT: vcvtne2ps2bf16 %ymm28, %ymm29, %ymm30 +# INTEL: vcvtne2ps2bf16 ymm30, ymm29, ymm28 +0x62,0x02,0x17,0x20,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 %ymm28, %ymm29, %ymm30 {%k7} +# INTEL: vcvtne2ps2bf16 ymm30 {k7}, ymm29, ymm28 +0x62,0x02,0x17,0x27,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 %ymm28, %ymm29, %ymm30 {%k7} {z} +# INTEL: vcvtne2ps2bf16 ymm30 {k7} {z}, ymm29, ymm28 +0x62,0x02,0x17,0xa7,0x72,0xf4 + +# ATT: vcvtne2ps2bf16 (%rcx), %ymm29, %ymm30 +# INTEL: vcvtne2ps2bf16 ymm30, ymm29, ymmword ptr [rcx] +0x62,0x62,0x17,0x20,0x72,0x31 + +# ATT: vcvtne2ps2bf16 291(%rax,%r14,8), %ymm29, %ymm30 +# INTEL: vcvtne2ps2bf16 ymm30, ymm29, ymmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x17,0x20,0x72,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vcvtne2ps2bf16 268435456(%rax,%r14,8), %ymm29, %ymm30 +# INTEL: vcvtne2ps2bf16 ymm30, ymm29, ymmword ptr [rax + 8*r14 + 268435456] +0x62,0x22,0x17,0x20,0x72,0xb4,0xf0,0x00,0x00,0x00,0x10 + +# ATT: vcvtne2ps2bf16 -32(%rsp), %ymm29, %ymm30 +# INTEL: vcvtne2ps2bf16 ymm30, ymm29, ymmword ptr [rsp - 32] +0x62,0x62,0x17,0x20,0x72,0x74,0x24,0xff + +# ATT: vcvtne2ps2bf16 (%rcx){1to8}, %ymm29, %ymm30 +# INTEL: vcvtne2ps2bf16 ymm30, ymm29, dword ptr [rcx]{1to8} +0x62,0x62,0x17,0x30,0x72,0x31 + +# ATT: vcvtne2ps2bf16 4064(%rdx), %ymm29, %ymm30 +# INTEL: vcvtne2ps2bf16 ymm30, ymm29, ymmword ptr [rdx + 4064] +0x62,0x62,0x17,0x20,0x72,0x72,0x7f + +# ATT: vcvtne2ps2bf16 -4096(%rdx), %ymm29, %ymm30 +# INTEL: vcvtne2ps2bf16 ymm30, ymm29, ymmword ptr [rdx - 4096] +0x62,0x62,0x17,0x20,0x72,0x72,0x80 + +# ATT: vcvtne2ps2bf16 508(%rdx){1to8}, %ymm29, %ymm30 +# INTEL: vcvtne2ps2bf16 ymm30, ymm29, dword ptr [rdx + 508]{1to8} +0x62,0x62,0x17,0x30,0x72,0x72,0x7f + +# ATT: vcvtne2ps2bf16 -512(%rdx){1to8}, %ymm29, %ymm30 +# INTEL: vcvtne2ps2bf16 ymm30, ymm29, dword ptr [rdx - 512]{1to8} +0x62,0x62,0x17,0x30,0x72,0x72,0x80 + +# ATT: vcvtneps2bf16 %xmm29, %xmm30 +# INTEL: vcvtneps2bf16 xmm30, xmm29 +0x62,0x02,0x7e,0x08,0x72,0xf5 + +# ATT: vcvtneps2bf16x 268435456(%rbp,%r14,8), %xmm30 {%k7} +# INTEL: vcvtneps2bf16 xmm30 {k7}, xmmword ptr [rbp + 8*r14 + 268435456] +0x62,0x22,0x7e,0x0f,0x72,0xb4,0xf5,0x00,0x00,0x00,0x10 + +# ATT: vcvtneps2bf16 (%r9){1to4}, %xmm30 +# INTEL: vcvtneps2bf16 xmm30, dword ptr [r9]{1to4} +0x62,0x42,0x7e,0x18,0x72,0x31 + +# ATT: vcvtneps2bf16x 2032(%rcx), %xmm30 +# INTEL: vcvtneps2bf16 xmm30, xmmword ptr [rcx + 2032] +0x62,0x62,0x7e,0x08,0x72,0x71,0x7f + +# ATT: vcvtneps2bf16 -512(%rdx){1to4}, %xmm30 {%k7} {z} +# INTEL: vcvtneps2bf16 xmm30 {k7} {z}, dword ptr [rdx - 512]{1to4} +0x62,0x62,0x7e,0x9f,0x72,0x72,0x80 + +# ATT: vcvtneps2bf16 %ymm29, %xmm30 +# INTEL: vcvtneps2bf16 xmm30, ymm29 +0x62,0x02,0x7e,0x28,0x72,0xf5 + +# ATT: vcvtneps2bf16y 268435456(%rbp,%r14,8), %xmm30 {%k7} +# INTEL: vcvtneps2bf16 xmm30 {k7}, ymmword ptr [rbp + 8*r14 + 268435456] +0x62,0x22,0x7e,0x2f,0x72,0xb4,0xf5,0x00,0x00,0x00,0x10 + +# ATT: vcvtneps2bf16 (%r9){1to8}, %xmm30 +# INTEL: vcvtneps2bf16 xmm30, dword ptr [r9]{1to8} +0x62,0x42,0x7e,0x38,0x72,0x31 + +# ATT: vcvtneps2bf16y 4064(%rcx), %xmm30 +# INTEL: vcvtneps2bf16 xmm30, ymmword ptr [rcx + 4064] +0x62,0x62,0x7e,0x28,0x72,0x71,0x7f + +# ATT: vcvtneps2bf16 -512(%rdx){1to8}, %xmm30 {%k7} {z} +# INTEL: vcvtneps2bf16 xmm30 {k7} {z}, dword ptr [rdx - 512]{1to8} +0x62,0x62,0x7e,0xbf,0x72,0x72,0x80 + +# ATT: vdpbf16ps %ymm28, %ymm29, %ymm30 +# INTEL: vdpbf16ps ymm30, ymm29, ymm28 +0x62,0x02,0x16,0x20,0x52,0xf4 + +# ATT: vdpbf16ps 268435456(%rbp,%r14,8), %ymm29, %ymm30 {%k7} +# INTEL: vdpbf16ps ymm30 {k7}, ymm29, ymmword ptr [rbp + 8*r14 + 268435456] +0x62,0x22,0x16,0x27,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10 + +# ATT: vdpbf16ps (%r9){1to8}, %ymm29, %ymm30 +# INTEL: vdpbf16ps ymm30, ymm29, dword ptr [r9]{1to8} +0x62,0x42,0x16,0x30,0x52,0x31 + +# ATT: vdpbf16ps 4064(%rcx), %ymm29, %ymm30 +# INTEL: vdpbf16ps ymm30, ymm29, ymmword ptr [rcx + 4064] +0x62,0x62,0x16,0x20,0x52,0x71,0x7f + +# ATT: vdpbf16ps -512(%rdx){1to8}, %ymm29, %ymm30 {%k7} {z} +# INTEL: vdpbf16ps ymm30 {k7} {z}, ymm29, dword ptr [rdx - 512]{1to8} +0x62,0x62,0x16,0xb7,0x52,0x72,0x80 + +# ATT: vdpbf16ps %xmm28, %xmm29, %xmm30 +# INTEL: vdpbf16ps xmm30, xmm29, xmm28 +0x62,0x02,0x16,0x00,0x52,0xf4 + +# ATT: vdpbf16ps 268435456(%rbp,%r14,8), %xmm29, %xmm30 {%k7} +# INTEL: vdpbf16ps xmm30 {k7}, xmm29, xmmword ptr [rbp + 8*r14 + 268435456] +0x62,0x22,0x16,0x07,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10 + +# ATT: vdpbf16ps (%r9){1to4}, %xmm29, %xmm30 +# INTEL: vdpbf16ps xmm30, xmm29, dword ptr [r9]{1to4} +0x62,0x42,0x16,0x10,0x52,0x31 + +# ATT: vdpbf16ps 2032(%rcx), %xmm29, %xmm30 +# INTEL: vdpbf16ps xmm30, xmm29, xmmword ptr [rcx + 2032] +0x62,0x62,0x16,0x00,0x52,0x71,0x7f + +# ATT: vdpbf16ps -512(%rdx){1to4}, %xmm29, %xmm30 {%k7} {z} +# INTEL: vdpbf16ps xmm30 {k7} {z}, xmm29, dword ptr [rdx - 512]{1to4} +0x62,0x62,0x16,0x97,0x52,0x72,0x80 diff --git a/llvm/test/MC/Disassembler/X86/avx512bf16-att.txt b/llvm/test/MC/Disassembler/X86/avx512bf16-att.txt deleted file mode 100644 index a6dc4b684c51..000000000000 --- a/llvm/test/MC/Disassembler/X86/avx512bf16-att.txt +++ /dev/null @@ -1,82 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=i686-apple-darwin9 | FileCheck %s - -# CHECK: vcvtne2ps2bf16 %zmm4, %zmm3, %zmm2 -0x62,0xf2,0x67,0x48,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 %zmm4, %zmm3, %zmm2 {%k7} -0x62,0xf2,0x67,0x4f,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 %zmm4, %zmm3, %zmm2 {%k7} {z} -0x62,0xf2,0x67,0xcf,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 268435456(%esp,%esi,8), %zmm3, %zmm2 -0x62,0xf2,0x67,0x48,0x72,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vcvtne2ps2bf16 291(%edi,%eax,4), %zmm3, %zmm2 {%k7} -0x62,0xf2,0x67,0x4f,0x72,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 (%eax){1to16}, %zmm3, %zmm2 -0x62,0xf2,0x67,0x58,0x72,0x10 - -# CHECK: vcvtne2ps2bf16 -2048(,%ebp,2), %zmm3, %zmm2 -0x62,0xf2,0x67,0x48,0x72,0x14,0x6d,0x00,0xf8,0xff,0xff - -# CHECK: vcvtne2ps2bf16 8128(%ecx), %zmm3, %zmm2 {%k7} {z} -0x62,0xf2,0x67,0xcf,0x72,0x51,0x7f - -# CHECK: vcvtne2ps2bf16 -512(%edx){1to16}, %zmm3, %zmm2 {%k7} {z} -0x62,0xf2,0x67,0xdf,0x72,0x52,0x80 - -# CHECK: vcvtneps2bf16 %zmm3, %ymm2 -0x62,0xf2,0x7e,0x48,0x72,0xd3 - -# CHECK: vcvtneps2bf16 %zmm3, %ymm2 {%k7} -0x62,0xf2,0x7e,0x4f,0x72,0xd3 - -# CHECK: vcvtneps2bf16 %zmm3, %ymm2 {%k7} {z} -0x62,0xf2,0x7e,0xcf,0x72,0xd3 - -# CHECK: vcvtneps2bf16 268435456(%esp,%esi,8), %ymm2 -0x62,0xf2,0x7e,0x48,0x72,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vcvtneps2bf16 291(%edi,%eax,4), %ymm2 {%k7} -0x62,0xf2,0x7e,0x4f,0x72,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vcvtneps2bf16 (%eax){1to16}, %ymm2 -0x62,0xf2,0x7e,0x58,0x72,0x10 - -# CHECK: vcvtneps2bf16 -2048(,%ebp,2), %ymm2 -0x62,0xf2,0x7e,0x48,0x72,0x14,0x6d,0x00,0xf8,0xff,0xff - -# CHECK: vcvtneps2bf16 8128(%ecx), %ymm2 {%k7} {z} -0x62,0xf2,0x7e,0xcf,0x72,0x51,0x7f - -# CHECK: vcvtneps2bf16 -512(%edx){1to16}, %ymm2 {%k7} {z} -0x62,0xf2,0x7e,0xdf,0x72,0x52,0x80 - -# CHECK: vdpbf16ps %zmm4, %zmm3, %zmm2 -0x62,0xf2,0x66,0x48,0x52,0xd4 - -# CHECK: vdpbf16ps %zmm4, %zmm3, %zmm2 {%k7} -0x62,0xf2,0x66,0x4f,0x52,0xd4 - -# CHECK: vdpbf16ps %zmm4, %zmm3, %zmm2 {%k7} {z} -0x62,0xf2,0x66,0xcf,0x52,0xd4 - -# CHECK: vdpbf16ps 268435456(%esp,%esi,8), %zmm3, %zmm2 -0x62,0xf2,0x66,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vdpbf16ps 291(%edi,%eax,4), %zmm3, %zmm2 {%k7} -0x62,0xf2,0x66,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vdpbf16ps (%eax){1to16}, %zmm3, %zmm2 -0x62,0xf2,0x66,0x58,0x52,0x10 - -# CHECK: vdpbf16ps -2048(,%ebp,2), %zmm3, %zmm2 -0x62,0xf2,0x66,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff - -# CHECK: vdpbf16ps 8128(%ecx), %zmm3, %zmm2 {%k7} {z} -0x62,0xf2,0x66,0xcf,0x52,0x51,0x7f - -# CHECK: vdpbf16ps -512(%edx){1to16}, %zmm3, %zmm2 {%k7} {z} -0x62,0xf2,0x66,0xdf,0x52,0x52,0x80 diff --git a/llvm/test/MC/Disassembler/X86/avx512bf16-intel.txt b/llvm/test/MC/Disassembler/X86/avx512bf16-intel.txt deleted file mode 100644 index 53d44fa7fb7a..000000000000 --- a/llvm/test/MC/Disassembler/X86/avx512bf16-intel.txt +++ /dev/null @@ -1,82 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=i686 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s - -# CHECK: vcvtne2ps2bf16 zmm2, zmm3, zmm4 -0x62,0xf2,0x67,0x48,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 zmm2 {k7}, zmm3, zmm4 -0x62,0xf2,0x67,0x4f,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 zmm2 {k7} {z}, zmm3, zmm4 -0x62,0xf2,0x67,0xcf,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456] -0x62,0xf2,0x67,0x48,0x72,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vcvtne2ps2bf16 zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291] -0x62,0xf2,0x67,0x4f,0x72,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 zmm2, zmm3, dword ptr [eax]{1to16} -0x62,0xf2,0x67,0x58,0x72,0x10 - -# CHECK: vcvtne2ps2bf16 zmm2, zmm3, zmmword ptr [2*ebp - 2048] -0x62,0xf2,0x67,0x48,0x72,0x14,0x6d,0x00,0xf8,0xff,0xff - -# CHECK: vcvtne2ps2bf16 zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128] -0x62,0xf2,0x67,0xcf,0x72,0x51,0x7f - -# CHECK: vcvtne2ps2bf16 zmm2 {k7} {z}, zmm3, dword ptr [edx - 512]{1to16} -0x62,0xf2,0x67,0xdf,0x72,0x52,0x80 - -# CHECK: vcvtneps2bf16 ymm2, zmm3 -0x62,0xf2,0x7e,0x48,0x72,0xd3 - -# CHECK: vcvtneps2bf16 ymm2 {k7}, zmm3 -0x62,0xf2,0x7e,0x4f,0x72,0xd3 - -# CHECK: vcvtneps2bf16 ymm2 {k7} {z}, zmm3 -0x62,0xf2,0x7e,0xcf,0x72,0xd3 - -# CHECK: vcvtneps2bf16 ymm2, zmmword ptr [esp + 8*esi + 268435456] -0x62,0xf2,0x7e,0x48,0x72,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vcvtneps2bf16 ymm2 {k7}, zmmword ptr [edi + 4*eax + 291] -0x62,0xf2,0x7e,0x4f,0x72,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vcvtneps2bf16 ymm2, dword ptr [eax]{1to16} -0x62,0xf2,0x7e,0x58,0x72,0x10 - -# CHECK: vcvtneps2bf16 ymm2, zmmword ptr [2*ebp - 2048] -0x62,0xf2,0x7e,0x48,0x72,0x14,0x6d,0x00,0xf8,0xff,0xff - -# CHECK: vcvtneps2bf16 ymm2 {k7} {z}, zmmword ptr [ecx + 8128] -0x62,0xf2,0x7e,0xcf,0x72,0x51,0x7f - -# CHECK: vcvtneps2bf16 ymm2 {k7} {z}, dword ptr [edx - 512]{1to16} -0x62,0xf2,0x7e,0xdf,0x72,0x52,0x80 - -# CHECK: vdpbf16ps zmm2, zmm3, zmm4 -0x62,0xf2,0x66,0x48,0x52,0xd4 - -# CHECK: vdpbf16ps zmm2 {k7}, zmm3, zmm4 -0x62,0xf2,0x66,0x4f,0x52,0xd4 - -# CHECK: vdpbf16ps zmm2 {k7} {z}, zmm3, zmm4 -0x62,0xf2,0x66,0xcf,0x52,0xd4 - -# CHECK: vdpbf16ps zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456] -0x62,0xf2,0x66,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vdpbf16ps zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291] -0x62,0xf2,0x66,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vdpbf16ps zmm2, zmm3, dword ptr [eax]{1to16} -0x62,0xf2,0x66,0x58,0x52,0x10 - -# CHECK: vdpbf16ps zmm2, zmm3, zmmword ptr [2*ebp - 2048] -0x62,0xf2,0x66,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff - -# CHECK: vdpbf16ps zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128] -0x62,0xf2,0x66,0xcf,0x52,0x51,0x7f - -# CHECK: vdpbf16ps zmm2 {k7} {z}, zmm3, dword ptr [edx - 512]{1to16} -0x62,0xf2,0x66,0xdf,0x52,0x52,0x80 diff --git a/llvm/test/MC/Disassembler/X86/avx512bf16vl-att.txt b/llvm/test/MC/Disassembler/X86/avx512bf16vl-att.txt deleted file mode 100644 index ea5e84ffab46..000000000000 --- a/llvm/test/MC/Disassembler/X86/avx512bf16vl-att.txt +++ /dev/null @@ -1,157 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=i686-apple-darwin9 | FileCheck %s - -# CHECK: vcvtne2ps2bf16 %ymm4, %ymm3, %ymm2 -0x62,0xf2,0x67,0x28,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 %ymm4, %ymm3, %ymm2 {%k7} -0x62,0xf2,0x67,0x2f,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 %ymm4, %ymm3, %ymm2 {%k7} {z} -0x62,0xf2,0x67,0xaf,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 %xmm4, %xmm3, %xmm2 -0x62,0xf2,0x67,0x08,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 %xmm4, %xmm3, %xmm2 {%k7} -0x62,0xf2,0x67,0x0f,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 %xmm4, %xmm3, %xmm2 {%k7} {z} -0x62,0xf2,0x67,0x8f,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 268435456(%esp,%esi,8), %ymm3, %ymm2 -0x62,0xf2,0x67,0x28,0x72,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vcvtne2ps2bf16 291(%edi,%eax,4), %ymm3, %ymm2 {%k7} -0x62,0xf2,0x67,0x2f,0x72,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 (%eax){1to8}, %ymm3, %ymm2 -0x62,0xf2,0x67,0x38,0x72,0x10 - -# CHECK: vcvtne2ps2bf16 -1024(,%ebp,2), %ymm3, %ymm2 -0x62,0xf2,0x67,0x28,0x72,0x14,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vcvtne2ps2bf16 4064(%ecx), %ymm3, %ymm2 {%k7} {z} -0x62,0xf2,0x67,0xaf,0x72,0x51,0x7f - -# CHECK: vcvtne2ps2bf16 -512(%edx){1to8}, %ymm3, %ymm2 {%k7} {z} -0x62,0xf2,0x67,0xbf,0x72,0x52,0x80 - -# CHECK: vcvtne2ps2bf16 268435456(%esp,%esi,8), %xmm3, %xmm2 -0x62,0xf2,0x67,0x08,0x72,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vcvtne2ps2bf16 291(%edi,%eax,4), %xmm3, %xmm2 {%k7} -0x62,0xf2,0x67,0x0f,0x72,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 (%eax){1to4}, %xmm3, %xmm2 -0x62,0xf2,0x67,0x18,0x72,0x10 - -# CHECK: vcvtne2ps2bf16 -512(,%ebp,2), %xmm3, %xmm2 -0x62,0xf2,0x67,0x08,0x72,0x14,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vcvtne2ps2bf16 2032(%ecx), %xmm3, %xmm2 {%k7} {z} -0x62,0xf2,0x67,0x8f,0x72,0x51,0x7f - -# CHECK: vcvtne2ps2bf16 -512(%edx){1to4}, %xmm3, %xmm2 {%k7} {z} -0x62,0xf2,0x67,0x9f,0x72,0x52,0x80 - -# CHECK: vcvtneps2bf16 %xmm3, %xmm2 -0x62,0xf2,0x7e,0x08,0x72,0xd3 - -# CHECK: vcvtneps2bf16 %xmm3, %xmm2 {%k7} -0x62,0xf2,0x7e,0x0f,0x72,0xd3 - -# CHECK: vcvtneps2bf16 %xmm3, %xmm2 {%k7} {z} -0x62,0xf2,0x7e,0x8f,0x72,0xd3 - -# CHECK: vcvtneps2bf16 %ymm3, %xmm2 -0x62,0xf2,0x7e,0x28,0x72,0xd3 - -# CHECK: vcvtneps2bf16 %ymm3, %xmm2 {%k7} -0x62,0xf2,0x7e,0x2f,0x72,0xd3 - -# CHECK: vcvtneps2bf16 %ymm3, %xmm2 {%k7} {z} -0x62,0xf2,0x7e,0xaf,0x72,0xd3 - -# CHECK: vcvtneps2bf16x 268435456(%esp,%esi,8), %xmm2 -0x62,0xf2,0x7e,0x08,0x72,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vcvtneps2bf16x 291(%edi,%eax,4), %xmm2 {%k7} -0x62,0xf2,0x7e,0x0f,0x72,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vcvtneps2bf16 (%eax){1to4}, %xmm2 -0x62,0xf2,0x7e,0x18,0x72,0x10 - -# CHECK: vcvtneps2bf16x -512(,%ebp,2), %xmm2 -0x62,0xf2,0x7e,0x08,0x72,0x14,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vcvtneps2bf16x 2032(%ecx), %xmm2 {%k7} {z} -0x62,0xf2,0x7e,0x8f,0x72,0x51,0x7f - -# CHECK: vcvtneps2bf16 -512(%edx){1to4}, %xmm2 {%k7} {z} -0x62,0xf2,0x7e,0x9f,0x72,0x52,0x80 - -# CHECK: vcvtneps2bf16 (%eax){1to8}, %xmm2 -0x62,0xf2,0x7e,0x38,0x72,0x10 - -# CHECK: vcvtneps2bf16y -1024(,%ebp,2), %xmm2 -0x62,0xf2,0x7e,0x28,0x72,0x14,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vcvtneps2bf16y 4064(%ecx), %xmm2 {%k7} {z} -0x62,0xf2,0x7e,0xaf,0x72,0x51,0x7f - -# CHECK: vcvtneps2bf16 -512(%edx){1to8}, %xmm2 {%k7} {z} -0x62,0xf2,0x7e,0xbf,0x72,0x52,0x80 - -# CHECK: vdpbf16ps %ymm4, %ymm3, %ymm2 -0x62,0xf2,0x66,0x28,0x52,0xd4 - -# CHECK: vdpbf16ps %ymm4, %ymm3, %ymm2 {%k7} -0x62,0xf2,0x66,0x2f,0x52,0xd4 - -# CHECK: vdpbf16ps %ymm4, %ymm3, %ymm2 {%k7} {z} -0x62,0xf2,0x66,0xaf,0x52,0xd4 - -# CHECK: vdpbf16ps %xmm4, %xmm3, %xmm2 -0x62,0xf2,0x66,0x08,0x52,0xd4 - -# CHECK: vdpbf16ps %xmm4, %xmm3, %xmm2 {%k7} -0x62,0xf2,0x66,0x0f,0x52,0xd4 - -# CHECK: vdpbf16ps %xmm4, %xmm3, %xmm2 {%k7} {z} -0x62,0xf2,0x66,0x8f,0x52,0xd4 - -# CHECK: vdpbf16ps 268435456(%esp,%esi,8), %ymm3, %ymm2 -0x62,0xf2,0x66,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vdpbf16ps 291(%edi,%eax,4), %ymm3, %ymm2 {%k7} -0x62,0xf2,0x66,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vdpbf16ps (%eax){1to8}, %ymm3, %ymm2 -0x62,0xf2,0x66,0x38,0x52,0x10 - -# CHECK: vdpbf16ps -1024(,%ebp,2), %ymm3, %ymm2 -0x62,0xf2,0x66,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vdpbf16ps 4064(%ecx), %ymm3, %ymm2 {%k7} {z} -0x62,0xf2,0x66,0xaf,0x52,0x51,0x7f - -# CHECK: vdpbf16ps -512(%edx){1to8}, %ymm3, %ymm2 {%k7} {z} -0x62,0xf2,0x66,0xbf,0x52,0x52,0x80 - -# CHECK: vdpbf16ps 268435456(%esp,%esi,8), %xmm3, %xmm2 -0x62,0xf2,0x66,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vdpbf16ps 291(%edi,%eax,4), %xmm3, %xmm2 {%k7} -0x62,0xf2,0x66,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vdpbf16ps (%eax){1to4}, %xmm3, %xmm2 -0x62,0xf2,0x66,0x18,0x52,0x10 - -# CHECK: vdpbf16ps -512(,%ebp,2), %xmm3, %xmm2 -0x62,0xf2,0x66,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vdpbf16ps 2032(%ecx), %xmm3, %xmm2 {%k7} {z} -0x62,0xf2,0x66,0x8f,0x52,0x51,0x7f - -# CHECK: vdpbf16ps -512(%edx){1to4}, %xmm3, %xmm2 {%k7} {z} -0x62,0xf2,0x66,0x9f,0x52,0x52,0x80 diff --git a/llvm/test/MC/Disassembler/X86/avx512bf16vl-intel.txt b/llvm/test/MC/Disassembler/X86/avx512bf16vl-intel.txt deleted file mode 100644 index 3d9dcb1879d4..000000000000 --- a/llvm/test/MC/Disassembler/X86/avx512bf16vl-intel.txt +++ /dev/null @@ -1,157 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=i686 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s - -# CHECK: vcvtne2ps2bf16 ymm2, ymm3, ymm4 -0x62,0xf2,0x67,0x28,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 ymm2 {k7}, ymm3, ymm4 -0x62,0xf2,0x67,0x2f,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 ymm2 {k7} {z}, ymm3, ymm4 -0x62,0xf2,0x67,0xaf,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 xmm2, xmm3, xmm4 -0x62,0xf2,0x67,0x08,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 xmm2 {k7}, xmm3, xmm4 -0x62,0xf2,0x67,0x0f,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 xmm2 {k7} {z}, xmm3, xmm4 -0x62,0xf2,0x67,0x8f,0x72,0xd4 - -# CHECK: vcvtne2ps2bf16 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -0x62,0xf2,0x67,0x28,0x72,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vcvtne2ps2bf16 ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291] -0x62,0xf2,0x67,0x2f,0x72,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 ymm2, ymm3, dword ptr [eax]{1to8} -0x62,0xf2,0x67,0x38,0x72,0x10 - -# CHECK: vcvtne2ps2bf16 ymm2, ymm3, ymmword ptr [2*ebp - 1024] -0x62,0xf2,0x67,0x28,0x72,0x14,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vcvtne2ps2bf16 ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064] -0x62,0xf2,0x67,0xaf,0x72,0x51,0x7f - -# CHECK: vcvtne2ps2bf16 ymm2 {k7} {z}, ymm3, dword ptr [edx - 512]{1to8} -0x62,0xf2,0x67,0xbf,0x72,0x52,0x80 - -# CHECK: vcvtne2ps2bf16 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0x62,0xf2,0x67,0x08,0x72,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vcvtne2ps2bf16 xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291] -0x62,0xf2,0x67,0x0f,0x72,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 xmm2, xmm3, dword ptr [eax]{1to4} -0x62,0xf2,0x67,0x18,0x72,0x10 - -# CHECK: vcvtne2ps2bf16 xmm2, xmm3, xmmword ptr [2*ebp - 512] -0x62,0xf2,0x67,0x08,0x72,0x14,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vcvtne2ps2bf16 xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032] -0x62,0xf2,0x67,0x8f,0x72,0x51,0x7f - -# CHECK: vcvtne2ps2bf16 xmm2 {k7} {z}, xmm3, dword ptr [edx - 512]{1to4} -0x62,0xf2,0x67,0x9f,0x72,0x52,0x80 - -# CHECK: vcvtneps2bf16 xmm2, xmm3 -0x62,0xf2,0x7e,0x08,0x72,0xd3 - -# CHECK: vcvtneps2bf16 xmm2 {k7}, xmm3 -0x62,0xf2,0x7e,0x0f,0x72,0xd3 - -# CHECK: vcvtneps2bf16 xmm2 {k7} {z}, xmm3 -0x62,0xf2,0x7e,0x8f,0x72,0xd3 - -# CHECK: vcvtneps2bf16 xmm2, ymm3 -0x62,0xf2,0x7e,0x28,0x72,0xd3 - -# CHECK: vcvtneps2bf16 xmm2 {k7}, ymm3 -0x62,0xf2,0x7e,0x2f,0x72,0xd3 - -# CHECK: vcvtneps2bf16 xmm2 {k7} {z}, ymm3 -0x62,0xf2,0x7e,0xaf,0x72,0xd3 - -# CHECK: vcvtneps2bf16 xmm2, xmmword ptr [esp + 8*esi + 268435456] -0x62,0xf2,0x7e,0x08,0x72,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vcvtneps2bf16 xmm2 {k7}, xmmword ptr [edi + 4*eax + 291] -0x62,0xf2,0x7e,0x0f,0x72,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vcvtneps2bf16 xmm2, dword ptr [eax]{1to4} -0x62,0xf2,0x7e,0x18,0x72,0x10 - -# CHECK: vcvtneps2bf16 xmm2, xmmword ptr [2*ebp - 512] -0x62,0xf2,0x7e,0x08,0x72,0x14,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vcvtneps2bf16 xmm2 {k7} {z}, xmmword ptr [ecx + 2032] -0x62,0xf2,0x7e,0x8f,0x72,0x51,0x7f - -# CHECK: vcvtneps2bf16 xmm2 {k7} {z}, dword ptr [edx - 512]{1to4} -0x62,0xf2,0x7e,0x9f,0x72,0x52,0x80 - -# CHECK: vcvtneps2bf16 xmm2, dword ptr [eax]{1to8} -0x62,0xf2,0x7e,0x38,0x72,0x10 - -# CHECK: vcvtneps2bf16 xmm2, ymmword ptr [2*ebp - 1024] -0x62,0xf2,0x7e,0x28,0x72,0x14,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vcvtneps2bf16 xmm2 {k7} {z}, ymmword ptr [ecx + 4064] -0x62,0xf2,0x7e,0xaf,0x72,0x51,0x7f - -# CHECK: vcvtneps2bf16 xmm2 {k7} {z}, dword ptr [edx - 512]{1to8} -0x62,0xf2,0x7e,0xbf,0x72,0x52,0x80 - -# CHECK: vdpbf16ps ymm2, ymm3, ymm4 -0x62,0xf2,0x66,0x28,0x52,0xd4 - -# CHECK: vdpbf16ps ymm2 {k7}, ymm3, ymm4 -0x62,0xf2,0x66,0x2f,0x52,0xd4 - -# CHECK: vdpbf16ps ymm2 {k7} {z}, ymm3, ymm4 -0x62,0xf2,0x66,0xaf,0x52,0xd4 - -# CHECK: vdpbf16ps xmm2, xmm3, xmm4 -0x62,0xf2,0x66,0x08,0x52,0xd4 - -# CHECK: vdpbf16ps xmm2 {k7}, xmm3, xmm4 -0x62,0xf2,0x66,0x0f,0x52,0xd4 - -# CHECK: vdpbf16ps xmm2 {k7} {z}, xmm3, xmm4 -0x62,0xf2,0x66,0x8f,0x52,0xd4 - -# CHECK: vdpbf16ps ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456] -0x62,0xf2,0x66,0x28,0x52,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vdpbf16ps ymm2 {k7}, ymm3, ymmword ptr [edi + 4*eax + 291] -0x62,0xf2,0x66,0x2f,0x52,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vdpbf16ps ymm2, ymm3, dword ptr [eax]{1to8} -0x62,0xf2,0x66,0x38,0x52,0x10 - -# CHECK: vdpbf16ps ymm2, ymm3, ymmword ptr [2*ebp - 1024] -0x62,0xf2,0x66,0x28,0x52,0x14,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vdpbf16ps ymm2 {k7} {z}, ymm3, ymmword ptr [ecx + 4064] -0x62,0xf2,0x66,0xaf,0x52,0x51,0x7f - -# CHECK: vdpbf16ps ymm2 {k7} {z}, ymm3, dword ptr [edx - 512]{1to8} -0x62,0xf2,0x66,0xbf,0x52,0x52,0x80 - -# CHECK: vdpbf16ps xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0x62,0xf2,0x66,0x08,0x52,0x94,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vdpbf16ps xmm2 {k7}, xmm3, xmmword ptr [edi + 4*eax + 291] -0x62,0xf2,0x66,0x0f,0x52,0x94,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vdpbf16ps xmm2, xmm3, dword ptr [eax]{1to4} -0x62,0xf2,0x66,0x18,0x52,0x10 - -# CHECK: vdpbf16ps xmm2, xmm3, xmmword ptr [2*ebp - 512] -0x62,0xf2,0x66,0x08,0x52,0x14,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vdpbf16ps xmm2 {k7} {z}, xmm3, xmmword ptr [ecx + 2032] -0x62,0xf2,0x66,0x8f,0x52,0x51,0x7f - -# CHECK: vdpbf16ps xmm2 {k7} {z}, xmm3, dword ptr [edx - 512]{1to4} -0x62,0xf2,0x66,0x9f,0x52,0x52,0x80 diff --git a/llvm/test/MC/Disassembler/X86/avx512bitalg.txt b/llvm/test/MC/Disassembler/X86/avx512bitalg.txt new file mode 100644 index 000000000000..13ab5d6dfa84 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/avx512bitalg.txt @@ -0,0 +1,170 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: vpopcntb %zmm23, %zmm21 +# INTEL: vpopcntb zmm21, zmm23 +0x62,0xa2,0x7d,0x48,0x54,0xef + +# ATT: vpopcntw %zmm23, %zmm21 +# INTEL: vpopcntw zmm21, zmm23 +0x62,0xa2,0xfd,0x48,0x54,0xef + +# ATT: vpopcntb %zmm3, %zmm1 {%k2} +# INTEL: vpopcntb zmm1 {k2}, zmm3 +0x62,0xf2,0x7d,0x4a,0x54,0xcb + +# ATT: vpopcntw %zmm3, %zmm1 {%k2} +# INTEL: vpopcntw zmm1 {k2}, zmm3 +0x62,0xf2,0xfd,0x4a,0x54,0xcb + +# ATT: vpopcntb (%rcx), %zmm1 +# INTEL: vpopcntb zmm1, zmmword ptr [rcx] +0x62,0xf2,0x7d,0x48,0x54,0x09 + +# ATT: vpopcntb -256(%rsp), %zmm1 +# INTEL: vpopcntb zmm1, zmmword ptr [rsp - 256] +0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0xfc + +# ATT: vpopcntb 256(%rsp), %zmm1 +# INTEL: vpopcntb zmm1, zmmword ptr [rsp + 256] +0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0x04 + +# ATT: vpopcntb 268435456(%rcx,%r14,8), %zmm1 +# INTEL: vpopcntb zmm1, zmmword ptr [rcx + 8*r14 + 268435456] +0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0x10 + +# ATT: vpopcntb -536870912(%rcx,%r14,8), %zmm1 +# INTEL: vpopcntb zmm1, zmmword ptr [rcx + 8*r14 - 536870912] +0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0xe0 + +# ATT: vpopcntb -536870910(%rcx,%r14,8), %zmm1 +# INTEL: vpopcntb zmm1, zmmword ptr [rcx + 8*r14 - 536870910] +0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x02,0x00,0x00,0xe0 + +# ATT: vpopcntw (%rcx), %zmm1 +# INTEL: vpopcntw zmm1, zmmword ptr [rcx] +0x62,0xf2,0xfd,0x48,0x54,0x09 + +# ATT: vpopcntw -256(%rsp), %zmm1 +# INTEL: vpopcntw zmm1, zmmword ptr [rsp - 256] +0x62,0xf2,0xfd,0x48,0x54,0x4c,0x24,0xfc + +# ATT: vpopcntw 256(%rsp), %zmm1 +# INTEL: vpopcntw zmm1, zmmword ptr [rsp + 256] +0x62,0xf2,0xfd,0x48,0x54,0x4c,0x24,0x04 + +# ATT: vpopcntw 268435456(%rcx,%r14,8), %zmm1 +# INTEL: vpopcntw zmm1, zmmword ptr [rcx + 8*r14 + 268435456] +0x62,0xb2,0xfd,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0x10 + +# ATT: vpopcntw -536870912(%rcx,%r14,8), %zmm1 +# INTEL: vpopcntw zmm1, zmmword ptr [rcx + 8*r14 - 536870912] +0x62,0xb2,0xfd,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0xe0 + +# ATT: vpopcntw -536870910(%rcx,%r14,8), %zmm1 +# INTEL: vpopcntw zmm1, zmmword ptr [rcx + 8*r14 - 536870910] +0x62,0xb2,0xfd,0x48,0x54,0x8c,0xf1,0x02,0x00,0x00,0xe0 + +# ATT: vpopcntb (%rcx), %zmm21 {%k2} +# INTEL: vpopcntb zmm21 {k2}, zmmword ptr [rcx] +0x62,0xe2,0x7d,0x4a,0x54,0x29 + +# ATT: vpopcntb -256(%rsp), %zmm21 {%k2} +# INTEL: vpopcntb zmm21 {k2}, zmmword ptr [rsp - 256] +0x62,0xe2,0x7d,0x4a,0x54,0x6c,0x24,0xfc + +# ATT: vpopcntb 256(%rsp), %zmm21 {%k2} +# INTEL: vpopcntb zmm21 {k2}, zmmword ptr [rsp + 256] +0x62,0xe2,0x7d,0x4a,0x54,0x6c,0x24,0x04 + +# ATT: vpopcntb 268435456(%rcx,%r14,8), %zmm21 {%k2} +# INTEL: vpopcntb zmm21 {k2}, zmmword ptr [rcx + 8*r14 + 268435456] +0x62,0xa2,0x7d,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0x10 + +# ATT: vpopcntb -536870912(%rcx,%r14,8), %zmm21 {%k2} +# INTEL: vpopcntb zmm21 {k2}, zmmword ptr [rcx + 8*r14 - 536870912] +0x62,0xa2,0x7d,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0xe0 + +# ATT: vpopcntb -536870910(%rcx,%r14,8), %zmm21 {%k2} +# INTEL: vpopcntb zmm21 {k2}, zmmword ptr [rcx + 8*r14 - 536870910] +0x62,0xa2,0x7d,0x4a,0x54,0xac,0xf1,0x02,0x00,0x00,0xe0 + +# ATT: vpopcntw (%rcx), %zmm21 {%k2} +# INTEL: vpopcntw zmm21 {k2}, zmmword ptr [rcx] +0x62,0xe2,0xfd,0x4a,0x54,0x29 + +# ATT: vpopcntw -256(%rsp), %zmm21 {%k2} +# INTEL: vpopcntw zmm21 {k2}, zmmword ptr [rsp - 256] +0x62,0xe2,0xfd,0x4a,0x54,0x6c,0x24,0xfc + +# ATT: vpopcntw 256(%rsp), %zmm21 {%k2} +# INTEL: vpopcntw zmm21 {k2}, zmmword ptr [rsp + 256] +0x62,0xe2,0xfd,0x4a,0x54,0x6c,0x24,0x04 + +# ATT: vpopcntw 268435456(%rcx,%r14,8), %zmm21 {%k2} +# INTEL: vpopcntw zmm21 {k2}, zmmword ptr [rcx + 8*r14 + 268435456] +0x62,0xa2,0xfd,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0x10 + +# ATT: vpopcntw -536870912(%rcx,%r14,8), %zmm21 {%k2} +# INTEL: vpopcntw zmm21 {k2}, zmmword ptr [rcx + 8*r14 - 536870912] +0x62,0xa2,0xfd,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0xe0 + +# ATT: vpopcntw -536870910(%rcx,%r14,8), %zmm21 {%k2} +# INTEL: vpopcntw zmm21 {k2}, zmmword ptr [rcx + 8*r14 - 536870910] +0x62,0xa2,0xfd,0x4a,0x54,0xac,0xf1,0x02,0x00,0x00,0xe0 + +# ATT: vpshufbitqmb %zmm2, %zmm23, %k1 +# INTEL: vpshufbitqmb k1, zmm23, zmm2 +0x62,0xf2,0x45,0x40,0x8f,0xca + +# ATT: vpshufbitqmb %zmm2, %zmm23, %k1 {%k2} +# INTEL: vpshufbitqmb k1 {k2}, zmm23, zmm2 +0x62,0xf2,0x45,0x42,0x8f,0xca + +# ATT: vpshufbitqmb (%rcx), %zmm23, %k1 +# INTEL: vpshufbitqmb k1, zmm23, zmmword ptr [rcx] +0x62,0xf2,0x45,0x40,0x8f,0x09 + +# ATT: vpshufbitqmb -256(%rsp), %zmm23, %k1 +# INTEL: vpshufbitqmb k1, zmm23, zmmword ptr [rsp - 256] +0x62,0xf2,0x45,0x40,0x8f,0x4c,0x24,0xfc + +# ATT: vpshufbitqmb 256(%rsp), %zmm23, %k1 +# INTEL: vpshufbitqmb k1, zmm23, zmmword ptr [rsp + 256] +0x62,0xf2,0x45,0x40,0x8f,0x4c,0x24,0x04 + +# ATT: vpshufbitqmb 268435456(%rcx,%r14,8), %zmm23, %k1 +# INTEL: vpshufbitqmb k1, zmm23, zmmword ptr [rcx + 8*r14 + 268435456] +0x62,0xb2,0x45,0x40,0x8f,0x8c,0xf1,0x00,0x00,0x00,0x10 + +# ATT: vpshufbitqmb -536870912(%rcx,%r14,8), %zmm23, %k1 +# INTEL: vpshufbitqmb k1, zmm23, zmmword ptr [rcx + 8*r14 - 536870912] +0x62,0xb2,0x45,0x40,0x8f,0x8c,0xf1,0x00,0x00,0x00,0xe0 + +# ATT: vpshufbitqmb -536870910(%rcx,%r14,8), %zmm23, %k1 +# INTEL: vpshufbitqmb k1, zmm23, zmmword ptr [rcx + 8*r14 - 536870910] +0x62,0xb2,0x45,0x40,0x8f,0x8c,0xf1,0x02,0x00,0x00,0xe0 + +# ATT: vpshufbitqmb (%rcx), %zmm23, %k1 {%k2} +# INTEL: vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rcx] +0x62,0xf2,0x45,0x42,0x8f,0x09 + +# ATT: vpshufbitqmb -256(%rsp), %zmm23, %k1 {%k2} +# INTEL: vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rsp - 256] +0x62,0xf2,0x45,0x42,0x8f,0x4c,0x24,0xfc + +# ATT: vpshufbitqmb 256(%rsp), %zmm23, %k1 {%k2} +# INTEL: vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rsp + 256] +0x62,0xf2,0x45,0x42,0x8f,0x4c,0x24,0x04 + +# ATT: vpshufbitqmb 268435456(%rcx,%r14,8), %zmm23, %k1 {%k2} +# INTEL: vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rcx + 8*r14 + 268435456] +0x62,0xb2,0x45,0x42,0x8f,0x8c,0xf1,0x00,0x00,0x00,0x10 + +# ATT: vpshufbitqmb -536870912(%rcx,%r14,8), %zmm23, %k1 {%k2} +# INTEL: vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rcx + 8*r14 - 536870912] +0x62,0xb2,0x45,0x42,0x8f,0x8c,0xf1,0x00,0x00,0x00,0xe0 + +# ATT: vpshufbitqmb -536870910(%rcx,%r14,8), %zmm23, %k1 {%k2} +# INTEL: vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rcx + 8*r14 - 536870910] +0x62,0xb2,0x45,0x42,0x8f,0x8c,0xf1,0x02,0x00,0x00,0xe0 diff --git a/llvm/test/MC/Disassembler/X86/avx512dq_vl.txt b/llvm/test/MC/Disassembler/X86/avx512dq_vl.txt new file mode 100644 index 000000000000..8cd9ed8e46e2 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/avx512dq_vl.txt @@ -0,0 +1,198 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: vcvtps2qq 128(%rcx), %xmm2 {%k2} {z} +# INTEL: vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x8a,0x7b,0x51,0x10 + +# ATT: vcvtps2qq 128(%rcx), %xmm2 {%k2} +# INTEL: vcvtps2qq xmm2 {k2}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x0a,0x7b,0x51,0x10 + +# ATT: vcvtps2qq 128(%rcx), %xmm2 +# INTEL: vcvtps2qq xmm2, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x08,0x7b,0x51,0x10 + +# ATT: vcvttps2qq 128(%rcx), %xmm1 {%k2} {z} +# INTEL: vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x8a,0x7a,0x49,0x10 + +# ATT: vcvttps2qq 128(%rcx), %xmm1 {%k2} +# INTEL: vcvttps2qq xmm1 {k2}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x0a,0x7a,0x49,0x10 + +# ATT: vcvttps2qq 128(%rcx), %xmm1 +# INTEL: vcvttps2qq xmm1, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x08,0x7a,0x49,0x10 + +# ATT: vcvtps2uqq 128(%rcx), %xmm1 {%k2} {z} +# INTEL: vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x8a,0x79,0x49,0x10 + +# ATT: vcvtps2uqq 128(%rcx), %xmm1 {%k2} +# INTEL: vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x0a,0x79,0x49,0x10 + +# ATT: vcvtps2uqq 128(%rcx), %xmm1 +# INTEL: vcvtps2uqq xmm1, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x08,0x79,0x49,0x10 + +# ATT: vcvttps2uqq 128(%rcx), %xmm1 {%k2} {z} +# INTEL: vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x8a,0x78,0x49,0x10 + +# ATT: vcvttps2uqq 128(%rcx), %xmm1 {%k2} +# INTEL: vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10 + +# ATT: vcvttps2uqq 128(%rcx), %xmm1 +# INTEL: vcvttps2uqq xmm1, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x08,0x78,0x49,0x10 + +# ATT: vcvtps2qq 128(%rcx), %xmm2 {%k2} {z} +# INTEL: vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x8a,0x7b,0x51,0x10 + +# ATT: vcvtps2qq 128(%rcx), %xmm2 {%k2} +# INTEL: vcvtps2qq xmm2 {k2}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x0a,0x7b,0x51,0x10 + +# ATT: vcvtps2qq 128(%rcx), %xmm2 +# INTEL: vcvtps2qq xmm2, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x08,0x7b,0x51,0x10 + +# ATT: vcvttps2qq 128(%rcx), %xmm1 {%k2} {z} +# INTEL: vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x8a,0x7a,0x49,0x10 + +# ATT: vcvttps2qq 128(%rcx), %xmm1 {%k2} +# INTEL: vcvttps2qq xmm1 {k2}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x0a,0x7a,0x49,0x10 + +# ATT: vcvttps2qq 128(%rcx), %xmm1 +# INTEL: vcvttps2qq xmm1, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x08,0x7a,0x49,0x10 + +# ATT: vcvtps2uqq 128(%rcx), %xmm1 {%k2} {z} +# INTEL: vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x8a,0x79,0x49,0x10 + +# ATT: vcvtps2uqq 128(%rcx), %xmm1 {%k2} +# INTEL: vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x0a,0x79,0x49,0x10 + +# ATT: vcvtps2uqq 128(%rcx), %xmm1 +# INTEL: vcvtps2uqq xmm1, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x08,0x79,0x49,0x10 + +# ATT: vcvttps2uqq 128(%rcx), %xmm1 {%k2} {z} +# INTEL: vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x8a,0x78,0x49,0x10 + +# ATT: vcvttps2uqq 128(%rcx), %xmm1 {%k2} +# INTEL: vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10 + +# ATT: vcvttps2uqq 128(%rcx), %xmm1 +# INTEL: vcvttps2uqq xmm1, qword ptr [rcx + 128] +0x62,0xf1,0x7d,0x08,0x78,0x49,0x10 + +# ATT: vfpclasspd $171, %xmm18, %k2 +# INTEL: vfpclasspd k2, xmm18, 171 +0x62,0xb3,0xfd,0x08,0x66,0xd2,0xab + +# ATT: vfpclasspd $171, %xmm18, %k2 {%k7} +# INTEL: vfpclasspd k2 {k7}, xmm18, 171 +0x62,0xb3,0xfd,0x0f,0x66,0xd2,0xab + +# ATT: vfpclasspdx $123, (%rcx), %k2 +# INTEL: vfpclasspd k2, xmmword ptr [rcx], 123 +0x62,0xf3,0xfd,0x08,0x66,0x11,0x7b + +# ATT: vfpclasspdx $123, (%rcx), %k2 {%k7} +# INTEL: vfpclasspd k2 {k7}, xmmword ptr [rcx], 123 +0x62,0xf3,0xfd,0x0f,0x66,0x11,0x7b + +# ATT: vfpclasspd $123, (%rcx){1to2}, %k2 +# INTEL: vfpclasspd k2, qword ptr [rcx]{1to2}, 123 +0x62,0xf3,0xfd,0x18,0x66,0x11,0x7b + +# ATT: vfpclasspd $123, (%rcx){1to2}, %k2 {%k7} +# INTEL: vfpclasspd k2 {k7}, qword ptr [rcx]{1to2}, 123 +0x62,0xf3,0xfd,0x1f,0x66,0x11,0x7b + +# ATT: vfpclassps $171, %xmm18, %k2 +# INTEL: vfpclassps k2, xmm18, 171 +0x62,0xb3,0x7d,0x08,0x66,0xd2,0xab + +# ATT: vfpclassps $171, %xmm18, %k2 {%k7} +# INTEL: vfpclassps k2 {k7}, xmm18, 171 +0x62,0xb3,0x7d,0x0f,0x66,0xd2,0xab + +# ATT: vfpclasspsx $123, (%rcx), %k2 +# INTEL: vfpclassps k2, xmmword ptr [rcx], 123 +0x62,0xf3,0x7d,0x08,0x66,0x11,0x7b + +# ATT: vfpclasspsx $123, (%rcx), %k2 {%k7} +# INTEL: vfpclassps k2 {k7}, xmmword ptr [rcx], 123 +0x62,0xf3,0x7d,0x0f,0x66,0x11,0x7b + +# ATT: vfpclassps $123, (%rcx){1to4}, %k2 +# INTEL: vfpclassps k2, dword ptr [rcx]{1to4}, 123 +0x62,0xf3,0x7d,0x18,0x66,0x11,0x7b + +# ATT: vfpclassps $123, (%rcx){1to4}, %k2 {%k7} +# INTEL: vfpclassps k2 {k7}, dword ptr [rcx]{1to4}, 123 +0x62,0xf3,0x7d,0x1f,0x66,0x11,0x7b + +# ATT: vfpclasspd $171, %ymm18, %k2 +# INTEL: vfpclasspd k2, ymm18, 171 +0x62,0xb3,0xfd,0x28,0x66,0xd2,0xab + +# ATT: vfpclasspd $171, %ymm18, %k2 {%k7} +# INTEL: vfpclasspd k2 {k7}, ymm18, 171 +0x62,0xb3,0xfd,0x2f,0x66,0xd2,0xab + +# ATT: vfpclasspdy $123, (%rcx), %k2 +# INTEL: vfpclasspd k2, ymmword ptr [rcx], 123 +0x62,0xf3,0xfd,0x28,0x66,0x11,0x7b + +# ATT: vfpclasspdy $123, (%rcx), %k2 {%k7} +# INTEL: vfpclasspd k2 {k7}, ymmword ptr [rcx], 123 +0x62,0xf3,0xfd,0x2f,0x66,0x11,0x7b + +# ATT: vfpclasspd $123, (%rcx){1to4}, %k2 +# INTEL: vfpclasspd k2, qword ptr [rcx]{1to4}, 123 +0x62,0xf3,0xfd,0x38,0x66,0x11,0x7b + +# ATT: vfpclasspd $123, (%rcx){1to4}, %k2 {%k7} +# INTEL: vfpclasspd k2 {k7}, qword ptr [rcx]{1to4}, 123 +0x62,0xf3,0xfd,0x3f,0x66,0x11,0x7b + +# ATT: vfpclassps $171, %ymm18, %k2 +# INTEL: vfpclassps k2, ymm18, 171 +0x62,0xb3,0x7d,0x28,0x66,0xd2,0xab + +# ATT: vfpclassps $171, %ymm18, %k2 {%k7} +# INTEL: vfpclassps k2 {k7}, ymm18, 171 +0x62,0xb3,0x7d,0x2f,0x66,0xd2,0xab + +# ATT: vfpclasspsy $123, (%rcx), %k2 +# INTEL: vfpclassps k2, ymmword ptr [rcx], 123 +0x62,0xf3,0x7d,0x28,0x66,0x11,0x7b + +# ATT: vfpclasspsy $123, (%rcx), %k2 {%k7} +# INTEL: vfpclassps k2 {k7}, ymmword ptr [rcx], 123 +0x62,0xf3,0x7d,0x2f,0x66,0x11,0x7b + +# ATT: vfpclassps $123, (%rcx){1to8}, %k2 +# INTEL: vfpclassps k2, dword ptr [rcx]{1to8}, 123 +0x62,0xf3,0x7d,0x38,0x66,0x11,0x7b + +# ATT: vfpclassps $123, (%rcx){1to8}, %k2 {%k7} +# INTEL: vfpclassps k2 {k7}, dword ptr [rcx]{1to8}, 123 +0x62,0xf3,0x7d,0x3f,0x66,0x11,0x7b + +# ATT: vcvttps2uqq 128(%ecx), %xmm1 {%k2} +# INTEL: vcvttps2uqq xmm1 {k2}, qword ptr [ecx + 128] +0x67,0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10 diff --git a/llvm/test/MC/Disassembler/X86/avx512vbmi.txt b/llvm/test/MC/Disassembler/X86/avx512vbmi.txt new file mode 100644 index 000000000000..5bec7c639377 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/avx512vbmi.txt @@ -0,0 +1,542 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: vpermb %xmm28, %xmm29, %xmm30 {%k7} +# INTEL: vpermb xmm30 {k7}, xmm29, xmm28 +0x62,0x02,0x15,0x07,0x8d,0xf4 + +# ATT: vpermb %xmm28, %xmm29, %xmm30 {%k7} {z} +# INTEL: vpermb xmm30 {k7} {z}, xmm29, xmm28 +0x62,0x02,0x15,0x87,0x8d,0xf4 + +# ATT: vpermb (%rcx), %xmm29, %xmm30 +# INTEL: vpermb xmm30, xmm29, xmmword ptr [rcx] +0x62,0x62,0x15,0x00,0x8d,0x31 + +# ATT: vpermb 291(%rax,%r14,8), %xmm29, %xmm30 +# INTEL: vpermb xmm30, xmm29, xmmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x15,0x00,0x8d,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vpermb 2032(%rdx), %xmm29, %xmm30 +# INTEL: vpermb xmm30, xmm29, xmmword ptr [rdx + 2032] +0x62,0x62,0x15,0x00,0x8d,0x72,0x7f + +# ATT: vpermb 2048(%rdx), %xmm29, %xmm30 +# INTEL: vpermb xmm30, xmm29, xmmword ptr [rdx + 2048] +0x62,0x62,0x15,0x00,0x8d,0xb2,0x00,0x08,0x00,0x00 + +# ATT: vpermb -2048(%rdx), %xmm29, %xmm30 +# INTEL: vpermb xmm30, xmm29, xmmword ptr [rdx - 2048] +0x62,0x62,0x15,0x00,0x8d,0x72,0x80 + +# ATT: vpermb -2064(%rdx), %xmm29, %xmm30 +# INTEL: vpermb xmm30, xmm29, xmmword ptr [rdx - 2064] +0x62,0x62,0x15,0x00,0x8d,0xb2,0xf0,0xf7,0xff,0xff + +# ATT: vpermb %ymm28, %ymm29, %ymm30 +# INTEL: vpermb ymm30, ymm29, ymm28 +0x62,0x02,0x15,0x20,0x8d,0xf4 + +# ATT: vpermb %ymm28, %ymm29, %ymm30 {%k7} +# INTEL: vpermb ymm30 {k7}, ymm29, ymm28 +0x62,0x02,0x15,0x27,0x8d,0xf4 + +# ATT: vpermb %ymm28, %ymm29, %ymm30 {%k7} {z} +# INTEL: vpermb ymm30 {k7} {z}, ymm29, ymm28 +0x62,0x02,0x15,0xa7,0x8d,0xf4 + +# ATT: vpermb (%rcx), %ymm29, %ymm30 +# INTEL: vpermb ymm30, ymm29, ymmword ptr [rcx] +0x62,0x62,0x15,0x20,0x8d,0x31 + +# ATT: vpermb 291(%rax,%r14,8), %ymm29, %ymm30 +# INTEL: vpermb ymm30, ymm29, ymmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x15,0x20,0x8d,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vpermb 4064(%rdx), %ymm29, %ymm30 +# INTEL: vpermb ymm30, ymm29, ymmword ptr [rdx + 4064] +0x62,0x62,0x15,0x20,0x8d,0x72,0x7f + +# ATT: vpermb 4096(%rdx), %ymm29, %ymm30 +# INTEL: vpermb ymm30, ymm29, ymmword ptr [rdx + 4096] +0x62,0x62,0x15,0x20,0x8d,0xb2,0x00,0x10,0x00,0x00 + +# ATT: vpermb -4096(%rdx), %ymm29, %ymm30 +# INTEL: vpermb ymm30, ymm29, ymmword ptr [rdx - 4096] +0x62,0x62,0x15,0x20,0x8d,0x72,0x80 + +# ATT: vpermb -4128(%rdx), %ymm29, %ymm30 +# INTEL: vpermb ymm30, ymm29, ymmword ptr [rdx - 4128] +0x62,0x62,0x15,0x20,0x8d,0xb2,0xe0,0xef,0xff,0xff + +# ATT: vpermb %xmm28, %xmm29, %xmm30 +# INTEL: vpermb xmm30, xmm29, xmm28 +0x62,0x02,0x15,0x00,0x8d,0xf4 + +# ATT: vpermb 4660(%rax,%r14,8), %xmm29, %xmm30 +# INTEL: vpermb xmm30, xmm29, xmmword ptr [rax + 8*r14 + 4660] +0x62,0x22,0x15,0x00,0x8d,0xb4,0xf0,0x34,0x12,0x00,0x00 + +# ATT: vpermb 4660(%rax,%r14,8), %ymm29, %ymm30 +# INTEL: vpermb ymm30, ymm29, ymmword ptr [rax + 8*r14 + 4660] +0x62,0x22,0x15,0x20,0x8d,0xb4,0xf0,0x34,0x12,0x00,0x00 + +# ATT: vpermb %zmm28, %zmm29, %zmm30 +# INTEL: vpermb zmm30, zmm29, zmm28 +0x62,0x02,0x15,0x40,0x8d,0xf4 + +# ATT: vpermb %zmm28, %zmm29, %zmm30 {%k7} +# INTEL: vpermb zmm30 {k7}, zmm29, zmm28 +0x62,0x02,0x15,0x47,0x8d,0xf4 + +# ATT: vpermb %zmm28, %zmm29, %zmm30 {%k7} {z} +# INTEL: vpermb zmm30 {k7} {z}, zmm29, zmm28 +0x62,0x02,0x15,0xc7,0x8d,0xf4 + +# ATT: vpermb (%rcx), %zmm29, %zmm30 +# INTEL: vpermb zmm30, zmm29, zmmword ptr [rcx] +0x62,0x62,0x15,0x40,0x8d,0x31 + +# ATT: vpermb 291(%rax,%r14,8), %zmm29, %zmm30 +# INTEL: vpermb zmm30, zmm29, zmmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x15,0x40,0x8d,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vpermb 8128(%rdx), %zmm29, %zmm30 +# INTEL: vpermb zmm30, zmm29, zmmword ptr [rdx + 8128] +0x62,0x62,0x15,0x40,0x8d,0x72,0x7f + +# ATT: vpermb 8192(%rdx), %zmm29, %zmm30 +# INTEL: vpermb zmm30, zmm29, zmmword ptr [rdx + 8192] +0x62,0x62,0x15,0x40,0x8d,0xb2,0x00,0x20,0x00,0x00 + +# ATT: vpermb -8192(%rdx), %zmm29, %zmm30 +# INTEL: vpermb zmm30, zmm29, zmmword ptr [rdx - 8192] +0x62,0x62,0x15,0x40,0x8d,0x72,0x80 + +# ATT: vpermb -8256(%rdx), %zmm29, %zmm30 +# INTEL: vpermb zmm30, zmm29, zmmword ptr [rdx - 8256] +0x62,0x62,0x15,0x40,0x8d,0xb2,0xc0,0xdf,0xff,0xff + +# ATT: vpermb 4660(%rax,%r14,8), %zmm29, %zmm30 +# INTEL: vpermb zmm30, zmm29, zmmword ptr [rax + 8*r14 + 4660] +0x62,0x22,0x15,0x40,0x8d,0xb4,0xf0,0x34,0x12,0x00,0x00 + +# ATT: vpermt2b %xmm28, %xmm29, %xmm30 +# INTEL: vpermt2b xmm30, xmm29, xmm28 +0x62,0x02,0x15,0x00,0x7d,0xf4 + +# ATT: vpermt2b %xmm28, %xmm29, %xmm30 {%k7} +# INTEL: vpermt2b xmm30 {k7}, xmm29, xmm28 +0x62,0x02,0x15,0x07,0x7d,0xf4 + +# ATT: vpermt2b %xmm28, %xmm29, %xmm30 {%k7} {z} +# INTEL: vpermt2b xmm30 {k7} {z}, xmm29, xmm28 +0x62,0x02,0x15,0x87,0x7d,0xf4 + +# ATT: vpermt2b (%rcx), %xmm29, %xmm30 +# INTEL: vpermt2b xmm30, xmm29, xmmword ptr [rcx] +0x62,0x62,0x15,0x00,0x7d,0x31 + +# ATT: vpermt2b 291(%rax,%r14,8), %xmm29, %xmm30 +# INTEL: vpermt2b xmm30, xmm29, xmmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x15,0x00,0x7d,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vpermt2b 2032(%rdx), %xmm29, %xmm30 +# INTEL: vpermt2b xmm30, xmm29, xmmword ptr [rdx + 2032] +0x62,0x62,0x15,0x00,0x7d,0x72,0x7f + +# ATT: vpermt2b 2048(%rdx), %xmm29, %xmm30 +# INTEL: vpermt2b xmm30, xmm29, xmmword ptr [rdx + 2048] +0x62,0x62,0x15,0x00,0x7d,0xb2,0x00,0x08,0x00,0x00 + +# ATT: vpermt2b -2048(%rdx), %xmm29, %xmm30 +# INTEL: vpermt2b xmm30, xmm29, xmmword ptr [rdx - 2048] +0x62,0x62,0x15,0x00,0x7d,0x72,0x80 + +# ATT: vpermt2b -2064(%rdx), %xmm29, %xmm30 +# INTEL: vpermt2b xmm30, xmm29, xmmword ptr [rdx - 2064] +0x62,0x62,0x15,0x00,0x7d,0xb2,0xf0,0xf7,0xff,0xff + +# ATT: vpermt2b %ymm28, %ymm29, %ymm30 +# INTEL: vpermt2b ymm30, ymm29, ymm28 +0x62,0x02,0x15,0x20,0x7d,0xf4 + +# ATT: vpermt2b %ymm28, %ymm29, %ymm30 {%k7} +# INTEL: vpermt2b ymm30 {k7}, ymm29, ymm28 +0x62,0x02,0x15,0x27,0x7d,0xf4 + +# ATT: vpermt2b %ymm28, %ymm29, %ymm30 {%k7} {z} +# INTEL: vpermt2b ymm30 {k7} {z}, ymm29, ymm28 +0x62,0x02,0x15,0xa7,0x7d,0xf4 + +# ATT: vpermt2b (%rcx), %ymm29, %ymm30 +# INTEL: vpermt2b ymm30, ymm29, ymmword ptr [rcx] +0x62,0x62,0x15,0x20,0x7d,0x31 + +# ATT: vpermt2b 291(%rax,%r14,8), %ymm29, %ymm30 +# INTEL: vpermt2b ymm30, ymm29, ymmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x15,0x20,0x7d,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vpermt2b 4064(%rdx), %ymm29, %ymm30 +# INTEL: vpermt2b ymm30, ymm29, ymmword ptr [rdx + 4064] +0x62,0x62,0x15,0x20,0x7d,0x72,0x7f + +# ATT: vpermt2b 4096(%rdx), %ymm29, %ymm30 +# INTEL: vpermt2b ymm30, ymm29, ymmword ptr [rdx + 4096] +0x62,0x62,0x15,0x20,0x7d,0xb2,0x00,0x10,0x00,0x00 + +# ATT: vpermt2b -4096(%rdx), %ymm29, %ymm30 +# INTEL: vpermt2b ymm30, ymm29, ymmword ptr [rdx - 4096] +0x62,0x62,0x15,0x20,0x7d,0x72,0x80 + +# ATT: vpermt2b -4128(%rdx), %ymm29, %ymm30 +# INTEL: vpermt2b ymm30, ymm29, ymmword ptr [rdx - 4128] +0x62,0x62,0x15,0x20,0x7d,0xb2,0xe0,0xef,0xff,0xff + +# ATT: vpermt2b 4660(%rax,%r14,8), %xmm29, %xmm30 +# INTEL: vpermt2b xmm30, xmm29, xmmword ptr [rax + 8*r14 + 4660] +0x62,0x22,0x15,0x00,0x7d,0xb4,0xf0,0x34,0x12,0x00,0x00 + +# ATT: vpermt2b 4660(%rax,%r14,8), %ymm29, %ymm30 +# INTEL: vpermt2b ymm30, ymm29, ymmword ptr [rax + 8*r14 + 4660] +0x62,0x22,0x15,0x20,0x7d,0xb4,0xf0,0x34,0x12,0x00,0x00 + +# ATT: vpermt2b %zmm28, %zmm29, %zmm30 +# INTEL: vpermt2b zmm30, zmm29, zmm28 +0x62,0x02,0x15,0x40,0x7d,0xf4 + +# ATT: vpermt2b %zmm28, %zmm29, %zmm30 {%k7} +# INTEL: vpermt2b zmm30 {k7}, zmm29, zmm28 +0x62,0x02,0x15,0x47,0x7d,0xf4 + +# ATT: vpermt2b %zmm28, %zmm29, %zmm30 {%k7} {z} +# INTEL: vpermt2b zmm30 {k7} {z}, zmm29, zmm28 +0x62,0x02,0x15,0xc7,0x7d,0xf4 + +# ATT: vpermt2b (%rcx), %zmm29, %zmm30 +# INTEL: vpermt2b zmm30, zmm29, zmmword ptr [rcx] +0x62,0x62,0x15,0x40,0x7d,0x31 + +# ATT: vpermt2b 291(%rax,%r14,8), %zmm29, %zmm30 +# INTEL: vpermt2b zmm30, zmm29, zmmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x15,0x40,0x7d,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vpermt2b 8128(%rdx), %zmm29, %zmm30 +# INTEL: vpermt2b zmm30, zmm29, zmmword ptr [rdx + 8128] +0x62,0x62,0x15,0x40,0x7d,0x72,0x7f + +# ATT: vpermt2b 8192(%rdx), %zmm29, %zmm30 +# INTEL: vpermt2b zmm30, zmm29, zmmword ptr [rdx + 8192] +0x62,0x62,0x15,0x40,0x7d,0xb2,0x00,0x20,0x00,0x00 + +# ATT: vpermt2b -8192(%rdx), %zmm29, %zmm30 +# INTEL: vpermt2b zmm30, zmm29, zmmword ptr [rdx - 8192] +0x62,0x62,0x15,0x40,0x7d,0x72,0x80 + +# ATT: vpermt2b -8256(%rdx), %zmm29, %zmm30 +# INTEL: vpermt2b zmm30, zmm29, zmmword ptr [rdx - 8256] +0x62,0x62,0x15,0x40,0x7d,0xb2,0xc0,0xdf,0xff,0xff + +# ATT: vpermt2b 4660(%rax,%r14,8), %zmm29, %zmm30 +# INTEL: vpermt2b zmm30, zmm29, zmmword ptr [rax + 8*r14 + 4660] +0x62,0x22,0x15,0x40,0x7d,0xb4,0xf0,0x34,0x12,0x00,0x00 + +# ATT: vpermi2b %xmm28, %xmm29, %xmm30 +# INTEL: vpermi2b xmm30, xmm29, xmm28 +0x62,0x02,0x15,0x00,0x75,0xf4 + +# ATT: vpermi2b %xmm28, %xmm29, %xmm30 {%k7} +# INTEL: vpermi2b xmm30 {k7}, xmm29, xmm28 +0x62,0x02,0x15,0x07,0x75,0xf4 + +# ATT: vpermi2b %xmm28, %xmm29, %xmm30 {%k7} {z} +# INTEL: vpermi2b xmm30 {k7} {z}, xmm29, xmm28 +0x62,0x02,0x15,0x87,0x75,0xf4 + +# ATT: vpermi2b (%rcx), %xmm29, %xmm30 +# INTEL: vpermi2b xmm30, xmm29, xmmword ptr [rcx] +0x62,0x62,0x15,0x00,0x75,0x31 + +# ATT: vpermi2b 291(%rax,%r14,8), %xmm29, %xmm30 +# INTEL: vpermi2b xmm30, xmm29, xmmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x15,0x00,0x75,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vpermi2b 2032(%rdx), %xmm29, %xmm30 +# INTEL: vpermi2b xmm30, xmm29, xmmword ptr [rdx + 2032] +0x62,0x62,0x15,0x00,0x75,0x72,0x7f + +# ATT: vpermi2b 2048(%rdx), %xmm29, %xmm30 +# INTEL: vpermi2b xmm30, xmm29, xmmword ptr [rdx + 2048] +0x62,0x62,0x15,0x00,0x75,0xb2,0x00,0x08,0x00,0x00 + +# ATT: vpermi2b -2048(%rdx), %xmm29, %xmm30 +# INTEL: vpermi2b xmm30, xmm29, xmmword ptr [rdx - 2048] +0x62,0x62,0x15,0x00,0x75,0x72,0x80 + +# ATT: vpermi2b -2064(%rdx), %xmm29, %xmm30 +# INTEL: vpermi2b xmm30, xmm29, xmmword ptr [rdx - 2064] +0x62,0x62,0x15,0x00,0x75,0xb2,0xf0,0xf7,0xff,0xff + +# ATT: vpermi2b %ymm28, %ymm29, %ymm30 +# INTEL: vpermi2b ymm30, ymm29, ymm28 +0x62,0x02,0x15,0x20,0x75,0xf4 + +# ATT: vpermi2b %ymm28, %ymm29, %ymm30 {%k7} +# INTEL: vpermi2b ymm30 {k7}, ymm29, ymm28 +0x62,0x02,0x15,0x27,0x75,0xf4 + +# ATT: vpermi2b %ymm28, %ymm29, %ymm30 {%k7} {z} +# INTEL: vpermi2b ymm30 {k7} {z}, ymm29, ymm28 +0x62,0x02,0x15,0xa7,0x75,0xf4 + +# ATT: vpermi2b (%rcx), %ymm29, %ymm30 +# INTEL: vpermi2b ymm30, ymm29, ymmword ptr [rcx] +0x62,0x62,0x15,0x20,0x75,0x31 + +# ATT: vpermi2b 291(%rax,%r14,8), %ymm29, %ymm30 +# INTEL: vpermi2b ymm30, ymm29, ymmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x15,0x20,0x75,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vpermi2b 4064(%rdx), %ymm29, %ymm30 +# INTEL: vpermi2b ymm30, ymm29, ymmword ptr [rdx + 4064] +0x62,0x62,0x15,0x20,0x75,0x72,0x7f + +# ATT: vpermi2b 4096(%rdx), %ymm29, %ymm30 +# INTEL: vpermi2b ymm30, ymm29, ymmword ptr [rdx + 4096] +0x62,0x62,0x15,0x20,0x75,0xb2,0x00,0x10,0x00,0x00 + +# ATT: vpermi2b -4096(%rdx), %ymm29, %ymm30 +# INTEL: vpermi2b ymm30, ymm29, ymmword ptr [rdx - 4096] +0x62,0x62,0x15,0x20,0x75,0x72,0x80 + +# ATT: vpermi2b -4128(%rdx), %ymm29, %ymm30 +# INTEL: vpermi2b ymm30, ymm29, ymmword ptr [rdx - 4128] +0x62,0x62,0x15,0x20,0x75,0xb2,0xe0,0xef,0xff,0xff + +# ATT: vpermi2b 4660(%rax,%r14,8), %xmm29, %xmm30 +# INTEL: vpermi2b xmm30, xmm29, xmmword ptr [rax + 8*r14 + 4660] +0x62,0x22,0x15,0x00,0x75,0xb4,0xf0,0x34,0x12,0x00,0x00 + +# ATT: vpermi2b 4660(%rax,%r14,8), %ymm29, %ymm30 +# INTEL: vpermi2b ymm30, ymm29, ymmword ptr [rax + 8*r14 + 4660] +0x62,0x22,0x15,0x20,0x75,0xb4,0xf0,0x34,0x12,0x00,0x00 + +# ATT: vpermi2b %zmm28, %zmm29, %zmm30 +# INTEL: vpermi2b zmm30, zmm29, zmm28 +0x62,0x02,0x15,0x40,0x75,0xf4 + +# ATT: vpermi2b %zmm28, %zmm29, %zmm30 {%k7} +# INTEL: vpermi2b zmm30 {k7}, zmm29, zmm28 +0x62,0x02,0x15,0x47,0x75,0xf4 + +# ATT: vpermi2b %zmm28, %zmm29, %zmm30 {%k7} {z} +# INTEL: vpermi2b zmm30 {k7} {z}, zmm29, zmm28 +0x62,0x02,0x15,0xc7,0x75,0xf4 + +# ATT: vpermi2b (%rcx), %zmm29, %zmm30 +# INTEL: vpermi2b zmm30, zmm29, zmmword ptr [rcx] +0x62,0x62,0x15,0x40,0x75,0x31 + +# ATT: vpermi2b 291(%rax,%r14,8), %zmm29, %zmm30 +# INTEL: vpermi2b zmm30, zmm29, zmmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x15,0x40,0x75,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vpermi2b 8128(%rdx), %zmm29, %zmm30 +# INTEL: vpermi2b zmm30, zmm29, zmmword ptr [rdx + 8128] +0x62,0x62,0x15,0x40,0x75,0x72,0x7f + +# ATT: vpermi2b 8192(%rdx), %zmm29, %zmm30 +# INTEL: vpermi2b zmm30, zmm29, zmmword ptr [rdx + 8192] +0x62,0x62,0x15,0x40,0x75,0xb2,0x00,0x20,0x00,0x00 + +# ATT: vpermi2b -8192(%rdx), %zmm29, %zmm30 +# INTEL: vpermi2b zmm30, zmm29, zmmword ptr [rdx - 8192] +0x62,0x62,0x15,0x40,0x75,0x72,0x80 + +# ATT: vpermi2b -8256(%rdx), %zmm29, %zmm30 +# INTEL: vpermi2b zmm30, zmm29, zmmword ptr [rdx - 8256] +0x62,0x62,0x15,0x40,0x75,0xb2,0xc0,0xdf,0xff,0xff + +# ATT: vpermi2b 4660(%rax,%r14,8), %zmm29, %zmm30 +# INTEL: vpermi2b zmm30, zmm29, zmmword ptr [rax + 8*r14 + 4660] +0x62,0x22,0x15,0x40,0x75,0xb4,0xf0,0x34,0x12,0x00,0x00 + +# ATT: vpmultishiftqb %xmm28, %xmm29, %xmm30 +# INTEL: vpmultishiftqb xmm30, xmm29, xmm28 +0x62,0x02,0x95,0x00,0x83,0xf4 + +# ATT: vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7} +# INTEL: vpmultishiftqb xmm30 {k7}, xmm29, xmm28 +0x62,0x02,0x95,0x07,0x83,0xf4 + +# ATT: vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7} {z} +# INTEL: vpmultishiftqb xmm30 {k7} {z}, xmm29, xmm28 +0x62,0x02,0x95,0x87,0x83,0xf4 + +# ATT: vpmultishiftqb (%rcx), %xmm29, %xmm30 +# INTEL: vpmultishiftqb xmm30, xmm29, xmmword ptr [rcx] +0x62,0x62,0x95,0x00,0x83,0x31 + +# ATT: vpmultishiftqb 291(%rax,%r14,8), %xmm29, %xmm30 +# INTEL: vpmultishiftqb xmm30, xmm29, xmmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x95,0x00,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vpmultishiftqb (%rcx){1to2}, %xmm29, %xmm30 +# INTEL: vpmultishiftqb xmm30, xmm29, qword ptr [rcx]{1to2} +0x62,0x62,0x95,0x10,0x83,0x31 + +# ATT: vpmultishiftqb 2032(%rdx), %xmm29, %xmm30 +# INTEL: vpmultishiftqb xmm30, xmm29, xmmword ptr [rdx + 2032] +0x62,0x62,0x95,0x00,0x83,0x72,0x7f + +# ATT: vpmultishiftqb 2048(%rdx), %xmm29, %xmm30 +# INTEL: vpmultishiftqb xmm30, xmm29, xmmword ptr [rdx + 2048] +0x62,0x62,0x95,0x00,0x83,0xb2,0x00,0x08,0x00,0x00 + +# ATT: vpmultishiftqb -2048(%rdx), %xmm29, %xmm30 +# INTEL: vpmultishiftqb xmm30, xmm29, xmmword ptr [rdx - 2048] +0x62,0x62,0x95,0x00,0x83,0x72,0x80 + +# ATT: vpmultishiftqb -2064(%rdx), %xmm29, %xmm30 +# INTEL: vpmultishiftqb xmm30, xmm29, xmmword ptr [rdx - 2064] +0x62,0x62,0x95,0x00,0x83,0xb2,0xf0,0xf7,0xff,0xff + +# ATT: vpmultishiftqb 1016(%rdx){1to2}, %xmm29, %xmm30 +# INTEL: vpmultishiftqb xmm30, xmm29, qword ptr [rdx + 1016]{1to2} +0x62,0x62,0x95,0x10,0x83,0x72,0x7f + +# ATT: vpmultishiftqb 1024(%rdx){1to2}, %xmm29, %xmm30 +# INTEL: vpmultishiftqb xmm30, xmm29, qword ptr [rdx + 1024]{1to2} +0x62,0x62,0x95,0x10,0x83,0xb2,0x00,0x04,0x00,0x00 + +# ATT: vpmultishiftqb -1024(%rdx){1to2}, %xmm29, %xmm30 +# INTEL: vpmultishiftqb xmm30, xmm29, qword ptr [rdx - 1024]{1to2} +0x62,0x62,0x95,0x10,0x83,0x72,0x80 + +# ATT: vpmultishiftqb -1032(%rdx){1to2}, %xmm29, %xmm30 +# INTEL: vpmultishiftqb xmm30, xmm29, qword ptr [rdx - 1032]{1to2} +0x62,0x62,0x95,0x10,0x83,0xb2,0xf8,0xfb,0xff,0xff + +# ATT: vpmultishiftqb %ymm28, %ymm29, %ymm30 +# INTEL: vpmultishiftqb ymm30, ymm29, ymm28 +0x62,0x02,0x95,0x20,0x83,0xf4 + +# ATT: vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7} +# INTEL: vpmultishiftqb ymm30 {k7}, ymm29, ymm28 +0x62,0x02,0x95,0x27,0x83,0xf4 + +# ATT: vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7} {z} +# INTEL: vpmultishiftqb ymm30 {k7} {z}, ymm29, ymm28 +0x62,0x02,0x95,0xa7,0x83,0xf4 + +# ATT: vpmultishiftqb (%rcx), %ymm29, %ymm30 +# INTEL: vpmultishiftqb ymm30, ymm29, ymmword ptr [rcx] +0x62,0x62,0x95,0x20,0x83,0x31 + +# ATT: vpmultishiftqb 291(%rax,%r14,8), %ymm29, %ymm30 +# INTEL: vpmultishiftqb ymm30, ymm29, ymmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x95,0x20,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vpmultishiftqb (%rcx){1to4}, %ymm29, %ymm30 +# INTEL: vpmultishiftqb ymm30, ymm29, qword ptr [rcx]{1to4} +0x62,0x62,0x95,0x30,0x83,0x31 + +# ATT: vpmultishiftqb 4064(%rdx), %ymm29, %ymm30 +# INTEL: vpmultishiftqb ymm30, ymm29, ymmword ptr [rdx + 4064] +0x62,0x62,0x95,0x20,0x83,0x72,0x7f + +# ATT: vpmultishiftqb 4096(%rdx), %ymm29, %ymm30 +# INTEL: vpmultishiftqb ymm30, ymm29, ymmword ptr [rdx + 4096] +0x62,0x62,0x95,0x20,0x83,0xb2,0x00,0x10,0x00,0x00 + +# ATT: vpmultishiftqb -4096(%rdx), %ymm29, %ymm30 +# INTEL: vpmultishiftqb ymm30, ymm29, ymmword ptr [rdx - 4096] +0x62,0x62,0x95,0x20,0x83,0x72,0x80 + +# ATT: vpmultishiftqb -4128(%rdx), %ymm29, %ymm30 +# INTEL: vpmultishiftqb ymm30, ymm29, ymmword ptr [rdx - 4128] +0x62,0x62,0x95,0x20,0x83,0xb2,0xe0,0xef,0xff,0xff + +# ATT: vpmultishiftqb 1016(%rdx){1to4}, %ymm29, %ymm30 +# INTEL: vpmultishiftqb ymm30, ymm29, qword ptr [rdx + 1016]{1to4} +0x62,0x62,0x95,0x30,0x83,0x72,0x7f + +# ATT: vpmultishiftqb 1024(%rdx){1to4}, %ymm29, %ymm30 +# INTEL: vpmultishiftqb ymm30, ymm29, qword ptr [rdx + 1024]{1to4} +0x62,0x62,0x95,0x30,0x83,0xb2,0x00,0x04,0x00,0x00 + +# ATT: vpmultishiftqb -1024(%rdx){1to4}, %ymm29, %ymm30 +# INTEL: vpmultishiftqb ymm30, ymm29, qword ptr [rdx - 1024]{1to4} +0x62,0x62,0x95,0x30,0x83,0x72,0x80 + +# ATT: vpmultishiftqb -1032(%rdx){1to4}, %ymm29, %ymm30 +# INTEL: vpmultishiftqb ymm30, ymm29, qword ptr [rdx - 1032]{1to4} +0x62,0x62,0x95,0x30,0x83,0xb2,0xf8,0xfb,0xff,0xff + +# ATT: vpmultishiftqb 4660(%rax,%r14,8), %xmm29, %xmm30 +# INTEL: vpmultishiftqb xmm30, xmm29, xmmword ptr [rax + 8*r14 + 4660] +0x62,0x22,0x95,0x00,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00 + +# ATT: vpmultishiftqb 4660(%rax,%r14,8), %ymm29, %ymm30 +# INTEL: vpmultishiftqb ymm30, ymm29, ymmword ptr [rax + 8*r14 + 4660] +0x62,0x22,0x95,0x20,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00 + +# ATT: vpmultishiftqb %zmm28, %zmm29, %zmm30 +# INTEL: vpmultishiftqb zmm30, zmm29, zmm28 +0x62,0x02,0x95,0x40,0x83,0xf4 + +# ATT: vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7} +# INTEL: vpmultishiftqb zmm30 {k7}, zmm29, zmm28 +0x62,0x02,0x95,0x47,0x83,0xf4 + +# ATT: vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7} {z} +# INTEL: vpmultishiftqb zmm30 {k7} {z}, zmm29, zmm28 +0x62,0x02,0x95,0xc7,0x83,0xf4 + +# ATT: vpmultishiftqb (%rcx), %zmm29, %zmm30 +# INTEL: vpmultishiftqb zmm30, zmm29, zmmword ptr [rcx] +0x62,0x62,0x95,0x40,0x83,0x31 + +# ATT: vpmultishiftqb 291(%rax,%r14,8), %zmm29, %zmm30 +# INTEL: vpmultishiftqb zmm30, zmm29, zmmword ptr [rax + 8*r14 + 291] +0x62,0x22,0x95,0x40,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00 + +# ATT: vpmultishiftqb (%rcx){1to8}, %zmm29, %zmm30 +# INTEL: vpmultishiftqb zmm30, zmm29, qword ptr [rcx]{1to8} +0x62,0x62,0x95,0x50,0x83,0x31 + +# ATT: vpmultishiftqb 8128(%rdx), %zmm29, %zmm30 +# INTEL: vpmultishiftqb zmm30, zmm29, zmmword ptr [rdx + 8128] +0x62,0x62,0x95,0x40,0x83,0x72,0x7f + +# ATT: vpmultishiftqb 8192(%rdx), %zmm29, %zmm30 +# INTEL: vpmultishiftqb zmm30, zmm29, zmmword ptr [rdx + 8192] +0x62,0x62,0x95,0x40,0x83,0xb2,0x00,0x20,0x00,0x00 + +# ATT: vpmultishiftqb -8192(%rdx), %zmm29, %zmm30 +# INTEL: vpmultishiftqb zmm30, zmm29, zmmword ptr [rdx - 8192] +0x62,0x62,0x95,0x40,0x83,0x72,0x80 + +# ATT: vpmultishiftqb -8256(%rdx), %zmm29, %zmm30 +# INTEL: vpmultishiftqb zmm30, zmm29, zmmword ptr [rdx - 8256] +0x62,0x62,0x95,0x40,0x83,0xb2,0xc0,0xdf,0xff,0xff + +# ATT: vpmultishiftqb 1016(%rdx){1to8}, %zmm29, %zmm30 +# INTEL: vpmultishiftqb zmm30, zmm29, qword ptr [rdx + 1016]{1to8} +0x62,0x62,0x95,0x50,0x83,0x72,0x7f + +# ATT: vpmultishiftqb 1024(%rdx){1to8}, %zmm29, %zmm30 +# INTEL: vpmultishiftqb zmm30, zmm29, qword ptr [rdx + 1024]{1to8} +0x62,0x62,0x95,0x50,0x83,0xb2,0x00,0x04,0x00,0x00 + +# ATT: vpmultishiftqb -1024(%rdx){1to8}, %zmm29, %zmm30 +# INTEL: vpmultishiftqb zmm30, zmm29, qword ptr [rdx - 1024]{1to8} +0x62,0x62,0x95,0x50,0x83,0x72,0x80 + +# ATT: vpmultishiftqb -1032(%rdx){1to8}, %zmm29, %zmm30 +# INTEL: vpmultishiftqb zmm30, zmm29, qword ptr [rdx - 1032]{1to8} +0x62,0x62,0x95,0x50,0x83,0xb2,0xf8,0xfb,0xff,0xff + +# ATT: vpmultishiftqb 4660(%rax,%r14,8), %zmm29, %zmm30 +# INTEL: vpmultishiftqb zmm30, zmm29, zmmword ptr [rax + 8*r14 + 4660] +0x62,0x22,0x95,0x40,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/X86/avx512vp2intersect-32.txt b/llvm/test/MC/Disassembler/X86/avx512vp2intersect-32.txt new file mode 100644 index 000000000000..cc1e3104e6ce --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/avx512vp2intersect-32.txt @@ -0,0 +1,226 @@ +# RUN: llvm-mc -triple i386 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple i386 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: vp2intersectq %zmm2, %zmm1, %k0 +# INTEL: vp2intersectq k0, zmm1, zmm2 +0x62,0xf2,0xf7,0x48,0x68,0xc2 + +# ATT: vp2intersectq (%edi), %zmm1, %k0 +# INTEL: vp2intersectq k0, zmm1, zmmword ptr [edi] +0x62,0xf2,0xf7,0x48,0x68,0x07 + +# ATT: vp2intersectq (%edi){1to8}, %zmm1, %k0 +# INTEL: vp2intersectq k0, zmm1, qword ptr [edi]{1to8} +0x62,0xf2,0xf7,0x58,0x68,0x07 + +# ATT: vp2intersectq %zmm2, %zmm1, %k0 +# INTEL: vp2intersectq k0, zmm1, zmm2 +0x62,0xf2,0xf7,0x48,0x68,0xc2 + +# ATT: vp2intersectq (%edi), %zmm1, %k0 +# INTEL: vp2intersectq k0, zmm1, zmmword ptr [edi] +0x62,0xf2,0xf7,0x48,0x68,0x07 + +# ATT: vp2intersectq (%edi){1to8}, %zmm1, %k0 +# INTEL: vp2intersectq k0, zmm1, qword ptr [edi]{1to8} +0x62,0xf2,0xf7,0x58,0x68,0x07 + +# ATT: vp2intersectq %zmm7, %zmm4, %k6 +# INTEL: vp2intersectq k6, zmm4, zmm7 +0x62,0xf2,0xdf,0x48,0x68,0xf7 + +# ATT: vp2intersectq (%esi), %zmm4, %k6 +# INTEL: vp2intersectq k6, zmm4, zmmword ptr [esi] +0x62,0xf2,0xdf,0x48,0x68,0x36 + +# ATT: vp2intersectq (%esi){1to8}, %zmm4, %k6 +# INTEL: vp2intersectq k6, zmm4, qword ptr [esi]{1to8} +0x62,0xf2,0xdf,0x58,0x68,0x36 + +# ATT: vp2intersectq %zmm7, %zmm4, %k6 +# INTEL: vp2intersectq k6, zmm4, zmm7 +0x62,0xf2,0xdf,0x48,0x68,0xf7 + +# ATT: vp2intersectq (%esi), %zmm4, %k6 +# INTEL: vp2intersectq k6, zmm4, zmmword ptr [esi] +0x62,0xf2,0xdf,0x48,0x68,0x36 + +# ATT: vp2intersectq (%esi){1to8}, %zmm4, %k6 +# INTEL: vp2intersectq k6, zmm4, qword ptr [esi]{1to8} +0x62,0xf2,0xdf,0x58,0x68,0x36 + +# ATT: vp2intersectq %ymm2, %ymm1, %k0 +# INTEL: vp2intersectq k0, ymm1, ymm2 +0x62,0xf2,0xf7,0x28,0x68,0xc2 + +# ATT: vp2intersectq (%edi), %ymm1, %k0 +# INTEL: vp2intersectq k0, ymm1, ymmword ptr [edi] +0x62,0xf2,0xf7,0x28,0x68,0x07 + +# ATT: vp2intersectq (%edi){1to4}, %ymm1, %k0 +# INTEL: vp2intersectq k0, ymm1, qword ptr [edi]{1to4} +0x62,0xf2,0xf7,0x38,0x68,0x07 + +# ATT: vp2intersectq %ymm2, %ymm1, %k0 +# INTEL: vp2intersectq k0, ymm1, ymm2 +0x62,0xf2,0xf7,0x28,0x68,0xc2 + +# ATT: vp2intersectq (%edi), %ymm1, %k0 +# INTEL: vp2intersectq k0, ymm1, ymmword ptr [edi] +0x62,0xf2,0xf7,0x28,0x68,0x07 + +# ATT: vp2intersectq (%edi){1to4}, %ymm1, %k0 +# INTEL: vp2intersectq k0, ymm1, qword ptr [edi]{1to4} +0x62,0xf2,0xf7,0x38,0x68,0x07 + +# ATT: vp2intersectq %ymm7, %ymm4, %k6 +# INTEL: vp2intersectq k6, ymm4, ymm7 +0x62,0xf2,0xdf,0x28,0x68,0xf7 + +# ATT: vp2intersectq (%esi), %ymm4, %k6 +# INTEL: vp2intersectq k6, ymm4, ymmword ptr [esi] +0x62,0xf2,0xdf,0x28,0x68,0x36 + +# ATT: vp2intersectq (%esi){1to4}, %ymm4, %k6 +# INTEL: vp2intersectq k6, ymm4, qword ptr [esi]{1to4} +0x62,0xf2,0xdf,0x38,0x68,0x36 + +# ATT: vp2intersectq %ymm7, %ymm4, %k6 +# INTEL: vp2intersectq k6, ymm4, ymm7 +0x62,0xf2,0xdf,0x28,0x68,0xf7 + +# ATT: vp2intersectq (%esi), %ymm4, %k6 +# INTEL: vp2intersectq k6, ymm4, ymmword ptr [esi] +0x62,0xf2,0xdf,0x28,0x68,0x36 + +# ATT: vp2intersectq %xmm2, %xmm1, %k0 +# INTEL: vp2intersectq k0, xmm1, xmm2 +0x62,0xf2,0xf7,0x08,0x68,0xc2 + +# ATT: vp2intersectq (%edi), %xmm1, %k0 +# INTEL: vp2intersectq k0, xmm1, xmmword ptr [edi] +0x62,0xf2,0xf7,0x08,0x68,0x07 + +# ATT: vp2intersectq (%edi){1to2}, %xmm1, %k0 +# INTEL: vp2intersectq k0, xmm1, qword ptr [edi]{1to2} +0x62,0xf2,0xf7,0x18,0x68,0x07 + +# ATT: vp2intersectq %xmm2, %xmm1, %k0 +# INTEL: vp2intersectq k0, xmm1, xmm2 +0x62,0xf2,0xf7,0x08,0x68,0xc2 + +# ATT: vp2intersectq (%edi), %xmm1, %k0 +# INTEL: vp2intersectq k0, xmm1, xmmword ptr [edi] +0x62,0xf2,0xf7,0x08,0x68,0x07 + +# ATT: vp2intersectq %xmm7, %xmm4, %k6 +# INTEL: vp2intersectq k6, xmm4, xmm7 +0x62,0xf2,0xdf,0x08,0x68,0xf7 + +# ATT: vp2intersectq (%esi), %xmm4, %k6 +# INTEL: vp2intersectq k6, xmm4, xmmword ptr [esi] +0x62,0xf2,0xdf,0x08,0x68,0x36 + +# ATT: vp2intersectq %xmm7, %xmm4, %k6 +# INTEL: vp2intersectq k6, xmm4, xmm7 +0x62,0xf2,0xdf,0x08,0x68,0xf7 + +# ATT: vp2intersectq (%esi), %xmm4, %k6 +# INTEL: vp2intersectq k6, xmm4, xmmword ptr [esi] +0x62,0xf2,0xdf,0x08,0x68,0x36 + +# ATT: vp2intersectd %zmm2, %zmm1, %k0 +# INTEL: vp2intersectd k0, zmm1, zmm2 +0x62,0xf2,0x77,0x48,0x68,0xc2 + +# ATT: vp2intersectd (%edi), %zmm1, %k0 +# INTEL: vp2intersectd k0, zmm1, zmmword ptr [edi] +0x62,0xf2,0x77,0x48,0x68,0x07 + +# ATT: vp2intersectd %zmm2, %zmm1, %k0 +# INTEL: vp2intersectd k0, zmm1, zmm2 +0x62,0xf2,0x77,0x48,0x68,0xc2 + +# ATT: vp2intersectd (%edi), %zmm1, %k0 +# INTEL: vp2intersectd k0, zmm1, zmmword ptr [edi] +0x62,0xf2,0x77,0x48,0x68,0x07 + +# ATT: vp2intersectd %zmm7, %zmm4, %k6 +# INTEL: vp2intersectd k6, zmm4, zmm7 +0x62,0xf2,0x5f,0x48,0x68,0xf7 + +# ATT: vp2intersectd (%esi), %zmm4, %k6 +# INTEL: vp2intersectd k6, zmm4, zmmword ptr [esi] +0x62,0xf2,0x5f,0x48,0x68,0x36 + +# ATT: vp2intersectd %zmm7, %zmm4, %k6 +# INTEL: vp2intersectd k6, zmm4, zmm7 +0x62,0xf2,0x5f,0x48,0x68,0xf7 + +# ATT: vp2intersectd (%esi), %zmm4, %k6 +# INTEL: vp2intersectd k6, zmm4, zmmword ptr [esi] +0x62,0xf2,0x5f,0x48,0x68,0x36 + +# ATT: vp2intersectd %ymm2, %ymm1, %k0 +# INTEL: vp2intersectd k0, ymm1, ymm2 +0x62,0xf2,0x77,0x28,0x68,0xc2 + +# ATT: vp2intersectd (%edi), %ymm1, %k0 +# INTEL: vp2intersectd k0, ymm1, ymmword ptr [edi] +0x62,0xf2,0x77,0x28,0x68,0x07 + +# ATT: vp2intersectd %ymm2, %ymm1, %k0 +# INTEL: vp2intersectd k0, ymm1, ymm2 +0x62,0xf2,0x77,0x28,0x68,0xc2 + +# ATT: vp2intersectd (%edi), %ymm1, %k0 +# INTEL: vp2intersectd k0, ymm1, ymmword ptr [edi] +0x62,0xf2,0x77,0x28,0x68,0x07 + +# ATT: vp2intersectd %ymm7, %ymm4, %k6 +# INTEL: vp2intersectd k6, ymm4, ymm7 +0x62,0xf2,0x5f,0x28,0x68,0xf7 + +# ATT: vp2intersectd (%esi), %ymm4, %k6 +# INTEL: vp2intersectd k6, ymm4, ymmword ptr [esi] +0x62,0xf2,0x5f,0x28,0x68,0x36 + +# ATT: vp2intersectd %ymm7, %ymm4, %k6 +# INTEL: vp2intersectd k6, ymm4, ymm7 +0x62,0xf2,0x5f,0x28,0x68,0xf7 + +# ATT: vp2intersectd (%esi), %ymm4, %k6 +# INTEL: vp2intersectd k6, ymm4, ymmword ptr [esi] +0x62,0xf2,0x5f,0x28,0x68,0x36 + +# ATT: vp2intersectd %xmm2, %xmm1, %k0 +# INTEL: vp2intersectd k0, xmm1, xmm2 +0x62,0xf2,0x77,0x08,0x68,0xc2 + +# ATT: vp2intersectd (%edi), %xmm1, %k0 +# INTEL: vp2intersectd k0, xmm1, xmmword ptr [edi] +0x62,0xf2,0x77,0x08,0x68,0x07 + +# ATT: vp2intersectd %xmm2, %xmm1, %k0 +# INTEL: vp2intersectd k0, xmm1, xmm2 +0x62,0xf2,0x77,0x08,0x68,0xc2 + +# ATT: vp2intersectd (%edi), %xmm1, %k0 +# INTEL: vp2intersectd k0, xmm1, xmmword ptr [edi] +0x62,0xf2,0x77,0x08,0x68,0x07 + +# ATT: vp2intersectd %xmm7, %xmm4, %k6 +# INTEL: vp2intersectd k6, xmm4, xmm7 +0x62,0xf2,0x5f,0x08,0x68,0xf7 + +# ATT: vp2intersectd (%esi), %xmm4, %k6 +# INTEL: vp2intersectd k6, xmm4, xmmword ptr [esi] +0x62,0xf2,0x5f,0x08,0x68,0x36 + +# ATT: vp2intersectd %xmm7, %xmm4, %k6 +# INTEL: vp2intersectd k6, xmm4, xmm7 +0x62,0xf2,0x5f,0x08,0x68,0xf7 + +# ATT: vp2intersectd (%esi), %xmm4, %k6 +# INTEL: vp2intersectd k6, xmm4, xmmword ptr [esi] +0x62,0xf2,0x5f,0x08,0x68,0x36 diff --git a/llvm/test/MC/Disassembler/X86/avx512vp2intersect-64.txt b/llvm/test/MC/Disassembler/X86/avx512vp2intersect-64.txt new file mode 100644 index 000000000000..e528140586ef --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/avx512vp2intersect-64.txt @@ -0,0 +1,226 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: vp2intersectq %zmm2, %zmm1, %k0 +# INTEL: vp2intersectq k0, zmm1, zmm2 +0x62,0xf2,0xf7,0x48,0x68,0xc2 + +# ATT: vp2intersectq (%rdi), %zmm1, %k0 +# INTEL: vp2intersectq k0, zmm1, zmmword ptr [rdi] +0x62,0xf2,0xf7,0x48,0x68,0x07 + +# ATT: vp2intersectq (%rdi){1to8}, %zmm1, %k0 +# INTEL: vp2intersectq k0, zmm1, qword ptr [rdi]{1to8} +0x62,0xf2,0xf7,0x58,0x68,0x07 + +# ATT: vp2intersectq %zmm2, %zmm1, %k0 +# INTEL: vp2intersectq k0, zmm1, zmm2 +0x62,0xf2,0xf7,0x48,0x68,0xc2 + +# ATT: vp2intersectq (%rdi), %zmm1, %k0 +# INTEL: vp2intersectq k0, zmm1, zmmword ptr [rdi] +0x62,0xf2,0xf7,0x48,0x68,0x07 + +# ATT: vp2intersectq (%rdi){1to8}, %zmm1, %k0 +# INTEL: vp2intersectq k0, zmm1, qword ptr [rdi]{1to8} +0x62,0xf2,0xf7,0x58,0x68,0x07 + +# ATT: vp2intersectq %zmm7, %zmm9, %k6 +# INTEL: vp2intersectq k6, zmm9, zmm7 +0x62,0xf2,0xb7,0x48,0x68,0xf7 + +# ATT: vp2intersectq (%rsi), %zmm9, %k6 +# INTEL: vp2intersectq k6, zmm9, zmmword ptr [rsi] +0x62,0xf2,0xb7,0x48,0x68,0x36 + +# ATT: vp2intersectq (%rsi){1to8}, %zmm9, %k6 +# INTEL: vp2intersectq k6, zmm9, qword ptr [rsi]{1to8} +0x62,0xf2,0xb7,0x58,0x68,0x36 + +# ATT: vp2intersectq %zmm7, %zmm9, %k6 +# INTEL: vp2intersectq k6, zmm9, zmm7 +0x62,0xf2,0xb7,0x48,0x68,0xf7 + +# ATT: vp2intersectq (%rsi), %zmm9, %k6 +# INTEL: vp2intersectq k6, zmm9, zmmword ptr [rsi] +0x62,0xf2,0xb7,0x48,0x68,0x36 + +# ATT: vp2intersectq (%rsi){1to8}, %zmm9, %k6 +# INTEL: vp2intersectq k6, zmm9, qword ptr [rsi]{1to8} +0x62,0xf2,0xb7,0x58,0x68,0x36 + +# ATT: vp2intersectq %ymm2, %ymm1, %k0 +# INTEL: vp2intersectq k0, ymm1, ymm2 +0x62,0xf2,0xf7,0x28,0x68,0xc2 + +# ATT: vp2intersectq (%rdi), %ymm1, %k0 +# INTEL: vp2intersectq k0, ymm1, ymmword ptr [rdi] +0x62,0xf2,0xf7,0x28,0x68,0x07 + +# ATT: vp2intersectq (%rdi){1to4}, %ymm1, %k0 +# INTEL: vp2intersectq k0, ymm1, qword ptr [rdi]{1to4} +0x62,0xf2,0xf7,0x38,0x68,0x07 + +# ATT: vp2intersectq %ymm2, %ymm1, %k0 +# INTEL: vp2intersectq k0, ymm1, ymm2 +0x62,0xf2,0xf7,0x28,0x68,0xc2 + +# ATT: vp2intersectq (%rdi), %ymm1, %k0 +# INTEL: vp2intersectq k0, ymm1, ymmword ptr [rdi] +0x62,0xf2,0xf7,0x28,0x68,0x07 + +# ATT: vp2intersectq (%rdi){1to4}, %ymm1, %k0 +# INTEL: vp2intersectq k0, ymm1, qword ptr [rdi]{1to4} +0x62,0xf2,0xf7,0x38,0x68,0x07 + +# ATT: vp2intersectq %ymm7, %ymm9, %k6 +# INTEL: vp2intersectq k6, ymm9, ymm7 +0x62,0xf2,0xb7,0x28,0x68,0xf7 + +# ATT: vp2intersectq (%rsi), %ymm9, %k6 +# INTEL: vp2intersectq k6, ymm9, ymmword ptr [rsi] +0x62,0xf2,0xb7,0x28,0x68,0x36 + +# ATT: vp2intersectq (%rsi){1to4}, %ymm9, %k6 +# INTEL: vp2intersectq k6, ymm9, qword ptr [rsi]{1to4} +0x62,0xf2,0xb7,0x38,0x68,0x36 + +# ATT: vp2intersectq %ymm7, %ymm9, %k6 +# INTEL: vp2intersectq k6, ymm9, ymm7 +0x62,0xf2,0xb7,0x28,0x68,0xf7 + +# ATT: vp2intersectq (%rsi), %ymm9, %k6 +# INTEL: vp2intersectq k6, ymm9, ymmword ptr [rsi] +0x62,0xf2,0xb7,0x28,0x68,0x36 + +# ATT: vp2intersectq %xmm2, %xmm1, %k0 +# INTEL: vp2intersectq k0, xmm1, xmm2 +0x62,0xf2,0xf7,0x08,0x68,0xc2 + +# ATT: vp2intersectq (%rdi), %xmm1, %k0 +# INTEL: vp2intersectq k0, xmm1, xmmword ptr [rdi] +0x62,0xf2,0xf7,0x08,0x68,0x07 + +# ATT: vp2intersectq (%rdi){1to2}, %xmm1, %k0 +# INTEL: vp2intersectq k0, xmm1, qword ptr [rdi]{1to2} +0x62,0xf2,0xf7,0x18,0x68,0x07 + +# ATT: vp2intersectq %xmm2, %xmm1, %k0 +# INTEL: vp2intersectq k0, xmm1, xmm2 +0x62,0xf2,0xf7,0x08,0x68,0xc2 + +# ATT: vp2intersectq (%rdi), %xmm1, %k0 +# INTEL: vp2intersectq k0, xmm1, xmmword ptr [rdi] +0x62,0xf2,0xf7,0x08,0x68,0x07 + +# ATT: vp2intersectq %xmm7, %xmm9, %k6 +# INTEL: vp2intersectq k6, xmm9, xmm7 +0x62,0xf2,0xb7,0x08,0x68,0xf7 + +# ATT: vp2intersectq (%rsi), %xmm9, %k6 +# INTEL: vp2intersectq k6, xmm9, xmmword ptr [rsi] +0x62,0xf2,0xb7,0x08,0x68,0x36 + +# ATT: vp2intersectq %xmm7, %xmm9, %k6 +# INTEL: vp2intersectq k6, xmm9, xmm7 +0x62,0xf2,0xb7,0x08,0x68,0xf7 + +# ATT: vp2intersectq (%rsi), %xmm9, %k6 +# INTEL: vp2intersectq k6, xmm9, xmmword ptr [rsi] +0x62,0xf2,0xb7,0x08,0x68,0x36 + +# ATT: vp2intersectd %zmm2, %zmm1, %k0 +# INTEL: vp2intersectd k0, zmm1, zmm2 +0x62,0xf2,0x77,0x48,0x68,0xc2 + +# ATT: vp2intersectd (%rdi), %zmm1, %k0 +# INTEL: vp2intersectd k0, zmm1, zmmword ptr [rdi] +0x62,0xf2,0x77,0x48,0x68,0x07 + +# ATT: vp2intersectd %zmm2, %zmm1, %k0 +# INTEL: vp2intersectd k0, zmm1, zmm2 +0x62,0xf2,0x77,0x48,0x68,0xc2 + +# ATT: vp2intersectd (%rdi), %zmm1, %k0 +# INTEL: vp2intersectd k0, zmm1, zmmword ptr [rdi] +0x62,0xf2,0x77,0x48,0x68,0x07 + +# ATT: vp2intersectd %zmm7, %zmm9, %k6 +# INTEL: vp2intersectd k6, zmm9, zmm7 +0x62,0xf2,0x37,0x48,0x68,0xf7 + +# ATT: vp2intersectd (%rsi), %zmm9, %k6 +# INTEL: vp2intersectd k6, zmm9, zmmword ptr [rsi] +0x62,0xf2,0x37,0x48,0x68,0x36 + +# ATT: vp2intersectd %zmm7, %zmm9, %k6 +# INTEL: vp2intersectd k6, zmm9, zmm7 +0x62,0xf2,0x37,0x48,0x68,0xf7 + +# ATT: vp2intersectd (%rsi), %zmm9, %k6 +# INTEL: vp2intersectd k6, zmm9, zmmword ptr [rsi] +0x62,0xf2,0x37,0x48,0x68,0x36 + +# ATT: vp2intersectd %ymm2, %ymm1, %k0 +# INTEL: vp2intersectd k0, ymm1, ymm2 +0x62,0xf2,0x77,0x28,0x68,0xc2 + +# ATT: vp2intersectd (%rdi), %ymm1, %k0 +# INTEL: vp2intersectd k0, ymm1, ymmword ptr [rdi] +0x62,0xf2,0x77,0x28,0x68,0x07 + +# ATT: vp2intersectd %ymm2, %ymm1, %k0 +# INTEL: vp2intersectd k0, ymm1, ymm2 +0x62,0xf2,0x77,0x28,0x68,0xc2 + +# ATT: vp2intersectd (%rdi), %ymm1, %k0 +# INTEL: vp2intersectd k0, ymm1, ymmword ptr [rdi] +0x62,0xf2,0x77,0x28,0x68,0x07 + +# ATT: vp2intersectd %ymm7, %ymm9, %k6 +# INTEL: vp2intersectd k6, ymm9, ymm7 +0x62,0xf2,0x37,0x28,0x68,0xf7 + +# ATT: vp2intersectd (%rsi), %ymm9, %k6 +# INTEL: vp2intersectd k6, ymm9, ymmword ptr [rsi] +0x62,0xf2,0x37,0x28,0x68,0x36 + +# ATT: vp2intersectd %ymm7, %ymm9, %k6 +# INTEL: vp2intersectd k6, ymm9, ymm7 +0x62,0xf2,0x37,0x28,0x68,0xf7 + +# ATT: vp2intersectd (%rsi), %ymm9, %k6 +# INTEL: vp2intersectd k6, ymm9, ymmword ptr [rsi] +0x62,0xf2,0x37,0x28,0x68,0x36 + +# ATT: vp2intersectd %xmm2, %xmm1, %k0 +# INTEL: vp2intersectd k0, xmm1, xmm2 +0x62,0xf2,0x77,0x08,0x68,0xc2 + +# ATT: vp2intersectd (%rdi), %xmm1, %k0 +# INTEL: vp2intersectd k0, xmm1, xmmword ptr [rdi] +0x62,0xf2,0x77,0x08,0x68,0x07 + +# ATT: vp2intersectd %xmm2, %xmm1, %k0 +# INTEL: vp2intersectd k0, xmm1, xmm2 +0x62,0xf2,0x77,0x08,0x68,0xc2 + +# ATT: vp2intersectd (%rdi), %xmm1, %k0 +# INTEL: vp2intersectd k0, xmm1, xmmword ptr [rdi] +0x62,0xf2,0x77,0x08,0x68,0x07 + +# ATT: vp2intersectd %xmm7, %xmm9, %k6 +# INTEL: vp2intersectd k6, xmm9, xmm7 +0x62,0xf2,0x37,0x08,0x68,0xf7 + +# ATT: vp2intersectd (%rsi), %xmm9, %k6 +# INTEL: vp2intersectd k6, xmm9, xmmword ptr [rsi] +0x62,0xf2,0x37,0x08,0x68,0x36 + +# ATT: vp2intersectd %xmm7, %xmm9, %k6 +# INTEL: vp2intersectd k6, xmm9, xmm7 +0x62,0xf2,0x37,0x08,0x68,0xf7 + +# ATT: vp2intersectd (%rsi), %xmm9, %k6 +# INTEL: vp2intersectd k6, xmm9, xmmword ptr [rsi] +0x62,0xf2,0x37,0x08,0x68,0x36 diff --git a/llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-32.txt b/llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-32.txt new file mode 100644 index 000000000000..814a81ad729b --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-32.txt @@ -0,0 +1,114 @@ +# RUN: llvm-mc -triple i386 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple i386 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: vp2intersectd %ymm4, %ymm3, %k6 +# INTEL: vp2intersectd k6, ymm3, ymm4 +0x62,0xf2,0x67,0x28,0x68,0xf4 + +# ATT: vp2intersectd %xmm4, %xmm3, %k6 +# INTEL: vp2intersectd k6, xmm3, xmm4 +0x62,0xf2,0x67,0x08,0x68,0xf4 + +# ATT: vp2intersectd 268435456(%esp,%esi,8), %ymm3, %k6 +# INTEL: vp2intersectd k6, ymm3, ymmword ptr [esp + 8*esi + 268435456] +0x62,0xf2,0x67,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vp2intersectd 291(%edi,%eax,4), %ymm3, %k6 +# INTEL: vp2intersectd k6, ymm3, ymmword ptr [edi + 4*eax + 291] +0x62,0xf2,0x67,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00 + +# ATT: vp2intersectd (%eax){1to8}, %ymm3, %k6 +# INTEL: vp2intersectd k6, ymm3, dword ptr [eax]{1to8} +0x62,0xf2,0x67,0x38,0x68,0x30 + +# ATT: vp2intersectd -1024(,%ebp,2), %ymm3, %k6 +# INTEL: vp2intersectd k6, ymm3, ymmword ptr [2*ebp - 1024] +0x62,0xf2,0x67,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff + +# ATT: vp2intersectd 4064(%ecx), %ymm3, %k6 +# INTEL: vp2intersectd k6, ymm3, ymmword ptr [ecx + 4064] +0x62,0xf2,0x67,0x28,0x68,0x71,0x7f + +# ATT: vp2intersectd -512(%edx){1to8}, %ymm3, %k6 +# INTEL: vp2intersectd k6, ymm3, dword ptr [edx - 512]{1to8} +0x62,0xf2,0x67,0x38,0x68,0x72,0x80 + +# ATT: vp2intersectd 268435456(%esp,%esi,8), %xmm3, %k6 +# INTEL: vp2intersectd k6, xmm3, xmmword ptr [esp + 8*esi + 268435456] +0x62,0xf2,0x67,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vp2intersectd 291(%edi,%eax,4), %xmm3, %k6 +# INTEL: vp2intersectd k6, xmm3, xmmword ptr [edi + 4*eax + 291] +0x62,0xf2,0x67,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00 + +# ATT: vp2intersectd (%eax){1to4}, %xmm3, %k6 +# INTEL: vp2intersectd k6, xmm3, dword ptr [eax]{1to4} +0x62,0xf2,0x67,0x18,0x68,0x30 + +# ATT: vp2intersectd -512(,%ebp,2), %xmm3, %k6 +# INTEL: vp2intersectd k6, xmm3, xmmword ptr [2*ebp - 512] +0x62,0xf2,0x67,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff + +# ATT: vp2intersectd 2032(%ecx), %xmm3, %k6 +# INTEL: vp2intersectd k6, xmm3, xmmword ptr [ecx + 2032] +0x62,0xf2,0x67,0x08,0x68,0x71,0x7f + +# ATT: vp2intersectd -512(%edx){1to4}, %xmm3, %k6 +# INTEL: vp2intersectd k6, xmm3, dword ptr [edx - 512]{1to4} +0x62,0xf2,0x67,0x18,0x68,0x72,0x80 + +# ATT: vp2intersectq %ymm4, %ymm3, %k6 +# INTEL: vp2intersectq k6, ymm3, ymm4 +0x62,0xf2,0xe7,0x28,0x68,0xf4 + +# ATT: vp2intersectq %xmm4, %xmm3, %k6 +# INTEL: vp2intersectq k6, xmm3, xmm4 +0x62,0xf2,0xe7,0x08,0x68,0xf4 + +# ATT: vp2intersectq 268435456(%esp,%esi,8), %ymm3, %k6 +# INTEL: vp2intersectq k6, ymm3, ymmword ptr [esp + 8*esi + 268435456] +0x62,0xf2,0xe7,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vp2intersectq 291(%edi,%eax,4), %ymm3, %k6 +# INTEL: vp2intersectq k6, ymm3, ymmword ptr [edi + 4*eax + 291] +0x62,0xf2,0xe7,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00 + +# ATT: vp2intersectq (%eax){1to4}, %ymm3, %k6 +# INTEL: vp2intersectq k6, ymm3, qword ptr [eax]{1to4} +0x62,0xf2,0xe7,0x38,0x68,0x30 + +# ATT: vp2intersectq -1024(,%ebp,2), %ymm3, %k6 +# INTEL: vp2intersectq k6, ymm3, ymmword ptr [2*ebp - 1024] +0x62,0xf2,0xe7,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff + +# ATT: vp2intersectq 4064(%ecx), %ymm3, %k6 +# INTEL: vp2intersectq k6, ymm3, ymmword ptr [ecx + 4064] +0x62,0xf2,0xe7,0x28,0x68,0x71,0x7f + +# ATT: vp2intersectq -1024(%edx){1to4}, %ymm3, %k6 +# INTEL: vp2intersectq k6, ymm3, qword ptr [edx - 1024]{1to4} +0x62,0xf2,0xe7,0x38,0x68,0x72,0x80 + +# ATT: vp2intersectq 268435456(%esp,%esi,8), %xmm3, %k6 +# INTEL: vp2intersectq k6, xmm3, xmmword ptr [esp + 8*esi + 268435456] +0x62,0xf2,0xe7,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10 + +# ATT: vp2intersectq 291(%edi,%eax,4), %xmm3, %k6 +# INTEL: vp2intersectq k6, xmm3, xmmword ptr [edi + 4*eax + 291] +0x62,0xf2,0xe7,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00 + +# ATT: vp2intersectq (%eax){1to2}, %xmm3, %k6 +# INTEL: vp2intersectq k6, xmm3, qword ptr [eax]{1to2} +0x62,0xf2,0xe7,0x18,0x68,0x30 + +# ATT: vp2intersectq -512(,%ebp,2), %xmm3, %k6 +# INTEL: vp2intersectq k6, xmm3, xmmword ptr [2*ebp - 512] +0x62,0xf2,0xe7,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff + +# ATT: vp2intersectq 2032(%ecx), %xmm3, %k6 +# INTEL: vp2intersectq k6, xmm3, xmmword ptr [ecx + 2032] +0x62,0xf2,0xe7,0x08,0x68,0x71,0x7f + +# ATT: vp2intersectq -1024(%edx){1to2}, %xmm3, %k6 +# INTEL: vp2intersectq k6, xmm3, qword ptr [edx - 1024]{1to2} +0x62,0xf2,0xe7,0x18,0x68,0x72,0x80 diff --git a/llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-64.txt b/llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-64.txt new file mode 100644 index 000000000000..2d4cbeb94b7c --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-64.txt @@ -0,0 +1,114 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: vp2intersectd %ymm24, %ymm23, %k6 +# INTEL: vp2intersectd k6, ymm23, ymm24 +0x62,0x92,0x47,0x20,0x68,0xf0 + +# ATT: vp2intersectd %xmm24, %xmm23, %k6 +# INTEL: vp2intersectd k6, xmm23, xmm24 +0x62,0x92,0x47,0x00,0x68,0xf0 + +# ATT: vp2intersectd 268435456(%rbp,%r14,8), %ymm23, %k6 +# INTEL: vp2intersectd k6, ymm23, ymmword ptr [rbp + 8*r14 + 268435456] +0x62,0xb2,0x47,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10 + +# ATT: vp2intersectd 291(%r8,%rax,4), %ymm23, %k6 +# INTEL: vp2intersectd k6, ymm23, ymmword ptr [r8 + 4*rax + 291] +0x62,0xd2,0x47,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00 + +# ATT: vp2intersectd (%rip){1to8}, %ymm23, %k6 +# INTEL: vp2intersectd k6, ymm23, dword ptr [rip]{1to8} +0x62,0xf2,0x47,0x30,0x68,0x35,0x00,0x00,0x00,0x00 + +# ATT: vp2intersectd -1024(,%rbp,2), %ymm23, %k6 +# INTEL: vp2intersectd k6, ymm23, ymmword ptr [2*rbp - 1024] +0x62,0xf2,0x47,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff + +# ATT: vp2intersectd 4064(%rcx), %ymm23, %k6 +# INTEL: vp2intersectd k6, ymm23, ymmword ptr [rcx + 4064] +0x62,0xf2,0x47,0x20,0x68,0x71,0x7f + +# ATT: vp2intersectd -512(%rdx){1to8}, %ymm23, %k6 +# INTEL: vp2intersectd k6, ymm23, dword ptr [rdx - 512]{1to8} +0x62,0xf2,0x47,0x30,0x68,0x72,0x80 + +# ATT: vp2intersectd 268435456(%rbp,%r14,8), %xmm23, %k6 +# INTEL: vp2intersectd k6, xmm23, xmmword ptr [rbp + 8*r14 + 268435456] +0x62,0xb2,0x47,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10 + +# ATT: vp2intersectd 291(%r8,%rax,4), %xmm23, %k6 +# INTEL: vp2intersectd k6, xmm23, xmmword ptr [r8 + 4*rax + 291] +0x62,0xd2,0x47,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00 + +# ATT: vp2intersectd (%rip){1to4}, %xmm23, %k6 +# INTEL: vp2intersectd k6, xmm23, dword ptr [rip]{1to4} +0x62,0xf2,0x47,0x10,0x68,0x35,0x00,0x00,0x00,0x00 + +# ATT: vp2intersectd -512(,%rbp,2), %xmm23, %k6 +# INTEL: vp2intersectd k6, xmm23, xmmword ptr [2*rbp - 512] +0x62,0xf2,0x47,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff + +# ATT: vp2intersectd 2032(%rcx), %xmm23, %k6 +# INTEL: vp2intersectd k6, xmm23, xmmword ptr [rcx + 2032] +0x62,0xf2,0x47,0x00,0x68,0x71,0x7f + +# ATT: vp2intersectd -512(%rdx){1to4}, %xmm23, %k6 +# INTEL: vp2intersectd k6, xmm23, dword ptr [rdx - 512]{1to4} +0x62,0xf2,0x47,0x10,0x68,0x72,0x80 + +# ATT: vp2intersectq %ymm24, %ymm23, %k6 +# INTEL: vp2intersectq k6, ymm23, ymm24 +0x62,0x92,0xc7,0x20,0x68,0xf0 + +# ATT: vp2intersectq %xmm24, %xmm23, %k6 +# INTEL: vp2intersectq k6, xmm23, xmm24 +0x62,0x92,0xc7,0x00,0x68,0xf0 + +# ATT: vp2intersectq 268435456(%rbp,%r14,8), %ymm23, %k6 +# INTEL: vp2intersectq k6, ymm23, ymmword ptr [rbp + 8*r14 + 268435456] +0x62,0xb2,0xc7,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10 + +# ATT: vp2intersectq 291(%r8,%rax,4), %ymm23, %k6 +# INTEL: vp2intersectq k6, ymm23, ymmword ptr [r8 + 4*rax + 291] +0x62,0xd2,0xc7,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00 + +# ATT: vp2intersectq (%rip){1to4}, %ymm23, %k6 +# INTEL: vp2intersectq k6, ymm23, qword ptr [rip]{1to4} +0x62,0xf2,0xc7,0x30,0x68,0x35,0x00,0x00,0x00,0x00 + +# ATT: vp2intersectq -1024(,%rbp,2), %ymm23, %k6 +# INTEL: vp2intersectq k6, ymm23, ymmword ptr [2*rbp - 1024] +0x62,0xf2,0xc7,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff + +# ATT: vp2intersectq 4064(%rcx), %ymm23, %k6 +# INTEL: vp2intersectq k6, ymm23, ymmword ptr [rcx + 4064] +0x62,0xf2,0xc7,0x20,0x68,0x71,0x7f + +# ATT: vp2intersectq -1024(%rdx){1to4}, %ymm23, %k6 +# INTEL: vp2intersectq k6, ymm23, qword ptr [rdx - 1024]{1to4} +0x62,0xf2,0xc7,0x30,0x68,0x72,0x80 + +# ATT: vp2intersectq 268435456(%rbp,%r14,8), %xmm23, %k6 +# INTEL: vp2intersectq k6, xmm23, xmmword ptr [rbp + 8*r14 + 268435456] +0x62,0xb2,0xc7,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10 + +# ATT: vp2intersectq 291(%r8,%rax,4), %xmm23, %k6 +# INTEL: vp2intersectq k6, xmm23, xmmword ptr [r8 + 4*rax + 291] +0x62,0xd2,0xc7,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00 + +# ATT: vp2intersectq (%rip){1to2}, %xmm23, %k6 +# INTEL: vp2intersectq k6, xmm23, qword ptr [rip]{1to2} +0x62,0xf2,0xc7,0x10,0x68,0x35,0x00,0x00,0x00,0x00 + +# ATT: vp2intersectq -512(,%rbp,2), %xmm23, %k6 +# INTEL: vp2intersectq k6, xmm23, xmmword ptr [2*rbp - 512] +0x62,0xf2,0xc7,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff + +# ATT: vp2intersectq 2032(%rcx), %xmm23, %k6 +# INTEL: vp2intersectq k6, xmm23, xmmword ptr [rcx + 2032] +0x62,0xf2,0xc7,0x00,0x68,0x71,0x7f + +# ATT: vp2intersectq -1024(%rdx){1to2}, %xmm23, %k6 +# INTEL: vp2intersectq k6, xmm23, qword ptr [rdx - 1024]{1to2} +0x62,0xf2,0xc7,0x10,0x68,0x72,0x80 diff --git a/llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-att.txt b/llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-att.txt deleted file mode 100644 index 9cb68e659c52..000000000000 --- a/llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-att.txt +++ /dev/null @@ -1,86 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=i686-apple-darwin9 | FileCheck %s - -# CHECK: vp2intersectd %ymm4, %ymm3, %k6 -0x62,0xf2,0x67,0x28,0x68,0xf4 - -# CHECK: vp2intersectd %xmm4, %xmm3, %k6 -0x62,0xf2,0x67,0x08,0x68,0xf4 - -# CHECK: vp2intersectd 268435456(%esp,%esi,8), %ymm3, %k6 -0x62,0xf2,0x67,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectd 291(%edi,%eax,4), %ymm3, %k6 -0x62,0xf2,0x67,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectd (%eax){1to8}, %ymm3, %k6 -0x62,0xf2,0x67,0x38,0x68,0x30 - -# CHECK: vp2intersectd -1024(,%ebp,2), %ymm3, %k6 -0x62,0xf2,0x67,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vp2intersectd 4064(%ecx), %ymm3, %k6 -0x62,0xf2,0x67,0x28,0x68,0x71,0x7f - -# CHECK: vp2intersectd -512(%edx){1to8}, %ymm3, %k6 -0x62,0xf2,0x67,0x38,0x68,0x72,0x80 - -# CHECK: vp2intersectd 268435456(%esp,%esi,8), %xmm3, %k6 -0x62,0xf2,0x67,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectd 291(%edi,%eax,4), %xmm3, %k6 -0x62,0xf2,0x67,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectd (%eax){1to4}, %xmm3, %k6 -0x62,0xf2,0x67,0x18,0x68,0x30 - -# CHECK: vp2intersectd -512(,%ebp,2), %xmm3, %k6 -0x62,0xf2,0x67,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vp2intersectd 2032(%ecx), %xmm3, %k6 -0x62,0xf2,0x67,0x08,0x68,0x71,0x7f - -# CHECK: vp2intersectd -512(%edx){1to4}, %xmm3, %k6 -0x62,0xf2,0x67,0x18,0x68,0x72,0x80 - -# CHECK: vp2intersectq %ymm4, %ymm3, %k6 -0x62,0xf2,0xe7,0x28,0x68,0xf4 - -# CHECK: vp2intersectq %xmm4, %xmm3, %k6 -0x62,0xf2,0xe7,0x08,0x68,0xf4 - -# CHECK: vp2intersectq 268435456(%esp,%esi,8), %ymm3, %k6 -0x62,0xf2,0xe7,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectq 291(%edi,%eax,4), %ymm3, %k6 -0x62,0xf2,0xe7,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectq (%eax){1to4}, %ymm3, %k6 -0x62,0xf2,0xe7,0x38,0x68,0x30 - -# CHECK: vp2intersectq -1024(,%ebp,2), %ymm3, %k6 -0x62,0xf2,0xe7,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vp2intersectq 4064(%ecx), %ymm3, %k6 -0x62,0xf2,0xe7,0x28,0x68,0x71,0x7f - -# CHECK: vp2intersectq -1024(%edx){1to4}, %ymm3, %k6 -0x62,0xf2,0xe7,0x38,0x68,0x72,0x80 - -# CHECK: vp2intersectq 268435456(%esp,%esi,8), %xmm3, %k6 -0x62,0xf2,0xe7,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectq 291(%edi,%eax,4), %xmm3, %k6 -0x62,0xf2,0xe7,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectq (%eax){1to2}, %xmm3, %k6 -0x62,0xf2,0xe7,0x18,0x68,0x30 - -# CHECK: vp2intersectq -512(,%ebp,2), %xmm3, %k6 -0x62,0xf2,0xe7,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vp2intersectq 2032(%ecx), %xmm3, %k6 -0x62,0xf2,0xe7,0x08,0x68,0x71,0x7f - -# CHECK: vp2intersectq -1024(%edx){1to2}, %xmm3, %k6 -0x62,0xf2,0xe7,0x18,0x68,0x72,0x80 - diff --git a/llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-intel.txt b/llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-intel.txt deleted file mode 100644 index 0c34a6ec016c..000000000000 --- a/llvm/test/MC/Disassembler/X86/avx512vp2intersectvl-intel.txt +++ /dev/null @@ -1,85 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=i386 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s - -# CHECK: vp2intersectd k6, ymm3, ymm4 -0x62,0xf2,0x67,0x28,0x68,0xf4 - -# CHECK: vp2intersectd k6, xmm3, xmm4 -0x62,0xf2,0x67,0x08,0x68,0xf4 - -# CHECK: vp2intersectd k6, ymm3, ymmword ptr [esp + 8*esi + 268435456] -0x62,0xf2,0x67,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectd k6, ymm3, ymmword ptr [edi + 4*eax + 291] -0x62,0xf2,0x67,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectd k6, ymm3, dword ptr [eax]{1to8} -0x62,0xf2,0x67,0x38,0x68,0x30 - -# CHECK: vp2intersectd k6, ymm3, ymmword ptr [2*ebp - 1024] -0x62,0xf2,0x67,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vp2intersectd k6, ymm3, ymmword ptr [ecx + 4064] -0x62,0xf2,0x67,0x28,0x68,0x71,0x7f - -# CHECK: vp2intersectd k6, ymm3, dword ptr [edx - 512]{1to8} -0x62,0xf2,0x67,0x38,0x68,0x72,0x80 - -# CHECK: vp2intersectd k6, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0x62,0xf2,0x67,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectd k6, xmm3, xmmword ptr [edi + 4*eax + 291] -0x62,0xf2,0x67,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectd k6, xmm3, dword ptr [eax]{1to4} -0x62,0xf2,0x67,0x18,0x68,0x30 - -# CHECK: vp2intersectd k6, xmm3, xmmword ptr [2*ebp - 512] -0x62,0xf2,0x67,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vp2intersectd k6, xmm3, xmmword ptr [ecx + 2032] -0x62,0xf2,0x67,0x08,0x68,0x71,0x7f - -# CHECK: vp2intersectd k6, xmm3, dword ptr [edx - 512]{1to4} -0x62,0xf2,0x67,0x18,0x68,0x72,0x80 - -# CHECK: vp2intersectq k6, ymm3, ymm4 -0x62,0xf2,0xe7,0x28,0x68,0xf4 - -# CHECK: vp2intersectq k6, xmm3, xmm4 -0x62,0xf2,0xe7,0x08,0x68,0xf4 - -# CHECK: vp2intersectq k6, ymm3, ymmword ptr [esp + 8*esi + 268435456] -0x62,0xf2,0xe7,0x28,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectq k6, ymm3, ymmword ptr [edi + 4*eax + 291] -0x62,0xf2,0xe7,0x28,0x68,0xb4,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectq k6, ymm3, qword ptr [eax]{1to4} -0x62,0xf2,0xe7,0x38,0x68,0x30 - -# CHECK: vp2intersectq k6, ymm3, ymmword ptr [2*ebp - 1024] -0x62,0xf2,0xe7,0x28,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vp2intersectq k6, ymm3, ymmword ptr [ecx + 4064] -0x62,0xf2,0xe7,0x28,0x68,0x71,0x7f - -# CHECK: vp2intersectq k6, ymm3, qword ptr [edx - 1024]{1to4} -0x62,0xf2,0xe7,0x38,0x68,0x72,0x80 - -# CHECK: vp2intersectq k6, xmm3, xmmword ptr [esp + 8*esi + 268435456] -0x62,0xf2,0xe7,0x08,0x68,0xb4,0xf4,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectq k6, xmm3, xmmword ptr [edi + 4*eax + 291] -0x62,0xf2,0xe7,0x08,0x68,0xb4,0x87,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectq k6, xmm3, qword ptr [eax]{1to2} -0x62,0xf2,0xe7,0x18,0x68,0x30 - -# CHECK: vp2intersectq k6, xmm3, xmmword ptr [2*ebp - 512] -0x62,0xf2,0xe7,0x08,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vp2intersectq k6, xmm3, xmmword ptr [ecx + 2032] -0x62,0xf2,0xe7,0x08,0x68,0x71,0x7f - -# CHECK: vp2intersectq k6, xmm3, qword ptr [edx - 1024]{1to2} -0x62,0xf2,0xe7,0x18,0x68,0x72,0x80 diff --git a/llvm/test/MC/Disassembler/X86/x86-64-avx512bf16-att.txt b/llvm/test/MC/Disassembler/X86/x86-64-avx512bf16-att.txt deleted file mode 100644 index 2b633a9a7cf8..000000000000 --- a/llvm/test/MC/Disassembler/X86/x86-64-avx512bf16-att.txt +++ /dev/null @@ -1,82 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s - -# CHECK: vcvtne2ps2bf16 %zmm24, %zmm23, %zmm22 -0x62,0x82,0x47,0x40,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 %zmm24, %zmm23, %zmm22 {%k7} -0x62,0x82,0x47,0x47,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 %zmm24, %zmm23, %zmm22 {%k7} {z} -0x62,0x82,0x47,0xc7,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 268435456(%rbp,%r14,8), %zmm23, %zmm22 -0x62,0xa2,0x47,0x40,0x72,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vcvtne2ps2bf16 291(%r8,%rax,4), %zmm23, %zmm22 {%k7} -0x62,0xc2,0x47,0x47,0x72,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 (%rip){1to16}, %zmm23, %zmm22 -0x62,0xe2,0x47,0x50,0x72,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 -2048(,%rbp,2), %zmm23, %zmm22 -0x62,0xe2,0x47,0x40,0x72,0x34,0x6d,0x00,0xf8,0xff,0xff - -# CHECK: vcvtne2ps2bf16 8128(%rcx), %zmm23, %zmm22 {%k7} {z} -0x62,0xe2,0x47,0xc7,0x72,0x71,0x7f - -# CHECK: vcvtne2ps2bf16 -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z} -0x62,0xe2,0x47,0xd7,0x72,0x72,0x80 - -# CHECK: vcvtneps2bf16 %zmm23, %ymm22 -0x62,0xa2,0x7e,0x48,0x72,0xf7 - -# CHECK: vcvtneps2bf16 %zmm23, %ymm22 {%k7} -0x62,0xa2,0x7e,0x4f,0x72,0xf7 - -# CHECK: vcvtneps2bf16 %zmm23, %ymm22 {%k7} {z} -0x62,0xa2,0x7e,0xcf,0x72,0xf7 - -# CHECK: vcvtneps2bf16 268435456(%rbp,%r14,8), %ymm22 -0x62,0xa2,0x7e,0x48,0x72,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vcvtneps2bf16 291(%r8,%rax,4), %ymm22 {%k7} -0x62,0xc2,0x7e,0x4f,0x72,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vcvtneps2bf16 (%rip){1to16}, %ymm22 -0x62,0xe2,0x7e,0x58,0x72,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vcvtneps2bf16 -2048(,%rbp,2), %ymm22 -0x62,0xe2,0x7e,0x48,0x72,0x34,0x6d,0x00,0xf8,0xff,0xff - -# CHECK: vcvtneps2bf16 8128(%rcx), %ymm22 {%k7} {z} -0x62,0xe2,0x7e,0xcf,0x72,0x71,0x7f - -# CHECK: vcvtneps2bf16 -512(%rdx){1to16}, %ymm22 {%k7} {z} -0x62,0xe2,0x7e,0xdf,0x72,0x72,0x80 - -# CHECK: vdpbf16ps %zmm24, %zmm23, %zmm22 -0x62,0x82,0x46,0x40,0x52,0xf0 - -# CHECK: vdpbf16ps %zmm24, %zmm23, %zmm22 {%k7} -0x62,0x82,0x46,0x47,0x52,0xf0 - -# CHECK: vdpbf16ps %zmm24, %zmm23, %zmm22 {%k7} {z} -0x62,0x82,0x46,0xc7,0x52,0xf0 - -# CHECK: vdpbf16ps 268435456(%rbp,%r14,8), %zmm23, %zmm22 -0x62,0xa2,0x46,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vdpbf16ps 291(%r8,%rax,4), %zmm23, %zmm22 {%k7} -0x62,0xc2,0x46,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vdpbf16ps (%rip){1to16}, %zmm23, %zmm22 -0x62,0xe2,0x46,0x50,0x52,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vdpbf16ps -2048(,%rbp,2), %zmm23, %zmm22 -0x62,0xe2,0x46,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff - -# CHECK: vdpbf16ps 8128(%rcx), %zmm23, %zmm22 {%k7} {z} -0x62,0xe2,0x46,0xc7,0x52,0x71,0x7f - -# CHECK: vdpbf16ps -512(%rdx){1to16}, %zmm23, %zmm22 {%k7} {z} -0x62,0xe2,0x46,0xd7,0x52,0x72,0x80 diff --git a/llvm/test/MC/Disassembler/X86/x86-64-avx512bf16-intel.txt b/llvm/test/MC/Disassembler/X86/x86-64-avx512bf16-intel.txt deleted file mode 100644 index 8bb3be91aed2..000000000000 --- a/llvm/test/MC/Disassembler/X86/x86-64-avx512bf16-intel.txt +++ /dev/null @@ -1,83 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s - -# CHECK: vcvtne2ps2bf16 zmm22, zmm23, zmm24 -0x62,0x82,0x47,0x40,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 zmm22 {k7}, zmm23, zmm24 -0x62,0x82,0x47,0x47,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 zmm22 {k7} {z}, zmm23, zmm24 -0x62,0x82,0x47,0xc7,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456] -0x62,0xa2,0x47,0x40,0x72,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vcvtne2ps2bf16 zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291] -0x62,0xc2,0x47,0x47,0x72,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 zmm22, zmm23, dword ptr [rip]{1to16} -0x62,0xe2,0x47,0x50,0x72,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 zmm22, zmm23, zmmword ptr [2*rbp - 2048] -0x62,0xe2,0x47,0x40,0x72,0x34,0x6d,0x00,0xf8,0xff,0xff - -# CHECK: vcvtne2ps2bf16 zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128] -0x62,0xe2,0x47,0xc7,0x72,0x71,0x7f - -# CHECK: vcvtne2ps2bf16 zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16} -0x62,0xe2,0x47,0xd7,0x72,0x72,0x80 - -# CHECK: vcvtneps2bf16 ymm22, zmm23 -0x62,0xa2,0x7e,0x48,0x72,0xf7 - -# CHECK: vcvtneps2bf16 ymm22 {k7}, zmm23 -0x62,0xa2,0x7e,0x4f,0x72,0xf7 - -# CHECK: vcvtneps2bf16 ymm22 {k7} {z}, zmm23 -0x62,0xa2,0x7e,0xcf,0x72,0xf7 - -# CHECK: vcvtneps2bf16 ymm22, zmmword ptr [rbp + 8*r14 + 268435456] -0x62,0xa2,0x7e,0x48,0x72,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vcvtneps2bf16 ymm22 {k7}, zmmword ptr [r8 + 4*rax + 291] -0x62,0xc2,0x7e,0x4f,0x72,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vcvtneps2bf16 ymm22, dword ptr [rip]{1to16} -0x62,0xe2,0x7e,0x58,0x72,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vcvtneps2bf16 ymm22, zmmword ptr [2*rbp - 2048] -0x62,0xe2,0x7e,0x48,0x72,0x34,0x6d,0x00,0xf8,0xff,0xff - -# CHECK: vcvtneps2bf16 ymm22 {k7} {z}, zmmword ptr [rcx + 8128] -0x62,0xe2,0x7e,0xcf,0x72,0x71,0x7f - -# CHECK: vcvtneps2bf16 ymm22 {k7} {z}, dword ptr [rdx - 512]{1to16} -0x62,0xe2,0x7e,0xdf,0x72,0x72,0x80 - -# CHECK: vdpbf16ps zmm22, zmm23, zmm24 -0x62,0x82,0x46,0x40,0x52,0xf0 - -# CHECK: vdpbf16ps zmm22 {k7}, zmm23, zmm24 -0x62,0x82,0x46,0x47,0x52,0xf0 - -# CHECK: vdpbf16ps zmm22 {k7} {z}, zmm23, zmm24 -0x62,0x82,0x46,0xc7,0x52,0xf0 - -# CHECK: vdpbf16ps zmm22, zmm23, zmmword ptr [rbp + 8*r14 + 268435456] -0x62,0xa2,0x46,0x40,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vdpbf16ps zmm22 {k7}, zmm23, zmmword ptr [r8 + 4*rax + 291] -0x62,0xc2,0x46,0x47,0x52,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vdpbf16ps zmm22, zmm23, dword ptr [rip]{1to16} -0x62,0xe2,0x46,0x50,0x52,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vdpbf16ps zmm22, zmm23, zmmword ptr [2*rbp - 2048] -0x62,0xe2,0x46,0x40,0x52,0x34,0x6d,0x00,0xf8,0xff,0xff - -# CHECK: vdpbf16ps zmm22 {k7} {z}, zmm23, zmmword ptr [rcx + 8128] -0x62,0xe2,0x46,0xc7,0x52,0x71,0x7f - -# CHECK: vdpbf16ps zmm22 {k7} {z}, zmm23, dword ptr [rdx - 512]{1to16} -0x62,0xe2,0x46,0xd7,0x52,0x72,0x80 - diff --git a/llvm/test/MC/Disassembler/X86/x86-64-avx512bf16vl-att.txt b/llvm/test/MC/Disassembler/X86/x86-64-avx512bf16vl-att.txt deleted file mode 100644 index e2bfc98b13a1..000000000000 --- a/llvm/test/MC/Disassembler/X86/x86-64-avx512bf16vl-att.txt +++ /dev/null @@ -1,158 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s - -# CHECK: vcvtne2ps2bf16 %ymm24, %ymm23, %ymm22 -0x62,0x82,0x47,0x20,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 %ymm24, %ymm23, %ymm22 {%k7} -0x62,0x82,0x47,0x27,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 %ymm24, %ymm23, %ymm22 {%k7} {z} -0x62,0x82,0x47,0xa7,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 %xmm24, %xmm23, %xmm22 -0x62,0x82,0x47,0x00,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 %xmm24, %xmm23, %xmm22 {%k7} -0x62,0x82,0x47,0x07,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 %xmm24, %xmm23, %xmm22 {%k7} {z} -0x62,0x82,0x47,0x87,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 268435456(%rbp,%r14,8), %ymm23, %ymm22 -0x62,0xa2,0x47,0x20,0x72,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vcvtne2ps2bf16 291(%r8,%rax,4), %ymm23, %ymm22 {%k7} -0x62,0xc2,0x47,0x27,0x72,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 (%rip){1to8}, %ymm23, %ymm22 -0x62,0xe2,0x47,0x30,0x72,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 -1024(,%rbp,2), %ymm23, %ymm22 -0x62,0xe2,0x47,0x20,0x72,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vcvtne2ps2bf16 4064(%rcx), %ymm23, %ymm22 {%k7} {z} -0x62,0xe2,0x47,0xa7,0x72,0x71,0x7f - -# CHECK: vcvtne2ps2bf16 -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z} -0x62,0xe2,0x47,0xb7,0x72,0x72,0x80 - -# CHECK: vcvtne2ps2bf16 268435456(%rbp,%r14,8), %xmm23, %xmm22 -0x62,0xa2,0x47,0x00,0x72,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vcvtne2ps2bf16 291(%r8,%rax,4), %xmm23, %xmm22 {%k7} -0x62,0xc2,0x47,0x07,0x72,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 (%rip){1to4}, %xmm23, %xmm22 -0x62,0xe2,0x47,0x10,0x72,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 -512(,%rbp,2), %xmm23, %xmm22 -0x62,0xe2,0x47,0x00,0x72,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vcvtne2ps2bf16 2032(%rcx), %xmm23, %xmm22 {%k7} {z} -0x62,0xe2,0x47,0x87,0x72,0x71,0x7f - -# CHECK: vcvtne2ps2bf16 -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z} -0x62,0xe2,0x47,0x97,0x72,0x72,0x80 - -# CHECK: vcvtneps2bf16 %xmm23, %xmm22 -0x62,0xa2,0x7e,0x08,0x72,0xf7 - -# CHECK: vcvtneps2bf16 %xmm23, %xmm22 {%k7} -0x62,0xa2,0x7e,0x0f,0x72,0xf7 - -# CHECK: vcvtneps2bf16 %xmm23, %xmm22 {%k7} {z} -0x62,0xa2,0x7e,0x8f,0x72,0xf7 - -# CHECK: vcvtneps2bf16 %ymm23, %xmm22 -0x62,0xa2,0x7e,0x28,0x72,0xf7 - -# CHECK: vcvtneps2bf16 %ymm23, %xmm22 {%k7} -0x62,0xa2,0x7e,0x2f,0x72,0xf7 - -# CHECK: vcvtneps2bf16 %ymm23, %xmm22 {%k7} {z} -0x62,0xa2,0x7e,0xaf,0x72,0xf7 - -# CHECK: vcvtneps2bf16x 268435456(%rbp,%r14,8), %xmm22 -0x62,0xa2,0x7e,0x08,0x72,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vcvtneps2bf16x 291(%r8,%rax,4), %xmm22 {%k7} -0x62,0xc2,0x7e,0x0f,0x72,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vcvtneps2bf16 (%rip){1to4}, %xmm22 -0x62,0xe2,0x7e,0x18,0x72,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vcvtneps2bf16x -512(,%rbp,2), %xmm22 -0x62,0xe2,0x7e,0x08,0x72,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vcvtneps2bf16x 2032(%rcx), %xmm22 {%k7} {z} -0x62,0xe2,0x7e,0x8f,0x72,0x71,0x7f - -# CHECK: vcvtneps2bf16 -512(%rdx){1to4}, %xmm22 {%k7} {z} -0x62,0xe2,0x7e,0x9f,0x72,0x72,0x80 - -# CHECK: vcvtneps2bf16 (%rip){1to8}, %xmm22 -0x62,0xe2,0x7e,0x38,0x72,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vcvtneps2bf16y -1024(,%rbp,2), %xmm22 -0x62,0xe2,0x7e,0x28,0x72,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vcvtneps2bf16y 4064(%rcx), %xmm22 {%k7} {z} -0x62,0xe2,0x7e,0xaf,0x72,0x71,0x7f - -# CHECK: vcvtneps2bf16 -512(%rdx){1to8}, %xmm22 {%k7} {z} -0x62,0xe2,0x7e,0xbf,0x72,0x72,0x80 - -# CHECK: vdpbf16ps %ymm24, %ymm23, %ymm22 -0x62,0x82,0x46,0x20,0x52,0xf0 - -# CHECK: vdpbf16ps %ymm24, %ymm23, %ymm22 {%k7} -0x62,0x82,0x46,0x27,0x52,0xf0 - -# CHECK: vdpbf16ps %ymm24, %ymm23, %ymm22 {%k7} {z} -0x62,0x82,0x46,0xa7,0x52,0xf0 - -# CHECK: vdpbf16ps %xmm24, %xmm23, %xmm22 -0x62,0x82,0x46,0x00,0x52,0xf0 - -# CHECK: vdpbf16ps %xmm24, %xmm23, %xmm22 {%k7} -0x62,0x82,0x46,0x07,0x52,0xf0 - -# CHECK: vdpbf16ps %xmm24, %xmm23, %xmm22 {%k7} {z} -0x62,0x82,0x46,0x87,0x52,0xf0 - -# CHECK: vdpbf16ps 268435456(%rbp,%r14,8), %ymm23, %ymm22 -0x62,0xa2,0x46,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vdpbf16ps 291(%r8,%rax,4), %ymm23, %ymm22 {%k7} -0x62,0xc2,0x46,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vdpbf16ps (%rip){1to8}, %ymm23, %ymm22 -0x62,0xe2,0x46,0x30,0x52,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vdpbf16ps -1024(,%rbp,2), %ymm23, %ymm22 -0x62,0xe2,0x46,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vdpbf16ps 4064(%rcx), %ymm23, %ymm22 {%k7} {z} -0x62,0xe2,0x46,0xa7,0x52,0x71,0x7f - -# CHECK: vdpbf16ps -512(%rdx){1to8}, %ymm23, %ymm22 {%k7} {z} -0x62,0xe2,0x46,0xb7,0x52,0x72,0x80 - -# CHECK: vdpbf16ps 268435456(%rbp,%r14,8), %xmm23, %xmm22 -0x62,0xa2,0x46,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vdpbf16ps 291(%r8,%rax,4), %xmm23, %xmm22 {%k7} -0x62,0xc2,0x46,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vdpbf16ps (%rip){1to4}, %xmm23, %xmm22 -0x62,0xe2,0x46,0x10,0x52,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vdpbf16ps -512(,%rbp,2), %xmm23, %xmm22 -0x62,0xe2,0x46,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vdpbf16ps 2032(%rcx), %xmm23, %xmm22 {%k7} {z} -0x62,0xe2,0x46,0x87,0x52,0x71,0x7f - -# CHECK: vdpbf16ps -512(%rdx){1to4}, %xmm23, %xmm22 {%k7} {z} -0x62,0xe2,0x46,0x97,0x52,0x72,0x80 - diff --git a/llvm/test/MC/Disassembler/X86/x86-64-avx512bf16vl-intel.txt b/llvm/test/MC/Disassembler/X86/x86-64-avx512bf16vl-intel.txt deleted file mode 100644 index 4def95ed8992..000000000000 --- a/llvm/test/MC/Disassembler/X86/x86-64-avx512bf16vl-intel.txt +++ /dev/null @@ -1,158 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s - -# CHECK: vcvtne2ps2bf16 ymm22, ymm23, ymm24 -0x62,0x82,0x47,0x20,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 ymm22 {k7}, ymm23, ymm24 -0x62,0x82,0x47,0x27,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 ymm22 {k7} {z}, ymm23, ymm24 -0x62,0x82,0x47,0xa7,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 xmm22, xmm23, xmm24 -0x62,0x82,0x47,0x00,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 xmm22 {k7}, xmm23, xmm24 -0x62,0x82,0x47,0x07,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 xmm22 {k7} {z}, xmm23, xmm24 -0x62,0x82,0x47,0x87,0x72,0xf0 - -# CHECK: vcvtne2ps2bf16 ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456] -0x62,0xa2,0x47,0x20,0x72,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vcvtne2ps2bf16 ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291] -0x62,0xc2,0x47,0x27,0x72,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 ymm22, ymm23, dword ptr [rip]{1to8} -0x62,0xe2,0x47,0x30,0x72,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 ymm22, ymm23, ymmword ptr [2*rbp - 1024] -0x62,0xe2,0x47,0x20,0x72,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vcvtne2ps2bf16 ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064] -0x62,0xe2,0x47,0xa7,0x72,0x71,0x7f - -# CHECK: vcvtne2ps2bf16 ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8} -0x62,0xe2,0x47,0xb7,0x72,0x72,0x80 - -# CHECK: vcvtne2ps2bf16 xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456] -0x62,0xa2,0x47,0x00,0x72,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vcvtne2ps2bf16 xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291] -0x62,0xc2,0x47,0x07,0x72,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 xmm22, xmm23, dword ptr [rip]{1to4} -0x62,0xe2,0x47,0x10,0x72,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vcvtne2ps2bf16 xmm22, xmm23, xmmword ptr [2*rbp - 512] -0x62,0xe2,0x47,0x00,0x72,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vcvtne2ps2bf16 xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032] -0x62,0xe2,0x47,0x87,0x72,0x71,0x7f - -# CHECK: vcvtne2ps2bf16 xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4} -0x62,0xe2,0x47,0x97,0x72,0x72,0x80 - -# CHECK: vcvtneps2bf16 xmm22, xmm23 -0x62,0xa2,0x7e,0x08,0x72,0xf7 - -# CHECK: vcvtneps2bf16 xmm22 {k7}, xmm23 -0x62,0xa2,0x7e,0x0f,0x72,0xf7 - -# CHECK: vcvtneps2bf16 xmm22 {k7} {z}, xmm23 -0x62,0xa2,0x7e,0x8f,0x72,0xf7 - -# CHECK: vcvtneps2bf16 xmm22, ymm23 -0x62,0xa2,0x7e,0x28,0x72,0xf7 - -# CHECK: vcvtneps2bf16 xmm22 {k7}, ymm23 -0x62,0xa2,0x7e,0x2f,0x72,0xf7 - -# CHECK: vcvtneps2bf16 xmm22 {k7} {z}, ymm23 -0x62,0xa2,0x7e,0xaf,0x72,0xf7 - -# CHECK: vcvtneps2bf16 xmm22, xmmword ptr [rbp + 8*r14 + 268435456] -0x62,0xa2,0x7e,0x08,0x72,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vcvtneps2bf16 xmm22 {k7}, xmmword ptr [r8 + 4*rax + 291] -0x62,0xc2,0x7e,0x0f,0x72,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vcvtneps2bf16 xmm22, dword ptr [rip]{1to4} -0x62,0xe2,0x7e,0x18,0x72,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vcvtneps2bf16 xmm22, xmmword ptr [2*rbp - 512] -0x62,0xe2,0x7e,0x08,0x72,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vcvtneps2bf16 xmm22 {k7} {z}, xmmword ptr [rcx + 2032] -0x62,0xe2,0x7e,0x8f,0x72,0x71,0x7f - -# CHECK: vcvtneps2bf16 xmm22 {k7} {z}, dword ptr [rdx - 512]{1to4} -0x62,0xe2,0x7e,0x9f,0x72,0x72,0x80 - -# CHECK: vcvtneps2bf16 xmm22, dword ptr [rip]{1to8} -0x62,0xe2,0x7e,0x38,0x72,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vcvtneps2bf16 xmm22, ymmword ptr [2*rbp - 1024] -0x62,0xe2,0x7e,0x28,0x72,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vcvtneps2bf16 xmm22 {k7} {z}, ymmword ptr [rcx + 4064] -0x62,0xe2,0x7e,0xaf,0x72,0x71,0x7f - -# CHECK: vcvtneps2bf16 xmm22 {k7} {z}, dword ptr [rdx - 512]{1to8} -0x62,0xe2,0x7e,0xbf,0x72,0x72,0x80 - -# CHECK: vdpbf16ps ymm22, ymm23, ymm24 -0x62,0x82,0x46,0x20,0x52,0xf0 - -# CHECK: vdpbf16ps ymm22 {k7}, ymm23, ymm24 -0x62,0x82,0x46,0x27,0x52,0xf0 - -# CHECK: vdpbf16ps ymm22 {k7} {z}, ymm23, ymm24 -0x62,0x82,0x46,0xa7,0x52,0xf0 - -# CHECK: vdpbf16ps xmm22, xmm23, xmm24 -0x62,0x82,0x46,0x00,0x52,0xf0 - -# CHECK: vdpbf16ps xmm22 {k7}, xmm23, xmm24 -0x62,0x82,0x46,0x07,0x52,0xf0 - -# CHECK: vdpbf16ps xmm22 {k7} {z}, xmm23, xmm24 -0x62,0x82,0x46,0x87,0x52,0xf0 - -# CHECK: vdpbf16ps ymm22, ymm23, ymmword ptr [rbp + 8*r14 + 268435456] -0x62,0xa2,0x46,0x20,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vdpbf16ps ymm22 {k7}, ymm23, ymmword ptr [r8 + 4*rax + 291] -0x62,0xc2,0x46,0x27,0x52,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vdpbf16ps ymm22, ymm23, dword ptr [rip]{1to8} -0x62,0xe2,0x46,0x30,0x52,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vdpbf16ps ymm22, ymm23, ymmword ptr [2*rbp - 1024] -0x62,0xe2,0x46,0x20,0x52,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vdpbf16ps ymm22 {k7} {z}, ymm23, ymmword ptr [rcx + 4064] -0x62,0xe2,0x46,0xa7,0x52,0x71,0x7f - -# CHECK: vdpbf16ps ymm22 {k7} {z}, ymm23, dword ptr [rdx - 512]{1to8} -0x62,0xe2,0x46,0xb7,0x52,0x72,0x80 - -# CHECK: vdpbf16ps xmm22, xmm23, xmmword ptr [rbp + 8*r14 + 268435456] -0x62,0xa2,0x46,0x00,0x52,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vdpbf16ps xmm22 {k7}, xmm23, xmmword ptr [r8 + 4*rax + 291] -0x62,0xc2,0x46,0x07,0x52,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vdpbf16ps xmm22, xmm23, dword ptr [rip]{1to4} -0x62,0xe2,0x46,0x10,0x52,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vdpbf16ps xmm22, xmm23, xmmword ptr [2*rbp - 512] -0x62,0xe2,0x46,0x00,0x52,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vdpbf16ps xmm22 {k7} {z}, xmm23, xmmword ptr [rcx + 2032] -0x62,0xe2,0x46,0x87,0x52,0x71,0x7f - -# CHECK: vdpbf16ps xmm22 {k7} {z}, xmm23, dword ptr [rdx - 512]{1to4} -0x62,0xe2,0x46,0x97,0x52,0x72,0x80 - diff --git a/llvm/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-att.txt b/llvm/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-att.txt deleted file mode 100644 index b166ccbf6ee0..000000000000 --- a/llvm/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-att.txt +++ /dev/null @@ -1,85 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s - -# CHECK: vp2intersectd %ymm24, %ymm23, %k6 -0x62,0x92,0x47,0x20,0x68,0xf0 - -# CHECK: vp2intersectd %xmm24, %xmm23, %k6 -0x62,0x92,0x47,0x00,0x68,0xf0 - -# CHECK: vp2intersectd 268435456(%rbp,%r14,8), %ymm23, %k6 -0x62,0xb2,0x47,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectd 291(%r8,%rax,4), %ymm23, %k6 -0x62,0xd2,0x47,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectd (%rip){1to8}, %ymm23, %k6 -0x62,0xf2,0x47,0x30,0x68,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vp2intersectd -1024(,%rbp,2), %ymm23, %k6 -0x62,0xf2,0x47,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vp2intersectd 4064(%rcx), %ymm23, %k6 -0x62,0xf2,0x47,0x20,0x68,0x71,0x7f - -# CHECK: vp2intersectd -512(%rdx){1to8}, %ymm23, %k6 -0x62,0xf2,0x47,0x30,0x68,0x72,0x80 - -# CHECK: vp2intersectd 268435456(%rbp,%r14,8), %xmm23, %k6 -0x62,0xb2,0x47,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectd 291(%r8,%rax,4), %xmm23, %k6 -0x62,0xd2,0x47,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectd (%rip){1to4}, %xmm23, %k6 -0x62,0xf2,0x47,0x10,0x68,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vp2intersectd -512(,%rbp,2), %xmm23, %k6 -0x62,0xf2,0x47,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vp2intersectd 2032(%rcx), %xmm23, %k6 -0x62,0xf2,0x47,0x00,0x68,0x71,0x7f - -# CHECK: vp2intersectd -512(%rdx){1to4}, %xmm23, %k6 -0x62,0xf2,0x47,0x10,0x68,0x72,0x80 - -# CHECK: vp2intersectq %ymm24, %ymm23, %k6 -0x62,0x92,0xc7,0x20,0x68,0xf0 - -# CHECK: vp2intersectq %xmm24, %xmm23, %k6 -0x62,0x92,0xc7,0x00,0x68,0xf0 - -# CHECK: vp2intersectq 268435456(%rbp,%r14,8), %ymm23, %k6 -0x62,0xb2,0xc7,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectq 291(%r8,%rax,4), %ymm23, %k6 -0x62,0xd2,0xc7,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectq (%rip){1to4}, %ymm23, %k6 -0x62,0xf2,0xc7,0x30,0x68,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vp2intersectq -1024(,%rbp,2), %ymm23, %k6 -0x62,0xf2,0xc7,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vp2intersectq 4064(%rcx), %ymm23, %k6 -0x62,0xf2,0xc7,0x20,0x68,0x71,0x7f - -# CHECK: vp2intersectq -1024(%rdx){1to4}, %ymm23, %k6 -0x62,0xf2,0xc7,0x30,0x68,0x72,0x80 - -# CHECK: vp2intersectq 268435456(%rbp,%r14,8), %xmm23, %k6 -0x62,0xb2,0xc7,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectq 291(%r8,%rax,4), %xmm23, %k6 -0x62,0xd2,0xc7,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectq (%rip){1to2}, %xmm23, %k6 -0x62,0xf2,0xc7,0x10,0x68,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vp2intersectq -512(,%rbp,2), %xmm23, %k6 -0x62,0xf2,0xc7,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vp2intersectq 2032(%rcx), %xmm23, %k6 -0x62,0xf2,0xc7,0x00,0x68,0x71,0x7f - -# CHECK: vp2intersectq -1024(%rdx){1to2}, %xmm23, %k6 -0x62,0xf2,0xc7,0x10,0x68,0x72,0x80 diff --git a/llvm/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-intel.txt b/llvm/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-intel.txt deleted file mode 100644 index b952b668454c..000000000000 --- a/llvm/test/MC/Disassembler/X86/x86-64-avx512vp2intersectvl-intel.txt +++ /dev/null @@ -1,85 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s - -# CHECK: vp2intersectd k6, ymm23, ymm24 -0x62,0x92,0x47,0x20,0x68,0xf0 - -# CHECK: vp2intersectd k6, xmm23, xmm24 -0x62,0x92,0x47,0x00,0x68,0xf0 - -# CHECK: vp2intersectd k6, ymm23, ymmword ptr [rbp + 8*r14 + 268435456] -0x62,0xb2,0x47,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectd k6, ymm23, ymmword ptr [r8 + 4*rax + 291] -0x62,0xd2,0x47,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectd k6, ymm23, dword ptr [rip]{1to8} -0x62,0xf2,0x47,0x30,0x68,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vp2intersectd k6, ymm23, ymmword ptr [2*rbp - 1024] -0x62,0xf2,0x47,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vp2intersectd k6, ymm23, ymmword ptr [rcx + 4064] -0x62,0xf2,0x47,0x20,0x68,0x71,0x7f - -# CHECK: vp2intersectd k6, ymm23, dword ptr [rdx - 512]{1to8} -0x62,0xf2,0x47,0x30,0x68,0x72,0x80 - -# CHECK: vp2intersectd k6, xmm23, xmmword ptr [rbp + 8*r14 + 268435456] -0x62,0xb2,0x47,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectd k6, xmm23, xmmword ptr [r8 + 4*rax + 291] -0x62,0xd2,0x47,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectd k6, xmm23, dword ptr [rip]{1to4} -0x62,0xf2,0x47,0x10,0x68,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vp2intersectd k6, xmm23, xmmword ptr [2*rbp - 512] -0x62,0xf2,0x47,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vp2intersectd k6, xmm23, xmmword ptr [rcx + 2032] -0x62,0xf2,0x47,0x00,0x68,0x71,0x7f - -# CHECK: vp2intersectd k6, xmm23, dword ptr [rdx - 512]{1to4} -0x62,0xf2,0x47,0x10,0x68,0x72,0x80 - -# CHECK: vp2intersectq k6, ymm23, ymm24 -0x62,0x92,0xc7,0x20,0x68,0xf0 - -# CHECK: vp2intersectq k6, xmm23, xmm24 -0x62,0x92,0xc7,0x00,0x68,0xf0 - -# CHECK: vp2intersectq k6, ymm23, ymmword ptr [rbp + 8*r14 + 268435456] -0x62,0xb2,0xc7,0x20,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectq k6, ymm23, ymmword ptr [r8 + 4*rax + 291] -0x62,0xd2,0xc7,0x20,0x68,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectq k6, ymm23, qword ptr [rip]{1to4} -0x62,0xf2,0xc7,0x30,0x68,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vp2intersectq k6, ymm23, ymmword ptr [2*rbp - 1024] -0x62,0xf2,0xc7,0x20,0x68,0x34,0x6d,0x00,0xfc,0xff,0xff - -# CHECK: vp2intersectq k6, ymm23, ymmword ptr [rcx + 4064] -0x62,0xf2,0xc7,0x20,0x68,0x71,0x7f - -# CHECK: vp2intersectq k6, ymm23, qword ptr [rdx - 1024]{1to4} -0x62,0xf2,0xc7,0x30,0x68,0x72,0x80 - -# CHECK: vp2intersectq k6, xmm23, xmmword ptr [rbp + 8*r14 + 268435456] -0x62,0xb2,0xc7,0x00,0x68,0xb4,0xf5,0x00,0x00,0x00,0x10 - -# CHECK: vp2intersectq k6, xmm23, xmmword ptr [r8 + 4*rax + 291] -0x62,0xd2,0xc7,0x00,0x68,0xb4,0x80,0x23,0x01,0x00,0x00 - -# CHECK: vp2intersectq k6, xmm23, qword ptr [rip]{1to2} -0x62,0xf2,0xc7,0x10,0x68,0x35,0x00,0x00,0x00,0x00 - -# CHECK: vp2intersectq k6, xmm23, xmmword ptr [2*rbp - 512] -0x62,0xf2,0xc7,0x00,0x68,0x34,0x6d,0x00,0xfe,0xff,0xff - -# CHECK: vp2intersectq k6, xmm23, xmmword ptr [rcx + 2032] -0x62,0xf2,0xc7,0x00,0x68,0x71,0x7f - -# CHECK: vp2intersectq k6, xmm23, qword ptr [rdx - 1024]{1to2} -0x62,0xf2,0xc7,0x10,0x68,0x72,0x80 diff --git a/llvm/test/MC/PowerPC/ppc32-ba.s b/llvm/test/MC/PowerPC/ppc32-ba.s index 133423b4e8c3..3b7814815534 100644 --- a/llvm/test/MC/PowerPC/ppc32-ba.s +++ b/llvm/test/MC/PowerPC/ppc32-ba.s @@ -1,6 +1,10 @@ # RUN: llvm-mc -triple powerpc-unknown-unknown --show-encoding %s | FileCheck %s -# Check that large immediates in 32bit mode are accepted. +# Check that large and/or negative immediates in 32-bit mode are accepted. -# CHECK: ba -33554432 # encoding: [0x4a,0x00,0x00,0x02] +# CHECK: ba 0xfe000000 # encoding: [0x4a,0x00,0x00,0x02] +# CHECK-NEXT: ba 0xfe000000 # encoding: [0x4a,0x00,0x00,0x02] +# CHECK-NEXT: ba 0xfffffc00 # encoding: [0x4b,0xff,0xfc,0x02] ba 0xfe000000 + ba (-33554432) + ba (-1024) diff --git a/llvm/test/MC/PowerPC/ppc64-operands.s b/llvm/test/MC/PowerPC/ppc64-operands.s index 9cd94bea6f81..366e1faf3135 100644 --- a/llvm/test/MC/PowerPC/ppc64-operands.s +++ b/llvm/test/MC/PowerPC/ppc64-operands.s @@ -128,16 +128,16 @@ # CHECK-LE: b .+1024 # encoding: [0x00,0x04,0x00,0x48] b 1024 -# CHECK-BE: ba 1024 # encoding: [0x48,0x00,0x04,0x02] -# CHECK-LE: ba 1024 # encoding: [0x02,0x04,0x00,0x48] +# CHECK-BE: ba 0x400 # encoding: [0x48,0x00,0x04,0x02] +# CHECK-LE: ba 0x400 # encoding: [0x02,0x04,0x00,0x48] ba 1024 # CHECK-BE: beq 0, .+1024 # encoding: [0x41,0x82,0x04,0x00] # CHECK-LE: beq 0, .+1024 # encoding: [0x00,0x04,0x82,0x41] beq 1024 -# CHECK-BE: beqa 0, 1024 # encoding: [0x41,0x82,0x04,0x02] -# CHECK-LE: beqa 0, 1024 # encoding: [0x02,0x04,0x82,0x41] +# CHECK-BE: beqa 0, 0x400 # encoding: [0x41,0x82,0x04,0x02] +# CHECK-LE: beqa 0, 0x400 # encoding: [0x02,0x04,0x82,0x41] beqa 1024 # CHECK-BE: # encoding: [0x42,0x9f,A,0bAAAAAA01] diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index aa919f266592..3ed48401e43f 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -309,5 +309,5 @@ .attribute arch, "rv32i_xcvbi" # CHECK: attribute 5, "rv32i2p1_xcvbi1p0" -.attribute arch, "rv32i_zicfilp0p2" -# CHECK: attribute 5, "rv32i2p1_zicfilp0p2" +.attribute arch, "rv32i_zicfilp0p4" +# CHECK: attribute 5, "rv32i2p1_zicfilp0p4" diff --git a/llvm/test/MC/X86/x86-32-avx.s b/llvm/test/MC/X86/avx-32-att.s index beba7faa1829..beba7faa1829 100644 --- a/llvm/test/MC/X86/x86-32-avx.s +++ b/llvm/test/MC/X86/avx-32-att.s diff --git a/llvm/test/MC/X86/x86_64-avx-encoding.s b/llvm/test/MC/X86/avx-64-att.s index 39ee048c3736..39ee048c3736 100644 --- a/llvm/test/MC/X86/x86_64-avx-encoding.s +++ b/llvm/test/MC/X86/avx-64-att.s diff --git a/llvm/test/MC/X86/intel-syntax-x86-64-avx.s b/llvm/test/MC/X86/avx-64-intel.s index c1f20d204a8c..c1f20d204a8c 100644 --- a/llvm/test/MC/X86/intel-syntax-x86-64-avx.s +++ b/llvm/test/MC/X86/avx-64-intel.s diff --git a/llvm/test/MC/X86/avx512-err.s b/llvm/test/MC/X86/avx512-att-errors.s index 96e8c267979f..96e8c267979f 100644 --- a/llvm/test/MC/X86/avx512-err.s +++ b/llvm/test/MC/X86/avx512-att-errors.s diff --git a/llvm/test/MC/X86/avx512-encodings.s b/llvm/test/MC/X86/avx512-att.s index d1f887852d51..d1f887852d51 100644 --- a/llvm/test/MC/X86/avx512-encodings.s +++ b/llvm/test/MC/X86/avx512-att.s diff --git a/llvm/test/MC/X86/intel-syntax-avx512-error.s b/llvm/test/MC/X86/avx512-intel-errors.s index 3454e3752a17..3454e3752a17 100644 --- a/llvm/test/MC/X86/intel-syntax-avx512-error.s +++ b/llvm/test/MC/X86/avx512-intel-errors.s diff --git a/llvm/test/MC/X86/intel-syntax-avx512.s b/llvm/test/MC/X86/avx512-intel.s index d8ad3c442617..d8ad3c442617 100644 --- a/llvm/test/MC/X86/intel-syntax-avx512.s +++ b/llvm/test/MC/X86/avx512-intel.s diff --git a/llvm/test/MC/X86/avx5124fmaps-encoding.s b/llvm/test/MC/X86/avx5124fmaps-att.s index 0e410745beb5..0e410745beb5 100644 --- a/llvm/test/MC/X86/avx5124fmaps-encoding.s +++ b/llvm/test/MC/X86/avx5124fmaps-att.s diff --git a/llvm/test/MC/X86/avx5124vnniw-encoding.s b/llvm/test/MC/X86/avx5124vnniw-att.s index a78d4bc4f8e7..a78d4bc4f8e7 100644 --- a/llvm/test/MC/X86/avx5124vnniw-encoding.s +++ b/llvm/test/MC/X86/avx5124vnniw-att.s diff --git a/llvm/test/MC/X86/avx512_bf16-encoding.s b/llvm/test/MC/X86/avx512_bf16-32-att.s index 675bc33dceb0..675bc33dceb0 100644 --- a/llvm/test/MC/X86/avx512_bf16-encoding.s +++ b/llvm/test/MC/X86/avx512_bf16-32-att.s diff --git a/llvm/test/MC/X86/intel-syntax-avx512_bf16.s b/llvm/test/MC/X86/avx512_bf16-32-intel.s index 3c9fca96deb6..3c9fca96deb6 100644 --- a/llvm/test/MC/X86/intel-syntax-avx512_bf16.s +++ b/llvm/test/MC/X86/avx512_bf16-32-intel.s diff --git a/llvm/test/MC/X86/x86-64-avx512_bf16-encoding.s b/llvm/test/MC/X86/avx512_bf16-64-att.s index dcd8f79fcb1b..dcd8f79fcb1b 100644 --- a/llvm/test/MC/X86/x86-64-avx512_bf16-encoding.s +++ b/llvm/test/MC/X86/avx512_bf16-64-att.s diff --git a/llvm/test/MC/X86/intel-syntax-x86-64-avx512_bf16.s b/llvm/test/MC/X86/avx512_bf16-64-intel.s index faaeaa7321d2..faaeaa7321d2 100644 --- a/llvm/test/MC/X86/intel-syntax-x86-64-avx512_bf16.s +++ b/llvm/test/MC/X86/avx512_bf16-64-intel.s diff --git a/llvm/test/MC/X86/avx512_bf16_vl-encoding.s b/llvm/test/MC/X86/avx512_bf16_vl-32-att.s index ffa42e25ed19..ffa42e25ed19 100644 --- a/llvm/test/MC/X86/avx512_bf16_vl-encoding.s +++ b/llvm/test/MC/X86/avx512_bf16_vl-32-att.s diff --git a/llvm/test/MC/X86/intel-syntax-avx512_bf16_vl.s b/llvm/test/MC/X86/avx512_bf16_vl-32-intel.s index d0310fd70289..d0310fd70289 100644 --- a/llvm/test/MC/X86/intel-syntax-avx512_bf16_vl.s +++ b/llvm/test/MC/X86/avx512_bf16_vl-32-intel.s diff --git a/llvm/test/MC/X86/x86-64-avx512_bf16_vl-encoding.s b/llvm/test/MC/X86/avx512_bf16_vl-64-att.s index 041a69008af7..041a69008af7 100644 --- a/llvm/test/MC/X86/x86-64-avx512_bf16_vl-encoding.s +++ b/llvm/test/MC/X86/avx512_bf16_vl-64-att.s diff --git a/llvm/test/MC/X86/intel-syntax-x86-64-avx512_bf16_vl.s b/llvm/test/MC/X86/avx512_bf16_vl-64-intel.s index e8c531175e1d..e8c531175e1d 100644 --- a/llvm/test/MC/X86/intel-syntax-x86-64-avx512_bf16_vl.s +++ b/llvm/test/MC/X86/avx512_bf16_vl-64-intel.s diff --git a/llvm/test/MC/X86/avx512bitalg-att.s b/llvm/test/MC/X86/avx512bitalg-att.s new file mode 100644 index 000000000000..3bf11ff8254e --- /dev/null +++ b/llvm/test/MC/X86/avx512bitalg-att.s @@ -0,0 +1,169 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s + +# CHECK: vpopcntb %zmm23, %zmm21 +# CHECK: encoding: [0x62,0xa2,0x7d,0x48,0x54,0xef] + vpopcntb %zmm23, %zmm21 + +# CHECK: vpopcntw %zmm23, %zmm21 +# CHECK: encoding: [0x62,0xa2,0xfd,0x48,0x54,0xef] + vpopcntw %zmm23, %zmm21 + +# CHECK: vpopcntb %zmm3, %zmm1 {%k2} +# CHECK: encoding: [0x62,0xf2,0x7d,0x4a,0x54,0xcb] + vpopcntb %zmm3, %zmm1 {%k2} + +# CHECK: vpopcntw %zmm3, %zmm1 {%k2} +# CHECK: encoding: [0x62,0xf2,0xfd,0x4a,0x54,0xcb] + vpopcntw %zmm3, %zmm1 {%k2} + +# CHECK: vpopcntb (%rcx), %zmm1 +# CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x09] + vpopcntb (%rcx), %zmm1 + +# CHECK: vpopcntb -256(%rsp), %zmm1 +# CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0xfc] + vpopcntb -256(%rsp), %zmm1 + +# CHECK: vpopcntb 256(%rsp), %zmm1 +# CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0x04] + vpopcntb 256(%rsp), %zmm1 + +# CHECK: vpopcntb 268435456(%rcx,%r14,8), %zmm1 +# CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0x10] + vpopcntb 268435456(%rcx,%r14,8), %zmm1 + +# CHECK: vpopcntb -536870912(%rcx,%r14,8), %zmm1 +# CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0xe0] + vpopcntb -536870912(%rcx,%r14,8), %zmm1 + +# CHECK: vpopcntb -536870910(%rcx,%r14,8), %zmm1 +# CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x02,0x00,0x00,0xe0] + vpopcntb -536870910(%rcx,%r14,8), %zmm1 + +# CHECK: vpopcntw (%rcx), %zmm1 +# CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x54,0x09] + vpopcntw (%rcx), %zmm1 + +# CHECK: vpopcntw -256(%rsp), %zmm1 +# CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x54,0x4c,0x24,0xfc] + vpopcntw -256(%rsp), %zmm1 + +# CHECK: vpopcntw 256(%rsp), %zmm1 +# CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x54,0x4c,0x24,0x04] + vpopcntw 256(%rsp), %zmm1 + +# CHECK: vpopcntw 268435456(%rcx,%r14,8), %zmm1 +# CHECK: encoding: [0x62,0xb2,0xfd,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0x10] + vpopcntw 268435456(%rcx,%r14,8), %zmm1 + +# CHECK: vpopcntw -536870912(%rcx,%r14,8), %zmm1 +# CHECK: encoding: [0x62,0xb2,0xfd,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0xe0] + vpopcntw -536870912(%rcx,%r14,8), %zmm1 + +# CHECK: vpopcntw -536870910(%rcx,%r14,8), %zmm1 +# CHECK: encoding: [0x62,0xb2,0xfd,0x48,0x54,0x8c,0xf1,0x02,0x00,0x00,0xe0] + vpopcntw -536870910(%rcx,%r14,8), %zmm1 + +# CHECK: vpopcntb (%rcx), %zmm21 {%k2} +# CHECK: encoding: [0x62,0xe2,0x7d,0x4a,0x54,0x29] + vpopcntb (%rcx), %zmm21 {%k2} + +# CHECK: vpopcntb -256(%rsp), %zmm21 {%k2} +# CHECK: encoding: [0x62,0xe2,0x7d,0x4a,0x54,0x6c,0x24,0xfc] + vpopcntb -256(%rsp), %zmm21 {%k2} + +# CHECK: vpopcntb 256(%rsp), %zmm21 {%k2} +# CHECK: encoding: [0x62,0xe2,0x7d,0x4a,0x54,0x6c,0x24,0x04] + vpopcntb 256(%rsp), %zmm21 {%k2} + +# CHECK: vpopcntb 268435456(%rcx,%r14,8), %zmm21 {%k2} +# CHECK: encoding: [0x62,0xa2,0x7d,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0x10] + vpopcntb 268435456(%rcx,%r14,8), %zmm21 {%k2} + +# CHECK: vpopcntb -536870912(%rcx,%r14,8), %zmm21 {%k2} +# CHECK: encoding: [0x62,0xa2,0x7d,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0xe0] + vpopcntb -536870912(%rcx,%r14,8), %zmm21 {%k2} + +# CHECK: vpopcntb -536870910(%rcx,%r14,8), %zmm21 {%k2} +# CHECK: encoding: [0x62,0xa2,0x7d,0x4a,0x54,0xac,0xf1,0x02,0x00,0x00,0xe0] + vpopcntb -536870910(%rcx,%r14,8), %zmm21 {%k2} + +# CHECK: vpopcntw (%rcx), %zmm21 {%k2} +# CHECK: encoding: [0x62,0xe2,0xfd,0x4a,0x54,0x29] + vpopcntw (%rcx), %zmm21 {%k2} + +# CHECK: vpopcntw -256(%rsp), %zmm21 {%k2} +# CHECK: encoding: [0x62,0xe2,0xfd,0x4a,0x54,0x6c,0x24,0xfc] + vpopcntw -256(%rsp), %zmm21 {%k2} + +# CHECK: vpopcntw 256(%rsp), %zmm21 {%k2} +# CHECK: encoding: [0x62,0xe2,0xfd,0x4a,0x54,0x6c,0x24,0x04] + vpopcntw 256(%rsp), %zmm21 {%k2} + +# CHECK: vpopcntw 268435456(%rcx,%r14,8), %zmm21 {%k2} +# CHECK: encoding: [0x62,0xa2,0xfd,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0x10] + vpopcntw 268435456(%rcx,%r14,8), %zmm21 {%k2} + +# CHECK: vpopcntw -536870912(%rcx,%r14,8), %zmm21 {%k2} +# CHECK: encoding: [0x62,0xa2,0xfd,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0xe0] + vpopcntw -536870912(%rcx,%r14,8), %zmm21 {%k2} + +# CHECK: vpopcntw -536870910(%rcx,%r14,8), %zmm21 {%k2} +# CHECK: encoding: [0x62,0xa2,0xfd,0x4a,0x54,0xac,0xf1,0x02,0x00,0x00,0xe0] + vpopcntw -536870910(%rcx,%r14,8), %zmm21 {%k2} + +# CHECK: vpshufbitqmb %zmm2, %zmm23, %k1 +# CHECK: encoding: [0x62,0xf2,0x45,0x40,0x8f,0xca] + vpshufbitqmb %zmm2, %zmm23, %k1 + +# CHECK: vpshufbitqmb %zmm2, %zmm23, %k1 {%k2} +# CHECK: encoding: [0x62,0xf2,0x45,0x42,0x8f,0xca] + vpshufbitqmb %zmm2, %zmm23, %k1 {%k2} + +# CHECK: vpshufbitqmb (%rcx), %zmm23, %k1 +# CHECK: encoding: [0x62,0xf2,0x45,0x40,0x8f,0x09] + vpshufbitqmb (%rcx), %zmm23, %k1 + +# CHECK: vpshufbitqmb -256(%rsp), %zmm23, %k1 +# CHECK: encoding: [0x62,0xf2,0x45,0x40,0x8f,0x4c,0x24,0xfc] + vpshufbitqmb -256(%rsp), %zmm23, %k1 + +# CHECK: vpshufbitqmb 256(%rsp), %zmm23, %k1 +# CHECK: encoding: [0x62,0xf2,0x45,0x40,0x8f,0x4c,0x24,0x04] + vpshufbitqmb 256(%rsp), %zmm23, %k1 + +# CHECK: vpshufbitqmb 268435456(%rcx,%r14,8), %zmm23, %k1 +# CHECK: encoding: [0x62,0xb2,0x45,0x40,0x8f,0x8c,0xf1,0x00,0x00,0x00,0x10] + vpshufbitqmb 268435456(%rcx,%r14,8), %zmm23, %k1 + +# CHECK: vpshufbitqmb -536870912(%rcx,%r14,8), %zmm23, %k1 +# CHECK: encoding: [0x62,0xb2,0x45,0x40,0x8f,0x8c,0xf1,0x00,0x00,0x00,0xe0] + vpshufbitqmb -536870912(%rcx,%r14,8), %zmm23, %k1 + +# CHECK: vpshufbitqmb -536870910(%rcx,%r14,8), %zmm23, %k1 +# CHECK: encoding: [0x62,0xb2,0x45,0x40,0x8f,0x8c,0xf1,0x02,0x00,0x00,0xe0] + vpshufbitqmb -536870910(%rcx,%r14,8), %zmm23, %k1 + +# CHECK: vpshufbitqmb (%rcx), %zmm23, %k1 {%k2} +# CHECK: encoding: [0x62,0xf2,0x45,0x42,0x8f,0x09] + vpshufbitqmb (%rcx), %zmm23, %k1 {%k2} + +# CHECK: vpshufbitqmb -256(%rsp), %zmm23, %k1 {%k2} +# CHECK: encoding: [0x62,0xf2,0x45,0x42,0x8f,0x4c,0x24,0xfc] + vpshufbitqmb -256(%rsp), %zmm23, %k1 {%k2} + +# CHECK: vpshufbitqmb 256(%rsp), %zmm23, %k1 {%k2} +# CHECK: encoding: [0x62,0xf2,0x45,0x42,0x8f,0x4c,0x24,0x04] + vpshufbitqmb 256(%rsp), %zmm23, %k1 {%k2} + +# CHECK: vpshufbitqmb 268435456(%rcx,%r14,8), %zmm23, %k1 {%k2} +# CHECK: encoding: [0x62,0xb2,0x45,0x42,0x8f,0x8c,0xf1,0x00,0x00,0x00,0x10] + vpshufbitqmb 268435456(%rcx,%r14,8), %zmm23, %k1 {%k2} + +# CHECK: vpshufbitqmb -536870912(%rcx,%r14,8), %zmm23, %k1 {%k2} +# CHECK: encoding: [0x62,0xb2,0x45,0x42,0x8f,0x8c,0xf1,0x00,0x00,0x00,0xe0] + vpshufbitqmb -536870912(%rcx,%r14,8), %zmm23, %k1 {%k2} + +# CHECK: vpshufbitqmb -536870910(%rcx,%r14,8), %zmm23, %k1 {%k2} +# CHECK: encoding: [0x62,0xb2,0x45,0x42,0x8f,0x8c,0xf1,0x02,0x00,0x00,0xe0] + vpshufbitqmb -536870910(%rcx,%r14,8), %zmm23, %k1 {%k2} diff --git a/llvm/test/MC/X86/avx512bitalg-encoding.s b/llvm/test/MC/X86/avx512bitalg-encoding.s deleted file mode 100644 index f8b507adfc09..000000000000 --- a/llvm/test/MC/X86/avx512bitalg-encoding.s +++ /dev/null @@ -1,170 +0,0 @@ -// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding < %s | FileCheck %s - -// CHECK: vpopcntb %zmm23, %zmm21 -// CHECK: encoding: [0x62,0xa2,0x7d,0x48,0x54,0xef] - vpopcntb %zmm23, %zmm21 - -// CHECK: vpopcntw %zmm23, %zmm21 -// CHECK: encoding: [0x62,0xa2,0xfd,0x48,0x54,0xef] - vpopcntw %zmm23, %zmm21 - -// CHECK: vpopcntb %zmm3, %zmm1 {%k2} -// CHECK: encoding: [0x62,0xf2,0x7d,0x4a,0x54,0xcb] - vpopcntb %zmm3, %zmm1 {%k2} - -// CHECK: vpopcntw %zmm3, %zmm1 {%k2} -// CHECK: encoding: [0x62,0xf2,0xfd,0x4a,0x54,0xcb] - vpopcntw %zmm3, %zmm1 {%k2} - -// CHECK: vpopcntb (%rcx), %zmm1 -// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x09] - vpopcntb (%rcx), %zmm1 - -// CHECK: vpopcntb -256(%rsp), %zmm1 -// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0xfc] - vpopcntb -256(%rsp), %zmm1 - -// CHECK: vpopcntb 256(%rsp), %zmm1 -// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0x04] - vpopcntb 256(%rsp), %zmm1 - -// CHECK: vpopcntb 268435456(%rcx,%r14,8), %zmm1 -// CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0x10] - vpopcntb 268435456(%rcx,%r14,8), %zmm1 - -// CHECK: vpopcntb -536870912(%rcx,%r14,8), %zmm1 -// CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0xe0] - vpopcntb -536870912(%rcx,%r14,8), %zmm1 - -// CHECK: vpopcntb -536870910(%rcx,%r14,8), %zmm1 -// CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x02,0x00,0x00,0xe0] - vpopcntb -536870910(%rcx,%r14,8), %zmm1 - -// CHECK: vpopcntw (%rcx), %zmm1 -// CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x54,0x09] - vpopcntw (%rcx), %zmm1 - -// CHECK: vpopcntw -256(%rsp), %zmm1 -// CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x54,0x4c,0x24,0xfc] - vpopcntw -256(%rsp), %zmm1 - -// CHECK: vpopcntw 256(%rsp), %zmm1 -// CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x54,0x4c,0x24,0x04] - vpopcntw 256(%rsp), %zmm1 - -// CHECK: vpopcntw 268435456(%rcx,%r14,8), %zmm1 -// CHECK: encoding: [0x62,0xb2,0xfd,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0x10] - vpopcntw 268435456(%rcx,%r14,8), %zmm1 - -// CHECK: vpopcntw -536870912(%rcx,%r14,8), %zmm1 -// CHECK: encoding: [0x62,0xb2,0xfd,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0xe0] - vpopcntw -536870912(%rcx,%r14,8), %zmm1 - -// CHECK: vpopcntw -536870910(%rcx,%r14,8), %zmm1 -// CHECK: encoding: [0x62,0xb2,0xfd,0x48,0x54,0x8c,0xf1,0x02,0x00,0x00,0xe0] - vpopcntw -536870910(%rcx,%r14,8), %zmm1 - -// CHECK: vpopcntb (%rcx), %zmm21 {%k2} -// CHECK: encoding: [0x62,0xe2,0x7d,0x4a,0x54,0x29] - vpopcntb (%rcx), %zmm21 {%k2} - -// CHECK: vpopcntb -256(%rsp), %zmm21 {%k2} -// CHECK: encoding: [0x62,0xe2,0x7d,0x4a,0x54,0x6c,0x24,0xfc] - vpopcntb -256(%rsp), %zmm21 {%k2} - -// CHECK: vpopcntb 256(%rsp), %zmm21 {%k2} -// CHECK: encoding: [0x62,0xe2,0x7d,0x4a,0x54,0x6c,0x24,0x04] - vpopcntb 256(%rsp), %zmm21 {%k2} - -// CHECK: vpopcntb 268435456(%rcx,%r14,8), %zmm21 {%k2} -// CHECK: encoding: [0x62,0xa2,0x7d,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0x10] - vpopcntb 268435456(%rcx,%r14,8), %zmm21 {%k2} - -// CHECK: vpopcntb -536870912(%rcx,%r14,8), %zmm21 {%k2} -// CHECK: encoding: [0x62,0xa2,0x7d,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0xe0] - vpopcntb -536870912(%rcx,%r14,8), %zmm21 {%k2} - -// CHECK: vpopcntb -536870910(%rcx,%r14,8), %zmm21 {%k2} -// CHECK: encoding: [0x62,0xa2,0x7d,0x4a,0x54,0xac,0xf1,0x02,0x00,0x00,0xe0] - vpopcntb -536870910(%rcx,%r14,8), %zmm21 {%k2} - -// CHECK: vpopcntw (%rcx), %zmm21 {%k2} -// CHECK: encoding: [0x62,0xe2,0xfd,0x4a,0x54,0x29] - vpopcntw (%rcx), %zmm21 {%k2} - -// CHECK: vpopcntw -256(%rsp), %zmm21 {%k2} -// CHECK: encoding: [0x62,0xe2,0xfd,0x4a,0x54,0x6c,0x24,0xfc] - vpopcntw -256(%rsp), %zmm21 {%k2} - -// CHECK: vpopcntw 256(%rsp), %zmm21 {%k2} -// CHECK: encoding: [0x62,0xe2,0xfd,0x4a,0x54,0x6c,0x24,0x04] - vpopcntw 256(%rsp), %zmm21 {%k2} - -// CHECK: vpopcntw 268435456(%rcx,%r14,8), %zmm21 {%k2} -// CHECK: encoding: [0x62,0xa2,0xfd,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0x10] - vpopcntw 268435456(%rcx,%r14,8), %zmm21 {%k2} - -// CHECK: vpopcntw -536870912(%rcx,%r14,8), %zmm21 {%k2} -// CHECK: encoding: [0x62,0xa2,0xfd,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0xe0] - vpopcntw -536870912(%rcx,%r14,8), %zmm21 {%k2} - -// CHECK: vpopcntw -536870910(%rcx,%r14,8), %zmm21 {%k2} -// CHECK: encoding: [0x62,0xa2,0xfd,0x4a,0x54,0xac,0xf1,0x02,0x00,0x00,0xe0] - vpopcntw -536870910(%rcx,%r14,8), %zmm21 {%k2} - -// CHECK: vpshufbitqmb %zmm2, %zmm23, %k1 -// CHECK: encoding: [0x62,0xf2,0x45,0x40,0x8f,0xca] - vpshufbitqmb %zmm2, %zmm23, %k1 - -// CHECK: vpshufbitqmb %zmm2, %zmm23, %k1 {%k2} -// CHECK: encoding: [0x62,0xf2,0x45,0x42,0x8f,0xca] - vpshufbitqmb %zmm2, %zmm23, %k1 {%k2} - -// CHECK: vpshufbitqmb (%rcx), %zmm23, %k1 -// CHECK: encoding: [0x62,0xf2,0x45,0x40,0x8f,0x09] - vpshufbitqmb (%rcx), %zmm23, %k1 - -// CHECK: vpshufbitqmb -256(%rsp), %zmm23, %k1 -// CHECK: encoding: [0x62,0xf2,0x45,0x40,0x8f,0x4c,0x24,0xfc] - vpshufbitqmb -256(%rsp), %zmm23, %k1 - -// CHECK: vpshufbitqmb 256(%rsp), %zmm23, %k1 -// CHECK: encoding: [0x62,0xf2,0x45,0x40,0x8f,0x4c,0x24,0x04] - vpshufbitqmb 256(%rsp), %zmm23, %k1 - -// CHECK: vpshufbitqmb 268435456(%rcx,%r14,8), %zmm23, %k1 -// CHECK: encoding: [0x62,0xb2,0x45,0x40,0x8f,0x8c,0xf1,0x00,0x00,0x00,0x10] - vpshufbitqmb 268435456(%rcx,%r14,8), %zmm23, %k1 - -// CHECK: vpshufbitqmb -536870912(%rcx,%r14,8), %zmm23, %k1 -// CHECK: encoding: [0x62,0xb2,0x45,0x40,0x8f,0x8c,0xf1,0x00,0x00,0x00,0xe0] - vpshufbitqmb -536870912(%rcx,%r14,8), %zmm23, %k1 - -// CHECK: vpshufbitqmb -536870910(%rcx,%r14,8), %zmm23, %k1 -// CHECK: encoding: [0x62,0xb2,0x45,0x40,0x8f,0x8c,0xf1,0x02,0x00,0x00,0xe0] - vpshufbitqmb -536870910(%rcx,%r14,8), %zmm23, %k1 - -// CHECK: vpshufbitqmb (%rcx), %zmm23, %k1 {%k2} -// CHECK: encoding: [0x62,0xf2,0x45,0x42,0x8f,0x09] - vpshufbitqmb (%rcx), %zmm23, %k1 {%k2} - -// CHECK: vpshufbitqmb -256(%rsp), %zmm23, %k1 {%k2} -// CHECK: encoding: [0x62,0xf2,0x45,0x42,0x8f,0x4c,0x24,0xfc] - vpshufbitqmb -256(%rsp), %zmm23, %k1 {%k2} - -// CHECK: vpshufbitqmb 256(%rsp), %zmm23, %k1 {%k2} -// CHECK: encoding: [0x62,0xf2,0x45,0x42,0x8f,0x4c,0x24,0x04] - vpshufbitqmb 256(%rsp), %zmm23, %k1 {%k2} - -// CHECK: vpshufbitqmb 268435456(%rcx,%r14,8), %zmm23, %k1 {%k2} -// CHECK: encoding: [0x62,0xb2,0x45,0x42,0x8f,0x8c,0xf1,0x00,0x00,0x00,0x10] - vpshufbitqmb 268435456(%rcx,%r14,8), %zmm23, %k1 {%k2} - -// CHECK: vpshufbitqmb -536870912(%rcx,%r14,8), %zmm23, %k1 {%k2} -// CHECK: encoding: [0x62,0xb2,0x45,0x42,0x8f,0x8c,0xf1,0x00,0x00,0x00,0xe0] - vpshufbitqmb -536870912(%rcx,%r14,8), %zmm23, %k1 {%k2} - -// CHECK: vpshufbitqmb -536870910(%rcx,%r14,8), %zmm23, %k1 {%k2} -// CHECK: encoding: [0x62,0xb2,0x45,0x42,0x8f,0x8c,0xf1,0x02,0x00,0x00,0xe0] - vpshufbitqmb -536870910(%rcx,%r14,8), %zmm23, %k1 {%k2} - diff --git a/llvm/test/MC/X86/avx512bitalg-intel.s b/llvm/test/MC/X86/avx512bitalg-intel.s new file mode 100644 index 000000000000..ab5e3ff0c1b7 --- /dev/null +++ b/llvm/test/MC/X86/avx512bitalg-intel.s @@ -0,0 +1,169 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s + +# CHECK: vpopcntb zmm21, zmm23 +# CHECK: encoding: [0x62,0xa2,0x7d,0x48,0x54,0xef] + vpopcntb zmm21, zmm23 + +# CHECK: vpopcntw zmm21, zmm23 +# CHECK: encoding: [0x62,0xa2,0xfd,0x48,0x54,0xef] + vpopcntw zmm21, zmm23 + +# CHECK: vpopcntb zmm1 {k2}, zmm3 +# CHECK: encoding: [0x62,0xf2,0x7d,0x4a,0x54,0xcb] + vpopcntb zmm1 {k2}, zmm3 + +# CHECK: vpopcntw zmm1 {k2}, zmm3 +# CHECK: encoding: [0x62,0xf2,0xfd,0x4a,0x54,0xcb] + vpopcntw zmm1 {k2}, zmm3 + +# CHECK: vpopcntb zmm1, zmmword ptr [rcx] +# CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x09] + vpopcntb zmm1, zmmword ptr [rcx] + +# CHECK: vpopcntb zmm1, zmmword ptr [rsp - 256] +# CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0xfc] + vpopcntb zmm1, zmmword ptr [rsp - 256] + +# CHECK: vpopcntb zmm1, zmmword ptr [rsp + 256] +# CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x54,0x4c,0x24,0x04] + vpopcntb zmm1, zmmword ptr [rsp + 256] + +# CHECK: vpopcntb zmm1, zmmword ptr [rcx + 8*r14 + 268435456] +# CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0x10] + vpopcntb zmm1, zmmword ptr [rcx + 8*r14 + 268435456] + +# CHECK: vpopcntb zmm1, zmmword ptr [rcx + 8*r14 - 536870912] +# CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0xe0] + vpopcntb zmm1, zmmword ptr [rcx + 8*r14 - 536870912] + +# CHECK: vpopcntb zmm1, zmmword ptr [rcx + 8*r14 - 536870910] +# CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x54,0x8c,0xf1,0x02,0x00,0x00,0xe0] + vpopcntb zmm1, zmmword ptr [rcx + 8*r14 - 536870910] + +# CHECK: vpopcntw zmm1, zmmword ptr [rcx] +# CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x54,0x09] + vpopcntw zmm1, zmmword ptr [rcx] + +# CHECK: vpopcntw zmm1, zmmword ptr [rsp - 256] +# CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x54,0x4c,0x24,0xfc] + vpopcntw zmm1, zmmword ptr [rsp - 256] + +# CHECK: vpopcntw zmm1, zmmword ptr [rsp + 256] +# CHECK: encoding: [0x62,0xf2,0xfd,0x48,0x54,0x4c,0x24,0x04] + vpopcntw zmm1, zmmword ptr [rsp + 256] + +# CHECK: vpopcntw zmm1, zmmword ptr [rcx + 8*r14 + 268435456] +# CHECK: encoding: [0x62,0xb2,0xfd,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0x10] + vpopcntw zmm1, zmmword ptr [rcx + 8*r14 + 268435456] + +# CHECK: vpopcntw zmm1, zmmword ptr [rcx + 8*r14 - 536870912] +# CHECK: encoding: [0x62,0xb2,0xfd,0x48,0x54,0x8c,0xf1,0x00,0x00,0x00,0xe0] + vpopcntw zmm1, zmmword ptr [rcx + 8*r14 - 536870912] + +# CHECK: vpopcntw zmm1, zmmword ptr [rcx + 8*r14 - 536870910] +# CHECK: encoding: [0x62,0xb2,0xfd,0x48,0x54,0x8c,0xf1,0x02,0x00,0x00,0xe0] + vpopcntw zmm1, zmmword ptr [rcx + 8*r14 - 536870910] + +# CHECK: vpopcntb zmm21 {k2}, zmmword ptr [rcx] +# CHECK: encoding: [0x62,0xe2,0x7d,0x4a,0x54,0x29] + vpopcntb zmm21 {k2}, zmmword ptr [rcx] + +# CHECK: vpopcntb zmm21 {k2}, zmmword ptr [rsp - 256] +# CHECK: encoding: [0x62,0xe2,0x7d,0x4a,0x54,0x6c,0x24,0xfc] + vpopcntb zmm21 {k2}, zmmword ptr [rsp - 256] + +# CHECK: vpopcntb zmm21 {k2}, zmmword ptr [rsp + 256] +# CHECK: encoding: [0x62,0xe2,0x7d,0x4a,0x54,0x6c,0x24,0x04] + vpopcntb zmm21 {k2}, zmmword ptr [rsp + 256] + +# CHECK: vpopcntb zmm21 {k2}, zmmword ptr [rcx + 8*r14 + 268435456] +# CHECK: encoding: [0x62,0xa2,0x7d,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0x10] + vpopcntb zmm21 {k2}, zmmword ptr [rcx + 8*r14 + 268435456] + +# CHECK: vpopcntb zmm21 {k2}, zmmword ptr [rcx + 8*r14 - 536870912] +# CHECK: encoding: [0x62,0xa2,0x7d,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0xe0] + vpopcntb zmm21 {k2}, zmmword ptr [rcx + 8*r14 - 536870912] + +# CHECK: vpopcntb zmm21 {k2}, zmmword ptr [rcx + 8*r14 - 536870910] +# CHECK: encoding: [0x62,0xa2,0x7d,0x4a,0x54,0xac,0xf1,0x02,0x00,0x00,0xe0] + vpopcntb zmm21 {k2}, zmmword ptr [rcx + 8*r14 - 536870910] + +# CHECK: vpopcntw zmm21 {k2}, zmmword ptr [rcx] +# CHECK: encoding: [0x62,0xe2,0xfd,0x4a,0x54,0x29] + vpopcntw zmm21 {k2}, zmmword ptr [rcx] + +# CHECK: vpopcntw zmm21 {k2}, zmmword ptr [rsp - 256] +# CHECK: encoding: [0x62,0xe2,0xfd,0x4a,0x54,0x6c,0x24,0xfc] + vpopcntw zmm21 {k2}, zmmword ptr [rsp - 256] + +# CHECK: vpopcntw zmm21 {k2}, zmmword ptr [rsp + 256] +# CHECK: encoding: [0x62,0xe2,0xfd,0x4a,0x54,0x6c,0x24,0x04] + vpopcntw zmm21 {k2}, zmmword ptr [rsp + 256] + +# CHECK: vpopcntw zmm21 {k2}, zmmword ptr [rcx + 8*r14 + 268435456] +# CHECK: encoding: [0x62,0xa2,0xfd,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0x10] + vpopcntw zmm21 {k2}, zmmword ptr [rcx + 8*r14 + 268435456] + +# CHECK: vpopcntw zmm21 {k2}, zmmword ptr [rcx + 8*r14 - 536870912] +# CHECK: encoding: [0x62,0xa2,0xfd,0x4a,0x54,0xac,0xf1,0x00,0x00,0x00,0xe0] + vpopcntw zmm21 {k2}, zmmword ptr [rcx + 8*r14 - 536870912] + +# CHECK: vpopcntw zmm21 {k2}, zmmword ptr [rcx + 8*r14 - 536870910] +# CHECK: encoding: [0x62,0xa2,0xfd,0x4a,0x54,0xac,0xf1,0x02,0x00,0x00,0xe0] + vpopcntw zmm21 {k2}, zmmword ptr [rcx + 8*r14 - 536870910] + +# CHECK: vpshufbitqmb k1, zmm23, zmm2 +# CHECK: encoding: [0x62,0xf2,0x45,0x40,0x8f,0xca] + vpshufbitqmb k1, zmm23, zmm2 + +# CHECK: vpshufbitqmb k1 {k2}, zmm23, zmm2 +# CHECK: encoding: [0x62,0xf2,0x45,0x42,0x8f,0xca] + vpshufbitqmb k1 {k2}, zmm23, zmm2 + +# CHECK: vpshufbitqmb k1, zmm23, zmmword ptr [rcx] +# CHECK: encoding: [0x62,0xf2,0x45,0x40,0x8f,0x09] + vpshufbitqmb k1, zmm23, zmmword ptr [rcx] + +# CHECK: vpshufbitqmb k1, zmm23, zmmword ptr [rsp - 256] +# CHECK: encoding: [0x62,0xf2,0x45,0x40,0x8f,0x4c,0x24,0xfc] + vpshufbitqmb k1, zmm23, zmmword ptr [rsp - 256] + +# CHECK: vpshufbitqmb k1, zmm23, zmmword ptr [rsp + 256] +# CHECK: encoding: [0x62,0xf2,0x45,0x40,0x8f,0x4c,0x24,0x04] + vpshufbitqmb k1, zmm23, zmmword ptr [rsp + 256] + +# CHECK: vpshufbitqmb k1, zmm23, zmmword ptr [rcx + 8*r14 + 268435456] +# CHECK: encoding: [0x62,0xb2,0x45,0x40,0x8f,0x8c,0xf1,0x00,0x00,0x00,0x10] + vpshufbitqmb k1, zmm23, zmmword ptr [rcx + 8*r14 + 268435456] + +# CHECK: vpshufbitqmb k1, zmm23, zmmword ptr [rcx + 8*r14 - 536870912] +# CHECK: encoding: [0x62,0xb2,0x45,0x40,0x8f,0x8c,0xf1,0x00,0x00,0x00,0xe0] + vpshufbitqmb k1, zmm23, zmmword ptr [rcx + 8*r14 - 536870912] + +# CHECK: vpshufbitqmb k1, zmm23, zmmword ptr [rcx + 8*r14 - 536870910] +# CHECK: encoding: [0x62,0xb2,0x45,0x40,0x8f,0x8c,0xf1,0x02,0x00,0x00,0xe0] + vpshufbitqmb k1, zmm23, zmmword ptr [rcx + 8*r14 - 536870910] + +# CHECK: vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rcx] +# CHECK: encoding: [0x62,0xf2,0x45,0x42,0x8f,0x09] + vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rcx] + +# CHECK: vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rsp - 256] +# CHECK: encoding: [0x62,0xf2,0x45,0x42,0x8f,0x4c,0x24,0xfc] + vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rsp - 256] + +# CHECK: vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rsp + 256] +# CHECK: encoding: [0x62,0xf2,0x45,0x42,0x8f,0x4c,0x24,0x04] + vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rsp + 256] + +# CHECK: vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rcx + 8*r14 + 268435456] +# CHECK: encoding: [0x62,0xb2,0x45,0x42,0x8f,0x8c,0xf1,0x00,0x00,0x00,0x10] + vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rcx + 8*r14 + 268435456] + +# CHECK: vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rcx + 8*r14 - 536870912] +# CHECK: encoding: [0x62,0xb2,0x45,0x42,0x8f,0x8c,0xf1,0x00,0x00,0x00,0xe0] + vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rcx + 8*r14 - 536870912] + +# CHECK: vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rcx + 8*r14 - 536870910] +# CHECK: encoding: [0x62,0xb2,0x45,0x42,0x8f,0x8c,0xf1,0x02,0x00,0x00,0xe0] + vpshufbitqmb k1 {k2}, zmm23, zmmword ptr [rcx + 8*r14 - 536870910] diff --git a/llvm/test/MC/X86/x86-64-avx512bw.s b/llvm/test/MC/X86/avx512bw-64-att.s index 1fedc377d3d5..1fedc377d3d5 100644 --- a/llvm/test/MC/X86/x86-64-avx512bw.s +++ b/llvm/test/MC/X86/avx512bw-64-att.s diff --git a/llvm/test/MC/X86/avx512bw-encoding.s b/llvm/test/MC/X86/avx512bw-att.s index 317f7ae89739..317f7ae89739 100644 --- a/llvm/test/MC/X86/avx512bw-encoding.s +++ b/llvm/test/MC/X86/avx512bw-att.s diff --git a/llvm/test/MC/X86/x86-64-avx512bw_vl.s b/llvm/test/MC/X86/avx512bw_vl-64-att.s index f423b6ff5336..f423b6ff5336 100644 --- a/llvm/test/MC/X86/x86-64-avx512bw_vl.s +++ b/llvm/test/MC/X86/avx512bw_vl-64-att.s diff --git a/llvm/test/MC/X86/x86-64-avx512cd.s b/llvm/test/MC/X86/avx512cd-att.s index 54cbdcb05643..54cbdcb05643 100644 --- a/llvm/test/MC/X86/x86-64-avx512cd.s +++ b/llvm/test/MC/X86/avx512cd-att.s diff --git a/llvm/test/MC/X86/x86-64-avx512cd_vl.s b/llvm/test/MC/X86/avx512cd_vl-att.s index 8919f9b06c83..8919f9b06c83 100644 --- a/llvm/test/MC/X86/x86-64-avx512cd_vl.s +++ b/llvm/test/MC/X86/avx512cd_vl-att.s diff --git a/llvm/test/MC/X86/x86-64-avx512dq.s b/llvm/test/MC/X86/avx512dq-att.s index 4510352ee7ce..4510352ee7ce 100644 --- a/llvm/test/MC/X86/x86-64-avx512dq.s +++ b/llvm/test/MC/X86/avx512dq-att.s diff --git a/llvm/test/MC/X86/avx512dq_vl-att.s b/llvm/test/MC/X86/avx512dq_vl-att.s new file mode 100644 index 000000000000..59600f726d7d --- /dev/null +++ b/llvm/test/MC/X86/avx512dq_vl-att.s @@ -0,0 +1,149 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s + +# CHECK: vcvtps2qq 128(%rcx), %xmm2 {%k2} {z} +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7b,0x51,0x10] + vcvtps2qq 128(%rcx), %xmm2 {%k2} {z} +# CHECK: vcvtps2qq 128(%rcx), %xmm2 {%k2} +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7b,0x51,0x10] + vcvtps2qq 128(%rcx), %xmm2 {%k2} +# CHECK: vcvtps2qq 128(%rcx), %xmm2 +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7b,0x51,0x10] + vcvtps2qq 128(%rcx), %xmm2 +# CHECK: vcvttps2qq 128(%rcx), %xmm1 {%k2} {z} +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7a,0x49,0x10] + vcvttps2qq 128(%rcx), %xmm1 {%k2} {z} +# CHECK: vcvttps2qq 128(%rcx), %xmm1 {%k2} +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7a,0x49,0x10] + vcvttps2qq 128(%rcx), %xmm1 {%k2} +# CHECK: vcvttps2qq 128(%rcx), %xmm1 +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7a,0x49,0x10] + vcvttps2qq 128(%rcx), %xmm1 +# CHECK: vcvtps2uqq 128(%rcx), %xmm1 {%k2} {z} +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x79,0x49,0x10] + vcvtps2uqq 128(%rcx), %xmm1 {%k2} {z} +# CHECK: vcvtps2uqq 128(%rcx), %xmm1 {%k2} +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x79,0x49,0x10] + vcvtps2uqq 128(%rcx), %xmm1 {%k2} +# CHECK: vcvtps2uqq 128(%rcx), %xmm1 +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x79,0x49,0x10] + vcvtps2uqq 128(%rcx), %xmm1 +# CHECK: vcvttps2uqq 128(%rcx), %xmm1 {%k2} {z} +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x78,0x49,0x10] + vcvttps2uqq 128(%rcx), %xmm1 {%k2} {z} +# CHECK: vcvttps2uqq 128(%rcx), %xmm1 {%k2} +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10] + vcvttps2uqq 128(%rcx), %xmm1 {%k2} +# CHECK: vcvttps2uqq 128(%rcx), %xmm1 +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x78,0x49,0x10] + vcvttps2uqq 128(%rcx), %xmm1 +# CHECK: vcvtps2qq 128(%rcx), %xmm2 {%k2} {z} +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7b,0x51,0x10] + vcvtps2qq 128(%rcx), %xmm2 {%k2} {z} +# CHECK: vcvtps2qq 128(%rcx), %xmm2 {%k2} +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7b,0x51,0x10] + vcvtps2qq 128(%rcx), %xmm2 {%k2} +# CHECK: vcvtps2qq 128(%rcx), %xmm2 +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7b,0x51,0x10] + vcvtps2qq 128(%rcx), %xmm2 +# CHECK: vcvttps2qq 128(%rcx), %xmm1 {%k2} {z} +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7a,0x49,0x10] + vcvttps2qq 128(%rcx), %xmm1 {%k2} {z} +# CHECK: vcvttps2qq 128(%rcx), %xmm1 {%k2} +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7a,0x49,0x10] + vcvttps2qq 128(%rcx), %xmm1 {%k2} +# CHECK: vcvttps2qq 128(%rcx), %xmm1 +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7a,0x49,0x10] + vcvttps2qq 128(%rcx), %xmm1 +# CHECK: vcvtps2uqq 128(%rcx), %xmm1 {%k2} {z} +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x79,0x49,0x10] + vcvtps2uqq 128(%rcx), %xmm1 {%k2} {z} +# CHECK: vcvtps2uqq 128(%rcx), %xmm1 {%k2} +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x79,0x49,0x10] + vcvtps2uqq 128(%rcx), %xmm1 {%k2} +# CHECK: vcvtps2uqq 128(%rcx), %xmm1 +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x79,0x49,0x10] + vcvtps2uqq 128(%rcx), %xmm1 +# CHECK: vcvttps2uqq 128(%rcx), %xmm1 {%k2} {z} +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x78,0x49,0x10] + vcvttps2uqq 128(%rcx), %xmm1 {%k2} {z} +# CHECK: vcvttps2uqq 128(%rcx), %xmm1 {%k2} +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10] + vcvttps2uqq 128(%rcx), %xmm1 {%k2} +# CHECK: vcvttps2uqq 128(%rcx), %xmm1 +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x78,0x49,0x10] + vcvttps2uqq 128(%rcx), %xmm1 +# CHECK: vfpclasspd $171, %xmm18, %k2 +# CHECK: encoding: [0x62,0xb3,0xfd,0x08,0x66,0xd2,0xab] + vfpclasspd $171, %xmm18, %k2 +# CHECK: vfpclasspd $171, %xmm18, %k2 {%k7} +# CHECK: encoding: [0x62,0xb3,0xfd,0x0f,0x66,0xd2,0xab] + vfpclasspd $171, %xmm18, %k2 {%k7} +# CHECK: vfpclasspdx $123, (%rcx), %k2 +# CHECK: encoding: [0x62,0xf3,0xfd,0x08,0x66,0x11,0x7b] + vfpclasspdx $123, (%rcx), %k2 +# CHECK: vfpclasspdx $123, (%rcx), %k2 {%k7} +# CHECK: encoding: [0x62,0xf3,0xfd,0x0f,0x66,0x11,0x7b] + vfpclasspdx $123, (%rcx), %k2 {%k7} +# CHECK: vfpclasspd $123, (%rcx){1to2}, %k2 +# CHECK: encoding: [0x62,0xf3,0xfd,0x18,0x66,0x11,0x7b] + vfpclasspd $123, (%rcx){1to2}, %k2 +# CHECK: vfpclasspd $123, (%rcx){1to2}, %k2 {%k7} +# CHECK: encoding: [0x62,0xf3,0xfd,0x1f,0x66,0x11,0x7b] + vfpclasspd $123, (%rcx){1to2}, %k2 {%k7} +# CHECK: vfpclassps $171, %xmm18, %k2 +# CHECK: encoding: [0x62,0xb3,0x7d,0x08,0x66,0xd2,0xab] + vfpclassps $171, %xmm18, %k2 +# CHECK: vfpclassps $171, %xmm18, %k2 {%k7} +# CHECK: encoding: [0x62,0xb3,0x7d,0x0f,0x66,0xd2,0xab] + vfpclassps $171, %xmm18, %k2 {%k7} +# CHECK: vfpclasspsx $123, (%rcx), %k2 +# CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x66,0x11,0x7b] + vfpclasspsx $123, (%rcx), %k2 +# CHECK: vfpclasspsx $123, (%rcx), %k2 {%k7} +# CHECK: encoding: [0x62,0xf3,0x7d,0x0f,0x66,0x11,0x7b] + vfpclasspsx $123, (%rcx), %k2 {%k7} +# CHECK: vfpclassps $123, (%rcx){1to4}, %k2 +# CHECK: encoding: [0x62,0xf3,0x7d,0x18,0x66,0x11,0x7b] + vfpclassps $123, (%rcx){1to4}, %k2 +# CHECK: vfpclassps $123, (%rcx){1to4}, %k2 {%k7} +# CHECK: encoding: [0x62,0xf3,0x7d,0x1f,0x66,0x11,0x7b] + vfpclassps $123, (%rcx){1to4}, %k2 {%k7} +# CHECK: vfpclasspd $171, %ymm18, %k2 +# CHECK: encoding: [0x62,0xb3,0xfd,0x28,0x66,0xd2,0xab] + vfpclasspd $171, %ymm18, %k2 +# CHECK: vfpclasspd $171, %ymm18, %k2 {%k7} +# CHECK: encoding: [0x62,0xb3,0xfd,0x2f,0x66,0xd2,0xab] + vfpclasspd $171, %ymm18, %k2 {%k7} +# CHECK: vfpclasspdy $123, (%rcx), %k2 +# CHECK: encoding: [0x62,0xf3,0xfd,0x28,0x66,0x11,0x7b] + vfpclasspdy $123, (%rcx), %k2 +# CHECK: vfpclasspdy $123, (%rcx), %k2 {%k7} +# CHECK: encoding: [0x62,0xf3,0xfd,0x2f,0x66,0x11,0x7b] + vfpclasspdy $123, (%rcx), %k2 {%k7} +# CHECK: vfpclasspd $123, (%rcx){1to4}, %k2 +# CHECK: encoding: [0x62,0xf3,0xfd,0x38,0x66,0x11,0x7b] + vfpclasspd $123, (%rcx){1to4}, %k2 +# CHECK: vfpclasspd $123, (%rcx){1to4}, %k2 {%k7} +# CHECK: encoding: [0x62,0xf3,0xfd,0x3f,0x66,0x11,0x7b] + vfpclasspd $123, (%rcx){1to4}, %k2 {%k7} +# CHECK: vfpclassps $171, %ymm18, %k2 +# CHECK: encoding: [0x62,0xb3,0x7d,0x28,0x66,0xd2,0xab] + vfpclassps $171, %ymm18, %k2 +# CHECK: vfpclassps $171, %ymm18, %k2 {%k7} +# CHECK: encoding: [0x62,0xb3,0x7d,0x2f,0x66,0xd2,0xab] + vfpclassps $171, %ymm18, %k2 {%k7} +# CHECK: vfpclasspsy $123, (%rcx), %k2 +# CHECK: encoding: [0x62,0xf3,0x7d,0x28,0x66,0x11,0x7b] + vfpclasspsy $123, (%rcx), %k2 +# CHECK: vfpclasspsy $123, (%rcx), %k2 {%k7} +# CHECK: encoding: [0x62,0xf3,0x7d,0x2f,0x66,0x11,0x7b] + vfpclasspsy $123, (%rcx), %k2 {%k7} +# CHECK: vfpclassps $123, (%rcx){1to8}, %k2 +# CHECK: encoding: [0x62,0xf3,0x7d,0x38,0x66,0x11,0x7b] + vfpclassps $123, (%rcx){1to8}, %k2 +# CHECK: vfpclassps $123, (%rcx){1to8}, %k2 {%k7} +# CHECK: encoding: [0x62,0xf3,0x7d,0x3f,0x66,0x11,0x7b] + vfpclassps $123, (%rcx){1to8}, %k2 {%k7} +# CHECK: vcvttps2uqq 128(%ecx), %xmm1 {%k2} +# CHECK: encoding: [0x67,0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10] + vcvttps2uqq 128(%ecx), %xmm1 {%k2} diff --git a/llvm/test/MC/X86/avx512dq_vl-intel.s b/llvm/test/MC/X86/avx512dq_vl-intel.s new file mode 100644 index 000000000000..71e9fc413677 --- /dev/null +++ b/llvm/test/MC/X86/avx512dq_vl-intel.s @@ -0,0 +1,149 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s + +# CHECK: vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7b,0x51,0x10] + vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 128] +# CHECK: vcvtps2qq xmm2 {k2}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7b,0x51,0x10] + vcvtps2qq xmm2 {k2}, qword ptr [rcx + 128] +# CHECK: vcvtps2qq xmm2, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7b,0x51,0x10] + vcvtps2qq xmm2, qword ptr [rcx + 128] +# CHECK: vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7a,0x49,0x10] + vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 128] +# CHECK: vcvttps2qq xmm1 {k2}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7a,0x49,0x10] + vcvttps2qq xmm1 {k2}, qword ptr [rcx + 128] +# CHECK: vcvttps2qq xmm1, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7a,0x49,0x10] + vcvttps2qq xmm1, qword ptr [rcx + 128] +# CHECK: vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x79,0x49,0x10] + vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] +# CHECK: vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x79,0x49,0x10] + vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128] +# CHECK: vcvtps2uqq xmm1, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x79,0x49,0x10] + vcvtps2uqq xmm1, qword ptr [rcx + 128] +# CHECK: vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x78,0x49,0x10] + vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] +# CHECK: vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10] + vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128] +# CHECK: vcvttps2uqq xmm1, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x78,0x49,0x10] + vcvttps2uqq xmm1, qword ptr [rcx + 128] +# CHECK: vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7b,0x51,0x10] + vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 128] +# CHECK: vcvtps2qq xmm2 {k2}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7b,0x51,0x10] + vcvtps2qq xmm2 {k2}, qword ptr [rcx + 128] +# CHECK: vcvtps2qq xmm2, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7b,0x51,0x10] + vcvtps2qq xmm2, qword ptr [rcx + 128] +# CHECK: vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7a,0x49,0x10] + vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 128] +# CHECK: vcvttps2qq xmm1 {k2}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7a,0x49,0x10] + vcvttps2qq xmm1 {k2}, qword ptr [rcx + 128] +# CHECK: vcvttps2qq xmm1, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7a,0x49,0x10] + vcvttps2qq xmm1, qword ptr [rcx + 128] +# CHECK: vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x79,0x49,0x10] + vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] +# CHECK: vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x79,0x49,0x10] + vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128] +# CHECK: vcvtps2uqq xmm1, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x79,0x49,0x10] + vcvtps2uqq xmm1, qword ptr [rcx + 128] +# CHECK: vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x78,0x49,0x10] + vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] +# CHECK: vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10] + vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128] +# CHECK: vcvttps2uqq xmm1, qword ptr [rcx + 128] +# CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x78,0x49,0x10] + vcvttps2uqq xmm1, qword ptr [rcx + 128] +# CHECK: vfpclasspd k2, xmm18, 171 +# CHECK: encoding: [0x62,0xb3,0xfd,0x08,0x66,0xd2,0xab] + vfpclasspd k2, xmm18, 171 +# CHECK: vfpclasspd k2 {k7}, xmm18, 171 +# CHECK: encoding: [0x62,0xb3,0xfd,0x0f,0x66,0xd2,0xab] + vfpclasspd k2 {k7}, xmm18, 171 +# CHECK: vfpclasspd k2, xmmword ptr [rcx], 123 +# CHECK: encoding: [0x62,0xf3,0xfd,0x08,0x66,0x11,0x7b] + vfpclasspd k2, xmmword ptr [rcx], 123 +# CHECK: vfpclasspd k2 {k7}, xmmword ptr [rcx], 123 +# CHECK: encoding: [0x62,0xf3,0xfd,0x0f,0x66,0x11,0x7b] + vfpclasspd k2 {k7}, xmmword ptr [rcx], 123 +# CHECK: vfpclasspd k2, qword ptr [rcx]{1to2}, 123 +# CHECK: encoding: [0x62,0xf3,0xfd,0x18,0x66,0x11,0x7b] + vfpclasspd k2, qword ptr [rcx]{1to2}, 123 +# CHECK: vfpclasspd k2 {k7}, qword ptr [rcx]{1to2}, 123 +# CHECK: encoding: [0x62,0xf3,0xfd,0x1f,0x66,0x11,0x7b] + vfpclasspd k2 {k7}, qword ptr [rcx]{1to2}, 123 +# CHECK: vfpclassps k2, xmm18, 171 +# CHECK: encoding: [0x62,0xb3,0x7d,0x08,0x66,0xd2,0xab] + vfpclassps k2, xmm18, 171 +# CHECK: vfpclassps k2 {k7}, xmm18, 171 +# CHECK: encoding: [0x62,0xb3,0x7d,0x0f,0x66,0xd2,0xab] + vfpclassps k2 {k7}, xmm18, 171 +# CHECK: vfpclassps k2, xmmword ptr [rcx], 123 +# CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x66,0x11,0x7b] + vfpclassps k2, xmmword ptr [rcx], 123 +# CHECK: vfpclassps k2 {k7}, xmmword ptr [rcx], 123 +# CHECK: encoding: [0x62,0xf3,0x7d,0x0f,0x66,0x11,0x7b] + vfpclassps k2 {k7}, xmmword ptr [rcx], 123 +# CHECK: vfpclassps k2, dword ptr [rcx]{1to4}, 123 +# CHECK: encoding: [0x62,0xf3,0x7d,0x18,0x66,0x11,0x7b] + vfpclassps k2, dword ptr [rcx]{1to4}, 123 +# CHECK: vfpclassps k2 {k7}, dword ptr [rcx]{1to4}, 123 +# CHECK: encoding: [0x62,0xf3,0x7d,0x1f,0x66,0x11,0x7b] + vfpclassps k2 {k7}, dword ptr [rcx]{1to4}, 123 +# CHECK: vfpclasspd k2, ymm18, 171 +# CHECK: encoding: [0x62,0xb3,0xfd,0x28,0x66,0xd2,0xab] + vfpclasspd k2, ymm18, 171 +# CHECK: vfpclasspd k2 {k7}, ymm18, 171 +# CHECK: encoding: [0x62,0xb3,0xfd,0x2f,0x66,0xd2,0xab] + vfpclasspd k2 {k7}, ymm18, 171 +# CHECK: vfpclasspd k2, ymmword ptr [rcx], 123 +# CHECK: encoding: [0x62,0xf3,0xfd,0x28,0x66,0x11,0x7b] + vfpclasspd k2, ymmword ptr [rcx], 123 +# CHECK: vfpclasspd k2 {k7}, ymmword ptr [rcx], 123 +# CHECK: encoding: [0x62,0xf3,0xfd,0x2f,0x66,0x11,0x7b] + vfpclasspd k2 {k7}, ymmword ptr [rcx], 123 +# CHECK: vfpclasspd k2, qword ptr [rcx]{1to4}, 123 +# CHECK: encoding: [0x62,0xf3,0xfd,0x38,0x66,0x11,0x7b] + vfpclasspd k2, qword ptr [rcx]{1to4}, 123 +# CHECK: vfpclasspd k2 {k7}, qword ptr [rcx]{1to4}, 123 +# CHECK: encoding: [0x62,0xf3,0xfd,0x3f,0x66,0x11,0x7b] + vfpclasspd k2 {k7}, qword ptr [rcx]{1to4}, 123 +# CHECK: vfpclassps k2, ymm18, 171 +# CHECK: encoding: [0x62,0xb3,0x7d,0x28,0x66,0xd2,0xab] + vfpclassps k2, ymm18, 171 +# CHECK: vfpclassps k2 {k7}, ymm18, 171 +# CHECK: encoding: [0x62,0xb3,0x7d,0x2f,0x66,0xd2,0xab] + vfpclassps k2 {k7}, ymm18, 171 +# CHECK: vfpclassps k2, ymmword ptr [rcx], 123 +# CHECK: encoding: [0x62,0xf3,0x7d,0x28,0x66,0x11,0x7b] + vfpclassps k2, ymmword ptr [rcx], 123 +# CHECK: vfpclassps k2 {k7}, ymmword ptr [rcx], 123 +# CHECK: encoding: [0x62,0xf3,0x7d,0x2f,0x66,0x11,0x7b] + vfpclassps k2 {k7}, ymmword ptr [rcx], 123 +# CHECK: vfpclassps k2, dword ptr [rcx]{1to8}, 123 +# CHECK: encoding: [0x62,0xf3,0x7d,0x38,0x66,0x11,0x7b] + vfpclassps k2, dword ptr [rcx]{1to8}, 123 +# CHECK: vfpclassps k2 {k7}, dword ptr [rcx]{1to8}, 123 +# CHECK: encoding: [0x62,0xf3,0x7d,0x3f,0x66,0x11,0x7b] + vfpclassps k2 {k7}, dword ptr [rcx]{1to8}, 123 +# CHECK: vcvttps2uqq xmm1 {k2}, qword ptr [ecx + 128] +# CHECK: encoding: [0x67,0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10] + vcvttps2uqq xmm1 {k2}, qword ptr [ecx + 128] diff --git a/llvm/test/MC/X86/x86-64-avx512f_vl.s b/llvm/test/MC/X86/avx512f_vl-att.s index d41f15ad83da..d41f15ad83da 100644 --- a/llvm/test/MC/X86/x86-64-avx512f_vl.s +++ b/llvm/test/MC/X86/avx512f_vl-att.s diff --git a/llvm/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s b/llvm/test/MC/X86/avx512f_vl-intel.s index 31c43afe5017..31c43afe5017 100644 --- a/llvm/test/MC/X86/intel-syntax-x86-64-avx512f_vl.s +++ b/llvm/test/MC/X86/avx512f_vl-intel.s diff --git a/llvm/test/MC/X86/avx512fp16.s b/llvm/test/MC/X86/avx512fp16-att.s index 13eaa7de6a69..13eaa7de6a69 100644 --- a/llvm/test/MC/X86/avx512fp16.s +++ b/llvm/test/MC/X86/avx512fp16-att.s diff --git a/llvm/test/MC/X86/intel-syntax-avx512fp16.s b/llvm/test/MC/X86/avx512fp16-intel.s index 8c48fa3116d6..8c48fa3116d6 100644 --- a/llvm/test/MC/X86/intel-syntax-avx512fp16.s +++ b/llvm/test/MC/X86/avx512fp16-intel.s diff --git a/llvm/test/MC/X86/avx512fp16vl.s b/llvm/test/MC/X86/avx512fp16vl-att.s index 989effae40de..989effae40de 100644 --- a/llvm/test/MC/X86/avx512fp16vl.s +++ b/llvm/test/MC/X86/avx512fp16vl-att.s diff --git a/llvm/test/MC/X86/intel-syntax-avx512fp16vl.s b/llvm/test/MC/X86/avx512fp16vl-intel.s index 39392f0b6e4b..39392f0b6e4b 100644 --- a/llvm/test/MC/X86/intel-syntax-avx512fp16vl.s +++ b/llvm/test/MC/X86/avx512fp16vl-intel.s diff --git a/llvm/test/MC/X86/avx512gfni-encoding.s b/llvm/test/MC/X86/avx512gfni-att.s index 975595deef58..975595deef58 100644 --- a/llvm/test/MC/X86/avx512gfni-encoding.s +++ b/llvm/test/MC/X86/avx512gfni-att.s diff --git a/llvm/test/MC/X86/avx512ifma-encoding.s b/llvm/test/MC/X86/avx512ifma-att.s index ae1e3c89e1d5..ae1e3c89e1d5 100644 --- a/llvm/test/MC/X86/avx512ifma-encoding.s +++ b/llvm/test/MC/X86/avx512ifma-att.s diff --git a/llvm/test/MC/X86/avx512ifmavl-encoding.s b/llvm/test/MC/X86/avx512ifmavl-att.s index 9871a2e1b94f..9871a2e1b94f 100644 --- a/llvm/test/MC/X86/avx512ifmavl-encoding.s +++ b/llvm/test/MC/X86/avx512ifmavl-att.s diff --git a/llvm/test/MC/X86/x86-64-avx512pf.s b/llvm/test/MC/X86/avx512pf-64-att.s index bae7fb0f235c..bae7fb0f235c 100644 --- a/llvm/test/MC/X86/x86-64-avx512pf.s +++ b/llvm/test/MC/X86/avx512pf-64-att.s diff --git a/llvm/test/MC/X86/avx512vaes-encoding.s b/llvm/test/MC/X86/avx512vaes-att.s index e688413a8aa3..e688413a8aa3 100644 --- a/llvm/test/MC/X86/avx512vaes-encoding.s +++ b/llvm/test/MC/X86/avx512vaes-att.s diff --git a/llvm/test/MC/X86/avx512vbmi-att.s b/llvm/test/MC/X86/avx512vbmi-att.s new file mode 100644 index 000000000000..028494514bfc --- /dev/null +++ b/llvm/test/MC/X86/avx512vbmi-att.s @@ -0,0 +1,542 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s + +# CHECK: vpermb %xmm28, %xmm29, %xmm30 {%k7} +# CHECK: encoding: [0x62,0x02,0x15,0x07,0x8d,0xf4] + vpermb %xmm28, %xmm29, %xmm30 {%k7} + +# CHECK: vpermb %xmm28, %xmm29, %xmm30 {%k7} {z} +# CHECK: encoding: [0x62,0x02,0x15,0x87,0x8d,0xf4] + vpermb %xmm28, %xmm29, %xmm30 {%k7} {z} + +# CHECK: vpermb (%rcx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0x31] + vpermb (%rcx), %xmm29, %xmm30 + +# CHECK: vpermb 291(%rax,%r14,8), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x22,0x15,0x00,0x8d,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermb 291(%rax,%r14,8), %xmm29, %xmm30 + +# CHECK: vpermb 2032(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0x72,0x7f] + vpermb 2032(%rdx), %xmm29, %xmm30 + +# CHECK: vpermb 2048(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0xb2,0x00,0x08,0x00,0x00] + vpermb 2048(%rdx), %xmm29, %xmm30 + +# CHECK: vpermb -2048(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0x72,0x80] + vpermb -2048(%rdx), %xmm29, %xmm30 + +# CHECK: vpermb -2064(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0xb2,0xf0,0xf7,0xff,0xff] + vpermb -2064(%rdx), %xmm29, %xmm30 + +# CHECK: vpermb %ymm28, %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x02,0x15,0x20,0x8d,0xf4] + vpermb %ymm28, %ymm29, %ymm30 + +# CHECK: vpermb %ymm28, %ymm29, %ymm30 {%k7} +# CHECK: encoding: [0x62,0x02,0x15,0x27,0x8d,0xf4] + vpermb %ymm28, %ymm29, %ymm30 {%k7} + +# CHECK: vpermb %ymm28, %ymm29, %ymm30 {%k7} {z} +# CHECK: encoding: [0x62,0x02,0x15,0xa7,0x8d,0xf4] + vpermb %ymm28, %ymm29, %ymm30 {%k7} {z} + +# CHECK: vpermb (%rcx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0x31] + vpermb (%rcx), %ymm29, %ymm30 + +# CHECK: vpermb 291(%rax,%r14,8), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x22,0x15,0x20,0x8d,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermb 291(%rax,%r14,8), %ymm29, %ymm30 + +# CHECK: vpermb 4064(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0x72,0x7f] + vpermb 4064(%rdx), %ymm29, %ymm30 + +# CHECK: vpermb 4096(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0xb2,0x00,0x10,0x00,0x00] + vpermb 4096(%rdx), %ymm29, %ymm30 + +# CHECK: vpermb -4096(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0x72,0x80] + vpermb -4096(%rdx), %ymm29, %ymm30 + +# CHECK: vpermb -4128(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0xb2,0xe0,0xef,0xff,0xff] + vpermb -4128(%rdx), %ymm29, %ymm30 + +# CHECK: vpermb %xmm28, %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x02,0x15,0x00,0x8d,0xf4] + vpermb %xmm28, %xmm29, %xmm30 + +# CHECK: vpermb 4660(%rax,%r14,8), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x22,0x15,0x00,0x8d,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermb 4660(%rax,%r14,8), %xmm29, %xmm30 + +# CHECK: vpermb 4660(%rax,%r14,8), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x22,0x15,0x20,0x8d,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermb 4660(%rax,%r14,8), %ymm29, %ymm30 + +# CHECK: vpermb %zmm28, %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x02,0x15,0x40,0x8d,0xf4] + vpermb %zmm28, %zmm29, %zmm30 + +# CHECK: vpermb %zmm28, %zmm29, %zmm30 {%k7} +# CHECK: encoding: [0x62,0x02,0x15,0x47,0x8d,0xf4] + vpermb %zmm28, %zmm29, %zmm30 {%k7} + +# CHECK: vpermb %zmm28, %zmm29, %zmm30 {%k7} {z} +# CHECK: encoding: [0x62,0x02,0x15,0xc7,0x8d,0xf4] + vpermb %zmm28, %zmm29, %zmm30 {%k7} {z} + +# CHECK: vpermb (%rcx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0x31] + vpermb (%rcx), %zmm29, %zmm30 + +# CHECK: vpermb 291(%rax,%r14,8), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x22,0x15,0x40,0x8d,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermb 291(%rax,%r14,8), %zmm29, %zmm30 + +# CHECK: vpermb 8128(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0x72,0x7f] + vpermb 8128(%rdx), %zmm29, %zmm30 + +# CHECK: vpermb 8192(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0xb2,0x00,0x20,0x00,0x00] + vpermb 8192(%rdx), %zmm29, %zmm30 + +# CHECK: vpermb -8192(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0x72,0x80] + vpermb -8192(%rdx), %zmm29, %zmm30 + +# CHECK: vpermb -8256(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0xb2,0xc0,0xdf,0xff,0xff] + vpermb -8256(%rdx), %zmm29, %zmm30 + +# CHECK: vpermb 4660(%rax,%r14,8), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x22,0x15,0x40,0x8d,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermb 4660(%rax,%r14,8), %zmm29, %zmm30 + +# CHECK: vpermt2b %xmm28, %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x02,0x15,0x00,0x7d,0xf4] + vpermt2b %xmm28, %xmm29, %xmm30 + +# CHECK: vpermt2b %xmm28, %xmm29, %xmm30 {%k7} +# CHECK: encoding: [0x62,0x02,0x15,0x07,0x7d,0xf4] + vpermt2b %xmm28, %xmm29, %xmm30 {%k7} + +# CHECK: vpermt2b %xmm28, %xmm29, %xmm30 {%k7} {z} +# CHECK: encoding: [0x62,0x02,0x15,0x87,0x7d,0xf4] + vpermt2b %xmm28, %xmm29, %xmm30 {%k7} {z} + +# CHECK: vpermt2b (%rcx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0x31] + vpermt2b (%rcx), %xmm29, %xmm30 + +# CHECK: vpermt2b 291(%rax,%r14,8), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x22,0x15,0x00,0x7d,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermt2b 291(%rax,%r14,8), %xmm29, %xmm30 + +# CHECK: vpermt2b 2032(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0x72,0x7f] + vpermt2b 2032(%rdx), %xmm29, %xmm30 + +# CHECK: vpermt2b 2048(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0xb2,0x00,0x08,0x00,0x00] + vpermt2b 2048(%rdx), %xmm29, %xmm30 + +# CHECK: vpermt2b -2048(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0x72,0x80] + vpermt2b -2048(%rdx), %xmm29, %xmm30 + +# CHECK: vpermt2b -2064(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0xb2,0xf0,0xf7,0xff,0xff] + vpermt2b -2064(%rdx), %xmm29, %xmm30 + +# CHECK: vpermt2b %ymm28, %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x02,0x15,0x20,0x7d,0xf4] + vpermt2b %ymm28, %ymm29, %ymm30 + +# CHECK: vpermt2b %ymm28, %ymm29, %ymm30 {%k7} +# CHECK: encoding: [0x62,0x02,0x15,0x27,0x7d,0xf4] + vpermt2b %ymm28, %ymm29, %ymm30 {%k7} + +# CHECK: vpermt2b %ymm28, %ymm29, %ymm30 {%k7} {z} +# CHECK: encoding: [0x62,0x02,0x15,0xa7,0x7d,0xf4] + vpermt2b %ymm28, %ymm29, %ymm30 {%k7} {z} + +# CHECK: vpermt2b (%rcx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0x31] + vpermt2b (%rcx), %ymm29, %ymm30 + +# CHECK: vpermt2b 291(%rax,%r14,8), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x22,0x15,0x20,0x7d,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermt2b 291(%rax,%r14,8), %ymm29, %ymm30 + +# CHECK: vpermt2b 4064(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0x72,0x7f] + vpermt2b 4064(%rdx), %ymm29, %ymm30 + +# CHECK: vpermt2b 4096(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0xb2,0x00,0x10,0x00,0x00] + vpermt2b 4096(%rdx), %ymm29, %ymm30 + +# CHECK: vpermt2b -4096(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0x72,0x80] + vpermt2b -4096(%rdx), %ymm29, %ymm30 + +# CHECK: vpermt2b -4128(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0xb2,0xe0,0xef,0xff,0xff] + vpermt2b -4128(%rdx), %ymm29, %ymm30 + +# CHECK: vpermt2b 4660(%rax,%r14,8), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x22,0x15,0x00,0x7d,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermt2b 4660(%rax,%r14,8), %xmm29, %xmm30 + +# CHECK: vpermt2b 4660(%rax,%r14,8), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x22,0x15,0x20,0x7d,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermt2b 4660(%rax,%r14,8), %ymm29, %ymm30 + +# CHECK: vpermt2b %zmm28, %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x02,0x15,0x40,0x7d,0xf4] + vpermt2b %zmm28, %zmm29, %zmm30 + +# CHECK: vpermt2b %zmm28, %zmm29, %zmm30 {%k7} +# CHECK: encoding: [0x62,0x02,0x15,0x47,0x7d,0xf4] + vpermt2b %zmm28, %zmm29, %zmm30 {%k7} + +# CHECK: vpermt2b %zmm28, %zmm29, %zmm30 {%k7} {z} +# CHECK: encoding: [0x62,0x02,0x15,0xc7,0x7d,0xf4] + vpermt2b %zmm28, %zmm29, %zmm30 {%k7} {z} + +# CHECK: vpermt2b (%rcx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0x31] + vpermt2b (%rcx), %zmm29, %zmm30 + +# CHECK: vpermt2b 291(%rax,%r14,8), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x22,0x15,0x40,0x7d,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermt2b 291(%rax,%r14,8), %zmm29, %zmm30 + +# CHECK: vpermt2b 8128(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0x72,0x7f] + vpermt2b 8128(%rdx), %zmm29, %zmm30 + +# CHECK: vpermt2b 8192(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0xb2,0x00,0x20,0x00,0x00] + vpermt2b 8192(%rdx), %zmm29, %zmm30 + +# CHECK: vpermt2b -8192(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0x72,0x80] + vpermt2b -8192(%rdx), %zmm29, %zmm30 + +# CHECK: vpermt2b -8256(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0xb2,0xc0,0xdf,0xff,0xff] + vpermt2b -8256(%rdx), %zmm29, %zmm30 + +# CHECK: vpermt2b 4660(%rax,%r14,8), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x22,0x15,0x40,0x7d,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermt2b 4660(%rax,%r14,8), %zmm29, %zmm30 + +# CHECK: vpermi2b %xmm28, %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x02,0x15,0x00,0x75,0xf4] + vpermi2b %xmm28, %xmm29, %xmm30 + +# CHECK: vpermi2b %xmm28, %xmm29, %xmm30 {%k7} +# CHECK: encoding: [0x62,0x02,0x15,0x07,0x75,0xf4] + vpermi2b %xmm28, %xmm29, %xmm30 {%k7} + +# CHECK: vpermi2b %xmm28, %xmm29, %xmm30 {%k7} {z} +# CHECK: encoding: [0x62,0x02,0x15,0x87,0x75,0xf4] + vpermi2b %xmm28, %xmm29, %xmm30 {%k7} {z} + +# CHECK: vpermi2b (%rcx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0x31] + vpermi2b (%rcx), %xmm29, %xmm30 + +# CHECK: vpermi2b 291(%rax,%r14,8), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x22,0x15,0x00,0x75,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermi2b 291(%rax,%r14,8), %xmm29, %xmm30 + +# CHECK: vpermi2b 2032(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0x72,0x7f] + vpermi2b 2032(%rdx), %xmm29, %xmm30 + +# CHECK: vpermi2b 2048(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0xb2,0x00,0x08,0x00,0x00] + vpermi2b 2048(%rdx), %xmm29, %xmm30 + +# CHECK: vpermi2b -2048(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0x72,0x80] + vpermi2b -2048(%rdx), %xmm29, %xmm30 + +# CHECK: vpermi2b -2064(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0xb2,0xf0,0xf7,0xff,0xff] + vpermi2b -2064(%rdx), %xmm29, %xmm30 + +# CHECK: vpermi2b %ymm28, %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x02,0x15,0x20,0x75,0xf4] + vpermi2b %ymm28, %ymm29, %ymm30 + +# CHECK: vpermi2b %ymm28, %ymm29, %ymm30 {%k7} +# CHECK: encoding: [0x62,0x02,0x15,0x27,0x75,0xf4] + vpermi2b %ymm28, %ymm29, %ymm30 {%k7} + +# CHECK: vpermi2b %ymm28, %ymm29, %ymm30 {%k7} {z} +# CHECK: encoding: [0x62,0x02,0x15,0xa7,0x75,0xf4] + vpermi2b %ymm28, %ymm29, %ymm30 {%k7} {z} + +# CHECK: vpermi2b (%rcx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0x31] + vpermi2b (%rcx), %ymm29, %ymm30 + +# CHECK: vpermi2b 291(%rax,%r14,8), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x22,0x15,0x20,0x75,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermi2b 291(%rax,%r14,8), %ymm29, %ymm30 + +# CHECK: vpermi2b 4064(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0x72,0x7f] + vpermi2b 4064(%rdx), %ymm29, %ymm30 + +# CHECK: vpermi2b 4096(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0xb2,0x00,0x10,0x00,0x00] + vpermi2b 4096(%rdx), %ymm29, %ymm30 + +# CHECK: vpermi2b -4096(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0x72,0x80] + vpermi2b -4096(%rdx), %ymm29, %ymm30 + +# CHECK: vpermi2b -4128(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0xb2,0xe0,0xef,0xff,0xff] + vpermi2b -4128(%rdx), %ymm29, %ymm30 + +# CHECK: vpermi2b 4660(%rax,%r14,8), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x22,0x15,0x00,0x75,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermi2b 4660(%rax,%r14,8), %xmm29, %xmm30 + +# CHECK: vpermi2b 4660(%rax,%r14,8), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x22,0x15,0x20,0x75,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermi2b 4660(%rax,%r14,8), %ymm29, %ymm30 + +# CHECK: vpermi2b %zmm28, %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x02,0x15,0x40,0x75,0xf4] + vpermi2b %zmm28, %zmm29, %zmm30 + +# CHECK: vpermi2b %zmm28, %zmm29, %zmm30 {%k7} +# CHECK: encoding: [0x62,0x02,0x15,0x47,0x75,0xf4] + vpermi2b %zmm28, %zmm29, %zmm30 {%k7} + +# CHECK: vpermi2b %zmm28, %zmm29, %zmm30 {%k7} {z} +# CHECK: encoding: [0x62,0x02,0x15,0xc7,0x75,0xf4] + vpermi2b %zmm28, %zmm29, %zmm30 {%k7} {z} + +# CHECK: vpermi2b (%rcx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0x31] + vpermi2b (%rcx), %zmm29, %zmm30 + +# CHECK: vpermi2b 291(%rax,%r14,8), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x22,0x15,0x40,0x75,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermi2b 291(%rax,%r14,8), %zmm29, %zmm30 + +# CHECK: vpermi2b 8128(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0x72,0x7f] + vpermi2b 8128(%rdx), %zmm29, %zmm30 + +# CHECK: vpermi2b 8192(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0xb2,0x00,0x20,0x00,0x00] + vpermi2b 8192(%rdx), %zmm29, %zmm30 + +# CHECK: vpermi2b -8192(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0x72,0x80] + vpermi2b -8192(%rdx), %zmm29, %zmm30 + +# CHECK: vpermi2b -8256(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0xb2,0xc0,0xdf,0xff,0xff] + vpermi2b -8256(%rdx), %zmm29, %zmm30 + +# CHECK: vpermi2b 4660(%rax,%r14,8), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x22,0x15,0x40,0x75,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermi2b 4660(%rax,%r14,8), %zmm29, %zmm30 + +# CHECK: vpmultishiftqb %xmm28, %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x02,0x95,0x00,0x83,0xf4] + vpmultishiftqb %xmm28, %xmm29, %xmm30 + +# CHECK: vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7} +# CHECK: encoding: [0x62,0x02,0x95,0x07,0x83,0xf4] + vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7} + +# CHECK: vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7} {z} +# CHECK: encoding: [0x62,0x02,0x95,0x87,0x83,0xf4] + vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7} {z} + +# CHECK: vpmultishiftqb (%rcx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0x31] + vpmultishiftqb (%rcx), %xmm29, %xmm30 + +# CHECK: vpmultishiftqb 291(%rax,%r14,8), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x22,0x95,0x00,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpmultishiftqb 291(%rax,%r14,8), %xmm29, %xmm30 + +# CHECK: vpmultishiftqb (%rcx){1to2}, %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0x31] + vpmultishiftqb (%rcx){1to2}, %xmm29, %xmm30 + + +# CHECK: vpmultishiftqb 2032(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0x72,0x7f] + vpmultishiftqb 2032(%rdx), %xmm29, %xmm30 + +# CHECK: vpmultishiftqb 2048(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0xb2,0x00,0x08,0x00,0x00] + vpmultishiftqb 2048(%rdx), %xmm29, %xmm30 + +# CHECK: vpmultishiftqb -2048(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0x72,0x80] + vpmultishiftqb -2048(%rdx), %xmm29, %xmm30 + +# CHECK: vpmultishiftqb -2064(%rdx), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0xb2,0xf0,0xf7,0xff,0xff] + vpmultishiftqb -2064(%rdx), %xmm29, %xmm30 + +# CHECK: vpmultishiftqb 1016(%rdx){1to2}, %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0x72,0x7f] + vpmultishiftqb 1016(%rdx){1to2}, %xmm29, %xmm30 + +# CHECK: vpmultishiftqb 1024(%rdx){1to2}, %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0xb2,0x00,0x04,0x00,0x00] + vpmultishiftqb 1024(%rdx){1to2}, %xmm29, %xmm30 + +# CHECK: vpmultishiftqb -1024(%rdx){1to2}, %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0x72,0x80] + vpmultishiftqb -1024(%rdx){1to2}, %xmm29, %xmm30 + +# CHECK: vpmultishiftqb -1032(%rdx){1to2}, %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0xb2,0xf8,0xfb,0xff,0xff] + vpmultishiftqb -1032(%rdx){1to2}, %xmm29, %xmm30 + +# CHECK: vpmultishiftqb %ymm28, %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x02,0x95,0x20,0x83,0xf4] + vpmultishiftqb %ymm28, %ymm29, %ymm30 + +# CHECK: vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7} +# CHECK: encoding: [0x62,0x02,0x95,0x27,0x83,0xf4] + vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7} + +# CHECK: vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7} {z} +# CHECK: encoding: [0x62,0x02,0x95,0xa7,0x83,0xf4] + vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7} {z} + +# CHECK: vpmultishiftqb (%rcx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0x31] + vpmultishiftqb (%rcx), %ymm29, %ymm30 + +# CHECK: vpmultishiftqb 291(%rax,%r14,8), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x22,0x95,0x20,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpmultishiftqb 291(%rax,%r14,8), %ymm29, %ymm30 + +# CHECK: vpmultishiftqb (%rcx){1to4}, %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0x31] + vpmultishiftqb (%rcx){1to4}, %ymm29, %ymm30 + +# CHECK: vpmultishiftqb 4064(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0x72,0x7f] + vpmultishiftqb 4064(%rdx), %ymm29, %ymm30 + +# CHECK: vpmultishiftqb 4096(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0xb2,0x00,0x10,0x00,0x00] + vpmultishiftqb 4096(%rdx), %ymm29, %ymm30 + +# CHECK: vpmultishiftqb -4096(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0x72,0x80] + vpmultishiftqb -4096(%rdx), %ymm29, %ymm30 + +# CHECK: vpmultishiftqb -4128(%rdx), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0xb2,0xe0,0xef,0xff,0xff] + vpmultishiftqb -4128(%rdx), %ymm29, %ymm30 + +# CHECK: vpmultishiftqb 1016(%rdx){1to4}, %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0x72,0x7f] + vpmultishiftqb 1016(%rdx){1to4}, %ymm29, %ymm30 + +# CHECK: vpmultishiftqb 1024(%rdx){1to4}, %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0xb2,0x00,0x04,0x00,0x00] + vpmultishiftqb 1024(%rdx){1to4}, %ymm29, %ymm30 + +# CHECK: vpmultishiftqb -1024(%rdx){1to4}, %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0x72,0x80] + vpmultishiftqb -1024(%rdx){1to4}, %ymm29, %ymm30 + +# CHECK: vpmultishiftqb -1032(%rdx){1to4}, %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0xb2,0xf8,0xfb,0xff,0xff] + vpmultishiftqb -1032(%rdx){1to4}, %ymm29, %ymm30 + +# CHECK: vpmultishiftqb 4660(%rax,%r14,8), %xmm29, %xmm30 +# CHECK: encoding: [0x62,0x22,0x95,0x00,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpmultishiftqb 4660(%rax,%r14,8), %xmm29, %xmm30 + +# CHECK: vpmultishiftqb 4660(%rax,%r14,8), %ymm29, %ymm30 +# CHECK: encoding: [0x62,0x22,0x95,0x20,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpmultishiftqb 4660(%rax,%r14,8), %ymm29, %ymm30 + +# CHECK: vpmultishiftqb %zmm28, %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x02,0x95,0x40,0x83,0xf4] + vpmultishiftqb %zmm28, %zmm29, %zmm30 + +# CHECK: vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7} +# CHECK: encoding: [0x62,0x02,0x95,0x47,0x83,0xf4] + vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7} + +# CHECK: vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7} {z} +# CHECK: encoding: [0x62,0x02,0x95,0xc7,0x83,0xf4] + vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7} {z} + +# CHECK: vpmultishiftqb (%rcx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0x31] + vpmultishiftqb (%rcx), %zmm29, %zmm30 + +# CHECK: vpmultishiftqb 291(%rax,%r14,8), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x22,0x95,0x40,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpmultishiftqb 291(%rax,%r14,8), %zmm29, %zmm30 + +# CHECK: vpmultishiftqb (%rcx){1to8}, %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0x31] + vpmultishiftqb (%rcx){1to8}, %zmm29, %zmm30 + +# CHECK: vpmultishiftqb 8128(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0x72,0x7f] + vpmultishiftqb 8128(%rdx), %zmm29, %zmm30 + +# CHECK: vpmultishiftqb 8192(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0xb2,0x00,0x20,0x00,0x00] + vpmultishiftqb 8192(%rdx), %zmm29, %zmm30 + +# CHECK: vpmultishiftqb -8192(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0x72,0x80] + vpmultishiftqb -8192(%rdx), %zmm29, %zmm30 + +# CHECK: vpmultishiftqb -8256(%rdx), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0xb2,0xc0,0xdf,0xff,0xff] + vpmultishiftqb -8256(%rdx), %zmm29, %zmm30 + +# CHECK: vpmultishiftqb 1016(%rdx){1to8}, %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0x72,0x7f] + vpmultishiftqb 1016(%rdx){1to8}, %zmm29, %zmm30 + +# CHECK: vpmultishiftqb 1024(%rdx){1to8}, %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0xb2,0x00,0x04,0x00,0x00] + vpmultishiftqb 1024(%rdx){1to8}, %zmm29, %zmm30 + +# CHECK: vpmultishiftqb -1024(%rdx){1to8}, %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0x72,0x80] + vpmultishiftqb -1024(%rdx){1to8}, %zmm29, %zmm30 + +# CHECK: vpmultishiftqb -1032(%rdx){1to8}, %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0xb2,0xf8,0xfb,0xff,0xff] + vpmultishiftqb -1032(%rdx){1to8}, %zmm29, %zmm30 + +# CHECK: vpmultishiftqb 4660(%rax,%r14,8), %zmm29, %zmm30 +# CHECK: encoding: [0x62,0x22,0x95,0x40,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpmultishiftqb 4660(%rax,%r14,8), %zmm29, %zmm30 diff --git a/llvm/test/MC/X86/avx512vbmi-encoding.s b/llvm/test/MC/X86/avx512vbmi-encoding.s deleted file mode 100644 index bf11e1999d25..000000000000 --- a/llvm/test/MC/X86/avx512vbmi-encoding.s +++ /dev/null @@ -1,543 +0,0 @@ -// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s - - vpermb %xmm28, %xmm29, %xmm30 {%k7} -//CHECK: vpermb %xmm28, %xmm29, %xmm30 {%k7} -//CHECK: encoding: [0x62,0x02,0x15,0x07,0x8d,0xf4] - - vpermb %xmm28, %xmm29, %xmm30 {%k7} {z} -//CHECK: vpermb %xmm28, %xmm29, %xmm30 {%k7} {z} -//CHECK: encoding: [0x62,0x02,0x15,0x87,0x8d,0xf4] - - vpermb (%rcx), %xmm29, %xmm30 -//CHECK: vpermb (%rcx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0x31] - - vpermb 0x123(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: vpermb 291(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x22,0x15,0x00,0x8d,0xb4,0xf0,0x23,0x01,0x00,0x00] - - vpermb 0x7f0(%rdx), %xmm29, %xmm30 -//CHECK: vpermb 2032(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0x72,0x7f] - - vpermb 0x800(%rdx), %xmm29, %xmm30 -//CHECK: vpermb 2048(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0xb2,0x00,0x08,0x00,0x00] - - vpermb -0x800(%rdx), %xmm29, %xmm30 -//CHECK: vpermb -2048(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0x72,0x80] - - vpermb -0x810(%rdx), %xmm29, %xmm30 -//CHECK: vpermb -2064(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0xb2,0xf0,0xf7,0xff,0xff] - - vpermb %ymm28, %ymm29, %ymm30 -//CHECK: vpermb %ymm28, %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x02,0x15,0x20,0x8d,0xf4] - - vpermb %ymm28, %ymm29, %ymm30 {%k7} -//CHECK: vpermb %ymm28, %ymm29, %ymm30 {%k7} -//CHECK: encoding: [0x62,0x02,0x15,0x27,0x8d,0xf4] - - vpermb %ymm28, %ymm29, %ymm30 {%k7} {z} -//CHECK: vpermb %ymm28, %ymm29, %ymm30 {%k7} {z} -//CHECK: encoding: [0x62,0x02,0x15,0xa7,0x8d,0xf4] - - vpermb (%rcx), %ymm29, %ymm30 -//CHECK: vpermb (%rcx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0x31] - - vpermb 0x123(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: vpermb 291(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x22,0x15,0x20,0x8d,0xb4,0xf0,0x23,0x01,0x00,0x00] - - vpermb 0xfe0(%rdx), %ymm29, %ymm30 -//CHECK: vpermb 4064(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0x72,0x7f] - - vpermb 0x1000(%rdx), %ymm29, %ymm30 -//CHECK: vpermb 4096(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0xb2,0x00,0x10,0x00,0x00] - - vpermb -0x1000(%rdx), %ymm29, %ymm30 -//CHECK: vpermb -4096(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0x72,0x80] - - vpermb -0x1020(%rdx), %ymm29, %ymm30 -//CHECK: vpermb -4128(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0xb2,0xe0,0xef,0xff,0xff] - - vpermb %xmm28, %xmm29, %xmm30 -//CHECK: vpermb %xmm28, %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x02,0x15,0x00,0x8d,0xf4] - - vpermb 0x1234(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: vpermb 4660(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x22,0x15,0x00,0x8d,0xb4,0xf0,0x34,0x12,0x00,0x00] - - vpermb 0x1234(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: vpermb 4660(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x22,0x15,0x20,0x8d,0xb4,0xf0,0x34,0x12,0x00,0x00] - - vpermb %zmm28, %zmm29, %zmm30 -//CHECK: vpermb %zmm28, %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x02,0x15,0x40,0x8d,0xf4] - - vpermb %zmm28, %zmm29, %zmm30 {%k7} -//CHECK: vpermb %zmm28, %zmm29, %zmm30 {%k7} -//CHECK: encoding: [0x62,0x02,0x15,0x47,0x8d,0xf4] - - vpermb %zmm28, %zmm29, %zmm30 {%k7} {z} -//CHECK: vpermb %zmm28, %zmm29, %zmm30 {%k7} {z} -//CHECK: encoding: [0x62,0x02,0x15,0xc7,0x8d,0xf4] - - vpermb (%rcx), %zmm29, %zmm30 -//CHECK: vpermb (%rcx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0x31] - - vpermb 0x123(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: vpermb 291(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x22,0x15,0x40,0x8d,0xb4,0xf0,0x23,0x01,0x00,0x00] - - vpermb 0x1fc0(%rdx), %zmm29, %zmm30 -//CHECK: vpermb 8128(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0x72,0x7f] - - vpermb 0x2000(%rdx), %zmm29, %zmm30 -//CHECK: vpermb 8192(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0xb2,0x00,0x20,0x00,0x00] - - vpermb -0x2000(%rdx), %zmm29, %zmm30 -//CHECK: vpermb -8192(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0x72,0x80] - - vpermb -0x2040(%rdx), %zmm29, %zmm30 -//CHECK: vpermb -8256(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0xb2,0xc0,0xdf,0xff,0xff] - - vpermb 0x1234(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: vpermb 4660(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x22,0x15,0x40,0x8d,0xb4,0xf0,0x34,0x12,0x00,0x00] - - vpermt2b %xmm28, %xmm29, %xmm30 -//CHECK: vpermt2b %xmm28, %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x02,0x15,0x00,0x7d,0xf4] - - vpermt2b %xmm28, %xmm29, %xmm30 {%k7} -//CHECK: vpermt2b %xmm28, %xmm29, %xmm30 {%k7} -//CHECK: encoding: [0x62,0x02,0x15,0x07,0x7d,0xf4] - - vpermt2b %xmm28, %xmm29, %xmm30 {%k7} {z} -//CHECK: vpermt2b %xmm28, %xmm29, %xmm30 {%k7} {z} -//CHECK: encoding: [0x62,0x02,0x15,0x87,0x7d,0xf4] - - vpermt2b (%rcx), %xmm29, %xmm30 -//CHECK: vpermt2b (%rcx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0x31] - - vpermt2b 0x123(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: vpermt2b 291(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x22,0x15,0x00,0x7d,0xb4,0xf0,0x23,0x01,0x00,0x00] - - vpermt2b 0x7f0(%rdx), %xmm29, %xmm30 -//CHECK: vpermt2b 2032(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0x72,0x7f] - - vpermt2b 0x800(%rdx), %xmm29, %xmm30 -//CHECK: vpermt2b 2048(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0xb2,0x00,0x08,0x00,0x00] - - vpermt2b -0x800(%rdx), %xmm29, %xmm30 -//CHECK: vpermt2b -2048(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0x72,0x80] - - vpermt2b -0x810(%rdx), %xmm29, %xmm30 -//CHECK: vpermt2b -2064(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0xb2,0xf0,0xf7,0xff,0xff] - - vpermt2b %ymm28, %ymm29, %ymm30 -//CHECK: vpermt2b %ymm28, %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x02,0x15,0x20,0x7d,0xf4] - - vpermt2b %ymm28, %ymm29, %ymm30 {%k7} -//CHECK: vpermt2b %ymm28, %ymm29, %ymm30 {%k7} -//CHECK: encoding: [0x62,0x02,0x15,0x27,0x7d,0xf4] - - vpermt2b %ymm28, %ymm29, %ymm30 {%k7} {z} -//CHECK: vpermt2b %ymm28, %ymm29, %ymm30 {%k7} {z} -//CHECK: encoding: [0x62,0x02,0x15,0xa7,0x7d,0xf4] - - vpermt2b (%rcx), %ymm29, %ymm30 -//CHECK: vpermt2b (%rcx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0x31] - - vpermt2b 0x123(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: vpermt2b 291(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x22,0x15,0x20,0x7d,0xb4,0xf0,0x23,0x01,0x00,0x00] - - vpermt2b 0xfe0(%rdx), %ymm29, %ymm30 -//CHECK: vpermt2b 4064(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0x72,0x7f] - - vpermt2b 0x1000(%rdx), %ymm29, %ymm30 -//CHECK: vpermt2b 4096(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0xb2,0x00,0x10,0x00,0x00] - - vpermt2b -0x1000(%rdx), %ymm29, %ymm30 -//CHECK: vpermt2b -4096(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0x72,0x80] - - vpermt2b -0x1020(%rdx), %ymm29, %ymm30 -//CHECK: vpermt2b -4128(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0xb2,0xe0,0xef,0xff,0xff] - - vpermt2b 0x1234(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: vpermt2b 4660(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x22,0x15,0x00,0x7d,0xb4,0xf0,0x34,0x12,0x00,0x00] - - vpermt2b 0x1234(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: vpermt2b 4660(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x22,0x15,0x20,0x7d,0xb4,0xf0,0x34,0x12,0x00,0x00] - - vpermt2b %zmm28, %zmm29, %zmm30 -//CHECK: vpermt2b %zmm28, %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x02,0x15,0x40,0x7d,0xf4] - - vpermt2b %zmm28, %zmm29, %zmm30 {%k7} -//CHECK: vpermt2b %zmm28, %zmm29, %zmm30 {%k7} -//CHECK: encoding: [0x62,0x02,0x15,0x47,0x7d,0xf4] - - vpermt2b %zmm28, %zmm29, %zmm30 {%k7} {z} -//CHECK: vpermt2b %zmm28, %zmm29, %zmm30 {%k7} {z} -//CHECK: encoding: [0x62,0x02,0x15,0xc7,0x7d,0xf4] - - vpermt2b (%rcx), %zmm29, %zmm30 -//CHECK: vpermt2b (%rcx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0x31] - - vpermt2b 0x123(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: vpermt2b 291(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x22,0x15,0x40,0x7d,0xb4,0xf0,0x23,0x01,0x00,0x00] - - vpermt2b 0x1fc0(%rdx), %zmm29, %zmm30 -//CHECK: vpermt2b 8128(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0x72,0x7f] - - vpermt2b 0x2000(%rdx), %zmm29, %zmm30 -//CHECK: vpermt2b 8192(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0xb2,0x00,0x20,0x00,0x00] - - vpermt2b -0x2000(%rdx), %zmm29, %zmm30 -//CHECK: vpermt2b -8192(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0x72,0x80] - - vpermt2b -0x2040(%rdx), %zmm29, %zmm30 -//CHECK: vpermt2b -8256(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0xb2,0xc0,0xdf,0xff,0xff] - - vpermt2b 0x1234(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: vpermt2b 4660(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x22,0x15,0x40,0x7d,0xb4,0xf0,0x34,0x12,0x00,0x00] - - vpermi2b %xmm28, %xmm29, %xmm30 -//CHECK: vpermi2b %xmm28, %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x02,0x15,0x00,0x75,0xf4] - - vpermi2b %xmm28, %xmm29, %xmm30 {%k7} -//CHECK: vpermi2b %xmm28, %xmm29, %xmm30 {%k7} -//CHECK: encoding: [0x62,0x02,0x15,0x07,0x75,0xf4] - - vpermi2b %xmm28, %xmm29, %xmm30 {%k7} {z} -//CHECK: vpermi2b %xmm28, %xmm29, %xmm30 {%k7} {z} -//CHECK: encoding: [0x62,0x02,0x15,0x87,0x75,0xf4] - - vpermi2b (%rcx), %xmm29, %xmm30 -//CHECK: vpermi2b (%rcx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0x31] - - vpermi2b 0x123(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: vpermi2b 291(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x22,0x15,0x00,0x75,0xb4,0xf0,0x23,0x01,0x00,0x00] - - vpermi2b 0x7f0(%rdx), %xmm29, %xmm30 -//CHECK: vpermi2b 2032(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0x72,0x7f] - - vpermi2b 0x800(%rdx), %xmm29, %xmm30 -//CHECK: vpermi2b 2048(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0xb2,0x00,0x08,0x00,0x00] - - vpermi2b -0x800(%rdx), %xmm29, %xmm30 -//CHECK: vpermi2b -2048(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0x72,0x80] - - vpermi2b -0x810(%rdx), %xmm29, %xmm30 -//CHECK: vpermi2b -2064(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0xb2,0xf0,0xf7,0xff,0xff] - - vpermi2b %ymm28, %ymm29, %ymm30 -//CHECK: vpermi2b %ymm28, %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x02,0x15,0x20,0x75,0xf4] - - vpermi2b %ymm28, %ymm29, %ymm30 {%k7} -//CHECK: vpermi2b %ymm28, %ymm29, %ymm30 {%k7} -//CHECK: encoding: [0x62,0x02,0x15,0x27,0x75,0xf4] - - vpermi2b %ymm28, %ymm29, %ymm30 {%k7} {z} -//CHECK: vpermi2b %ymm28, %ymm29, %ymm30 {%k7} {z} -//CHECK: encoding: [0x62,0x02,0x15,0xa7,0x75,0xf4] - - vpermi2b (%rcx), %ymm29, %ymm30 -//CHECK: vpermi2b (%rcx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0x31] - - vpermi2b 0x123(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: vpermi2b 291(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x22,0x15,0x20,0x75,0xb4,0xf0,0x23,0x01,0x00,0x00] - - vpermi2b 0xfe0(%rdx), %ymm29, %ymm30 -//CHECK: vpermi2b 4064(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0x72,0x7f] - - vpermi2b 0x1000(%rdx), %ymm29, %ymm30 -//CHECK: vpermi2b 4096(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0xb2,0x00,0x10,0x00,0x00] - - vpermi2b -0x1000(%rdx), %ymm29, %ymm30 -//CHECK: vpermi2b -4096(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0x72,0x80] - - vpermi2b -0x1020(%rdx), %ymm29, %ymm30 -//CHECK: vpermi2b -4128(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0xb2,0xe0,0xef,0xff,0xff] - - vpermi2b 0x1234(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: vpermi2b 4660(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x22,0x15,0x00,0x75,0xb4,0xf0,0x34,0x12,0x00,0x00] - - vpermi2b 0x1234(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: vpermi2b 4660(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x22,0x15,0x20,0x75,0xb4,0xf0,0x34,0x12,0x00,0x00] - - vpermi2b %zmm28, %zmm29, %zmm30 -//CHECK: vpermi2b %zmm28, %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x02,0x15,0x40,0x75,0xf4] - - vpermi2b %zmm28, %zmm29, %zmm30 {%k7} -//CHECK: vpermi2b %zmm28, %zmm29, %zmm30 {%k7} -//CHECK: encoding: [0x62,0x02,0x15,0x47,0x75,0xf4] - - vpermi2b %zmm28, %zmm29, %zmm30 {%k7} {z} -//CHECK: vpermi2b %zmm28, %zmm29, %zmm30 {%k7} {z} -//CHECK: encoding: [0x62,0x02,0x15,0xc7,0x75,0xf4] - - vpermi2b (%rcx), %zmm29, %zmm30 -//CHECK: vpermi2b (%rcx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0x31] - - vpermi2b 0x123(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: vpermi2b 291(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x22,0x15,0x40,0x75,0xb4,0xf0,0x23,0x01,0x00,0x00] - - vpermi2b 0x1fc0(%rdx), %zmm29, %zmm30 -//CHECK: vpermi2b 8128(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0x72,0x7f] - - vpermi2b 0x2000(%rdx), %zmm29, %zmm30 -//CHECK: vpermi2b 8192(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0xb2,0x00,0x20,0x00,0x00] - - vpermi2b -0x2000(%rdx), %zmm29, %zmm30 -//CHECK: vpermi2b -8192(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0x72,0x80] - - vpermi2b -0x2040(%rdx), %zmm29, %zmm30 -//CHECK: vpermi2b -8256(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0xb2,0xc0,0xdf,0xff,0xff] - - vpermi2b 0x1234(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: vpermi2b 4660(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x22,0x15,0x40,0x75,0xb4,0xf0,0x34,0x12,0x00,0x00] - - vpmultishiftqb %xmm28, %xmm29, %xmm30 -//CHECK: vpmultishiftqb %xmm28, %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x02,0x95,0x00,0x83,0xf4] - - vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7} -//CHECK: vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7} -//CHECK: encoding: [0x62,0x02,0x95,0x07,0x83,0xf4] - - vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7} {z} -//CHECK: vpmultishiftqb %xmm28, %xmm29, %xmm30 {%k7} {z} -//CHECK: encoding: [0x62,0x02,0x95,0x87,0x83,0xf4] - - vpmultishiftqb (%rcx), %xmm29, %xmm30 -//CHECK: vpmultishiftqb (%rcx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0x31] - - vpmultishiftqb 0x123(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: vpmultishiftqb 291(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x22,0x95,0x00,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00] - - vpmultishiftqb (%rcx){1to2}, %xmm29, %xmm30 -//CHECK: vpmultishiftqb (%rcx){1to2}, %xmm29, %xmm30 - -//CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0x31] - - vpmultishiftqb 0x7f0(%rdx), %xmm29, %xmm30 -//CHECK: vpmultishiftqb 2032(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0x72,0x7f] - - vpmultishiftqb 0x800(%rdx), %xmm29, %xmm30 -//CHECK: vpmultishiftqb 2048(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0xb2,0x00,0x08,0x00,0x00] - - vpmultishiftqb -0x800(%rdx), %xmm29, %xmm30 -//CHECK: vpmultishiftqb -2048(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0x72,0x80] - - vpmultishiftqb -0x810(%rdx), %xmm29, %xmm30 -//CHECK: vpmultishiftqb -2064(%rdx), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0xb2,0xf0,0xf7,0xff,0xff] - - vpmultishiftqb 0x3f8(%rdx){1to2}, %xmm29, %xmm30 -//CHECK: vpmultishiftqb 1016(%rdx){1to2}, %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0x72,0x7f] - - vpmultishiftqb 0x400(%rdx){1to2}, %xmm29, %xmm30 -//CHECK: vpmultishiftqb 1024(%rdx){1to2}, %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0xb2,0x00,0x04,0x00,0x00] - - vpmultishiftqb -0x400(%rdx){1to2}, %xmm29, %xmm30 -//CHECK: vpmultishiftqb -1024(%rdx){1to2}, %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0x72,0x80] - - vpmultishiftqb -0x408(%rdx){1to2}, %xmm29, %xmm30 -//CHECK: vpmultishiftqb -1032(%rdx){1to2}, %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0xb2,0xf8,0xfb,0xff,0xff] - - vpmultishiftqb %ymm28, %ymm29, %ymm30 -//CHECK: vpmultishiftqb %ymm28, %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x02,0x95,0x20,0x83,0xf4] - - vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7} -//CHECK: vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7} -//CHECK: encoding: [0x62,0x02,0x95,0x27,0x83,0xf4] - - vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7} {z} -//CHECK: vpmultishiftqb %ymm28, %ymm29, %ymm30 {%k7} {z} -//CHECK: encoding: [0x62,0x02,0x95,0xa7,0x83,0xf4] - - vpmultishiftqb (%rcx), %ymm29, %ymm30 -//CHECK: vpmultishiftqb (%rcx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0x31] - - vpmultishiftqb 0x123(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: vpmultishiftqb 291(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x22,0x95,0x20,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00] - - vpmultishiftqb (%rcx){1to4}, %ymm29, %ymm30 -//CHECK: vpmultishiftqb (%rcx){1to4}, %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0x31] - - vpmultishiftqb 0xfe0(%rdx), %ymm29, %ymm30 -//CHECK: vpmultishiftqb 4064(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0x72,0x7f] - - vpmultishiftqb 0x1000(%rdx), %ymm29, %ymm30 -//CHECK: vpmultishiftqb 4096(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0xb2,0x00,0x10,0x00,0x00] - - vpmultishiftqb -0x1000(%rdx), %ymm29, %ymm30 -//CHECK: vpmultishiftqb -4096(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0x72,0x80] - - vpmultishiftqb -0x1020(%rdx), %ymm29, %ymm30 -//CHECK: vpmultishiftqb -4128(%rdx), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0xb2,0xe0,0xef,0xff,0xff] - - vpmultishiftqb 0x3f8(%rdx){1to4}, %ymm29, %ymm30 -//CHECK: vpmultishiftqb 1016(%rdx){1to4}, %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0x72,0x7f] - - vpmultishiftqb 0x400(%rdx){1to4}, %ymm29, %ymm30 -//CHECK: vpmultishiftqb 1024(%rdx){1to4}, %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0xb2,0x00,0x04,0x00,0x00] - - vpmultishiftqb -0x400(%rdx){1to4}, %ymm29, %ymm30 -//CHECK: vpmultishiftqb -1024(%rdx){1to4}, %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0x72,0x80] - - vpmultishiftqb -0x408(%rdx){1to4}, %ymm29, %ymm30 -//CHECK: vpmultishiftqb -1032(%rdx){1to4}, %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0xb2,0xf8,0xfb,0xff,0xff] - - vpmultishiftqb 0x1234(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: vpmultishiftqb 4660(%rax,%r14,8), %xmm29, %xmm30 -//CHECK: encoding: [0x62,0x22,0x95,0x00,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00] - - vpmultishiftqb 0x1234(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: vpmultishiftqb 4660(%rax,%r14,8), %ymm29, %ymm30 -//CHECK: encoding: [0x62,0x22,0x95,0x20,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00] - - vpmultishiftqb %zmm28, %zmm29, %zmm30 -//CHECK: vpmultishiftqb %zmm28, %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x02,0x95,0x40,0x83,0xf4] - - vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7} -//CHECK: vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7} -//CHECK: encoding: [0x62,0x02,0x95,0x47,0x83,0xf4] - - vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7} {z} -//CHECK: vpmultishiftqb %zmm28, %zmm29, %zmm30 {%k7} {z} -//CHECK: encoding: [0x62,0x02,0x95,0xc7,0x83,0xf4] - - vpmultishiftqb (%rcx), %zmm29, %zmm30 -//CHECK: vpmultishiftqb (%rcx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0x31] - - vpmultishiftqb 0x123(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: vpmultishiftqb 291(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x22,0x95,0x40,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00] - - vpmultishiftqb (%rcx){1to8}, %zmm29, %zmm30 -//CHECK: vpmultishiftqb (%rcx){1to8}, %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0x31] - - vpmultishiftqb 0x1fc0(%rdx), %zmm29, %zmm30 -//CHECK: vpmultishiftqb 8128(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0x72,0x7f] - - vpmultishiftqb 0x2000(%rdx), %zmm29, %zmm30 -//CHECK: vpmultishiftqb 8192(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0xb2,0x00,0x20,0x00,0x00] - - vpmultishiftqb -0x2000(%rdx), %zmm29, %zmm30 -//CHECK: vpmultishiftqb -8192(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0x72,0x80] - - vpmultishiftqb -0x2040(%rdx), %zmm29, %zmm30 -//CHECK: vpmultishiftqb -8256(%rdx), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0xb2,0xc0,0xdf,0xff,0xff] - - vpmultishiftqb 0x3f8(%rdx){1to8}, %zmm29, %zmm30 -//CHECK: vpmultishiftqb 1016(%rdx){1to8}, %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0x72,0x7f] - - vpmultishiftqb 0x400(%rdx){1to8}, %zmm29, %zmm30 -//CHECK: vpmultishiftqb 1024(%rdx){1to8}, %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0xb2,0x00,0x04,0x00,0x00] - - vpmultishiftqb -0x400(%rdx){1to8}, %zmm29, %zmm30 -//CHECK: vpmultishiftqb -1024(%rdx){1to8}, %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0x72,0x80] - - vpmultishiftqb -0x408(%rdx){1to8}, %zmm29, %zmm30 -//CHECK: vpmultishiftqb -1032(%rdx){1to8}, %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0xb2,0xf8,0xfb,0xff,0xff] - - vpmultishiftqb 0x1234(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: vpmultishiftqb 4660(%rax,%r14,8), %zmm29, %zmm30 -//CHECK: encoding: [0x62,0x22,0x95,0x40,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00] - diff --git a/llvm/test/MC/X86/avx512vbmi-intel.s b/llvm/test/MC/X86/avx512vbmi-intel.s new file mode 100644 index 000000000000..e17b06e4c997 --- /dev/null +++ b/llvm/test/MC/X86/avx512vbmi-intel.s @@ -0,0 +1,542 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s + +# CHECK: vpermb xmm30 {k7}, xmm29, xmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x07,0x8d,0xf4] + vpermb xmm30 {k7}, xmm29, xmm28 + +# CHECK: vpermb xmm30 {k7} {z}, xmm29, xmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x87,0x8d,0xf4] + vpermb xmm30 {k7} {z}, xmm29, xmm28 + +# CHECK: vpermb xmm30, xmm29, xmmword ptr [rcx] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0x31] + vpermb xmm30, xmm29, xmmword ptr [rcx] + +# CHECK: vpermb xmm30, xmm29, xmmword ptr [rax + 8*r14 + 291] +# CHECK: encoding: [0x62,0x22,0x15,0x00,0x8d,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermb xmm30, xmm29, xmmword ptr [rax + 8*r14 + 291] + +# CHECK: vpermb xmm30, xmm29, xmmword ptr [rdx + 2032] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0x72,0x7f] + vpermb xmm30, xmm29, xmmword ptr [rdx + 2032] + +# CHECK: vpermb xmm30, xmm29, xmmword ptr [rdx + 2048] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0xb2,0x00,0x08,0x00,0x00] + vpermb xmm30, xmm29, xmmword ptr [rdx + 2048] + +# CHECK: vpermb xmm30, xmm29, xmmword ptr [rdx - 2048] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0x72,0x80] + vpermb xmm30, xmm29, xmmword ptr [rdx - 2048] + +# CHECK: vpermb xmm30, xmm29, xmmword ptr [rdx - 2064] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x8d,0xb2,0xf0,0xf7,0xff,0xff] + vpermb xmm30, xmm29, xmmword ptr [rdx - 2064] + +# CHECK: vpermb ymm30, ymm29, ymm28 +# CHECK: encoding: [0x62,0x02,0x15,0x20,0x8d,0xf4] + vpermb ymm30, ymm29, ymm28 + +# CHECK: vpermb ymm30 {k7}, ymm29, ymm28 +# CHECK: encoding: [0x62,0x02,0x15,0x27,0x8d,0xf4] + vpermb ymm30 {k7}, ymm29, ymm28 + +# CHECK: vpermb ymm30 {k7} {z}, ymm29, ymm28 +# CHECK: encoding: [0x62,0x02,0x15,0xa7,0x8d,0xf4] + vpermb ymm30 {k7} {z}, ymm29, ymm28 + +# CHECK: vpermb ymm30, ymm29, ymmword ptr [rcx] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0x31] + vpermb ymm30, ymm29, ymmword ptr [rcx] + +# CHECK: vpermb ymm30, ymm29, ymmword ptr [rax + 8*r14 + 291] +# CHECK: encoding: [0x62,0x22,0x15,0x20,0x8d,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermb ymm30, ymm29, ymmword ptr [rax + 8*r14 + 291] + +# CHECK: vpermb ymm30, ymm29, ymmword ptr [rdx + 4064] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0x72,0x7f] + vpermb ymm30, ymm29, ymmword ptr [rdx + 4064] + +# CHECK: vpermb ymm30, ymm29, ymmword ptr [rdx + 4096] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0xb2,0x00,0x10,0x00,0x00] + vpermb ymm30, ymm29, ymmword ptr [rdx + 4096] + +# CHECK: vpermb ymm30, ymm29, ymmword ptr [rdx - 4096] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0x72,0x80] + vpermb ymm30, ymm29, ymmword ptr [rdx - 4096] + +# CHECK: vpermb ymm30, ymm29, ymmword ptr [rdx - 4128] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x8d,0xb2,0xe0,0xef,0xff,0xff] + vpermb ymm30, ymm29, ymmword ptr [rdx - 4128] + +# CHECK: vpermb xmm30, xmm29, xmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x00,0x8d,0xf4] + vpermb xmm30, xmm29, xmm28 + +# CHECK: vpermb xmm30, xmm29, xmmword ptr [rax + 8*r14 + 4660] +# CHECK: encoding: [0x62,0x22,0x15,0x00,0x8d,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermb xmm30, xmm29, xmmword ptr [rax + 8*r14 + 4660] + +# CHECK: vpermb ymm30, ymm29, ymmword ptr [rax + 8*r14 + 4660] +# CHECK: encoding: [0x62,0x22,0x15,0x20,0x8d,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermb ymm30, ymm29, ymmword ptr [rax + 8*r14 + 4660] + +# CHECK: vpermb zmm30, zmm29, zmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x40,0x8d,0xf4] + vpermb zmm30, zmm29, zmm28 + +# CHECK: vpermb zmm30 {k7}, zmm29, zmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x47,0x8d,0xf4] + vpermb zmm30 {k7}, zmm29, zmm28 + +# CHECK: vpermb zmm30 {k7} {z}, zmm29, zmm28 +# CHECK: encoding: [0x62,0x02,0x15,0xc7,0x8d,0xf4] + vpermb zmm30 {k7} {z}, zmm29, zmm28 + +# CHECK: vpermb zmm30, zmm29, zmmword ptr [rcx] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0x31] + vpermb zmm30, zmm29, zmmword ptr [rcx] + +# CHECK: vpermb zmm30, zmm29, zmmword ptr [rax + 8*r14 + 291] +# CHECK: encoding: [0x62,0x22,0x15,0x40,0x8d,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermb zmm30, zmm29, zmmword ptr [rax + 8*r14 + 291] + +# CHECK: vpermb zmm30, zmm29, zmmword ptr [rdx + 8128] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0x72,0x7f] + vpermb zmm30, zmm29, zmmword ptr [rdx + 8128] + +# CHECK: vpermb zmm30, zmm29, zmmword ptr [rdx + 8192] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0xb2,0x00,0x20,0x00,0x00] + vpermb zmm30, zmm29, zmmword ptr [rdx + 8192] + +# CHECK: vpermb zmm30, zmm29, zmmword ptr [rdx - 8192] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0x72,0x80] + vpermb zmm30, zmm29, zmmword ptr [rdx - 8192] + +# CHECK: vpermb zmm30, zmm29, zmmword ptr [rdx - 8256] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x8d,0xb2,0xc0,0xdf,0xff,0xff] + vpermb zmm30, zmm29, zmmword ptr [rdx - 8256] + +# CHECK: vpermb zmm30, zmm29, zmmword ptr [rax + 8*r14 + 4660] +# CHECK: encoding: [0x62,0x22,0x15,0x40,0x8d,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermb zmm30, zmm29, zmmword ptr [rax + 8*r14 + 4660] + +# CHECK: vpermt2b xmm30, xmm29, xmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x00,0x7d,0xf4] + vpermt2b xmm30, xmm29, xmm28 + +# CHECK: vpermt2b xmm30 {k7}, xmm29, xmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x07,0x7d,0xf4] + vpermt2b xmm30 {k7}, xmm29, xmm28 + +# CHECK: vpermt2b xmm30 {k7} {z}, xmm29, xmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x87,0x7d,0xf4] + vpermt2b xmm30 {k7} {z}, xmm29, xmm28 + +# CHECK: vpermt2b xmm30, xmm29, xmmword ptr [rcx] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0x31] + vpermt2b xmm30, xmm29, xmmword ptr [rcx] + +# CHECK: vpermt2b xmm30, xmm29, xmmword ptr [rax + 8*r14 + 291] +# CHECK: encoding: [0x62,0x22,0x15,0x00,0x7d,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermt2b xmm30, xmm29, xmmword ptr [rax + 8*r14 + 291] + +# CHECK: vpermt2b xmm30, xmm29, xmmword ptr [rdx + 2032] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0x72,0x7f] + vpermt2b xmm30, xmm29, xmmword ptr [rdx + 2032] + +# CHECK: vpermt2b xmm30, xmm29, xmmword ptr [rdx + 2048] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0xb2,0x00,0x08,0x00,0x00] + vpermt2b xmm30, xmm29, xmmword ptr [rdx + 2048] + +# CHECK: vpermt2b xmm30, xmm29, xmmword ptr [rdx - 2048] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0x72,0x80] + vpermt2b xmm30, xmm29, xmmword ptr [rdx - 2048] + +# CHECK: vpermt2b xmm30, xmm29, xmmword ptr [rdx - 2064] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x7d,0xb2,0xf0,0xf7,0xff,0xff] + vpermt2b xmm30, xmm29, xmmword ptr [rdx - 2064] + +# CHECK: vpermt2b ymm30, ymm29, ymm28 +# CHECK: encoding: [0x62,0x02,0x15,0x20,0x7d,0xf4] + vpermt2b ymm30, ymm29, ymm28 + +# CHECK: vpermt2b ymm30 {k7}, ymm29, ymm28 +# CHECK: encoding: [0x62,0x02,0x15,0x27,0x7d,0xf4] + vpermt2b ymm30 {k7}, ymm29, ymm28 + +# CHECK: vpermt2b ymm30 {k7} {z}, ymm29, ymm28 +# CHECK: encoding: [0x62,0x02,0x15,0xa7,0x7d,0xf4] + vpermt2b ymm30 {k7} {z}, ymm29, ymm28 + +# CHECK: vpermt2b ymm30, ymm29, ymmword ptr [rcx] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0x31] + vpermt2b ymm30, ymm29, ymmword ptr [rcx] + +# CHECK: vpermt2b ymm30, ymm29, ymmword ptr [rax + 8*r14 + 291] +# CHECK: encoding: [0x62,0x22,0x15,0x20,0x7d,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermt2b ymm30, ymm29, ymmword ptr [rax + 8*r14 + 291] + +# CHECK: vpermt2b ymm30, ymm29, ymmword ptr [rdx + 4064] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0x72,0x7f] + vpermt2b ymm30, ymm29, ymmword ptr [rdx + 4064] + +# CHECK: vpermt2b ymm30, ymm29, ymmword ptr [rdx + 4096] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0xb2,0x00,0x10,0x00,0x00] + vpermt2b ymm30, ymm29, ymmword ptr [rdx + 4096] + +# CHECK: vpermt2b ymm30, ymm29, ymmword ptr [rdx - 4096] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0x72,0x80] + vpermt2b ymm30, ymm29, ymmword ptr [rdx - 4096] + +# CHECK: vpermt2b ymm30, ymm29, ymmword ptr [rdx - 4128] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x7d,0xb2,0xe0,0xef,0xff,0xff] + vpermt2b ymm30, ymm29, ymmword ptr [rdx - 4128] + +# CHECK: vpermt2b xmm30, xmm29, xmmword ptr [rax + 8*r14 + 4660] +# CHECK: encoding: [0x62,0x22,0x15,0x00,0x7d,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermt2b xmm30, xmm29, xmmword ptr [rax + 8*r14 + 4660] + +# CHECK: vpermt2b ymm30, ymm29, ymmword ptr [rax + 8*r14 + 4660] +# CHECK: encoding: [0x62,0x22,0x15,0x20,0x7d,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermt2b ymm30, ymm29, ymmword ptr [rax + 8*r14 + 4660] + +# CHECK: vpermt2b zmm30, zmm29, zmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x40,0x7d,0xf4] + vpermt2b zmm30, zmm29, zmm28 + +# CHECK: vpermt2b zmm30 {k7}, zmm29, zmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x47,0x7d,0xf4] + vpermt2b zmm30 {k7}, zmm29, zmm28 + +# CHECK: vpermt2b zmm30 {k7} {z}, zmm29, zmm28 +# CHECK: encoding: [0x62,0x02,0x15,0xc7,0x7d,0xf4] + vpermt2b zmm30 {k7} {z}, zmm29, zmm28 + +# CHECK: vpermt2b zmm30, zmm29, zmmword ptr [rcx] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0x31] + vpermt2b zmm30, zmm29, zmmword ptr [rcx] + +# CHECK: vpermt2b zmm30, zmm29, zmmword ptr [rax + 8*r14 + 291] +# CHECK: encoding: [0x62,0x22,0x15,0x40,0x7d,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermt2b zmm30, zmm29, zmmword ptr [rax + 8*r14 + 291] + +# CHECK: vpermt2b zmm30, zmm29, zmmword ptr [rdx + 8128] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0x72,0x7f] + vpermt2b zmm30, zmm29, zmmword ptr [rdx + 8128] + +# CHECK: vpermt2b zmm30, zmm29, zmmword ptr [rdx + 8192] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0xb2,0x00,0x20,0x00,0x00] + vpermt2b zmm30, zmm29, zmmword ptr [rdx + 8192] + +# CHECK: vpermt2b zmm30, zmm29, zmmword ptr [rdx - 8192] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0x72,0x80] + vpermt2b zmm30, zmm29, zmmword ptr [rdx - 8192] + +# CHECK: vpermt2b zmm30, zmm29, zmmword ptr [rdx - 8256] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x7d,0xb2,0xc0,0xdf,0xff,0xff] + vpermt2b zmm30, zmm29, zmmword ptr [rdx - 8256] + +# CHECK: vpermt2b zmm30, zmm29, zmmword ptr [rax + 8*r14 + 4660] +# CHECK: encoding: [0x62,0x22,0x15,0x40,0x7d,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermt2b zmm30, zmm29, zmmword ptr [rax + 8*r14 + 4660] + +# CHECK: vpermi2b xmm30, xmm29, xmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x00,0x75,0xf4] + vpermi2b xmm30, xmm29, xmm28 + +# CHECK: vpermi2b xmm30 {k7}, xmm29, xmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x07,0x75,0xf4] + vpermi2b xmm30 {k7}, xmm29, xmm28 + +# CHECK: vpermi2b xmm30 {k7} {z}, xmm29, xmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x87,0x75,0xf4] + vpermi2b xmm30 {k7} {z}, xmm29, xmm28 + +# CHECK: vpermi2b xmm30, xmm29, xmmword ptr [rcx] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0x31] + vpermi2b xmm30, xmm29, xmmword ptr [rcx] + +# CHECK: vpermi2b xmm30, xmm29, xmmword ptr [rax + 8*r14 + 291] +# CHECK: encoding: [0x62,0x22,0x15,0x00,0x75,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermi2b xmm30, xmm29, xmmword ptr [rax + 8*r14 + 291] + +# CHECK: vpermi2b xmm30, xmm29, xmmword ptr [rdx + 2032] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0x72,0x7f] + vpermi2b xmm30, xmm29, xmmword ptr [rdx + 2032] + +# CHECK: vpermi2b xmm30, xmm29, xmmword ptr [rdx + 2048] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0xb2,0x00,0x08,0x00,0x00] + vpermi2b xmm30, xmm29, xmmword ptr [rdx + 2048] + +# CHECK: vpermi2b xmm30, xmm29, xmmword ptr [rdx - 2048] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0x72,0x80] + vpermi2b xmm30, xmm29, xmmword ptr [rdx - 2048] + +# CHECK: vpermi2b xmm30, xmm29, xmmword ptr [rdx - 2064] +# CHECK: encoding: [0x62,0x62,0x15,0x00,0x75,0xb2,0xf0,0xf7,0xff,0xff] + vpermi2b xmm30, xmm29, xmmword ptr [rdx - 2064] + +# CHECK: vpermi2b ymm30, ymm29, ymm28 +# CHECK: encoding: [0x62,0x02,0x15,0x20,0x75,0xf4] + vpermi2b ymm30, ymm29, ymm28 + +# CHECK: vpermi2b ymm30 {k7}, ymm29, ymm28 +# CHECK: encoding: [0x62,0x02,0x15,0x27,0x75,0xf4] + vpermi2b ymm30 {k7}, ymm29, ymm28 + +# CHECK: vpermi2b ymm30 {k7} {z}, ymm29, ymm28 +# CHECK: encoding: [0x62,0x02,0x15,0xa7,0x75,0xf4] + vpermi2b ymm30 {k7} {z}, ymm29, ymm28 + +# CHECK: vpermi2b ymm30, ymm29, ymmword ptr [rcx] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0x31] + vpermi2b ymm30, ymm29, ymmword ptr [rcx] + +# CHECK: vpermi2b ymm30, ymm29, ymmword ptr [rax + 8*r14 + 291] +# CHECK: encoding: [0x62,0x22,0x15,0x20,0x75,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermi2b ymm30, ymm29, ymmword ptr [rax + 8*r14 + 291] + +# CHECK: vpermi2b ymm30, ymm29, ymmword ptr [rdx + 4064] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0x72,0x7f] + vpermi2b ymm30, ymm29, ymmword ptr [rdx + 4064] + +# CHECK: vpermi2b ymm30, ymm29, ymmword ptr [rdx + 4096] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0xb2,0x00,0x10,0x00,0x00] + vpermi2b ymm30, ymm29, ymmword ptr [rdx + 4096] + +# CHECK: vpermi2b ymm30, ymm29, ymmword ptr [rdx - 4096] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0x72,0x80] + vpermi2b ymm30, ymm29, ymmword ptr [rdx - 4096] + +# CHECK: vpermi2b ymm30, ymm29, ymmword ptr [rdx - 4128] +# CHECK: encoding: [0x62,0x62,0x15,0x20,0x75,0xb2,0xe0,0xef,0xff,0xff] + vpermi2b ymm30, ymm29, ymmword ptr [rdx - 4128] + +# CHECK: vpermi2b xmm30, xmm29, xmmword ptr [rax + 8*r14 + 4660] +# CHECK: encoding: [0x62,0x22,0x15,0x00,0x75,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermi2b xmm30, xmm29, xmmword ptr [rax + 8*r14 + 4660] + +# CHECK: vpermi2b ymm30, ymm29, ymmword ptr [rax + 8*r14 + 4660] +# CHECK: encoding: [0x62,0x22,0x15,0x20,0x75,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermi2b ymm30, ymm29, ymmword ptr [rax + 8*r14 + 4660] + +# CHECK: vpermi2b zmm30, zmm29, zmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x40,0x75,0xf4] + vpermi2b zmm30, zmm29, zmm28 + +# CHECK: vpermi2b zmm30 {k7}, zmm29, zmm28 +# CHECK: encoding: [0x62,0x02,0x15,0x47,0x75,0xf4] + vpermi2b zmm30 {k7}, zmm29, zmm28 + +# CHECK: vpermi2b zmm30 {k7} {z}, zmm29, zmm28 +# CHECK: encoding: [0x62,0x02,0x15,0xc7,0x75,0xf4] + vpermi2b zmm30 {k7} {z}, zmm29, zmm28 + +# CHECK: vpermi2b zmm30, zmm29, zmmword ptr [rcx] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0x31] + vpermi2b zmm30, zmm29, zmmword ptr [rcx] + +# CHECK: vpermi2b zmm30, zmm29, zmmword ptr [rax + 8*r14 + 291] +# CHECK: encoding: [0x62,0x22,0x15,0x40,0x75,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpermi2b zmm30, zmm29, zmmword ptr [rax + 8*r14 + 291] + +# CHECK: vpermi2b zmm30, zmm29, zmmword ptr [rdx + 8128] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0x72,0x7f] + vpermi2b zmm30, zmm29, zmmword ptr [rdx + 8128] + +# CHECK: vpermi2b zmm30, zmm29, zmmword ptr [rdx + 8192] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0xb2,0x00,0x20,0x00,0x00] + vpermi2b zmm30, zmm29, zmmword ptr [rdx + 8192] + +# CHECK: vpermi2b zmm30, zmm29, zmmword ptr [rdx - 8192] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0x72,0x80] + vpermi2b zmm30, zmm29, zmmword ptr [rdx - 8192] + +# CHECK: vpermi2b zmm30, zmm29, zmmword ptr [rdx - 8256] +# CHECK: encoding: [0x62,0x62,0x15,0x40,0x75,0xb2,0xc0,0xdf,0xff,0xff] + vpermi2b zmm30, zmm29, zmmword ptr [rdx - 8256] + +# CHECK: vpermi2b zmm30, zmm29, zmmword ptr [rax + 8*r14 + 4660] +# CHECK: encoding: [0x62,0x22,0x15,0x40,0x75,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpermi2b zmm30, zmm29, zmmword ptr [rax + 8*r14 + 4660] + +# CHECK: vpmultishiftqb xmm30, xmm29, xmm28 +# CHECK: encoding: [0x62,0x02,0x95,0x00,0x83,0xf4] + vpmultishiftqb xmm30, xmm29, xmm28 + +# CHECK: vpmultishiftqb xmm30 {k7}, xmm29, xmm28 +# CHECK: encoding: [0x62,0x02,0x95,0x07,0x83,0xf4] + vpmultishiftqb xmm30 {k7}, xmm29, xmm28 + +# CHECK: vpmultishiftqb xmm30 {k7} {z}, xmm29, xmm28 +# CHECK: encoding: [0x62,0x02,0x95,0x87,0x83,0xf4] + vpmultishiftqb xmm30 {k7} {z}, xmm29, xmm28 + +# CHECK: vpmultishiftqb xmm30, xmm29, xmmword ptr [rcx] +# CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0x31] + vpmultishiftqb xmm30, xmm29, xmmword ptr [rcx] + +# CHECK: vpmultishiftqb xmm30, xmm29, xmmword ptr [rax + 8*r14 + 291] +# CHECK: encoding: [0x62,0x22,0x95,0x00,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpmultishiftqb xmm30, xmm29, xmmword ptr [rax + 8*r14 + 291] + +# CHECK: vpmultishiftqb xmm30, xmm29, qword ptr [rcx]{1to2} +# CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0x31] + vpmultishiftqb xmm30, xmm29, qword ptr [rcx]{1to2} + + +# CHECK: vpmultishiftqb xmm30, xmm29, xmmword ptr [rdx + 2032] +# CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0x72,0x7f] + vpmultishiftqb xmm30, xmm29, xmmword ptr [rdx + 2032] + +# CHECK: vpmultishiftqb xmm30, xmm29, xmmword ptr [rdx + 2048] +# CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0xb2,0x00,0x08,0x00,0x00] + vpmultishiftqb xmm30, xmm29, xmmword ptr [rdx + 2048] + +# CHECK: vpmultishiftqb xmm30, xmm29, xmmword ptr [rdx - 2048] +# CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0x72,0x80] + vpmultishiftqb xmm30, xmm29, xmmword ptr [rdx - 2048] + +# CHECK: vpmultishiftqb xmm30, xmm29, xmmword ptr [rdx - 2064] +# CHECK: encoding: [0x62,0x62,0x95,0x00,0x83,0xb2,0xf0,0xf7,0xff,0xff] + vpmultishiftqb xmm30, xmm29, xmmword ptr [rdx - 2064] + +# CHECK: vpmultishiftqb xmm30, xmm29, qword ptr [rdx + 1016]{1to2} +# CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0x72,0x7f] + vpmultishiftqb xmm30, xmm29, qword ptr [rdx + 1016]{1to2} + +# CHECK: vpmultishiftqb xmm30, xmm29, qword ptr [rdx + 1024]{1to2} +# CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0xb2,0x00,0x04,0x00,0x00] + vpmultishiftqb xmm30, xmm29, qword ptr [rdx + 1024]{1to2} + +# CHECK: vpmultishiftqb xmm30, xmm29, qword ptr [rdx - 1024]{1to2} +# CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0x72,0x80] + vpmultishiftqb xmm30, xmm29, qword ptr [rdx - 1024]{1to2} + +# CHECK: vpmultishiftqb xmm30, xmm29, qword ptr [rdx - 1032]{1to2} +# CHECK: encoding: [0x62,0x62,0x95,0x10,0x83,0xb2,0xf8,0xfb,0xff,0xff] + vpmultishiftqb xmm30, xmm29, qword ptr [rdx - 1032]{1to2} + +# CHECK: vpmultishiftqb ymm30, ymm29, ymm28 +# CHECK: encoding: [0x62,0x02,0x95,0x20,0x83,0xf4] + vpmultishiftqb ymm30, ymm29, ymm28 + +# CHECK: vpmultishiftqb ymm30 {k7}, ymm29, ymm28 +# CHECK: encoding: [0x62,0x02,0x95,0x27,0x83,0xf4] + vpmultishiftqb ymm30 {k7}, ymm29, ymm28 + +# CHECK: vpmultishiftqb ymm30 {k7} {z}, ymm29, ymm28 +# CHECK: encoding: [0x62,0x02,0x95,0xa7,0x83,0xf4] + vpmultishiftqb ymm30 {k7} {z}, ymm29, ymm28 + +# CHECK: vpmultishiftqb ymm30, ymm29, ymmword ptr [rcx] +# CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0x31] + vpmultishiftqb ymm30, ymm29, ymmword ptr [rcx] + +# CHECK: vpmultishiftqb ymm30, ymm29, ymmword ptr [rax + 8*r14 + 291] +# CHECK: encoding: [0x62,0x22,0x95,0x20,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpmultishiftqb ymm30, ymm29, ymmword ptr [rax + 8*r14 + 291] + +# CHECK: vpmultishiftqb ymm30, ymm29, qword ptr [rcx]{1to4} +# CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0x31] + vpmultishiftqb ymm30, ymm29, qword ptr [rcx]{1to4} + +# CHECK: vpmultishiftqb ymm30, ymm29, ymmword ptr [rdx + 4064] +# CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0x72,0x7f] + vpmultishiftqb ymm30, ymm29, ymmword ptr [rdx + 4064] + +# CHECK: vpmultishiftqb ymm30, ymm29, ymmword ptr [rdx + 4096] +# CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0xb2,0x00,0x10,0x00,0x00] + vpmultishiftqb ymm30, ymm29, ymmword ptr [rdx + 4096] + +# CHECK: vpmultishiftqb ymm30, ymm29, ymmword ptr [rdx - 4096] +# CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0x72,0x80] + vpmultishiftqb ymm30, ymm29, ymmword ptr [rdx - 4096] + +# CHECK: vpmultishiftqb ymm30, ymm29, ymmword ptr [rdx - 4128] +# CHECK: encoding: [0x62,0x62,0x95,0x20,0x83,0xb2,0xe0,0xef,0xff,0xff] + vpmultishiftqb ymm30, ymm29, ymmword ptr [rdx - 4128] + +# CHECK: vpmultishiftqb ymm30, ymm29, qword ptr [rdx + 1016]{1to4} +# CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0x72,0x7f] + vpmultishiftqb ymm30, ymm29, qword ptr [rdx + 1016]{1to4} + +# CHECK: vpmultishiftqb ymm30, ymm29, qword ptr [rdx + 1024]{1to4} +# CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0xb2,0x00,0x04,0x00,0x00] + vpmultishiftqb ymm30, ymm29, qword ptr [rdx + 1024]{1to4} + +# CHECK: vpmultishiftqb ymm30, ymm29, qword ptr [rdx - 1024]{1to4} +# CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0x72,0x80] + vpmultishiftqb ymm30, ymm29, qword ptr [rdx - 1024]{1to4} + +# CHECK: vpmultishiftqb ymm30, ymm29, qword ptr [rdx - 1032]{1to4} +# CHECK: encoding: [0x62,0x62,0x95,0x30,0x83,0xb2,0xf8,0xfb,0xff,0xff] + vpmultishiftqb ymm30, ymm29, qword ptr [rdx - 1032]{1to4} + +# CHECK: vpmultishiftqb xmm30, xmm29, xmmword ptr [rax + 8*r14 + 4660] +# CHECK: encoding: [0x62,0x22,0x95,0x00,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpmultishiftqb xmm30, xmm29, xmmword ptr [rax + 8*r14 + 4660] + +# CHECK: vpmultishiftqb ymm30, ymm29, ymmword ptr [rax + 8*r14 + 4660] +# CHECK: encoding: [0x62,0x22,0x95,0x20,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpmultishiftqb ymm30, ymm29, ymmword ptr [rax + 8*r14 + 4660] + +# CHECK: vpmultishiftqb zmm30, zmm29, zmm28 +# CHECK: encoding: [0x62,0x02,0x95,0x40,0x83,0xf4] + vpmultishiftqb zmm30, zmm29, zmm28 + +# CHECK: vpmultishiftqb zmm30 {k7}, zmm29, zmm28 +# CHECK: encoding: [0x62,0x02,0x95,0x47,0x83,0xf4] + vpmultishiftqb zmm30 {k7}, zmm29, zmm28 + +# CHECK: vpmultishiftqb zmm30 {k7} {z}, zmm29, zmm28 +# CHECK: encoding: [0x62,0x02,0x95,0xc7,0x83,0xf4] + vpmultishiftqb zmm30 {k7} {z}, zmm29, zmm28 + +# CHECK: vpmultishiftqb zmm30, zmm29, zmmword ptr [rcx] +# CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0x31] + vpmultishiftqb zmm30, zmm29, zmmword ptr [rcx] + +# CHECK: vpmultishiftqb zmm30, zmm29, zmmword ptr [rax + 8*r14 + 291] +# CHECK: encoding: [0x62,0x22,0x95,0x40,0x83,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpmultishiftqb zmm30, zmm29, zmmword ptr [rax + 8*r14 + 291] + +# CHECK: vpmultishiftqb zmm30, zmm29, qword ptr [rcx]{1to8} +# CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0x31] + vpmultishiftqb zmm30, zmm29, qword ptr [rcx]{1to8} + +# CHECK: vpmultishiftqb zmm30, zmm29, zmmword ptr [rdx + 8128] +# CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0x72,0x7f] + vpmultishiftqb zmm30, zmm29, zmmword ptr [rdx + 8128] + +# CHECK: vpmultishiftqb zmm30, zmm29, zmmword ptr [rdx + 8192] +# CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0xb2,0x00,0x20,0x00,0x00] + vpmultishiftqb zmm30, zmm29, zmmword ptr [rdx + 8192] + +# CHECK: vpmultishiftqb zmm30, zmm29, zmmword ptr [rdx - 8192] +# CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0x72,0x80] + vpmultishiftqb zmm30, zmm29, zmmword ptr [rdx - 8192] + +# CHECK: vpmultishiftqb zmm30, zmm29, zmmword ptr [rdx - 8256] +# CHECK: encoding: [0x62,0x62,0x95,0x40,0x83,0xb2,0xc0,0xdf,0xff,0xff] + vpmultishiftqb zmm30, zmm29, zmmword ptr [rdx - 8256] + +# CHECK: vpmultishiftqb zmm30, zmm29, qword ptr [rdx + 1016]{1to8} +# CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0x72,0x7f] + vpmultishiftqb zmm30, zmm29, qword ptr [rdx + 1016]{1to8} + +# CHECK: vpmultishiftqb zmm30, zmm29, qword ptr [rdx + 1024]{1to8} +# CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0xb2,0x00,0x04,0x00,0x00] + vpmultishiftqb zmm30, zmm29, qword ptr [rdx + 1024]{1to8} + +# CHECK: vpmultishiftqb zmm30, zmm29, qword ptr [rdx - 1024]{1to8} +# CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0x72,0x80] + vpmultishiftqb zmm30, zmm29, qword ptr [rdx - 1024]{1to8} + +# CHECK: vpmultishiftqb zmm30, zmm29, qword ptr [rdx - 1032]{1to8} +# CHECK: encoding: [0x62,0x62,0x95,0x50,0x83,0xb2,0xf8,0xfb,0xff,0xff] + vpmultishiftqb zmm30, zmm29, qword ptr [rdx - 1032]{1to8} + +# CHECK: vpmultishiftqb zmm30, zmm29, zmmword ptr [rax + 8*r14 + 4660] +# CHECK: encoding: [0x62,0x22,0x95,0x40,0x83,0xb4,0xf0,0x34,0x12,0x00,0x00] + vpmultishiftqb zmm30, zmm29, zmmword ptr [rax + 8*r14 + 4660] diff --git a/llvm/test/MC/X86/avx512vbmi2-encoding.s b/llvm/test/MC/X86/avx512vbmi2-att.s index 200a24022f11..200a24022f11 100644 --- a/llvm/test/MC/X86/avx512vbmi2-encoding.s +++ b/llvm/test/MC/X86/avx512vbmi2-att.s diff --git a/llvm/test/MC/X86/avx512vbmi2vl-encoding.s b/llvm/test/MC/X86/avx512vbmi2vl-att.s index 94c8bff89ac3..94c8bff89ac3 100644 --- a/llvm/test/MC/X86/avx512vbmi2vl-encoding.s +++ b/llvm/test/MC/X86/avx512vbmi2vl-att.s diff --git a/llvm/test/MC/X86/intel-syntax-x86-avx512vbmi_vl.s b/llvm/test/MC/X86/avx512vbmi_vl-intel.s index 758b0938c796..758b0938c796 100644 --- a/llvm/test/MC/X86/intel-syntax-x86-avx512vbmi_vl.s +++ b/llvm/test/MC/X86/avx512vbmi_vl-intel.s diff --git a/llvm/test/MC/X86/avx512vl-encoding.s b/llvm/test/MC/X86/avx512vl-att.s index 01cca33369f1..01cca33369f1 100644 --- a/llvm/test/MC/X86/avx512vl-encoding.s +++ b/llvm/test/MC/X86/avx512vl-att.s diff --git a/llvm/test/MC/X86/avx512vl_bitalg-encoding.s b/llvm/test/MC/X86/avx512vl_bitalg-att.s index 6e5892c4ef00..6e5892c4ef00 100644 --- a/llvm/test/MC/X86/avx512vl_bitalg-encoding.s +++ b/llvm/test/MC/X86/avx512vl_bitalg-att.s diff --git a/llvm/test/MC/X86/avx512vl_gfni-encoding.s b/llvm/test/MC/X86/avx512vl_gfni-att.s index a44211332de6..a44211332de6 100644 --- a/llvm/test/MC/X86/avx512vl_gfni-encoding.s +++ b/llvm/test/MC/X86/avx512vl_gfni-att.s diff --git a/llvm/test/MC/X86/avx512vl_vaes-encoding.s b/llvm/test/MC/X86/avx512vl_vaes-att.s index ade414f1ed6a..ade414f1ed6a 100644 --- a/llvm/test/MC/X86/avx512vl_vaes-encoding.s +++ b/llvm/test/MC/X86/avx512vl_vaes-att.s diff --git a/llvm/test/MC/X86/avx512vl_vnni-encoding.s b/llvm/test/MC/X86/avx512vl_vnni-att.s index 04ace0495e8a..04ace0495e8a 100644 --- a/llvm/test/MC/X86/avx512vl_vnni-encoding.s +++ b/llvm/test/MC/X86/avx512vl_vnni-att.s diff --git a/llvm/test/MC/X86/avx512vnni-encoding.s b/llvm/test/MC/X86/avx512vnni-att.s index 3ece620cdd83..3ece620cdd83 100644 --- a/llvm/test/MC/X86/avx512vnni-encoding.s +++ b/llvm/test/MC/X86/avx512vnni-att.s diff --git a/llvm/test/MC/X86/avx512vp2intersect-32-att.s b/llvm/test/MC/X86/avx512vp2intersect-32-att.s new file mode 100644 index 000000000000..e1b0dc5f210c --- /dev/null +++ b/llvm/test/MC/X86/avx512vp2intersect-32-att.s @@ -0,0 +1,225 @@ +# RUN: llvm-mc -triple i386 -show-encoding %s | FileCheck %s + +# CHECK: vp2intersectq %zmm2, %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2] + vp2intersectq %zmm2, %zmm1, %k0 + +# CHECK: vp2intersectq (%edi), %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07] + vp2intersectq (%edi), %zmm1, %k0 + +# CHECK: vp2intersectq (%edi){1to8}, %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07] + vp2intersectq (%edi){1to8}, %zmm1, %k0 + +# CHECK: vp2intersectq %zmm2, %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2] + vp2intersectq %zmm2, %zmm1, %k0 + +# CHECK: vp2intersectq (%edi), %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07] + vp2intersectq (%edi), %zmm1, %k0 + +# CHECK: vp2intersectq (%edi){1to8}, %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07] + vp2intersectq (%edi){1to8}, %zmm1, %k0 + +# CHECK: vp2intersectq %zmm7, %zmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7] + vp2intersectq %zmm7, %zmm4, %k6 + +# CHECK: vp2intersectq (%esi), %zmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0x36] + vp2intersectq (%esi), %zmm4, %k6 + +# CHECK: vp2intersectq (%esi){1to8}, %zmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x58,0x68,0x36] + vp2intersectq (%esi){1to8}, %zmm4, %k6 + +# CHECK: vp2intersectq %zmm7, %zmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7] + vp2intersectq %zmm7, %zmm4, %k6 + +# CHECK: vp2intersectq (%esi), %zmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0x36] + vp2intersectq (%esi), %zmm4, %k6 + +# CHECK: vp2intersectq (%esi){1to8}, %zmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x58,0x68,0x36] + vp2intersectq (%esi){1to8}, %zmm4, %k6 + +# CHECK: vp2intersectq %ymm2, %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2] + vp2intersectq %ymm2, %ymm1, %k0 + +# CHECK: vp2intersectq (%edi), %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07] + vp2intersectq (%edi), %ymm1, %k0 + +# CHECK: vp2intersectq (%edi){1to4}, %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07] + vp2intersectq (%edi){1to4}, %ymm1, %k0 + +# CHECK: vp2intersectq %ymm2, %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2] + vp2intersectq %ymm2, %ymm1, %k0 + +# CHECK: vp2intersectq (%edi), %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07] + vp2intersectq (%edi), %ymm1, %k0 + +# CHECK: vp2intersectq (%edi){1to4}, %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07] + vp2intersectq (%edi){1to4}, %ymm1, %k0 + +# CHECK: vp2intersectq %ymm7, %ymm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0xf7] + vp2intersectq %ymm7, %ymm4, %k6 + +# CHECK: vp2intersectq (%esi), %ymm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0x36] + vp2intersectq (%esi), %ymm4, %k6 + +# CHECK: vp2intersectq (%esi){1to4}, %ymm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x38,0x68,0x36] + vp2intersectq (%esi){1to4}, %ymm4, %k6 + +# CHECK: vp2intersectq %ymm7, %ymm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0xf7] + vp2intersectq %ymm7, %ymm4, %k6 + +# CHECK: vp2intersectq (%esi), %ymm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0x36] + vp2intersectq (%esi), %ymm4, %k6 + +# CHECK: vp2intersectq %xmm2, %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2] + vp2intersectq %xmm2, %xmm1, %k0 + +# CHECK: vp2intersectq (%edi), %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07] + vp2intersectq (%edi), %xmm1, %k0 + +# CHECK: vp2intersectq (%edi){1to2}, %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x18,0x68,0x07] + vp2intersectq (%edi){1to2}, %xmm1, %k0 + +# CHECK: vp2intersectq %xmm2, %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2] + vp2intersectq %xmm2, %xmm1, %k0 + +# CHECK: vp2intersectq (%edi), %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07] + vp2intersectq (%edi), %xmm1, %k0 + +# CHECK: vp2intersectq %xmm7, %xmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0xf7] + vp2intersectq %xmm7, %xmm4, %k6 + +# CHECK: vp2intersectq (%esi), %xmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0x36] + vp2intersectq (%esi), %xmm4, %k6 + +# CHECK: vp2intersectq %xmm7, %xmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0xf7] + vp2intersectq %xmm7, %xmm4, %k6 + +# CHECK: vp2intersectq (%esi), %xmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0x36] + vp2intersectq (%esi), %xmm4, %k6 + +# CHECK: vp2intersectd %zmm2, %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2] + vp2intersectd %zmm2, %zmm1, %k0 + +# CHECK: vp2intersectd (%edi), %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07] + vp2intersectd (%edi), %zmm1, %k0 + +# CHECK: vp2intersectd %zmm2, %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2] + vp2intersectd %zmm2, %zmm1, %k0 + +# CHECK: vp2intersectd (%edi), %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07] + vp2intersectd (%edi), %zmm1, %k0 + +# CHECK: vp2intersectd %zmm7, %zmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0xf7] + vp2intersectd %zmm7, %zmm4, %k6 + +# CHECK: vp2intersectd (%esi), %zmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0x36] + vp2intersectd (%esi), %zmm4, %k6 + +# CHECK: vp2intersectd %zmm7, %zmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0xf7] + vp2intersectd %zmm7, %zmm4, %k6 + +# CHECK: vp2intersectd (%esi), %zmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0x36] + vp2intersectd (%esi), %zmm4, %k6 + +# CHECK: vp2intersectd %ymm2, %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2] + vp2intersectd %ymm2, %ymm1, %k0 + +# CHECK: vp2intersectd (%edi), %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07] + vp2intersectd (%edi), %ymm1, %k0 + +# CHECK: vp2intersectd %ymm2, %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2] + vp2intersectd %ymm2, %ymm1, %k0 + +# CHECK: vp2intersectd (%edi), %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07] + vp2intersectd (%edi), %ymm1, %k0 + +# CHECK: vp2intersectd %ymm7, %ymm4, %k6 +# CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0xf7] + vp2intersectd %ymm7, %ymm4, %k6 + +# CHECK: vp2intersectd (%esi), %ymm4, %k6 +# CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0x36] + vp2intersectd (%esi), %ymm4, %k6 + +# CHECK: vp2intersectd %ymm7, %ymm4, %k6 +# CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0xf7] + vp2intersectd %ymm7, %ymm4, %k6 + +# CHECK: vp2intersectd (%esi), %ymm4, %k6 +# CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0x36] + vp2intersectd (%esi), %ymm4, %k6 + +# CHECK: vp2intersectd %xmm2, %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2] + vp2intersectd %xmm2, %xmm1, %k0 + +# CHECK: vp2intersectd (%edi), %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07] + vp2intersectd (%edi), %xmm1, %k0 + +# CHECK: vp2intersectd %xmm2, %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2] + vp2intersectd %xmm2, %xmm1, %k0 + +# CHECK: vp2intersectd (%edi), %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07] + vp2intersectd (%edi), %xmm1, %k0 + +# CHECK: vp2intersectd %xmm7, %xmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0xf7] + vp2intersectd %xmm7, %xmm4, %k6 + +# CHECK: vp2intersectd (%esi), %xmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0x36] + vp2intersectd (%esi), %xmm4, %k6 + +# CHECK: vp2intersectd %xmm7, %xmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0xf7] + vp2intersectd %xmm7, %xmm4, %k6 + +# CHECK: vp2intersectd (%esi), %xmm4, %k6 +# CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0x36] + vp2intersectd (%esi), %xmm4, %k6 diff --git a/llvm/test/MC/X86/avx512vp2intersect-32-intel.s b/llvm/test/MC/X86/avx512vp2intersect-32-intel.s new file mode 100644 index 000000000000..a406842b5735 --- /dev/null +++ b/llvm/test/MC/X86/avx512vp2intersect-32-intel.s @@ -0,0 +1,225 @@ +# RUN: llvm-mc -triple i386 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s + +# CHECK: vp2intersectq k0, zmm1, zmm2 +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2] + vp2intersectq k0, zmm1, zmm2 + +# CHECK: vp2intersectq k0, zmm1, zmmword ptr [edi] +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07] + vp2intersectq k0, zmm1, zmmword ptr [edi] + +# CHECK: vp2intersectq k0, zmm1, qword ptr [edi]{1to8} +# CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07] + vp2intersectq k0, zmm1, qword ptr [edi]{1to8} + +# CHECK: vp2intersectq k0, zmm1, zmm2 +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2] + vp2intersectq k0, zmm1, zmm2 + +# CHECK: vp2intersectq k0, zmm1, zmmword ptr [edi] +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07] + vp2intersectq k0, zmm1, zmmword ptr [edi] + +# CHECK: vp2intersectq k0, zmm1, qword ptr [edi]{1to8} +# CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07] + vp2intersectq k0, zmm1, qword ptr [edi]{1to8} + +# CHECK: vp2intersectq k6, zmm4, zmm7 +# CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7] + vp2intersectq k6, zmm4, zmm7 + +# CHECK: vp2intersectq k6, zmm4, zmmword ptr [esi] +# CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0x36] + vp2intersectq k6, zmm4, zmmword ptr [esi] + +# CHECK: vp2intersectq k6, zmm4, qword ptr [esi]{1to8} +# CHECK: encoding: [0x62,0xf2,0xdf,0x58,0x68,0x36] + vp2intersectq k6, zmm4, qword ptr [esi]{1to8} + +# CHECK: vp2intersectq k6, zmm4, zmm7 +# CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7] + vp2intersectq k6, zmm4, zmm7 + +# CHECK: vp2intersectq k6, zmm4, zmmword ptr [esi] +# CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0x36] + vp2intersectq k6, zmm4, zmmword ptr [esi] + +# CHECK: vp2intersectq k6, zmm4, qword ptr [esi]{1to8} +# CHECK: encoding: [0x62,0xf2,0xdf,0x58,0x68,0x36] + vp2intersectq k6, zmm4, qword ptr [esi]{1to8} + +# CHECK: vp2intersectq k0, ymm1, ymm2 +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2] + vp2intersectq k0, ymm1, ymm2 + +# CHECK: vp2intersectq k0, ymm1, ymmword ptr [edi] +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07] + vp2intersectq k0, ymm1, ymmword ptr [edi] + +# CHECK: vp2intersectq k0, ymm1, qword ptr [edi]{1to4} +# CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07] + vp2intersectq k0, ymm1, qword ptr [edi]{1to4} + +# CHECK: vp2intersectq k0, ymm1, ymm2 +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2] + vp2intersectq k0, ymm1, ymm2 + +# CHECK: vp2intersectq k0, ymm1, ymmword ptr [edi] +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07] + vp2intersectq k0, ymm1, ymmword ptr [edi] + +# CHECK: vp2intersectq k0, ymm1, qword ptr [edi]{1to4} +# CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07] + vp2intersectq k0, ymm1, qword ptr [edi]{1to4} + +# CHECK: vp2intersectq k6, ymm4, ymm7 +# CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0xf7] + vp2intersectq k6, ymm4, ymm7 + +# CHECK: vp2intersectq k6, ymm4, ymmword ptr [esi] +# CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0x36] + vp2intersectq k6, ymm4, ymmword ptr [esi] + +# CHECK: vp2intersectq k6, ymm4, qword ptr [esi]{1to4} +# CHECK: encoding: [0x62,0xf2,0xdf,0x38,0x68,0x36] + vp2intersectq k6, ymm4, qword ptr [esi]{1to4} + +# CHECK: vp2intersectq k6, ymm4, ymm7 +# CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0xf7] + vp2intersectq k6, ymm4, ymm7 + +# CHECK: vp2intersectq k6, ymm4, ymmword ptr [esi] +# CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0x36] + vp2intersectq k6, ymm4, ymmword ptr [esi] + +# CHECK: vp2intersectq k0, xmm1, xmm2 +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2] + vp2intersectq k0, xmm1, xmm2 + +# CHECK: vp2intersectq k0, xmm1, xmmword ptr [edi] +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07] + vp2intersectq k0, xmm1, xmmword ptr [edi] + +# CHECK: vp2intersectq k0, xmm1, qword ptr [edi]{1to2} +# CHECK: encoding: [0x62,0xf2,0xf7,0x18,0x68,0x07] + vp2intersectq k0, xmm1, qword ptr [edi]{1to2} + +# CHECK: vp2intersectq k0, xmm1, xmm2 +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2] + vp2intersectq k0, xmm1, xmm2 + +# CHECK: vp2intersectq k0, xmm1, xmmword ptr [edi] +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07] + vp2intersectq k0, xmm1, xmmword ptr [edi] + +# CHECK: vp2intersectq k6, xmm4, xmm7 +# CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0xf7] + vp2intersectq k6, xmm4, xmm7 + +# CHECK: vp2intersectq k6, xmm4, xmmword ptr [esi] +# CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0x36] + vp2intersectq k6, xmm4, xmmword ptr [esi] + +# CHECK: vp2intersectq k6, xmm4, xmm7 +# CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0xf7] + vp2intersectq k6, xmm4, xmm7 + +# CHECK: vp2intersectq k6, xmm4, xmmword ptr [esi] +# CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0x36] + vp2intersectq k6, xmm4, xmmword ptr [esi] + +# CHECK: vp2intersectd k0, zmm1, zmm2 +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2] + vp2intersectd k0, zmm1, zmm2 + +# CHECK: vp2intersectd k0, zmm1, zmmword ptr [edi] +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07] + vp2intersectd k0, zmm1, zmmword ptr [edi] + +# CHECK: vp2intersectd k0, zmm1, zmm2 +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2] + vp2intersectd k0, zmm1, zmm2 + +# CHECK: vp2intersectd k0, zmm1, zmmword ptr [edi] +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07] + vp2intersectd k0, zmm1, zmmword ptr [edi] + +# CHECK: vp2intersectd k6, zmm4, zmm7 +# CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0xf7] + vp2intersectd k6, zmm4, zmm7 + +# CHECK: vp2intersectd k6, zmm4, zmmword ptr [esi] +# CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0x36] + vp2intersectd k6, zmm4, zmmword ptr [esi] + +# CHECK: vp2intersectd k6, zmm4, zmm7 +# CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0xf7] + vp2intersectd k6, zmm4, zmm7 + +# CHECK: vp2intersectd k6, zmm4, zmmword ptr [esi] +# CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0x36] + vp2intersectd k6, zmm4, zmmword ptr [esi] + +# CHECK: vp2intersectd k0, ymm1, ymm2 +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2] + vp2intersectd k0, ymm1, ymm2 + +# CHECK: vp2intersectd k0, ymm1, ymmword ptr [edi] +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07] + vp2intersectd k0, ymm1, ymmword ptr [edi] + +# CHECK: vp2intersectd k0, ymm1, ymm2 +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2] + vp2intersectd k0, ymm1, ymm2 + +# CHECK: vp2intersectd k0, ymm1, ymmword ptr [edi] +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07] + vp2intersectd k0, ymm1, ymmword ptr [edi] + +# CHECK: vp2intersectd k6, ymm4, ymm7 +# CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0xf7] + vp2intersectd k6, ymm4, ymm7 + +# CHECK: vp2intersectd k6, ymm4, ymmword ptr [esi] +# CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0x36] + vp2intersectd k6, ymm4, ymmword ptr [esi] + +# CHECK: vp2intersectd k6, ymm4, ymm7 +# CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0xf7] + vp2intersectd k6, ymm4, ymm7 + +# CHECK: vp2intersectd k6, ymm4, ymmword ptr [esi] +# CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0x36] + vp2intersectd k6, ymm4, ymmword ptr [esi] + +# CHECK: vp2intersectd k0, xmm1, xmm2 +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2] + vp2intersectd k0, xmm1, xmm2 + +# CHECK: vp2intersectd k0, xmm1, xmmword ptr [edi] +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07] + vp2intersectd k0, xmm1, xmmword ptr [edi] + +# CHECK: vp2intersectd k0, xmm1, xmm2 +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2] + vp2intersectd k0, xmm1, xmm2 + +# CHECK: vp2intersectd k0, xmm1, xmmword ptr [edi] +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07] + vp2intersectd k0, xmm1, xmmword ptr [edi] + +# CHECK: vp2intersectd k6, xmm4, xmm7 +# CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0xf7] + vp2intersectd k6, xmm4, xmm7 + +# CHECK: vp2intersectd k6, xmm4, xmmword ptr [esi] +# CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0x36] + vp2intersectd k6, xmm4, xmmword ptr [esi] + +# CHECK: vp2intersectd k6, xmm4, xmm7 +# CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0xf7] + vp2intersectd k6, xmm4, xmm7 + +# CHECK: vp2intersectd k6, xmm4, xmmword ptr [esi] +# CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0x36] + vp2intersectd k6, xmm4, xmmword ptr [esi] diff --git a/llvm/test/MC/X86/avx512vp2intersect-64-att.s b/llvm/test/MC/X86/avx512vp2intersect-64-att.s new file mode 100644 index 000000000000..e90541bb11ef --- /dev/null +++ b/llvm/test/MC/X86/avx512vp2intersect-64-att.s @@ -0,0 +1,226 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s + + +# CHECK: vp2intersectq %zmm2, %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2] + vp2intersectq %zmm2, %zmm1, %k0 + +# CHECK: vp2intersectq (%rdi), %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07] + vp2intersectq (%rdi), %zmm1, %k0 + +# CHECK: vp2intersectq (%rdi){1to8}, %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07] + vp2intersectq (%rdi){1to8}, %zmm1, %k0 + +# CHECK: vp2intersectq %zmm2, %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2] + vp2intersectq %zmm2, %zmm1, %k0 + +# CHECK: vp2intersectq (%rdi), %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07] + vp2intersectq (%rdi), %zmm1, %k0 + +# CHECK: vp2intersectq (%rdi){1to8}, %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07] + vp2intersectq (%rdi){1to8}, %zmm1, %k0 + +# CHECK: vp2intersectq %zmm7, %zmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0xf7] + vp2intersectq %zmm7, %zmm9, %k6 + +# CHECK: vp2intersectq (%rsi), %zmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0x36] + vp2intersectq (%rsi), %zmm9, %k6 + +# CHECK: vp2intersectq (%rsi){1to8}, %zmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x58,0x68,0x36] + vp2intersectq (%rsi){1to8}, %zmm9, %k6 + +# CHECK: vp2intersectq %zmm7, %zmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0xf7] + vp2intersectq %zmm7, %zmm9, %k6 + +# CHECK: vp2intersectq (%rsi), %zmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0x36] + vp2intersectq (%rsi), %zmm9, %k6 + +# CHECK: vp2intersectq (%rsi){1to8}, %zmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x58,0x68,0x36] + vp2intersectq (%rsi){1to8}, %zmm9, %k6 + +# CHECK: vp2intersectq %ymm2, %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2] + vp2intersectq %ymm2, %ymm1, %k0 + +# CHECK: vp2intersectq (%rdi), %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07] + vp2intersectq (%rdi), %ymm1, %k0 + +# CHECK: vp2intersectq (%rdi){1to4}, %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07] + vp2intersectq (%rdi){1to4}, %ymm1, %k0 + +# CHECK: vp2intersectq %ymm2, %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2] + vp2intersectq %ymm2, %ymm1, %k0 + +# CHECK: vp2intersectq (%rdi), %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07] + vp2intersectq (%rdi), %ymm1, %k0 + +# CHECK: vp2intersectq (%rdi){1to4}, %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07] + vp2intersectq (%rdi){1to4}, %ymm1, %k0 + +# CHECK: vp2intersectq %ymm7, %ymm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0xf7] + vp2intersectq %ymm7, %ymm9, %k6 + +# CHECK: vp2intersectq (%rsi), %ymm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0x36] + vp2intersectq (%rsi), %ymm9, %k6 + +# CHECK: vp2intersectq (%rsi){1to4}, %ymm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x38,0x68,0x36] + vp2intersectq (%rsi){1to4}, %ymm9, %k6 + +# CHECK: vp2intersectq %ymm7, %ymm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0xf7] + vp2intersectq %ymm7, %ymm9, %k6 + +# CHECK: vp2intersectq (%rsi), %ymm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0x36] + vp2intersectq (%rsi), %ymm9, %k6 + +# CHECK: vp2intersectq %xmm2, %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2] + vp2intersectq %xmm2, %xmm1, %k0 + +# CHECK: vp2intersectq (%rdi), %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07] + vp2intersectq (%rdi), %xmm1, %k0 + +# CHECK: vp2intersectq (%rdi){1to2}, %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x18,0x68,0x07] + vp2intersectq (%rdi){1to2}, %xmm1, %k0 + +# CHECK: vp2intersectq %xmm2, %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2] + vp2intersectq %xmm2, %xmm1, %k0 + +# CHECK: vp2intersectq (%rdi), %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07] + vp2intersectq (%rdi), %xmm1, %k0 + +# CHECK: vp2intersectq %xmm7, %xmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0xf7] + vp2intersectq %xmm7, %xmm9, %k6 + +# CHECK: vp2intersectq (%rsi), %xmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0x36] + vp2intersectq (%rsi), %xmm9, %k6 + +# CHECK: vp2intersectq %xmm7, %xmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0xf7] + vp2intersectq %xmm7, %xmm9, %k6 + +# CHECK: vp2intersectq (%rsi), %xmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0x36] + vp2intersectq (%rsi), %xmm9, %k6 + +# CHECK: vp2intersectd %zmm2, %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2] + vp2intersectd %zmm2, %zmm1, %k0 + +# CHECK: vp2intersectd (%rdi), %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07] + vp2intersectd (%rdi), %zmm1, %k0 + +# CHECK: vp2intersectd %zmm2, %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2] + vp2intersectd %zmm2, %zmm1, %k0 + +# CHECK: vp2intersectd (%rdi), %zmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07] + vp2intersectd (%rdi), %zmm1, %k0 + +# CHECK: vp2intersectd %zmm7, %zmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0xf7] + vp2intersectd %zmm7, %zmm9, %k6 + +# CHECK: vp2intersectd (%rsi), %zmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0x36] + vp2intersectd (%rsi), %zmm9, %k6 + +# CHECK: vp2intersectd %zmm7, %zmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0xf7] + vp2intersectd %zmm7, %zmm9, %k6 + +# CHECK: vp2intersectd (%rsi), %zmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0x36] + vp2intersectd (%rsi), %zmm9, %k6 + +# CHECK: vp2intersectd %ymm2, %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2] + vp2intersectd %ymm2, %ymm1, %k0 + +# CHECK: vp2intersectd (%rdi), %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07] + vp2intersectd (%rdi), %ymm1, %k0 + +# CHECK: vp2intersectd %ymm2, %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2] + vp2intersectd %ymm2, %ymm1, %k0 + +# CHECK: vp2intersectd (%rdi), %ymm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07] + vp2intersectd (%rdi), %ymm1, %k0 + +# CHECK: vp2intersectd %ymm7, %ymm9, %k6 +# CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0xf7] + vp2intersectd %ymm7, %ymm9, %k6 + +# CHECK: vp2intersectd (%rsi), %ymm9, %k6 +# CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0x36] + vp2intersectd (%rsi), %ymm9, %k6 + +# CHECK: vp2intersectd %ymm7, %ymm9, %k6 +# CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0xf7] + vp2intersectd %ymm7, %ymm9, %k6 + +# CHECK: vp2intersectd (%rsi), %ymm9, %k6 +# CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0x36] + vp2intersectd (%rsi), %ymm9, %k6 + +# CHECK: vp2intersectd %xmm2, %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2] + vp2intersectd %xmm2, %xmm1, %k0 + +# CHECK: vp2intersectd (%rdi), %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07] + vp2intersectd (%rdi), %xmm1, %k0 + +# CHECK: vp2intersectd %xmm2, %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2] + vp2intersectd %xmm2, %xmm1, %k0 + +# CHECK: vp2intersectd (%rdi), %xmm1, %k0 +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07] + vp2intersectd (%rdi), %xmm1, %k0 + +# CHECK: vp2intersectd %xmm7, %xmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0xf7] + vp2intersectd %xmm7, %xmm9, %k6 + +# CHECK: vp2intersectd (%rsi), %xmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0x36] + vp2intersectd (%rsi), %xmm9, %k6 + +# CHECK: vp2intersectd %xmm7, %xmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0xf7] + vp2intersectd %xmm7, %xmm9, %k6 + +# CHECK: vp2intersectd (%rsi), %xmm9, %k6 +# CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0x36] + vp2intersectd (%rsi), %xmm9, %k6 diff --git a/llvm/test/MC/X86/avx512vp2intersect-64-intel.s b/llvm/test/MC/X86/avx512vp2intersect-64-intel.s new file mode 100644 index 000000000000..3cdf49d2b037 --- /dev/null +++ b/llvm/test/MC/X86/avx512vp2intersect-64-intel.s @@ -0,0 +1,226 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s + + +# CHECK: vp2intersectq k0, zmm1, zmm2 +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2] + vp2intersectq k0, zmm1, zmm2 + +# CHECK: vp2intersectq k0, zmm1, zmmword ptr [rdi] +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07] + vp2intersectq k0, zmm1, zmmword ptr [rdi] + +# CHECK: vp2intersectq k0, zmm1, qword ptr [rdi]{1to8} +# CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07] + vp2intersectq k0, zmm1, qword ptr [rdi]{1to8} + +# CHECK: vp2intersectq k0, zmm1, zmm2 +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2] + vp2intersectq k0, zmm1, zmm2 + +# CHECK: vp2intersectq k0, zmm1, zmmword ptr [rdi] +# CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07] + vp2intersectq k0, zmm1, zmmword ptr [rdi] + +# CHECK: vp2intersectq k0, zmm1, qword ptr [rdi]{1to8} +# CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07] + vp2intersectq k0, zmm1, qword ptr [rdi]{1to8} + +# CHECK: vp2intersectq k6, zmm9, zmm7 +# CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0xf7] + vp2intersectq k6, zmm9, zmm7 + +# CHECK: vp2intersectq k6, zmm9, zmmword ptr [rsi] +# CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0x36] + vp2intersectq k6, zmm9, zmmword ptr [rsi] + +# CHECK: vp2intersectq k6, zmm9, qword ptr [rsi]{1to8} +# CHECK: encoding: [0x62,0xf2,0xb7,0x58,0x68,0x36] + vp2intersectq k6, zmm9, qword ptr [rsi]{1to8} + +# CHECK: vp2intersectq k6, zmm9, zmm7 +# CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0xf7] + vp2intersectq k6, zmm9, zmm7 + +# CHECK: vp2intersectq k6, zmm9, zmmword ptr [rsi] +# CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0x36] + vp2intersectq k6, zmm9, zmmword ptr [rsi] + +# CHECK: vp2intersectq k6, zmm9, qword ptr [rsi]{1to8} +# CHECK: encoding: [0x62,0xf2,0xb7,0x58,0x68,0x36] + vp2intersectq k6, zmm9, qword ptr [rsi]{1to8} + +# CHECK: vp2intersectq k0, ymm1, ymm2 +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2] + vp2intersectq k0, ymm1, ymm2 + +# CHECK: vp2intersectq k0, ymm1, ymmword ptr [rdi] +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07] + vp2intersectq k0, ymm1, ymmword ptr [rdi] + +# CHECK: vp2intersectq k0, ymm1, qword ptr [rdi]{1to4} +# CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07] + vp2intersectq k0, ymm1, qword ptr [rdi]{1to4} + +# CHECK: vp2intersectq k0, ymm1, ymm2 +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2] + vp2intersectq k0, ymm1, ymm2 + +# CHECK: vp2intersectq k0, ymm1, ymmword ptr [rdi] +# CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07] + vp2intersectq k0, ymm1, ymmword ptr [rdi] + +# CHECK: vp2intersectq k0, ymm1, qword ptr [rdi]{1to4} +# CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07] + vp2intersectq k0, ymm1, qword ptr [rdi]{1to4} + +# CHECK: vp2intersectq k6, ymm9, ymm7 +# CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0xf7] + vp2intersectq k6, ymm9, ymm7 + +# CHECK: vp2intersectq k6, ymm9, ymmword ptr [rsi] +# CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0x36] + vp2intersectq k6, ymm9, ymmword ptr [rsi] + +# CHECK: vp2intersectq k6, ymm9, qword ptr [rsi]{1to4} +# CHECK: encoding: [0x62,0xf2,0xb7,0x38,0x68,0x36] + vp2intersectq k6, ymm9, qword ptr [rsi]{1to4} + +# CHECK: vp2intersectq k6, ymm9, ymm7 +# CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0xf7] + vp2intersectq k6, ymm9, ymm7 + +# CHECK: vp2intersectq k6, ymm9, ymmword ptr [rsi] +# CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0x36] + vp2intersectq k6, ymm9, ymmword ptr [rsi] + +# CHECK: vp2intersectq k0, xmm1, xmm2 +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2] + vp2intersectq k0, xmm1, xmm2 + +# CHECK: vp2intersectq k0, xmm1, xmmword ptr [rdi] +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07] + vp2intersectq k0, xmm1, xmmword ptr [rdi] + +# CHECK: vp2intersectq k0, xmm1, qword ptr [rdi]{1to2} +# CHECK: encoding: [0x62,0xf2,0xf7,0x18,0x68,0x07] + vp2intersectq k0, xmm1, qword ptr [rdi]{1to2} + +# CHECK: vp2intersectq k0, xmm1, xmm2 +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2] + vp2intersectq k0, xmm1, xmm2 + +# CHECK: vp2intersectq k0, xmm1, xmmword ptr [rdi] +# CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07] + vp2intersectq k0, xmm1, xmmword ptr [rdi] + +# CHECK: vp2intersectq k6, xmm9, xmm7 +# CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0xf7] + vp2intersectq k6, xmm9, xmm7 + +# CHECK: vp2intersectq k6, xmm9, xmmword ptr [rsi] +# CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0x36] + vp2intersectq k6, xmm9, xmmword ptr [rsi] + +# CHECK: vp2intersectq k6, xmm9, xmm7 +# CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0xf7] + vp2intersectq k6, xmm9, xmm7 + +# CHECK: vp2intersectq k6, xmm9, xmmword ptr [rsi] +# CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0x36] + vp2intersectq k6, xmm9, xmmword ptr [rsi] + +# CHECK: vp2intersectd k0, zmm1, zmm2 +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2] + vp2intersectd k0, zmm1, zmm2 + +# CHECK: vp2intersectd k0, zmm1, zmmword ptr [rdi] +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07] + vp2intersectd k0, zmm1, zmmword ptr [rdi] + +# CHECK: vp2intersectd k0, zmm1, zmm2 +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2] + vp2intersectd k0, zmm1, zmm2 + +# CHECK: vp2intersectd k0, zmm1, zmmword ptr [rdi] +# CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07] + vp2intersectd k0, zmm1, zmmword ptr [rdi] + +# CHECK: vp2intersectd k6, zmm9, zmm7 +# CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0xf7] + vp2intersectd k6, zmm9, zmm7 + +# CHECK: vp2intersectd k6, zmm9, zmmword ptr [rsi] +# CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0x36] + vp2intersectd k6, zmm9, zmmword ptr [rsi] + +# CHECK: vp2intersectd k6, zmm9, zmm7 +# CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0xf7] + vp2intersectd k6, zmm9, zmm7 + +# CHECK: vp2intersectd k6, zmm9, zmmword ptr [rsi] +# CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0x36] + vp2intersectd k6, zmm9, zmmword ptr [rsi] + +# CHECK: vp2intersectd k0, ymm1, ymm2 +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2] + vp2intersectd k0, ymm1, ymm2 + +# CHECK: vp2intersectd k0, ymm1, ymmword ptr [rdi] +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07] + vp2intersectd k0, ymm1, ymmword ptr [rdi] + +# CHECK: vp2intersectd k0, ymm1, ymm2 +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2] + vp2intersectd k0, ymm1, ymm2 + +# CHECK: vp2intersectd k0, ymm1, ymmword ptr [rdi] +# CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07] + vp2intersectd k0, ymm1, ymmword ptr [rdi] + +# CHECK: vp2intersectd k6, ymm9, ymm7 +# CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0xf7] + vp2intersectd k6, ymm9, ymm7 + +# CHECK: vp2intersectd k6, ymm9, ymmword ptr [rsi] +# CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0x36] + vp2intersectd k6, ymm9, ymmword ptr [rsi] + +# CHECK: vp2intersectd k6, ymm9, ymm7 +# CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0xf7] + vp2intersectd k6, ymm9, ymm7 + +# CHECK: vp2intersectd k6, ymm9, ymmword ptr [rsi] +# CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0x36] + vp2intersectd k6, ymm9, ymmword ptr [rsi] + +# CHECK: vp2intersectd k0, xmm1, xmm2 +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2] + vp2intersectd k0, xmm1, xmm2 + +# CHECK: vp2intersectd k0, xmm1, xmmword ptr [rdi] +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07] + vp2intersectd k0, xmm1, xmmword ptr [rdi] + +# CHECK: vp2intersectd k0, xmm1, xmm2 +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2] + vp2intersectd k0, xmm1, xmm2 + +# CHECK: vp2intersectd k0, xmm1, xmmword ptr [rdi] +# CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07] + vp2intersectd k0, xmm1, xmmword ptr [rdi] + +# CHECK: vp2intersectd k6, xmm9, xmm7 +# CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0xf7] + vp2intersectd k6, xmm9, xmm7 + +# CHECK: vp2intersectd k6, xmm9, xmmword ptr [rsi] +# CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0x36] + vp2intersectd k6, xmm9, xmmword ptr [rsi] + +# CHECK: vp2intersectd k6, xmm9, xmm7 +# CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0xf7] + vp2intersectd k6, xmm9, xmm7 + +# CHECK: vp2intersectd k6, xmm9, xmmword ptr [rsi] +# CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0x36] + vp2intersectd k6, xmm9, xmmword ptr [rsi] diff --git a/llvm/test/MC/X86/avx512vp2intersectvl-att.s b/llvm/test/MC/X86/avx512vp2intersectvl-32-att.s index afd589027afb..afd589027afb 100644 --- a/llvm/test/MC/X86/avx512vp2intersectvl-att.s +++ b/llvm/test/MC/X86/avx512vp2intersectvl-32-att.s diff --git a/llvm/test/MC/X86/avx512vp2intersectvl-intel.s b/llvm/test/MC/X86/avx512vp2intersectvl-32-intel.s index 188d1bb461f7..188d1bb461f7 100644 --- a/llvm/test/MC/X86/avx512vp2intersectvl-intel.s +++ b/llvm/test/MC/X86/avx512vp2intersectvl-32-intel.s diff --git a/llvm/test/MC/X86/x86-64-avx512vp2intersectvl-att.s b/llvm/test/MC/X86/avx512vp2intersectvl-64-att.s index 040075b2ebe3..040075b2ebe3 100644 --- a/llvm/test/MC/X86/x86-64-avx512vp2intersectvl-att.s +++ b/llvm/test/MC/X86/avx512vp2intersectvl-64-att.s diff --git a/llvm/test/MC/X86/x86-64-avx512vp2intersectvl-intel.s b/llvm/test/MC/X86/avx512vp2intersectvl-64-intel.s index dd89c3ff7158..dd89c3ff7158 100644 --- a/llvm/test/MC/X86/x86-64-avx512vp2intersectvl-intel.s +++ b/llvm/test/MC/X86/avx512vp2intersectvl-64-intel.s diff --git a/llvm/test/MC/X86/x86-64-avx512vpopcntdq.s b/llvm/test/MC/X86/avx512vpopcntdq-64-att.s index 2f74be79167d..2f74be79167d 100644 --- a/llvm/test/MC/X86/x86-64-avx512vpopcntdq.s +++ b/llvm/test/MC/X86/avx512vpopcntdq-64-att.s diff --git a/llvm/test/MC/X86/x86_64-avx-clmul-encoding.s b/llvm/test/MC/X86/avx_clmul-att.s index 67e82c6cd0d2..67e82c6cd0d2 100644 --- a/llvm/test/MC/X86/x86_64-avx-clmul-encoding.s +++ b/llvm/test/MC/X86/avx_clmul-att.s diff --git a/llvm/test/MC/X86/avx_vaes-encoding.s b/llvm/test/MC/X86/avx_vaes-att.s index 40f45e6e3894..40f45e6e3894 100644 --- a/llvm/test/MC/X86/avx_vaes-encoding.s +++ b/llvm/test/MC/X86/avx_vaes-att.s diff --git a/llvm/test/MC/X86/intel-syntax-avx_vnni.s b/llvm/test/MC/X86/avx_vnni-32-intel.s index b905ed82f0c2..b905ed82f0c2 100644 --- a/llvm/test/MC/X86/intel-syntax-avx_vnni.s +++ b/llvm/test/MC/X86/avx_vnni-32-intel.s diff --git a/llvm/test/MC/X86/x86-64-avx_vnni-encoding.s b/llvm/test/MC/X86/avx_vnni-64-att.s index 8fc7f113b002..8fc7f113b002 100644 --- a/llvm/test/MC/X86/x86-64-avx_vnni-encoding.s +++ b/llvm/test/MC/X86/avx_vnni-64-att.s diff --git a/llvm/test/MC/X86/intel-syntax-x86-64-avx_vnni.s b/llvm/test/MC/X86/avx_vnni-64-intel.s index 48966b3a0736..48966b3a0736 100644 --- a/llvm/test/MC/X86/intel-syntax-x86-64-avx_vnni.s +++ b/llvm/test/MC/X86/avx_vnni-64-intel.s diff --git a/llvm/test/MC/X86/avx_vnni-encoding.s b/llvm/test/MC/X86/avx_vnni-att-32.s index 7baf2a2c4006..7baf2a2c4006 100644 --- a/llvm/test/MC/X86/avx_vnni-encoding.s +++ b/llvm/test/MC/X86/avx_vnni-att-32.s diff --git a/llvm/test/MC/X86/x86_64-bmi-encoding.s b/llvm/test/MC/X86/bmi-att.s index 3e69d4af0b79..3e69d4af0b79 100644 --- a/llvm/test/MC/X86/x86_64-bmi-encoding.s +++ b/llvm/test/MC/X86/bmi-att.s diff --git a/llvm/test/MC/X86/cet-encoding.s b/llvm/test/MC/X86/cet-att.s index 10c3c3ddabbe..10c3c3ddabbe 100644 --- a/llvm/test/MC/X86/cet-encoding.s +++ b/llvm/test/MC/X86/cet-att.s diff --git a/llvm/test/MC/X86/x86_64-fma3-encoding.s b/llvm/test/MC/X86/fma3-att.s index d08a7329a09f..d08a7329a09f 100644 --- a/llvm/test/MC/X86/x86_64-fma3-encoding.s +++ b/llvm/test/MC/X86/fma3-att.s diff --git a/llvm/test/MC/X86/x86_64-fma4-encoding.s b/llvm/test/MC/X86/fma4-att.s index c9bd954e9049..c9bd954e9049 100644 --- a/llvm/test/MC/X86/x86_64-fma4-encoding.s +++ b/llvm/test/MC/X86/fma4-att.s diff --git a/llvm/test/MC/X86/gfni-encoding.s b/llvm/test/MC/X86/gfni-att.s index 669c130b83fa..669c130b83fa 100644 --- a/llvm/test/MC/X86/gfni-encoding.s +++ b/llvm/test/MC/X86/gfni-att.s diff --git a/llvm/test/MC/X86/x86_64-hle-encoding.s b/llvm/test/MC/X86/hle-att.s index aaaca7d9c026..aaaca7d9c026 100644 --- a/llvm/test/MC/X86/x86_64-hle-encoding.s +++ b/llvm/test/MC/X86/hle-att.s diff --git a/llvm/test/MC/X86/intel-syntax-x86-avx512dq_vl.s b/llvm/test/MC/X86/intel-syntax-x86-avx512dq_vl.s deleted file mode 100644 index e2d6850623a9..000000000000 --- a/llvm/test/MC/X86/intel-syntax-x86-avx512dq_vl.s +++ /dev/null @@ -1,193 +0,0 @@ -// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s - -// CHECK: vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7b,0x51,0x10] - vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 0x80] - -// CHECK: vcvtps2qq xmm2 {k2}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7b,0x51,0x10] - vcvtps2qq xmm2 {k2}, qword ptr [rcx + 0x80] - -// CHECK: vcvtps2qq xmm2, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7b,0x51,0x10] - vcvtps2qq xmm2, qword ptr [rcx + 0x80] - -// CHECK: vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7a,0x49,0x10] - vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 0x80] - -// CHECK: vcvttps2qq xmm1 {k2}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7a,0x49,0x10] - vcvttps2qq xmm1 {k2}, qword ptr [rcx + 0x80] - -// CHECK: vcvttps2qq xmm1, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7a,0x49,0x10] - vcvttps2qq xmm1, qword ptr [rcx + 0x80] - -// CHECK: vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x79,0x49,0x10] - vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] - -// CHECK: vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x79,0x49,0x10] - vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128] - -// CHECK: vcvtps2uqq xmm1, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x79,0x49,0x10] - vcvtps2uqq xmm1, qword ptr [rcx + 128] - -// CHECK: vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x78,0x49,0x10] - vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] - -// CHECK: vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10] - vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128] - -// CHECK: vcvttps2uqq xmm1, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x78,0x49,0x10] - vcvttps2uqq xmm1, qword ptr [rcx + 128] - -// CHECK: vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7b,0x51,0x10] - vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 0x80] - -// CHECK: vcvtps2qq xmm2 {k2}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7b,0x51,0x10] - vcvtps2qq xmm2 {k2}, qword ptr [rcx + 0x80] - -// CHECK: vcvtps2qq xmm2, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7b,0x51,0x10] - vcvtps2qq xmm2, qword ptr [rcx + 0x80] - -// CHECK: vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x7a,0x49,0x10] - vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 0x80] - -// CHECK: vcvttps2qq xmm1 {k2}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x7a,0x49,0x10] - vcvttps2qq xmm1 {k2}, qword ptr [rcx + 0x80] - -// CHECK: vcvttps2qq xmm1, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x7a,0x49,0x10] - vcvttps2qq xmm1, qword ptr [rcx + 0x80] - -// CHECK: vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x79,0x49,0x10] - vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] - -// CHECK: vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x79,0x49,0x10] - vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128] - -// CHECK: vcvtps2uqq xmm1, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x79,0x49,0x10] - vcvtps2uqq xmm1, qword ptr [rcx + 128] - -// CHECK: vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x8a,0x78,0x49,0x10] - vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128] - -// CHECK: vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10] - vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128] - -// CHECK: vcvttps2uqq xmm1, qword ptr [rcx + 128] -// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0x78,0x49,0x10] - vcvttps2uqq xmm1, qword ptr [rcx + 128] - -// CHECK: vfpclasspd k2, xmm18, 171 -// CHECK: encoding: [0x62,0xb3,0xfd,0x08,0x66,0xd2,0xab] - vfpclasspd k2, xmm18, 0xab - -// CHECK: vfpclasspd k2 {k7}, xmm18, 171 -// CHECK: encoding: [0x62,0xb3,0xfd,0x0f,0x66,0xd2,0xab] - vfpclasspd k2 {k7}, xmm18, 0xab - -// CHECK: vfpclasspd k2, xmmword ptr [rcx], 123 -// CHECK: encoding: [0x62,0xf3,0xfd,0x08,0x66,0x11,0x7b] - vfpclasspd k2, xmmword ptr [rcx], 0x7b - -// CHECK: vfpclasspd k2 {k7}, xmmword ptr [rcx], 123 -// CHECK: encoding: [0x62,0xf3,0xfd,0x0f,0x66,0x11,0x7b] - vfpclasspd k2 {k7}, xmmword ptr [rcx], 0x7b - -// CHECK: vfpclasspd k2, qword ptr [rcx]{1to2}, 123 -// CHECK: encoding: [0x62,0xf3,0xfd,0x18,0x66,0x11,0x7b] - vfpclasspd k2, qword ptr [rcx]{1to2}, 0x7b - -// CHECK: vfpclasspd k2 {k7}, qword ptr [rcx]{1to2}, 123 -// CHECK: encoding: [0x62,0xf3,0xfd,0x1f,0x66,0x11,0x7b] - vfpclasspd k2 {k7}, qword ptr [rcx]{1to2}, 0x7b - -// CHECK: vfpclassps k2, xmm18, 171 -// CHECK: encoding: [0x62,0xb3,0x7d,0x08,0x66,0xd2,0xab] - vfpclassps k2, xmm18, 0xab - -// CHECK: vfpclassps k2 {k7}, xmm18, 171 -// CHECK: encoding: [0x62,0xb3,0x7d,0x0f,0x66,0xd2,0xab] - vfpclassps k2 {k7}, xmm18, 0xab - -// CHECK: vfpclassps k2, xmmword ptr [rcx], 123 -// CHECK: encoding: [0x62,0xf3,0x7d,0x08,0x66,0x11,0x7b] - vfpclassps k2, xmmword ptr [rcx], 0x7b - -// CHECK: vfpclassps k2 {k7}, xmmword ptr [rcx], 123 -// CHECK: encoding: [0x62,0xf3,0x7d,0x0f,0x66,0x11,0x7b] - vfpclassps k2 {k7}, xmmword ptr [rcx], 0x7b - -// CHECK: vfpclassps k2, dword ptr [rcx]{1to4}, 123 -// CHECK: encoding: [0x62,0xf3,0x7d,0x18,0x66,0x11,0x7b] - vfpclassps k2, dword ptr [rcx]{1to4}, 0x7b - -// CHECK: vfpclassps k2 {k7}, dword ptr [rcx]{1to4}, 123 -// CHECK: encoding: [0x62,0xf3,0x7d,0x1f,0x66,0x11,0x7b] - vfpclassps k2 {k7}, dword ptr [rcx]{1to4}, 0x7b - -// CHECK: vfpclasspd k2, ymm18, 171 -// CHECK: encoding: [0x62,0xb3,0xfd,0x28,0x66,0xd2,0xab] - vfpclasspd k2, ymm18, 0xab - -// CHECK: vfpclasspd k2 {k7}, ymm18, 171 -// CHECK: encoding: [0x62,0xb3,0xfd,0x2f,0x66,0xd2,0xab] - vfpclasspd k2 {k7}, ymm18, 0xab - -// CHECK: vfpclasspd k2, ymmword ptr [rcx], 123 -// CHECK: encoding: [0x62,0xf3,0xfd,0x28,0x66,0x11,0x7b] - vfpclasspd k2, ymmword ptr [rcx], 0x7b - -// CHECK: vfpclasspd k2 {k7}, ymmword ptr [rcx], 123 -// CHECK: encoding: [0x62,0xf3,0xfd,0x2f,0x66,0x11,0x7b] - vfpclasspd k2 {k7}, ymmword ptr [rcx], 0x7b - -// CHECK: vfpclasspd k2, qword ptr [rcx]{1to4}, 123 -// CHECK: encoding: [0x62,0xf3,0xfd,0x38,0x66,0x11,0x7b] - vfpclasspd k2, qword ptr [rcx]{1to4}, 0x7b - -// CHECK: vfpclasspd k2 {k7}, qword ptr [rcx]{1to4}, 123 -// CHECK: encoding: [0x62,0xf3,0xfd,0x3f,0x66,0x11,0x7b] - vfpclasspd k2 {k7}, qword ptr [rcx]{1to4}, 0x7b - -// CHECK: vfpclassps k2, ymm18, 171 -// CHECK: encoding: [0x62,0xb3,0x7d,0x28,0x66,0xd2,0xab] - vfpclassps k2, ymm18, 0xab - -// CHECK: vfpclassps k2 {k7}, ymm18, 171 -// CHECK: encoding: [0x62,0xb3,0x7d,0x2f,0x66,0xd2,0xab] - vfpclassps k2 {k7}, ymm18, 0xab - -// CHECK: vfpclassps k2, ymmword ptr [rcx], 123 -// CHECK: encoding: [0x62,0xf3,0x7d,0x28,0x66,0x11,0x7b] - vfpclassps k2, ymmword ptr [rcx], 0x7b - -// CHECK: vfpclassps k2 {k7}, ymmword ptr [rcx], 123 -// CHECK: encoding: [0x62,0xf3,0x7d,0x2f,0x66,0x11,0x7b] - vfpclassps k2 {k7}, ymmword ptr [rcx], 0x7b - -// CHECK: vfpclassps k2, dword ptr [rcx]{1to8}, 123 -// CHECK: encoding: [0x62,0xf3,0x7d,0x38,0x66,0x11,0x7b] - vfpclassps k2, dword ptr [rcx]{1to8}, 0x7b - -// CHECK: vfpclassps k2 {k7}, dword ptr [rcx]{1to8}, 123 -// CHECK: encoding: [0x62,0xf3,0x7d,0x3f,0x66,0x11,0x7b] - vfpclassps k2 {k7}, dword ptr [rcx]{1to8}, 0x7b diff --git a/llvm/test/MC/X86/lwp-x86_64.s b/llvm/test/MC/X86/lwp-64-att.s index 92f15967461e..92f15967461e 100644 --- a/llvm/test/MC/X86/lwp-x86_64.s +++ b/llvm/test/MC/X86/lwp-64-att.s diff --git a/llvm/test/MC/X86/lwp.s b/llvm/test/MC/X86/lwp-att.s index 43d6f2cd7e3b..43d6f2cd7e3b 100644 --- a/llvm/test/MC/X86/lwp.s +++ b/llvm/test/MC/X86/lwp-att.s diff --git a/llvm/test/MC/X86/x86-64-msrlist.s b/llvm/test/MC/X86/msrlist-64-att.s index 7e7866141fe7..7e7866141fe7 100644 --- a/llvm/test/MC/X86/x86-64-msrlist.s +++ b/llvm/test/MC/X86/msrlist-64-att.s diff --git a/llvm/test/MC/X86/x86_64-rand-encoding.s b/llvm/test/MC/X86/rand-att.s index 3a8cb817bc1a..3a8cb817bc1a 100644 --- a/llvm/test/MC/X86/x86_64-rand-encoding.s +++ b/llvm/test/MC/X86/rand-att.s diff --git a/llvm/test/MC/X86/x86-64-rao-int-att.s b/llvm/test/MC/X86/raoint-64-att.s index 214b639afd34..214b639afd34 100644 --- a/llvm/test/MC/X86/x86-64-rao-int-att.s +++ b/llvm/test/MC/X86/raoint-64-att.s diff --git a/llvm/test/MC/X86/x86-64-rao-int-intel.s b/llvm/test/MC/X86/raoint-64-intel.s index aa0a848b3225..aa0a848b3225 100644 --- a/llvm/test/MC/X86/x86-64-rao-int-intel.s +++ b/llvm/test/MC/X86/raoint-64-intel.s diff --git a/llvm/test/MC/X86/x86_64-rtm-encoding.s b/llvm/test/MC/X86/rtm-att.s index d9975d67b314..d9975d67b314 100644 --- a/llvm/test/MC/X86/x86_64-rtm-encoding.s +++ b/llvm/test/MC/X86/rtm-att.s diff --git a/llvm/test/MC/X86/x86_64-sse4a.s b/llvm/test/MC/X86/sse4a-att.s index e5ed69e5b2c3..e5ed69e5b2c3 100644 --- a/llvm/test/MC/X86/x86_64-sse4a.s +++ b/llvm/test/MC/X86/sse4a-att.s diff --git a/llvm/test/MC/X86/x86_64-tbm-encoding.s b/llvm/test/MC/X86/tbm-att.s index 8c7fe2184487..8c7fe2184487 100644 --- a/llvm/test/MC/X86/x86_64-tbm-encoding.s +++ b/llvm/test/MC/X86/tbm-att.s diff --git a/llvm/test/MC/X86/x86-32-avx512_vp2intersect-intel.s b/llvm/test/MC/X86/x86-32-avx512_vp2intersect-intel.s deleted file mode 100644 index 3ea3e4fd6465..000000000000 --- a/llvm/test/MC/X86/x86-32-avx512_vp2intersect-intel.s +++ /dev/null @@ -1,57 +0,0 @@ -// RUN: llvm-mc -triple i386-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s -// CHECK: vp2intersectd k4, zmm3, zmm4 -// CHECK: encoding: [0x62,0xf2,0x67,0x48,0x68,0xe4] - vp2intersectd k4, zmm3, zmm4 - -// CHECK: vp2intersectd k4, zmm3, zmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0x62,0xf2,0x67,0x48,0x68,0xa4,0xf4,0x00,0x00,0x00,0x10] - vp2intersectd k4, zmm3, zmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vp2intersectd k4, zmm3, zmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0x62,0xf2,0x67,0x48,0x68,0xa4,0x87,0x23,0x01,0x00,0x00] - vp2intersectd k4, zmm3, zmmword ptr [edi + 4*eax + 291] - -// CHECK: vp2intersectd k4, zmm3, dword ptr [eax]{1to16} -// CHECK: encoding: [0x62,0xf2,0x67,0x58,0x68,0x20] - vp2intersectd k4, zmm3, dword ptr [eax]{1to16} - -// CHECK: vp2intersectd k4, zmm3, zmmword ptr [2*ebp - 2048] -// CHECK: encoding: [0x62,0xf2,0x67,0x48,0x68,0x24,0x6d,0x00,0xf8,0xff,0xff] - vp2intersectd k4, zmm3, zmmword ptr [2*ebp - 2048] - -// CHECK: vp2intersectd k4, zmm3, zmmword ptr [ecx + 8128] -// CHECK: encoding: [0x62,0xf2,0x67,0x48,0x68,0x61,0x7f] - vp2intersectd k4, zmm3, zmmword ptr [ecx + 8128] - -// CHECK: vp2intersectd k4, zmm3, dword ptr [edx - 512]{1to16} -// CHECK: encoding: [0x62,0xf2,0x67,0x58,0x68,0x62,0x80] - vp2intersectd k4, zmm3, dword ptr [edx - 512]{1to16} - -// CHECK: vp2intersectq k4, zmm3, zmm4 -// CHECK: encoding: [0x62,0xf2,0xe7,0x48,0x68,0xe4] - vp2intersectq k4, zmm3, zmm4 - -// CHECK: vp2intersectq k4, zmm3, zmmword ptr [esp + 8*esi + 268435456] -// CHECK: encoding: [0x62,0xf2,0xe7,0x48,0x68,0xa4,0xf4,0x00,0x00,0x00,0x10] - vp2intersectq k4, zmm3, zmmword ptr [esp + 8*esi + 268435456] - -// CHECK: vp2intersectq k4, zmm3, zmmword ptr [edi + 4*eax + 291] -// CHECK: encoding: [0x62,0xf2,0xe7,0x48,0x68,0xa4,0x87,0x23,0x01,0x00,0x00] - vp2intersectq k4, zmm3, zmmword ptr [edi + 4*eax + 291] - -// CHECK: vp2intersectq k4, zmm3, qword ptr [eax]{1to8} -// CHECK: encoding: [0x62,0xf2,0xe7,0x58,0x68,0x20] - vp2intersectq k4, zmm3, qword ptr [eax]{1to8} - -// CHECK: vp2intersectq k4, zmm3, zmmword ptr [2*ebp - 2048] -// CHECK: encoding: [0x62,0xf2,0xe7,0x48,0x68,0x24,0x6d,0x00,0xf8,0xff,0xff] - vp2intersectq k4, zmm3, zmmword ptr [2*ebp - 2048] - -// CHECK: vp2intersectq k4, zmm3, zmmword ptr [ecx + 8128] -// CHECK: encoding: [0x62,0xf2,0xe7,0x48,0x68,0x61,0x7f] - vp2intersectq k4, zmm3, zmmword ptr [ecx + 8128] - -// CHECK: vp2intersectq k4, zmm3, qword ptr [edx - 1024]{1to8} -// CHECK: encoding: [0x62,0xf2,0xe7,0x58,0x68,0x62,0x80] - vp2intersectq k4, zmm3, qword ptr [edx - 1024]{1to8} - diff --git a/llvm/test/MC/X86/x86-32-avx512vp2intersect-att.s b/llvm/test/MC/X86/x86-32-avx512vp2intersect-att.s deleted file mode 100644 index 49aca2a32126..000000000000 --- a/llvm/test/MC/X86/x86-32-avx512vp2intersect-att.s +++ /dev/null @@ -1,225 +0,0 @@ -// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s - -// CHECK: vp2intersectq %zmm2, %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2] -vp2intersectq %zmm2, %zmm1, %k0 - -// CHECK: vp2intersectq (%edi), %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07] -vp2intersectq (%edi), %zmm1, %k0 - -// CHECK: vp2intersectq (%edi){1to8}, %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07] -vp2intersectq (%edi){1to8}, %zmm1, %k0 - -// CHECK: vp2intersectq %zmm2, %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2] -vp2intersectq %zmm2, %zmm1, %k1 - -// CHECK: vp2intersectq (%edi), %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07] -vp2intersectq (%edi), %zmm1, %k1 - -// CHECK: vp2intersectq (%edi){1to8}, %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07] -vp2intersectq (%edi){1to8}, %zmm1, %k1 - -// CHECK: vp2intersectq %zmm7, %zmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7] -vp2intersectq %zmm7, %zmm4, %k6 - -// CHECK: vp2intersectq (%esi), %zmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0x36] -vp2intersectq (%esi), %zmm4, %k6 - -// CHECK: vp2intersectq (%esi){1to8}, %zmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x58,0x68,0x36] -vp2intersectq (%esi){1to8}, %zmm4, %k6 - -// CHECK: vp2intersectq %zmm7, %zmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0xf7] -vp2intersectq %zmm7, %zmm4, %k7 - -// CHECK: vp2intersectq (%esi), %zmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x48,0x68,0x36] -vp2intersectq (%esi), %zmm4, %k7 - -// CHECK: vp2intersectq (%esi){1to8}, %zmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x58,0x68,0x36] -vp2intersectq (%esi){1to8}, %zmm4, %k7 - -// CHECK: vp2intersectq %ymm2, %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2] -vp2intersectq %ymm2, %ymm1, %k0 - -// CHECK: vp2intersectq (%edi), %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07] -vp2intersectq (%edi), %ymm1, %k0 - -// CHECK: vp2intersectq (%edi){1to4}, %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07] -vp2intersectq (%edi){1to4}, %ymm1, %k0 - -// CHECK: vp2intersectq %ymm2, %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2] -vp2intersectq %ymm2, %ymm1, %k1 - -// CHECK: vp2intersectq (%edi), %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07] -vp2intersectq (%edi), %ymm1, %k1 - -// CHECK: vp2intersectq (%edi){1to4}, %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07] -vp2intersectq (%edi){1to4}, %ymm1, %k1 - -// CHECK: vp2intersectq %ymm7, %ymm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0xf7] -vp2intersectq %ymm7, %ymm4, %k6 - -// CHECK: vp2intersectq (%esi), %ymm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0x36] -vp2intersectq (%esi), %ymm4, %k6 - -// CHECK: vp2intersectq (%esi){1to4}, %ymm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x38,0x68,0x36] -vp2intersectq (%esi){1to4}, %ymm4, %k6 - -// CHECK: vp2intersectq %ymm7, %ymm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0xf7] -vp2intersectq %ymm7, %ymm4, %k7 - -// CHECK: vp2intersectq (%esi), %ymm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x28,0x68,0x36] -vp2intersectq (%esi), %ymm4, %k7 - -// CHECK: vp2intersectq %xmm2, %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2] -vp2intersectq %xmm2, %xmm1, %k0 - -// CHECK: vp2intersectq (%edi), %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07] -vp2intersectq (%edi), %xmm1, %k0 - -// CHECK: vp2intersectq (%edi){1to2}, %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x18,0x68,0x07] -vp2intersectq (%edi){1to2}, %xmm1, %k0 - -// CHECK: vp2intersectq %xmm2, %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2] -vp2intersectq %xmm2, %xmm1, %k1 - -// CHECK: vp2intersectq (%edi), %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07] -vp2intersectq (%edi), %xmm1, %k1 - -// CHECK: vp2intersectq %xmm7, %xmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0xf7] -vp2intersectq %xmm7, %xmm4, %k6 - -// CHECK: vp2intersectq (%esi), %xmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0x36] -vp2intersectq (%esi), %xmm4, %k6 - -// CHECK: vp2intersectq %xmm7, %xmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0xf7] -vp2intersectq %xmm7, %xmm4, %k7 - -// CHECK: vp2intersectq (%esi), %xmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0xdf,0x08,0x68,0x36] -vp2intersectq (%esi), %xmm4, %k7 - -// CHECK: vp2intersectd %zmm2, %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2] -vp2intersectd %zmm2, %zmm1, %k0 - -// CHECK: vp2intersectd (%edi), %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07] -vp2intersectd (%edi), %zmm1, %k0 - -// CHECK: vp2intersectd %zmm2, %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2] -vp2intersectd %zmm2, %zmm1, %k1 - -// CHECK: vp2intersectd (%edi), %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07] -vp2intersectd (%edi), %zmm1, %k1 - -// CHECK: vp2intersectd %zmm7, %zmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0xf7] -vp2intersectd %zmm7, %zmm4, %k6 - -// CHECK: vp2intersectd (%esi), %zmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0x36] -vp2intersectd (%esi), %zmm4, %k6 - -// CHECK: vp2intersectd %zmm7, %zmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0xf7] -vp2intersectd %zmm7, %zmm4, %k7 - -// CHECK: vp2intersectd (%esi), %zmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0x5f,0x48,0x68,0x36] -vp2intersectd (%esi), %zmm4, %k7 - -// CHECK: vp2intersectd %ymm2, %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2] -vp2intersectd %ymm2, %ymm1, %k0 - -// CHECK: vp2intersectd (%edi), %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07] -vp2intersectd (%edi), %ymm1, %k0 - -// CHECK: vp2intersectd %ymm2, %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2] -vp2intersectd %ymm2, %ymm1, %k1 - -// CHECK: vp2intersectd (%edi), %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07] -vp2intersectd (%edi), %ymm1, %k1 - -// CHECK: vp2intersectd %ymm7, %ymm4, %k6 -// CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0xf7] -vp2intersectd %ymm7, %ymm4, %k6 - -// CHECK: vp2intersectd (%esi), %ymm4, %k6 -// CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0x36] -vp2intersectd (%esi), %ymm4, %k6 - -// CHECK: vp2intersectd %ymm7, %ymm4, %k6 -// CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0xf7] -vp2intersectd %ymm7, %ymm4, %k7 - -// CHECK: vp2intersectd (%esi), %ymm4, %k6 -// CHECK: encoding: [0x62,0xf2,0x5f,0x28,0x68,0x36] -vp2intersectd (%esi), %ymm4, %k7 - -// CHECK: vp2intersectd %xmm2, %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2] -vp2intersectd %xmm2, %xmm1, %k0 - -// CHECK: vp2intersectd (%edi), %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07] -vp2intersectd (%edi), %xmm1, %k0 - -// CHECK: vp2intersectd %xmm2, %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2] -vp2intersectd %xmm2, %xmm1, %k1 - -// CHECK: vp2intersectd (%edi), %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07] -vp2intersectd (%edi), %xmm1, %k1 - -// CHECK: vp2intersectd %xmm7, %xmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0xf7] -vp2intersectd %xmm7, %xmm4, %k6 - -// CHECK: vp2intersectd (%esi), %xmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0x36] -vp2intersectd (%esi), %xmm4, %k6 - -// CHECK: vp2intersectd %xmm7, %xmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0xf7] -vp2intersectd %xmm7, %xmm4, %k7 - -// CHECK: vp2intersectd (%esi), %xmm4, %k6 -// CHECK: encoding: [0x62,0xf2,0x5f,0x08,0x68,0x36] -vp2intersectd (%esi), %xmm4, %k7 diff --git a/llvm/test/MC/X86/x86-64-avx512_vp2intersect-intel.s b/llvm/test/MC/X86/x86-64-avx512_vp2intersect-intel.s deleted file mode 100644 index 1dd9501bb261..000000000000 --- a/llvm/test/MC/X86/x86-64-avx512_vp2intersect-intel.s +++ /dev/null @@ -1,57 +0,0 @@ -// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s -// CHECK: vp2intersectd k4, zmm23, zmm24 -// CHECK: encoding: [0x62,0x92,0x47,0x40,0x68,0xe0] - vp2intersectd k4, zmm23, zmm24 - -// CHECK: vp2intersectd k4, zmm23, zmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0x62,0xb2,0x47,0x40,0x68,0xa4,0xf5,0x00,0x00,0x00,0x10] - vp2intersectd k4, zmm23, zmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vp2intersectd k4, zmm23, zmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0x62,0xd2,0x47,0x40,0x68,0xa4,0x80,0x23,0x01,0x00,0x00] - vp2intersectd k4, zmm23, zmmword ptr [r8 + 4*rax + 291] - -// CHECK: vp2intersectd k4, zmm23, dword ptr [rip]{1to16} -// CHECK: encoding: [0x62,0xf2,0x47,0x50,0x68,0x25,0x00,0x00,0x00,0x00] - vp2intersectd k4, zmm23, dword ptr [rip]{1to16} - -// CHECK: vp2intersectd k4, zmm23, zmmword ptr [2*rbp - 2048] -// CHECK: encoding: [0x62,0xf2,0x47,0x40,0x68,0x24,0x6d,0x00,0xf8,0xff,0xff] - vp2intersectd k4, zmm23, zmmword ptr [2*rbp - 2048] - -// CHECK: vp2intersectd k4, zmm23, zmmword ptr [rcx + 8128] -// CHECK: encoding: [0x62,0xf2,0x47,0x40,0x68,0x61,0x7f] - vp2intersectd k4, zmm23, zmmword ptr [rcx + 8128] - -// CHECK: vp2intersectd k4, zmm23, dword ptr [rdx - 512]{1to16} -// CHECK: encoding: [0x62,0xf2,0x47,0x50,0x68,0x62,0x80] - vp2intersectd k4, zmm23, dword ptr [rdx - 512]{1to16} - -// CHECK: vp2intersectq k4, zmm23, zmm24 -// CHECK: encoding: [0x62,0x92,0xc7,0x40,0x68,0xe0] - vp2intersectq k4, zmm23, zmm24 - -// CHECK: vp2intersectq k4, zmm23, zmmword ptr [rbp + 8*r14 + 268435456] -// CHECK: encoding: [0x62,0xb2,0xc7,0x40,0x68,0xa4,0xf5,0x00,0x00,0x00,0x10] - vp2intersectq k4, zmm23, zmmword ptr [rbp + 8*r14 + 268435456] - -// CHECK: vp2intersectq k4, zmm23, zmmword ptr [r8 + 4*rax + 291] -// CHECK: encoding: [0x62,0xd2,0xc7,0x40,0x68,0xa4,0x80,0x23,0x01,0x00,0x00] - vp2intersectq k4, zmm23, zmmword ptr [r8 + 4*rax + 291] - -// CHECK: vp2intersectq k4, zmm23, qword ptr [rip]{1to8} -// CHECK: encoding: [0x62,0xf2,0xc7,0x50,0x68,0x25,0x00,0x00,0x00,0x00] - vp2intersectq k4, zmm23, qword ptr [rip]{1to8} - -// CHECK: vp2intersectq k4, zmm23, zmmword ptr [2*rbp - 2048] -// CHECK: encoding: [0x62,0xf2,0xc7,0x40,0x68,0x24,0x6d,0x00,0xf8,0xff,0xff] - vp2intersectq k4, zmm23, zmmword ptr [2*rbp - 2048] - -// CHECK: vp2intersectq k4, zmm23, zmmword ptr [rcx + 8128] -// CHECK: encoding: [0x62,0xf2,0xc7,0x40,0x68,0x61,0x7f] - vp2intersectq k4, zmm23, zmmword ptr [rcx + 8128] - -// CHECK: vp2intersectq k4, zmm23, qword ptr [rdx - 1024]{1to8} -// CHECK: encoding: [0x62,0xf2,0xc7,0x50,0x68,0x62,0x80] - vp2intersectq k4, zmm23, qword ptr [rdx - 1024]{1to8} - diff --git a/llvm/test/MC/X86/x86-64-avx512vp2intersect-att.s b/llvm/test/MC/X86/x86-64-avx512vp2intersect-att.s deleted file mode 100644 index 72e907f9b384..000000000000 --- a/llvm/test/MC/X86/x86-64-avx512vp2intersect-att.s +++ /dev/null @@ -1,231 +0,0 @@ -// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s - -// v8i64 vectors -// CHECK: vp2intersectq %zmm2, %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2] -vp2intersectq %zmm2, %zmm1, %k0 - -// CHECK: vp2intersectq (%rdi), %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07] -vp2intersectq (%rdi), %zmm1, %k0 - -// CHECK: vp2intersectq (%rdi){1to8}, %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07] -vp2intersectq (%rdi){1to8}, %zmm1, %k0 - -// CHECK: vp2intersectq %zmm2, %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0xc2] -vp2intersectq %zmm2, %zmm1, %k1 - -// CHECK: vp2intersectq (%rdi), %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x48,0x68,0x07] -vp2intersectq (%rdi), %zmm1, %k1 - -// CHECK: vp2intersectq (%rdi){1to8}, %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x58,0x68,0x07] -vp2intersectq (%rdi){1to8}, %zmm1, %k1 - -// CHECK: vp2intersectq %zmm7, %zmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0xf7] -vp2intersectq %zmm7, %zmm9, %k6 - -// CHECK: vp2intersectq (%rsi), %zmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0x36] -vp2intersectq (%rsi), %zmm9, %k6 - -// CHECK: vp2intersectq (%rsi){1to8}, %zmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x58,0x68,0x36] -vp2intersectq (%rsi){1to8}, %zmm9, %k6 - -// CHECK: vp2intersectq %zmm7, %zmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0xf7] -vp2intersectq %zmm7, %zmm9, %k7 - -// CHECK: vp2intersectq (%rsi), %zmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x48,0x68,0x36] -vp2intersectq (%rsi), %zmm9, %k7 - -// CHECK: vp2intersectq (%rsi){1to8}, %zmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x58,0x68,0x36] -vp2intersectq (%rsi){1to8}, %zmm9, %k7 - -// v4i64 vectors -// CHECK: vp2intersectq %ymm2, %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2] -vp2intersectq %ymm2, %ymm1, %k0 - -// CHECK: vp2intersectq (%rdi), %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07] -vp2intersectq (%rdi), %ymm1, %k0 - -// CHECK: vp2intersectq (%rdi){1to4}, %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07] -vp2intersectq (%rdi){1to4}, %ymm1, %k0 - -// CHECK: vp2intersectq %ymm2, %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0xc2] -vp2intersectq %ymm2, %ymm1, %k1 - -// CHECK: vp2intersectq (%rdi), %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x28,0x68,0x07] -vp2intersectq (%rdi), %ymm1, %k1 - -// CHECK: vp2intersectq (%rdi){1to4}, %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x38,0x68,0x07] -vp2intersectq (%rdi){1to4}, %ymm1, %k1 - -// CHECK: vp2intersectq %ymm7, %ymm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0xf7] -vp2intersectq %ymm7, %ymm9, %k6 - -// CHECK: vp2intersectq (%rsi), %ymm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0x36] -vp2intersectq (%rsi), %ymm9, %k6 - -// CHECK: vp2intersectq (%rsi){1to4}, %ymm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x38,0x68,0x36] -vp2intersectq (%rsi){1to4}, %ymm9, %k6 - -// CHECK: vp2intersectq %ymm7, %ymm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0xf7] -vp2intersectq %ymm7, %ymm9, %k7 - -// CHECK: vp2intersectq (%rsi), %ymm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x28,0x68,0x36] -vp2intersectq (%rsi), %ymm9, %k7 - -// v2i64 vectors -// CHECK: vp2intersectq %xmm2, %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2] -vp2intersectq %xmm2, %xmm1, %k0 - -// CHECK: vp2intersectq (%rdi), %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07] -vp2intersectq (%rdi), %xmm1, %k0 - -// CHECK: vp2intersectq (%rdi){1to2}, %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x18,0x68,0x07] -vp2intersectq (%rdi){1to2}, %xmm1, %k0 - -// CHECK: vp2intersectq %xmm2, %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0xc2] -vp2intersectq %xmm2, %xmm1, %k1 - -// CHECK: vp2intersectq (%rdi), %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0xf7,0x08,0x68,0x07] -vp2intersectq (%rdi), %xmm1, %k1 - -// CHECK: vp2intersectq %xmm7, %xmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0xf7] -vp2intersectq %xmm7, %xmm9, %k6 - -// CHECK: vp2intersectq (%rsi), %xmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0x36] -vp2intersectq (%rsi), %xmm9, %k6 - -// CHECK: vp2intersectq %xmm7, %xmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0xf7] -vp2intersectq %xmm7, %xmm9, %k7 - -// CHECK: vp2intersectq (%rsi), %xmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0xb7,0x08,0x68,0x36] -vp2intersectq (%rsi), %xmm9, %k7 - -// v16i32 vectors -// CHECK: vp2intersectd %zmm2, %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2] -vp2intersectd %zmm2, %zmm1, %k0 - -// CHECK: vp2intersectd (%rdi), %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07] -vp2intersectd (%rdi), %zmm1, %k0 - -// CHECK: vp2intersectd %zmm2, %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0xc2] -vp2intersectd %zmm2, %zmm1, %k1 - -// CHECK: vp2intersectd (%rdi), %zmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x48,0x68,0x07] -vp2intersectd (%rdi), %zmm1, %k1 - -// CHECK: vp2intersectd %zmm7, %zmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0xf7] -vp2intersectd %zmm7, %zmm9, %k6 - -// CHECK: vp2intersectd (%rsi), %zmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0x36] -vp2intersectd (%rsi), %zmm9, %k6 - -// CHECK: vp2intersectd %zmm7, %zmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0xf7] -vp2intersectd %zmm7, %zmm9, %k7 - -// CHECK: vp2intersectd (%rsi), %zmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0x37,0x48,0x68,0x36] -vp2intersectd (%rsi), %zmm9, %k7 - -// v8i32 vectors -// CHECK: vp2intersectd %ymm2, %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2] -vp2intersectd %ymm2, %ymm1, %k0 - -// CHECK: vp2intersectd (%rdi), %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07] -vp2intersectd (%rdi), %ymm1, %k0 - -// CHECK: vp2intersectd %ymm2, %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0xc2] -vp2intersectd %ymm2, %ymm1, %k1 - -// CHECK: vp2intersectd (%rdi), %ymm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x28,0x68,0x07] -vp2intersectd (%rdi), %ymm1, %k1 - -// CHECK: vp2intersectd %ymm7, %ymm9, %k6 -// CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0xf7] -vp2intersectd %ymm7, %ymm9, %k6 - -// CHECK: vp2intersectd (%rsi), %ymm9, %k6 -// CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0x36] -vp2intersectd (%rsi), %ymm9, %k6 - -// CHECK: vp2intersectd %ymm7, %ymm9, %k6 -// CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0xf7] -vp2intersectd %ymm7, %ymm9, %k7 - -// CHECK: vp2intersectd (%rsi), %ymm9, %k6 -// CHECK: encoding: [0x62,0xf2,0x37,0x28,0x68,0x36] -vp2intersectd (%rsi), %ymm9, %k7 - -// v4i32 vectors -// CHECK: vp2intersectd %xmm2, %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2] -vp2intersectd %xmm2, %xmm1, %k0 - -// CHECK: vp2intersectd (%rdi), %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07] -vp2intersectd (%rdi), %xmm1, %k0 - -// CHECK: vp2intersectd %xmm2, %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0xc2] -vp2intersectd %xmm2, %xmm1, %k1 - -// CHECK: vp2intersectd (%rdi), %xmm1, %k0 -// CHECK: encoding: [0x62,0xf2,0x77,0x08,0x68,0x07] -vp2intersectd (%rdi), %xmm1, %k1 - -// CHECK: vp2intersectd %xmm7, %xmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0xf7] -vp2intersectd %xmm7, %xmm9, %k6 - -// CHECK: vp2intersectd (%rsi), %xmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0x36] -vp2intersectd (%rsi), %xmm9, %k6 - -// CHECK: vp2intersectd %xmm7, %xmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0xf7] -vp2intersectd %xmm7, %xmm9, %k7 - -// CHECK: vp2intersectd (%rsi), %xmm9, %k6 -// CHECK: encoding: [0x62,0xf2,0x37,0x08,0x68,0x36] -vp2intersectd (%rsi), %xmm9, %k7 diff --git a/llvm/test/MC/X86/x86_64-xop-encoding.s b/llvm/test/MC/X86/xop-att.s index 48f30ec9e36b..48f30ec9e36b 100644 --- a/llvm/test/MC/X86/x86_64-xop-encoding.s +++ b/llvm/test/MC/X86/xop-att.s diff --git a/llvm/test/TableGen/ContextlessPredicates.td b/llvm/test/TableGen/ContextlessPredicates.td index 0f4c4d0c450e..5e4e69069c3e 100644 --- a/llvm/test/TableGen/ContextlessPredicates.td +++ b/llvm/test/TableGen/ContextlessPredicates.td @@ -20,55 +20,53 @@ def INSN : I<(outs GPR32:$dst), (ins GPR32Op:$src1, GPR32Op:$src2), []>; def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) , (INSN GPR32:$ptr, GPR32:$val)>; -// CHECK_NOPT-LABEL: const int64_t *MyTargetInstructionSelector::getMatchTable() const { -// CHECK_NOPT-NEXT: constexpr static int64_t MatchTable0[] = { -// CHECK_NOPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ 46, // Rule ID 0 // -// CHECK_NOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// CHECK_NOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ATOMICRMW_XCHG, -// CHECK_NOPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, -// CHECK_NOPT-NEXT: // MIs[0] DstI[dst] -// CHECK_NOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK_NOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, -// CHECK_NOPT-NEXT: // MIs[0] ptr -// CHECK_NOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// CHECK_NOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, -// CHECK_NOPT-NEXT: // MIs[0] val -// CHECK_NOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK_NOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, -// CHECK_NOPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_test_atomic_op_frag, -// CHECK_NOPT-NEXT: // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>> => (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val) -// CHECK_NOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::INSN, -// CHECK_NOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK_NOPT-NEXT: // GIR_Coverage, 0, -// CHECK_NOPT-NEXT: GIR_Done, -// CHECK_NOPT-NEXT: // Label 0: @46 -// CHECK_NOPT-NEXT: GIM_Reject, -// CHECK_NOPT-NEXT: }; -// CHECK_NOPT-NEXT: return MatchTable0; -// CHECK_NOPT-NEXT: } -// -// +// CHECK_NOPT-LABEL: const uint8_t *MyTargetInstructionSelector::getMatchTable() const { +// CHECK_NOPT-NEXT: constexpr static uint8_t MatchTable0[] = { +// CHECK_NOPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(58), // Rule ID 0 // +// CHECK_NOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, +// CHECK_NOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ATOMICRMW_XCHG), +// CHECK_NOPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), +// CHECK_NOPT-NEXT: // MIs[0] DstI[dst] +// CHECK_NOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK_NOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK_NOPT-NEXT: // MIs[0] ptr +// CHECK_NOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, +// CHECK_NOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK_NOPT-NEXT: // MIs[0] val +// CHECK_NOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK_NOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK_NOPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_test_atomic_op_frag), +// CHECK_NOPT-NEXT: // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>> => (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val) +// CHECK_NOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN), +// CHECK_NOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK_NOPT-NEXT: // GIR_Coverage, 0, +// CHECK_NOPT-NEXT: GIR_Done, +// CHECK_NOPT-NEXT: // Label 0: @58 +// CHECK_NOPT-NEXT: GIM_Reject, +// CHECK_NOPT-NEXT: }; +// CHECK_NOPT-NEXT: return MatchTable0; +// CHECK_NOPT-NEXT: } -// CHECK_OPT-LABEL: const int64_t *MyTargetInstructionSelector::getMatchTable() const { -// CHECK_OPT-NEXT: constexpr static int64_t MatchTable0[] = { -// CHECK_OPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ 43, // Rule ID 0 // -// CHECK_OPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ATOMICRMW_XCHG, -// CHECK_OPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK_OPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK_OPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, -// CHECK_OPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, -// CHECK_OPT-NEXT: // MIs[0] ptr -// CHECK_OPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// CHECK_OPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, -// CHECK_OPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, -// CHECK_OPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_test_atomic_op_frag, -// CHECK_OPT-NEXT: // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>> => (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val) -// CHECK_OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::INSN, -// CHECK_OPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK_OPT-NEXT: // GIR_Coverage, 0, -// CHECK_OPT-NEXT: GIR_Done, -// CHECK_OPT-NEXT: // Label 0: @43 -// CHECK_OPT-NEXT: GIM_Reject, -// CHECK_OPT-NEXT: }; -// CHECK_OPT-NEXT: return MatchTable0; -// CHECK_OPT-NEXT: } +// CHECK_OPT-LABEL: const uint8_t *MyTargetInstructionSelector::getMatchTable() const { +// CHECK_OPT-NEXT: constexpr static uint8_t MatchTable0[] = { +// CHECK_OPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(55), // Rule ID 0 // +// CHECK_OPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ATOMICRMW_XCHG), +// CHECK_OPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK_OPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK_OPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), +// CHECK_OPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK_OPT-NEXT: // MIs[0] ptr +// CHECK_OPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, +// CHECK_OPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK_OPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK_OPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_test_atomic_op_frag), +// CHECK_OPT-NEXT: // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>> => (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val) +// CHECK_OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN), +// CHECK_OPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK_OPT-NEXT: // GIR_Coverage, 0, +// CHECK_OPT-NEXT: GIR_Done, +// CHECK_OPT-NEXT: // Label 0: @55 +// CHECK_OPT-NEXT: GIM_Reject, +// CHECK_OPT-NEXT: }; +// CHECK_OPT-NEXT: return MatchTable0; +// CHECK_OPT-NEXT: } diff --git a/llvm/test/TableGen/DefaultOpsGlobalISel.td b/llvm/test/TableGen/DefaultOpsGlobalISel.td index c997467c570a..9fb95e852e48 100644 --- a/llvm/test/TableGen/DefaultOpsGlobalISel.td +++ b/llvm/test/TableGen/DefaultOpsGlobalISel.td @@ -31,101 +31,200 @@ def omod : OperandWithDefaultOps <i32, (ops (i32 0))>; def clamp : OperandWithDefaultOps <i1, (ops (i1 0))>; -// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FMAXNUM, -// CHECK: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_SelectSrcMods, -// CHECK: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/1, GICP_gi_SelectSrcMods, -// CHECK: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FMAX, -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // mods0 -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0 -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/1, // mods1 -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/1, /*SubOperand*/0, // src1 -// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, - - -// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FFLOOR, -// CHECK: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/0, GICP_gi_SelectClampOMod, -// CHECK: // (ffloor:{ *:[f32] } (SelectClampOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod, i1:{ *:[i1] }:$clamp)) => (FLOMP:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, omod:{ *:[i32] }:$omod) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FLOMP, -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0 -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/2, // clamp -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // omod - - -// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCANONICALIZE, -// CHECK: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FMAX, -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // mods -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // mods -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src -// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, - - -// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCOS, -// CHECK: // (fcos:{ *:[f32] } (SelectOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$omod)) => (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FLAMP, -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0 -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // omod -// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0, - - -// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FEXP2, -// CHECK: // (fexp2:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FEEPLE:{ *:[f32] } FPR32:{ *:[f32] }:$src0, (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0), clamp:{ *:[i1] }:$clamp) - -// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::FFOO, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, // src0 -// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*Imm*/0, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FEEPLE, -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0 -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, - - -// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FSIN, -// CHECK: // (fsin:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FFOO:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FFOO, -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0 -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, - - -// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FSQRT, -// CHECK: // (fsqrt:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, 93:{ *:[i32] }, clamp:{ *:[i1] }:$clamp) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FLAMP, -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src0 -// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/93, -// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // clamp -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, - -// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_ROUND, -// CHECK: // (fround:{ *:[f32] } f32:{ *:[f32] }:$src0) => (FBAR:{ *:[f32] } f32:{ *:[f32] }:$src0) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FBAR, -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 -// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, - -// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_TRUNC, -// CHECK: // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$src0) => (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FFOO, -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 -// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, - +// CHECK: const uint8_t *MyTargetInstructionSelector::getMatchTable() const { +// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(79), // Rule ID 3 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FMAXNUM), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: // MIs[0] SelectSrcMods:src0:mods0 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectSrcMods), +// CHECK-NEXT: // MIs[0] SelectSrcMods:src1:mods1 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_SelectSrcMods), +// CHECK-NEXT: // (fmaxnum:{ *:[f32] } (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src0, src_mods:{ *:[i32] }:$mods0), (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src1, src_mods:{ *:[i32] }:$mods1)) => (FMAX:{ *:[f32] } src_mods:{ *:[i32] }:$mods0, f32:{ *:[f32] }:$src0, src_mods:{ *:[i32] }:$mods1, f32:{ *:[f32] }:$src1) +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FMAX), +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods0 +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // mods1 +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, +// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 3, +// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: // Label 0: @79 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(139), // Rule ID 2 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FFLOOR), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: // MIs[0] SelectClampOMod:src0:omod:clamp +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClampOMod), +// CHECK-NEXT: // (ffloor:{ *:[f32] } (SelectClampOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod, i1:{ *:[i1] }:$clamp)) => (FLOMP:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, omod:{ *:[i32] }:$omod) +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FLOMP), +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // omod +// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 2, +// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: // Label 1: @139 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(207), // Rule ID 8 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: // MIs[0] SelectSrcMods:src:mods +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectSrcMods), +// CHECK-NEXT: // (fcanonicalize:{ *:[f32] } (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$mods)) => (FMAX:{ *:[f32] } ?:{ *:[i32] }:$mods, ?:{ *:[f32] }:$src, ?:{ *:[i32] }:$mods, ?:{ *:[f32] }:$src, 0:{ *:[i1] }) +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FMAX), +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, +// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 8, +// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: // Label 2: @207 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(265), // Rule ID 5 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCOS), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: // MIs[0] SelectOMod:src0:omod +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectOMod), +// CHECK-NEXT: // (fcos:{ *:[f32] } (SelectOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$omod)) => (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod) +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FLAMP), +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // omod +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, +// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 5, +// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: // Label 3: @265 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(345), // Rule ID 7 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FEXP2), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: // MIs[0] SelectClamp:src0:clamp +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp), +// CHECK-NEXT: // (fexp2:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FEEPLE:{ *:[f32] } FPR32:{ *:[f32] }:$src0, (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0), clamp:{ *:[i1] }:$clamp) +// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::FFOO), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*Imm*/0, +// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FEEPLE), +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp +// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 7, +// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: // Label 4: @345 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(400), // Rule ID 0 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FSIN), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: // MIs[0] SelectClamp:src0:clamp +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp), +// CHECK-NEXT: // (fsin:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FFOO:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp) +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FFOO), +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp +// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 0, +// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: // Label 5: @400 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(458), // Rule ID 6 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FSQRT), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: // MIs[0] SelectClamp:src0:clamp +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp), +// CHECK-NEXT: // (fsqrt:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, 93:{ *:[i32] }, clamp:{ *:[i1] }:$clamp) +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FLAMP), +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/93, +// CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp +// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 6, +// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: // Label 6: @458 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(503), // Rule ID 1 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: // MIs[0] src0 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: // (fround:{ *:[f32] } f32:{ *:[f32] }:$src0) => (FBAR:{ *:[f32] } f32:{ *:[f32] }:$src0) +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FBAR), +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, +// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 1, +// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: // Label 7: @503 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(548), // Rule ID 4 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: // MIs[0] src0 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$src0) => (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0) +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FFOO), +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, +// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 4, +// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: // Label 8: @548 +// CHECK-NEXT: GIM_Reject, +// CHECK-NEXT: }; // Size: 549 bytes +// CHECK-NEXT: return MatchTable0; +// CHECK-NEXT: } // Have default operand with explicit value from complex pattern. def FFOO : I<(outs FPR32:$dst), (ins FPR32:$src0, clamp:$clamp), diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-eraseroot.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-eraseroot.td index 0dd265c14ddc..25fdd887b20b 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-eraseroot.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-eraseroot.td @@ -17,11 +17,11 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ Test0, ]>; -// CHECK: const int64_t *GenMyCombiner::getMatchTable() const { -// CHECK-NEXT: constexpr static int64_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ 10, // Rule ID 0 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_STORE, +// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { +// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(15), // Rule ID 0 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_STORE), // CHECK-NEXT: // MIs[0] a // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] b @@ -29,7 +29,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // Combiner Rule #0: Test0 // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 0: @10 +// CHECK-NEXT: // Label 0: @15 // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: }; // CHECK-NEXT: return MatchTable0; diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td index 6ae1305aa1aa..f4f1faf7cc6d 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td @@ -26,14 +26,14 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ ReplaceTemp ]>; -// CHECK: const int64_t *GenMyCombiner::getMatchTable() const { -// CHECK-NEXT: constexpr static int64_t MatchTable0[] = { -// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/65, 181, /*)*//*default:*//*Label 2*/ 193, -// CHECK-NEXT: /*TargetOpcode::G_UNMERGE_VALUES*//*Label 0*/ 121, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -// CHECK-NEXT: /*TargetOpcode::G_FNEG*//*Label 1*/ 166, -// CHECK-NEXT: // Label 0: @121 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ 165, // Rule ID 1 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule1Enabled, +// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { +// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { +// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(65), GIMT_Encode2(181), /*)*//*default:*//*Label 2*/ GIMT_Encode4(556), +// CHECK-NEXT: /*TargetOpcode::G_UNMERGE_VALUES*//*Label 0*/ GIMT_Encode4(474), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), +// CHECK-NEXT: /*TargetOpcode::G_FNEG*//*Label 1*/ GIMT_Encode4(524), +// CHECK-NEXT: // Label 0: @474 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(523), // Rule ID 1 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule1Enabled), // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: // MIs[0] a // CHECK-NEXT: // No operand predicates @@ -41,7 +41,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] tmp // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, // CHECK-NEXT: // MIs[1] x // CHECK-NEXT: // No operand predicates @@ -50,23 +50,23 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: // Combiner Rule #1: ReplaceTemp -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::G_UNMERGE_VALUES, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UNMERGE_VALUES), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // a -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_ReplaceRegWithTempReg, /*OldInsnID*/0, /*OldOpIdx*/1, /*TempRegID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 3: @165 +// CHECK-NEXT: // Label 3: @523 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 1: @166 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ 192, // Rule ID 0 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK-NEXT: // Label 1: @524 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(555), // Rule ID 0 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] tmp // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), // CHECK-NEXT: // MIs[1] src // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIM_CheckCanReplaceReg, /*OldInsnID*/0, /*OldOpIdx*/0, /*NewInsnId*/1, /*NewOpIdx*/1, @@ -75,10 +75,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIR_ReplaceReg, /*OldInsnID*/0, /*OldOpIdx*/0, /*NewInsnId*/1, /*NewOpIdx*/1, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 4: @192 +// CHECK-NEXT: // Label 4: @555 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 2: @193 +// CHECK-NEXT: // Label 2: @556 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; +// CHECK-NEXT: }; // Size: 557 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td index fd5f7db0b4f1..d0c0eba9e397 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td @@ -32,61 +32,61 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ CImmInstTest1 ]>; -// CHECK: const int64_t *GenMyCombiner::getMatchTable() const { -// CHECK-NEXT: constexpr static int64_t MatchTable0[] = { -// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/19, 127, /*)*//*default:*//*Label 3*/ 195, -// CHECK-NEXT: /*TargetOpcode::COPY*//*Label 0*/ 113, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -// CHECK-NEXT: /*TargetOpcode::G_CONSTANT*//*Label 1*/ 139, 0, 0, 0, 0, 0, -// CHECK-NEXT: /*TargetOpcode::G_ZEXT*//*Label 2*/ 166, -// CHECK-NEXT: // Label 0: @113 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ 138, // Rule ID 0 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { +// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { +// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(19), GIMT_Encode2(127), /*)*//*default:*//*Label 3*/ GIMT_Encode4(559), +// CHECK-NEXT: /*TargetOpcode::COPY*//*Label 0*/ GIMT_Encode4(442), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), +// CHECK-NEXT: /*TargetOpcode::G_CONSTANT*//*Label 1*/ GIMT_Encode4(473), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), +// CHECK-NEXT: /*TargetOpcode::G_ZEXT*//*Label 2*/ GIMT_Encode4(519), +// CHECK-NEXT: // Label 0: @442 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(472), // Rule ID 0 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: // MIs[0] a // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, +// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, // CHECK-NEXT: // Combiner Rule #0: InstTest0 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // a -// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0, +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 4: @138 +// CHECK-NEXT: // Label 4: @472 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 1: @139 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ 165, // Rule ID 2 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule2Enabled, +// CHECK-NEXT: // Label 1: @473 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(518), // Rule ID 2 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule2Enabled), // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: // MIs[0] a // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 0, +// CHECK-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #2: CImmInstTest1 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::G_CONSTANT, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // a -// CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/GILLT_s32, /*Imm*/42, +// CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/GILLT_s32, /*Imm*/GIMT_Encode8(42), // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 5: @165 +// CHECK-NEXT: // Label 5: @518 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 2: @166 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ 194, // Rule ID 1 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule1Enabled, +// CHECK-NEXT: // Label 2: @519 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(558), // Rule ID 1 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule1Enabled), // CHECK-NEXT: // MIs[0] a // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] Operand 1 -// CHECK-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0, +// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0, +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #1: InstTest1 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // a -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 6: @194 +// CHECK-NEXT: // Label 6: @558 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 3: @195 +// CHECK-NEXT: // Label 3: @559 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; +// CHECK-NEXT: }; // Size: 560 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td index 9f02ff174936..22e4d2d5d9d1 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td @@ -15,32 +15,32 @@ def MIFlagsTest : GICombineRule< def MyCombiner: GICombiner<"GenMyCombiner", [MIFlagsTest]>; -// CHECK: const int64_t *GenMyCombiner::getMatchTable() const { -// CHECK-NEXT: constexpr static int64_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ 49, // Rule ID 0 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SEXT, +// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { +// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(68), // Rule ID 0 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SEXT), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] tmp // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, -// CHECK-NEXT: GIM_MIFlags, /*MI*/1, MachineInstr::FmNsz | MachineInstr::FmReassoc, -// CHECK-NEXT: GIM_MIFlagsNot, /*MI*/1, MachineInstr::FmArcp | MachineInstr::FmNoNans, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), +// CHECK-NEXT: GIM_MIFlags, /*MI*/1, GIMT_Encode4(MachineInstr::FmNsz | MachineInstr::FmReassoc), +// CHECK-NEXT: GIM_MIFlagsNot, /*MI*/1, GIMT_Encode4(MachineInstr::FmArcp | MachineInstr::FmNoNans), // CHECK-NEXT: // MIs[1] src // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: // Combiner Rule #0: MIFlagsTest -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::G_MUL, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src // CHECK-NEXT: GIR_CopyMIFlags, /*InsnID*/0, /*OldInsnID*/1, -// CHECK-NEXT: GIR_SetMIFlags, /*InsnID*/0, MachineInstr::FmReassoc, -// CHECK-NEXT: GIR_UnsetMIFlags, /*InsnID*/0, MachineInstr::FmNsz | MachineInstr::FmArcp, +// CHECK-NEXT: GIR_SetMIFlags, /*InsnID*/0, GIMT_Encode4(MachineInstr::FmReassoc), +// CHECK-NEXT: GIR_UnsetMIFlags, /*InsnID*/0, GIMT_Encode4(MachineInstr::FmNsz | MachineInstr::FmArcp), // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 0: @49 +// CHECK-NEXT: // Label 0: @68 // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: }; // CHECK-NEXT: return MatchTable0; diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td index fa2451aa9582..06368db75e3b 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td @@ -19,33 +19,33 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ InstTest0, ]>; -// CHECK: const int64_t *GenMyCombiner::getMatchTable() const { -// CHECK-NEXT: constexpr static int64_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ 73, // Rule ID 0 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL, +// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { +// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(79), // Rule ID 0 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s8, // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: // MIs[1] b // CHECK-NEXT: GIM_CheckIsSameOperandIgnoreCopies, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, // CHECK-NEXT: // Combiner Rule #0: InstTest0 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::G_ADD, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // c // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::G_ADD, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // b -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 0: @73 +// CHECK-NEXT: // Label 0: @79 // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: }; // CHECK-NEXT: return MatchTable0; diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td index b62ebcf24687..fdcb31e96797 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td @@ -26,69 +26,69 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ Test0 ]>; -// CHECK: const int64_t *GenMyCombiner::getMatchTable() const { -// CHECK-NEXT: constexpr static int64_t MatchTable0[] = { -// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/119, 182, /*)*//*default:*//*Label 3*/ 152, -// CHECK-NEXT: /*TargetOpcode::G_TRUNC*//*Label 0*/ 68, 0, 0, 0, 0, 0, 0, -// CHECK-NEXT: /*TargetOpcode::G_ZEXT*//*Label 1*/ 93, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -// CHECK-NEXT: /*TargetOpcode::G_FPEXT*//*Label 2*/ 127, -// CHECK-NEXT: // Label 0: @68 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ 92, // Rule ID 1 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { +// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { +// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(119), GIMT_Encode2(182), /*)*//*default:*//*Label 3*/ GIMT_Encode4(380), +// CHECK-NEXT: /*TargetOpcode::G_TRUNC*//*Label 0*/ GIMT_Encode4(262), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), +// CHECK-NEXT: /*TargetOpcode::G_ZEXT*//*Label 1*/ GIMT_Encode4(298), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), +// CHECK-NEXT: /*TargetOpcode::G_FPEXT*//*Label 2*/ GIMT_Encode4(344), +// CHECK-NEXT: // Label 0: @262 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(297), // Rule ID 1 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] root // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] __Test0_match_0.z // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0, +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[1]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 4: @92 +// CHECK-NEXT: // Label 4: @297 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 1: @93 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ 126, // Rule ID 0 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK-NEXT: // Label 1: @298 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(343), // Rule ID 0 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] root // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] __Test0_match_0.b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[1] __Test0_match_0.x // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0, +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[0]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 5: @126 +// CHECK-NEXT: // Label 5: @343 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 2: @127 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ 151, // Rule ID 2 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK-NEXT: // Label 2: @344 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(379), // Rule ID 2 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] root // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] __Test0_match_0.z // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0, +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[2]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 6: @151 +// CHECK-NEXT: // Label 6: @379 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 3: @152 +// CHECK-NEXT: // Label 3: @380 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; +// CHECK-NEXT: }; // Size: 381 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td index 22cd2be819de..2b5cfb4f6de2 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td @@ -157,166 +157,166 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: return false; // CHECK-NEXT: } -// CHECK: const int64_t *GenMyCombiner::getMatchTable() const { -// CHECK-NEXT: constexpr static int64_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ 682, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_AND, -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ 76, // Rule ID 7 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { +// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(850), +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND), +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(99), // Rule ID 7 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] cst0 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[1] a.z // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] tmp // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), // CHECK-NEXT: // MIs[2] cst1 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[3] b.z // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[2] cst2 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[4] c.z // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner21, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner22, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner23, +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner21), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner22), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner23), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/4, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0, +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[1], b[1], c[1]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 1: @76 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ 156, // Rule ID 6 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK-NEXT: // Label 1: @99 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(199), // Rule ID 6 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] cst0 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[1] a.z // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] tmp // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), // CHECK-NEXT: // MIs[2] cst1 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[3] b.z // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[2] cst2 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[4] c.b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[5] c.x // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner18, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner19, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner20, +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner18), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner19), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner20), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/4, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/5, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0, +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[1], b[1], c[0]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 2: @156 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ 236, // Rule ID 5 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK-NEXT: // Label 2: @199 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(299), // Rule ID 5 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] cst0 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[1] a.z // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] tmp // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), // CHECK-NEXT: // MIs[2] cst1 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[3] b.b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[4] b.x // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[2] cst2 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[5] c.z // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner15, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner16, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner17, +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner15), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner16), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner17), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/4, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/5, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0, +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[1], b[0], c[1]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 3: @236 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ 325, // Rule ID 4 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK-NEXT: // Label 3: @299 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(409), // Rule ID 4 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] cst0 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[1] a.z // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] tmp // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), // CHECK-NEXT: // MIs[2] cst1 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[3] b.b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[4] b.x // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[2] cst2 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[5] c.b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[6] c.x // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner12, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner13, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner14, +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner12), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner13), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner14), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, @@ -324,89 +324,89 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/5, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/6, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0, +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[1], b[0], c[0]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 4: @325 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ 405, // Rule ID 3 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK-NEXT: // Label 4: @409 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(509), // Rule ID 3 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] cst0 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[1] a.b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[2] a.x // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] tmp // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), // CHECK-NEXT: // MIs[3] cst1 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[4] b.z // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[3] cst2 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/5, /*MI*/3, /*OpIdx*/2, // MIs[5] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[5] c.z // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner9, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner10, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner11, +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner9), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner10), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner11), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/4, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/5, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0, +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[0], b[1], c[1]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 5: @405 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ 494, // Rule ID 2 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK-NEXT: // Label 5: @509 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(619), // Rule ID 2 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] cst0 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[1] a.b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[2] a.x // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] tmp // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), // CHECK-NEXT: // MIs[3] cst1 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[4] b.z // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[3] cst2 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/5, /*MI*/3, /*OpIdx*/2, // MIs[5] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[5] c.b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[6] c.x // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner6, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner7, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner8, +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner6), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner7), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner8), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, @@ -414,46 +414,46 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/5, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/6, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0, +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[0], b[1], c[0]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 6: @494 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ 583, // Rule ID 1 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK-NEXT: // Label 6: @619 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(729), // Rule ID 1 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] cst0 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[1] a.b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[2] a.x // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] tmp // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), // CHECK-NEXT: // MIs[3] cst1 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[4] b.b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[5] b.x // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[3] cst2 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[6] c.z // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner3, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner4, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner5, +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner3), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner4), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner5), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, @@ -461,49 +461,49 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/5, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/6, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0, +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[0], b[0], c[1]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 7: @583 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ 681, // Rule ID 0 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK-NEXT: // Label 7: @729 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(849), // Rule ID 0 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] cst0 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[1] a.b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[2] a.x // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] tmp // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), // CHECK-NEXT: // MIs[3] cst1 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[4] b.b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[5] b.x // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[3] cst2 // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/6, /*MI*/3, /*OpIdx*/2, // MIs[6] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/6, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[6] c.b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/7, /*MI*/6, /*OpIdx*/1, // MIs[7] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/7, TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[7] c.x // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner0, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner1, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner2, +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner0), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner1), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner2), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, @@ -512,18 +512,18 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/6, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/7, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0, +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[0], b[0], c[0]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 8: @681 +// CHECK-NEXT: // Label 8: @849 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 0: @682 +// CHECK-NEXT: // Label 0: @850 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; +// CHECK-NEXT: }; // Size: 851 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td index 496d86aeef2d..3cffee7ab581 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td @@ -14,33 +14,33 @@ def Test0 : GICombineRule< (apply (G_SUB $dst, (GITypeOf<"$src"> 0), $tmp), (G_CONSTANT GITypeOf<"$dst">:$tmp, (GITypeOf<"$src"> 42)))>; -// CHECK: const int64_t *GenMyCombiner::getMatchTable() const { -// CHECK-NEXT: constexpr static int64_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ 57, // Rule ID 0 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL, +// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { +// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(75), // Rule ID 0 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: // MIs[0] dst -// CHECK-NEXT: GIM_RecordRegType, /*MI*/0, /*Op*/0, /*TempTypeIdx*/-1, +// CHECK-NEXT: GIM_RecordRegType, /*MI*/0, /*Op*/0, /*TempTypeIdx*/uint8_t(-1), // CHECK-NEXT: // MIs[0] src -// CHECK-NEXT: GIM_RecordRegType, /*MI*/0, /*Op*/1, /*TempTypeIdx*/-2, +// CHECK-NEXT: GIM_RecordRegType, /*MI*/0, /*Op*/1, /*TempTypeIdx*/uint8_t(-2), // CHECK-NEXT: // MIs[0] Operand 2 -// CHECK-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, -// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/-2, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/1, /*Val*/0, -// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/-1, +// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), +// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/uint8_t(-2), +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/1, /*Val*/GIMT_Encode8(0), +// CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/uint8_t(-1), // CHECK-NEXT: // Combiner Rule #0: Test0 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::G_CONSTANT, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, -// CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/-2, /*Imm*/42, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT), +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, +// CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/uint8_t(-2), /*Imm*/GIMT_Encode8(42), // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::G_SUB, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_SUB), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // dst -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 0: @57 +// CHECK-NEXT: // Label 0: @75 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; +// CHECK-NEXT: }; // Size: 76 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td index 5226795cd9d3..cc77bfdd29c3 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-variadics.td @@ -35,25 +35,25 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ InstTest3 ]>; -// CHECK: const int64_t *GenMyCombiner::getMatchTable() const { -// CHECK-NEXT: constexpr static int64_t MatchTable0[] = { -// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/65, 69, /*)*//*default:*//*Label 2*/ 51, -// CHECK-NEXT: /*TargetOpcode::G_UNMERGE_VALUES*//*Label 0*/ 9, 0, 0, -// CHECK-NEXT: /*TargetOpcode::G_BUILD_VECTOR*//*Label 1*/ 30, -// CHECK-NEXT: // Label 0: @9 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ 19, // Rule ID 2 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule2Enabled, +// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { +// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { +// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(65), GIMT_Encode2(69), /*)*//*default:*//*Label 2*/ GIMT_Encode4(88), +// CHECK-NEXT: /*TargetOpcode::G_UNMERGE_VALUES*//*Label 0*/ GIMT_Encode4(26), GIMT_Encode4(0), GIMT_Encode4(0), +// CHECK-NEXT: /*TargetOpcode::G_BUILD_VECTOR*//*Label 1*/ GIMT_Encode4(57), +// CHECK-NEXT: // Label 0: @26 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(41), // Rule ID 2 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule2Enabled), // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: // MIs[0] a // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] b // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // Combiner Rule #2: InstTest2 -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 3: @19 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ 29, // Rule ID 3 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule3Enabled, +// CHECK-NEXT: // Label 3: @41 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(56), // Rule ID 3 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule3Enabled), // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, // CHECK-NEXT: // MIs[0] a // CHECK-NEXT: // No operand predicates @@ -64,24 +64,24 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // MIs[0] d // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // Combiner Rule #3: InstTest3 -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 4: @29 +// CHECK-NEXT: // Label 4: @56 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 1: @30 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ 40, // Rule ID 1 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule1Enabled, +// CHECK-NEXT: // Label 1: @57 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(72), // Rule ID 1 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule1Enabled), // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: // MIs[0] a // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] b // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // Combiner Rule #1: InstTest1 -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 5: @40 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ 50, // Rule ID 0 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK-NEXT: // Label 5: @72 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(87), // Rule ID 0 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, // CHECK-NEXT: // MIs[0] a // CHECK-NEXT: // No operand predicates @@ -92,11 +92,11 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // MIs[0] d // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // Combiner Rule #0: InstTest0 -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 6: @50 +// CHECK-NEXT: // Label 6: @87 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 2: @51 +// CHECK-NEXT: // Label 2: @88 // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: }; // CHECK-NEXT: return MatchTable0; diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td index 6777089f846f..61dbbac745fa 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td @@ -130,127 +130,127 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: } // Verify match table. -// CHECK: const int64_t *GenMyCombiner::getMatchTable() const { -// CHECK-NEXT: constexpr static int64_t MatchTable0[] = { -// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/19, 127, /*)*//*default:*//*Label 6*/ 268, -// CHECK-NEXT: /*TargetOpcode::COPY*//*Label 0*/ 113, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -// CHECK-NEXT: /*TargetOpcode::G_AND*//*Label 1*/ 142, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -// CHECK-NEXT: /*TargetOpcode::G_STORE*//*Label 2*/ 182, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -// CHECK-NEXT: /*TargetOpcode::G_TRUNC*//*Label 3*/ 217, 0, 0, 0, 0, -// CHECK-NEXT: /*TargetOpcode::G_SEXT*//*Label 4*/ 232, 0, -// CHECK-NEXT: /*TargetOpcode::G_ZEXT*//*Label 5*/ 240, -// CHECK-NEXT: // Label 0: @113 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ 134, // Rule ID 4 // -// CHECK-NEXT: GIM_CheckFeatures, GIFBS_HasAnswerToEverything, -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule3Enabled, +// CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { +// CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { +// CHECK-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(19), GIMT_Encode2(127), /*)*//*default:*//*Label 6*/ GIMT_Encode4(657), +// CHECK-NEXT: /*TargetOpcode::COPY*//*Label 0*/ GIMT_Encode4(442), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), +// CHECK-NEXT: /*TargetOpcode::G_AND*//*Label 1*/ GIMT_Encode4(484), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), +// CHECK-NEXT: /*TargetOpcode::G_STORE*//*Label 2*/ GIMT_Encode4(537), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), +// CHECK-NEXT: /*TargetOpcode::G_TRUNC*//*Label 3*/ GIMT_Encode4(579), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), +// CHECK-NEXT: /*TargetOpcode::G_SEXT*//*Label 4*/ GIMT_Encode4(604), GIMT_Encode4(0), +// CHECK-NEXT: /*TargetOpcode::G_ZEXT*//*Label 5*/ GIMT_Encode4(617), +// CHECK-NEXT: // Label 0: @442 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(471), // Rule ID 4 // +// CHECK-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAnswerToEverything), +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule3Enabled), // CHECK-NEXT: // MIs[0] a // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] b // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[1] c // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner0, +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner0), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: // Combiner Rule #3: InstTest1 -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 7: @134 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ 141, // Rule ID 3 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule2Enabled, +// CHECK-NEXT: // Label 7: @471 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(483), // Rule ID 3 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule2Enabled), // CHECK-NEXT: // MIs[0] a // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] b // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // Combiner Rule #2: InstTest0 -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner1, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner1), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 8: @141 +// CHECK-NEXT: // Label 8: @483 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 1: @142 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 9*/ 181, // Rule ID 6 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule5Enabled, +// CHECK-NEXT: // Label 1: @484 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 9*/ GIMT_Encode4(536), // Rule ID 6 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule5Enabled), // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] x // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), // CHECK-NEXT: // MIs[1] z -// CHECK-NEXT: GIM_CheckLiteralInt, /*MI*/1, /*Op*/1, -42, -// CHECK-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 43, +// CHECK-NEXT: GIM_CheckLiteralInt, /*MI*/1, /*Op*/1, GIMT_Encode8(-42), +// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 43, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: // Combiner Rule #5: InOutInstTest1 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::G_TRUNC, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 9: @181 +// CHECK-NEXT: // Label 9: @536 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 2: @182 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 10*/ 216, // Rule ID 5 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule4Enabled, +// CHECK-NEXT: // Label 2: @537 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 10*/ GIMT_Encode4(578), // Rule ID 5 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule4Enabled), // CHECK-NEXT: // MIs[0] tmp // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), // CHECK-NEXT: // MIs[1] ext // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] ptr // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: // Combiner Rule #4: InOutInstTest0 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::G_STORE, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_STORE), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ext // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ptr -// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, +// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner2, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner2), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 10: @216 +// CHECK-NEXT: // Label 10: @578 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 3: @217 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 11*/ 224, // Rule ID 0 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule0Enabled, +// CHECK-NEXT: // Label 3: @579 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 11*/ GIMT_Encode4(591), // Rule ID 0 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // Combiner Rule #0: WipOpcodeTest0; wip_match_opcode 'G_TRUNC' -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 11: @224 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 12*/ 231, // Rule ID 1 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule1Enabled, +// CHECK-NEXT: // Label 11: @591 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 12*/ GIMT_Encode4(603), // Rule ID 1 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule1Enabled), // CHECK-NEXT: // Combiner Rule #1: WipOpcodeTest1; wip_match_opcode 'G_TRUNC' -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 12: @231 +// CHECK-NEXT: // Label 12: @603 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 4: @232 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 13*/ 239, // Rule ID 2 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule1Enabled, +// CHECK-NEXT: // Label 4: @604 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 13*/ GIMT_Encode4(616), // Rule ID 2 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule1Enabled), // CHECK-NEXT: // Combiner Rule #1: WipOpcodeTest1; wip_match_opcode 'G_SEXT' -// CHECK-NEXT: GIR_CustomAction, GICXXCustomAction_CombineApplyGICombiner0, +// CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 13: @239 +// CHECK-NEXT: // Label 13: @616 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 5: @240 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 14*/ 267, // Rule ID 7 // -// CHECK-NEXT: GIM_CheckSimplePredicate, GICXXPred_Simple_IsRule6Enabled, +// CHECK-NEXT: // Label 5: @617 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 14*/ GIMT_Encode4(656), // Rule ID 7 // +// CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule6Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] cst // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_GICombiner1, +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner1), // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/0, +// CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #6: PatFragTest0 @ [__PatFragTest0_match_1[0]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 14: @267 +// CHECK-NEXT: // Label 14: @656 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 6: @268 +// CHECK-NEXT: // Label 6: @657 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; // Size: 2152 bytes +// CHECK-NEXT: }; // Size: 658 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelEmitter-PR39045.td b/llvm/test/TableGen/GlobalISelEmitter-PR39045.td index 55e5aa2e905d..5407222121bb 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-PR39045.td +++ b/llvm/test/TableGen/GlobalISelEmitter-PR39045.td @@ -2,8 +2,8 @@ // RUN: FileCheck %s < %t // Both predicates should be tested -// CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_pat_frag_b, -// CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_pat_frag_a, +// CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_pat_frag_b), +// CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_pat_frag_a), include "llvm/Target/Target.td" include "GlobalISelEmitterCommon.td" diff --git a/llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td b/llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td index 0a12cc0bf856..8d6dedf2f920 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td +++ b/llvm/test/TableGen/GlobalISelEmitter-SDNodeXForm-timm.td @@ -18,19 +18,19 @@ def int_mytarget_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [Imm def SLEEP : I<(outs), (ins i32imm:$src0), []>; def FOO : I<(outs GPR32:$dst), (ins GPR32:$src0, i32imm:$src1), []>; -// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC, -// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mytarget_foo, +// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC), +// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_foo), // GISEL: GIM_CheckIsImm, /*MI*/0, /*Op*/3, -// GISEL: GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GICR_renderShiftImml1, // src1 +// GISEL: GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderShiftImml1), // src1 def : Pat< (int_mytarget_foo i32:$src0, (i32 timm:$src1)), (FOO GPR32:$src0, (shiftl_1 $src1)) >; -// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, -// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mytarget_sleep, +// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS), +// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mytarget_sleep), // GISEL: GIM_CheckIsImm, /*MI*/0, /*Op*/1, -// GISEL: GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*OperandRenderer*/GICR_renderShiftImml1, // src0 +// GISEL: GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*OperandRenderer*/GIMT_Encode2(GICR_renderShiftImml1), // src0 def : Pat< (int_mytarget_sleep (i32 timm:$src0)), (SLEEP (shiftl_1 $src0)) diff --git a/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td b/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td index 5263eed007bd..081c9e863459 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td +++ b/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td @@ -5,15 +5,15 @@ include "GlobalISelEmitterCommon.td" def ST_ATOM_B32 : I<(outs), (ins GPR32Op:$val, GPR32Op:$ptr), []>; -// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_STORE, -// GISEL-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, -// GISEL-NEXT: GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, +// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_STORE), +// GISEL-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), +// GISEL-NEXT: GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, // GISEL-NEXT: // MIs[0] val // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, // GISEL-NEXT: // MIs[0] ptr // GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, // GISEL-NEXT: // (atomic_store i32:{ *:[i32] }:$val, iPTR:{ *:[iPTR] }:$ptr)<<P:Predicate_atomic_store_8>> => (ST_ATOM_B32 GPR32Op:{ *:[i32] }:$val, GPR32Op:{ *:[i32] }:$ptr) -// GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ST_ATOM_B32, +// GISEL-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ST_ATOM_B32), def : Pat< // (atomic_store_8 iPTR:$ptr, i32:$val), (atomic_store_8 i32:$val, iPTR:$ptr), diff --git a/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td b/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td index 5d39278ed986..eae29308aa1b 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td +++ b/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td @@ -12,21 +12,21 @@ include "GlobalISelEmitterCommon.td" // GISEL-OPT: GIM_Try, // GISEL-OPT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, -// GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, +// GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), // GISEL-OPT: GIM_CheckIsBuildVectorAllZeros, /*MI*/1, // GISEL-OPT: GIM_Try, // GISEL-OPT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, -// GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, +// GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), // GISEL-OPT: GIM_CheckIsBuildVectorAllOnes, /*MI*/1, -// GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LSHR, +// GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LSHR), // GISEL-NOOPT: // MIs[0] Operand 2 // GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, // GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] -// GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, +// GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), // GISEL-NOOPT-NEXT: GIM_CheckIsBuildVectorAllOnes, /*MI*/1, // GISEL-NOOPT-NEXT: // MIs[1] Operand 0 // GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16, @@ -37,11 +37,11 @@ def VFOOONES : I<(outs VecReg128:$dst), (ins VecReg128:$src0), >; -// GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SHL, +// GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SHL), // GISEL-NOOPT: // MIs[0] Operand 2 // GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, // GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] -// GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC, +// GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), // GISEL-NOOPT-NEXT: GIM_CheckIsBuildVectorAllZeros, /*MI*/1, // GISEL-NOOPT-NEXT: // MIs[1] Operand 0 // GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16, diff --git a/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td b/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td index 2f39bf49af4d..bfbeee466b1c 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td +++ b/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td @@ -22,19 +22,19 @@ def CAT1 : I<(outs GPR32:$dst), (ins GPR32:$src0), []>; // Test immarg intrinsic pattern // Make sure there is no type check. -// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, -// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mytarget_sleep, +// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS), +// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mytarget_sleep), // GISEL-NEXT: // MIs[0] Operand 1 -// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 0, +// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(0), def : Pat< (int_mytarget_sleep 0), (SLEEP0) >; -// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, -// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mytarget_sleep, +// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS), +// GISEL: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mytarget_sleep), // GISEL-NEXT: // MIs[0] Operand 1 -// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 1, +// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(1), def : Pat< (int_mytarget_sleep 1), (SLEEP1) @@ -42,21 +42,20 @@ def : Pat< // Check a non-intrinsic instruction with an immediate parameter. -// GISEL: GIM_CheckOpcode, /*MI*/0, MyTarget::G_TGT_CAT, +// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_TGT_CAT), // GISEL: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // GISEL-NEXT: // MIs[0] Operand 2 -// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, 0, +// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0), def : Pat< (TgtCat i32:$src0, 0), (CAT0 GPR32:$src0) >; -// GISEL: GIM_CheckOpcode, /*MI*/0, MyTarget::G_TGT_CAT, +// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_TGT_CAT), // GISEL: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // GISEL-NEXT: // MIs[0] Operand 2 -// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, 93, +// GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(93), def : Pat< (TgtCat i32:$src0, 93), (CAT1 GPR32:$src0) >; - diff --git a/llvm/test/TableGen/GlobalISelEmitter-input-discard.td b/llvm/test/TableGen/GlobalISelEmitter-input-discard.td index 68a9553a8b73..7731cdefac85 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-input-discard.td +++ b/llvm/test/TableGen/GlobalISelEmitter-input-discard.td @@ -8,21 +8,21 @@ def int_tgt_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; // Test that using srcvalue works for discarded pattern inputs. def FOO : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32Op:$src1), []>; -// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, +// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS), // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, -// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::tgt_foo, +// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::tgt_foo), // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // (intrinsic_w_chain:{ *:[i32] } {{[0-9]+}}:{ *:[iPTR] }, srcvalue:{ *:[i32] }, i32:{ *:[i32] }:$src1) => (FOO:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GPR32:{ *:[i32] }:$src1) // GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, -// GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), +// GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FOO, +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FOO), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// GISEL-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0, // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, diff --git a/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td b/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td index 64cf31f3772e..f962a7dadf74 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td +++ b/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td @@ -21,22 +21,22 @@ def : GINodeEquiv<G_TWO_OUT, two_out>; def : Pat<(two_out GPR32:$val), (THREE_OUTS GPR32:$val)>; -// CHECK: GIM_CheckOpcode, /*MI*/0, MyTarget::G_TWO_OUT, +// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_TWO_OUT), // CHECK-NEXT: // MIs[0] DstI[out1] // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] DstI[out2] // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] val // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (two_out:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$val) => (THREE_OUTS:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$val) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::THREE_OUTS, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::THREE_OUTS), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[out1] // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // DstI[out2] -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead, +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, diff --git a/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td b/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td index 85ac3ace0364..37ce7416fa51 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td +++ b/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td @@ -29,21 +29,21 @@ def : Pat<(loadpost (p0 GPR32:$addr), (i32 GPR32:$off)), (LDPost GPR32:$addr, GPR32:$off) >; -// CHECK: GIM_CheckOpcode, /*MI*/0, MyTarget::G_POST_LOAD, +// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_POST_LOAD), // CHECK-NEXT: // MIs[0] DstI[val] // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] DstI[ptr_out] // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_p0s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] addr // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_p0s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] off // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (loadpost:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$addr, GPR32:{ *:[i32] }:$off) => (LDPost:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$addr, GPR32:{ *:[i32] }:$off) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LDPost, +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LDPost), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // Test where a whole new MIR instruction is created during ISel @@ -63,21 +63,21 @@ def : GINodeEquiv<G_TWO_IN, two_in>; // Swap the input operands for an easy way to force the creation of a new instruction def : Pat<(two_in GPR32:$i1, GPR32:$i2), (TWO_INS GPR32:$i2, GPR32:$i1)>; -// CHECK: GIM_CheckOpcode, /*MI*/0, MyTarget::G_TWO_IN, +// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_TWO_IN), // CHECK-NEXT: // MIs[0] DstI[out1] // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] DstI[out2] // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] i1 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] i2 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (two_in:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$i1, GPR32:{ *:[i32] }:$i2) => (TWO_INS:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$i2, GPR32:{ *:[i32] }:$i1) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::TWO_INS, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::TWO_INS), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[out1] // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // DstI[out2] // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // i2 diff --git a/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td index 61f79bc04b27..437686a69b5e 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td +++ b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td @@ -31,32 +31,32 @@ def A0w : RegisterClass<"MyTarget", [i16], 16, (add a0wl)>; def A0 : RegisterClass<"MyTarget", [i32], 32, (add a0)>; // CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ANYEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ANYEXT), // CHECK-NEXT: // MIs[0] DstI[dst] // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::A0RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::A0RegClassID), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, // CHECK-NEXT: // (anyext:{ *:[i16] } i8:{ *:[i8] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), A0b:{ *:[i8] }:$src, lo8:{ *:[i32] }), lo16:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src -// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*Imm*/3, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, MyTarget::A0RegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, MyTarget::A0RegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, MyTarget::A0bRegClassID, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*Imm*/3, +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(MyTarget::A0RegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(MyTarget::A0RegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(MyTarget::A0bRegClassID), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, MyTarget::lo16, +// CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(MyTarget::lo16), // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, MyTarget::A0wRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, MyTarget::A0RegClassID, +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(MyTarget::A0wRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(MyTarget::A0RegClassID), def : Pat<(i16 (anyext i8:$src)), (i16 (EXTRACT_SUBREG (i32 (INSERT_SUBREG diff --git a/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td b/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td index 313aac16c235..86a6e1651fca 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td +++ b/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td @@ -3,12 +3,12 @@ include "llvm/Target/Target.td" include "GlobalISelEmitterCommon.td" -// CHECK: constexpr static int64_t MatchTable0[] = { +// CHECK: constexpr static uint8_t MatchTable0[] = { // CHECK-NEXT: GIM_Try, -// CHECK-NEXT: GIM_CheckOpcode{{.*}}TargetOpcode::G_ANYEXT, +// CHECK-NEXT: GIM_CheckOpcode{{.*}}GIMT_Encode2(TargetOpcode::G_ANYEXT), // CHECK-NEXT: GIM_CheckType{{.*}}/*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckType{{.*}}/*Type*/GILLT_s8, -// CHECK-NEXT: GIM_CheckRegBankForClass{{.*}}/*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass{{.*}}/*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (anyext:{{.*}}=>{{.*}}(SELECT_I4: // CHECK: GIR_Done, // CHECK-NEXT: // Label 0: diff --git a/llvm/test/TableGen/GlobalISelEmitter-output-discard.td b/llvm/test/TableGen/GlobalISelEmitter-output-discard.td index 1cfe49dee097..50a9ef8ddf57 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-output-discard.td +++ b/llvm/test/TableGen/GlobalISelEmitter-output-discard.td @@ -7,16 +7,16 @@ include "GlobalISelEmitterCommon.td" def ADD_CO : I<(outs GPR32:$dst, GPR8:$flag), (ins GPR32Op:$src0, GPR32Op:$src1), []>; -// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, +// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (ADD_CO:{ *:[i32] }:{ *:[i8] } GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1) // GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8, -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ADD_CO, +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD_CO), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead, +// GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0, diff --git a/llvm/test/TableGen/GlobalISelEmitter-setcc.td b/llvm/test/TableGen/GlobalISelEmitter-setcc.td index 933489b31bc3..38add7627f50 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-setcc.td +++ b/llvm/test/TableGen/GlobalISelEmitter-setcc.td @@ -6,15 +6,15 @@ include "GlobalISelEmitterCommon.td" // GISEL: GIM_Try // GISEL: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, -// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCMP, -// GISEL: GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ, +// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCMP), +// GISEL: GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), def FCMPOEQ : I<(outs GPR32:$dst), (ins FPR32Op:$src0, FPR32:$src1), [(set GPR32:$dst, (i32 (setcc f32:$src0, f32:$src1, SETOEQ)))]>; // GISEL: GIM_Try // GISEL: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, -// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ICMP, -// GISEL: GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, +// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ICMP), +// GISEL: GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), def ICMPEQ : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32:$src1), [(set GPR32:$dst, (i32 (setcc i32:$src0, i32:$src1, SETEQ)))]>; diff --git a/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td b/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td index 63ad5d5cd03d..6495c10df237 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td +++ b/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td @@ -21,21 +21,21 @@ class PredI<dag OOps, dag IOps, list<dag> Pat> def INST : PredI<(outs GPR32:$dst), (ins GPR32:$src), []>; // CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LOAD), // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, -// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, +// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // CHECK-NEXT: // MIs[0] DstI[dst] // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (INST:{ *:[i32] } GPR32:{ *:[i32] }:$src) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INST, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INST), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src -// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::NoRegister, /*AddRegisterRegFlags*/0, -// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, +// CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), +// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, def : Pat<(i32 (load GPR32:$src)), diff --git a/llvm/test/TableGen/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter.td index 562fdefcd3d6..eab2acd6cb1e 100644 --- a/llvm/test/TableGen/GlobalISelEmitter.td +++ b/llvm/test/TableGen/GlobalISelEmitter.td @@ -79,7 +79,7 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; } // CHECK-NEXT: bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; // CHECK-NEXT: bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; // CHECK-NEXT: bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; -// CHECK-NEXT: const int64_t *getMatchTable() const override; +// CHECK-NEXT: const uint8_t *getMatchTable() const override; // CHECK-NEXT: bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; // CHECK-NEXT: bool testSimplePredicate(unsigned PredicateID) const override; // CHECK-NEXT: void runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override; @@ -224,77 +224,77 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; } // CHECK-NEXT: return true; // CHECK-NEXT: } -// CHECK: const int64_t * +// CHECK: const uint8_t * // CHECK-LABEL: MyTargetInstructionSelector::getMatchTable() const { // CHECK-NEXT: MatchTable0[] = { //===- Test a pattern with multiple ComplexPatterns in multiple instrs ----===// // -// R19O-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]], -// R19O-NEXT: /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]], -// R19O: /*TargetOpcode::G_SELECT*//*Label [[CASE_SELECT_NUM:[0-9]+]]*/ [[CASE_SELECT:[0-9]+]], +// R19O-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2({{[0-9]+}}), GIMT_Encode2({{[0-9]+}}), /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ GIMT_Encode4([[DEFAULT:[0-9]+]]), +// R19O-NEXT: /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_ADD:[0-9]+]]), +// R19O: /*TargetOpcode::G_SELECT*//*Label [[CASE_SELECT_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_SELECT:[0-9]+]]), // R19O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]] // R19O: // Label [[CASE_SELECT_NUM]]: @[[CASE_SELECT]] -// R19O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]], +// R19O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]), // R19O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, // R19O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // R19O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, // R19O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, // -// R19C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// R19C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // -// R19O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, -// R19O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// R19O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R19O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R19N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, -// R19N-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SELECT, +// R19N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SELECT), // R19N-NEXT: // MIs[0] DstI[dst] // R19N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R19N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// R19N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R19N-NEXT: // MIs[0] src1 // R19N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// R19N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// R19N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R19N-NEXT: // MIs[0] complex_rr:src2a:src2b // R19N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, // -// R19N-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex_rr, +// R19N-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_complex_rr), // R19N-NEXT: // MIs[0] Operand 3 // R19N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, // R19C-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] // R19N-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, -// R19C-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SELECT, +// R19C-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SELECT), // R19N-NEXT: // MIs[1] Operand 0 // R19N-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, // R19N-NEXT: // MIs[1] src3 // R19C-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, // R19O-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, // R19O-NEXT: GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, -// R19N-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// R19N-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R19N-NEXT: // MIs[1] src4 // R19N-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, -// R19N-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/1, GICP_gi_complex, +// R19N-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_complex), // R19N-NEXT: // MIs[1] complex:src5a:src5b // R19N-NEXT: GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, -// R19N-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/2, GICP_gi_complex, -// R19O-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// R19N-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_complex), +// R19O-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R19C-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// R19O-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex_rr, -// R19O-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/1, GICP_gi_complex, -// R19O-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/2, GICP_gi_complex, +// R19O-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_complex_rr), +// R19O-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_complex), +// R19O-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_complex), // R19C-NEXT: // (select:{ *:[i32] } GPR32:{ *:[i32] }:$src1, (complex_rr:{ *:[i32] } GPR32:{ *:[i32] }:$src2a, GPR32:{ *:[i32] }:$src2b), (select:{ *:[i32] } GPR32:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src4, (complex:{ *:[i32] } i32imm:{ *:[i32] }:$src5a, i32imm:{ *:[i32] }:$src5b))) => (INSN3:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2b, GPR32:{ *:[i32] }:$src2a, (INSN4:{ *:[i32] } GPR32:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src4, i32imm:{ *:[i32] }:$src5a, i32imm:{ *:[i32] }:$src5b)) // R19C-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// R19C-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::INSN4, -// R19C-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, +// R19C-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::INSN4), +// R19C-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // R19C-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src3 -// R19C-NEXT: GIR_ComplexRenderer, /*InsnID*/1, /*RendererID*/1, -// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/2, /*SubOperand*/0, // src5a -// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/2, /*SubOperand*/1, // src5b +// R19C-NEXT: GIR_ComplexRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), +// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src5a +// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src5b // R19C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// R19C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN3, -// R19C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// R19C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN3), +// R19C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // R19C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 -// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/1, // src2b -// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/0, /*SubOperand*/0, // src2a -// R19C-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2b +// R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2a +// R19C-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // R19C-NEXT: GIR_EraseFromParent, /*InsnID*/0, // R19C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // R19C-NEXT: // GIR_Coverage, 19, @@ -319,51 +319,51 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b), (INSN4 GPR32:$src3, complex:$src4, i32imm:$src5a, i32imm:$src5b))>; -// R21O-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]], -// R21O-NEXT: /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]], -// R21O: /*TargetOpcode::G_SELECT*//*Label [[CASE_SELECT_NUM:[0-9]+]]*/ [[CASE_SELECT:[0-9]+]], +// R21O-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2({{[0-9]+}}), GIMT_Encode2({{[0-9]+}}), /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ GIMT_Encode4([[DEFAULT:[0-9]+]]), +// R21O-NEXT: /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_ADD:[0-9]+]]), +// R21O: /*TargetOpcode::G_SELECT*//*Label [[CASE_SELECT_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_SELECT:[0-9]+]]), // R21O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]] // R21O: // Label [[CASE_SELECT_NUM]]: @[[CASE_SELECT]] -// R21O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]], +// R21O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]), // R21O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, // R21O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // R21O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, // R21O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, // -// R21C-NEXT: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 19 // +// R21C-NEXT: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ GIMT_Encode4([[PREV:[0-9]+]]), // Rule ID 19 // // R21C-NOT: GIR_Done, // R21C: // GIR_Coverage, 19, // R21C-NEXT: GIR_Done, // R21C-NEXT: // Label [[PREV_NUM]]: @[[PREV]] -// R21C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 21 // +// R21C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // Rule ID 21 // // -// R21O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, -// R21O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// R21O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R21O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R21N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, -// R21N-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SELECT, +// R21N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SELECT), // R21N-NEXT: // MIs[0] DstI[dst] // R21N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R21N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// R21N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R21N-NEXT: // MIs[0] src1 // R21N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// R21N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// R21N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R21N-NEXT: // MIs[0] src2 // R21N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, // -// R21O-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_frag, -// R21C-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex, +// R21O-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_frag), +// R21C-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_complex), // R21N-NEXT: // MIs[0] src3 // R21N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, -// R21C-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_complex, -// R21N-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_frag, +// R21C-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_complex), +// R21N-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_frag), // R21C-NEXT: // (select:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2, complex:{ *:[i32] }:$src3)<<P:Predicate_frag>> => (INSN2:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src2) -// R21C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN2, -// R21C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// R21C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN2), +// R21C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // R21C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 -// R21C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/1, -// R21C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, -// R21C-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, +// R21C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), +// R21C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), +// R21C-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0 // R21C-NEXT: GIR_EraseFromParent, /*InsnID*/0, // R21C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // R21C-NEXT: // GIR_Coverage, 21, @@ -379,40 +379,40 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b), //===- Test a pattern with ComplexPattern operands. -----------------------===// // -// R20O-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]], -// R20O-NEXT: /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]], -// R20O: /*TargetOpcode::G_SUB*//*Label [[CASE_SUB_NUM:[0-9]+]]*/ [[CASE_SUB:[0-9]+]], +// R20O-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2({{[0-9]+}}), GIMT_Encode2({{[0-9]+}}), /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ GIMT_Encode4([[DEFAULT:[0-9]+]]), +// R20O-NEXT: /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_ADD:[0-9]+]]), +// R20O: /*TargetOpcode::G_SUB*//*Label [[CASE_SUB_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_SUB:[0-9]+]]), // R20O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]] // R20O: // Label [[CASE_SUB_NUM]]: @[[CASE_SUB]] -// R20O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]], +// R20O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]), // R20O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, // R20O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // R20O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// R20O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// R20O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // -// R20N: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 21 // +// R20N: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ GIMT_Encode4([[PREV:[0-9]+]]), // Rule ID 21 // // R20N: // Label [[PREV_NUM]]: @[[PREV]] // -// R20C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 20 // +// R20C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // Rule ID 20 // // // R20N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// R20N-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB, +// R20N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB), // R20N-NEXT: // MIs[0] DstI[dst] // R20N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R20N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// R20N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R20N-NEXT: // MIs[0] src1 // R20N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // -// R20N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// R20N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R20N-NEXT: // MIs[0] src2 // R20N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// R20O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, -// R20C-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex, +// R20O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R20C-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_complex), // R20C-NEXT: // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2) => (INSN1:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2) -// R20C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN1, -// R20C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// R20C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN1), +// R20C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // R20C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 -// R20C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0, +// R20C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // R20C-NEXT: GIR_EraseFromParent, /*InsnID*/0, // R20C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // R20C-NEXT: // GIR_Coverage, 20, @@ -444,64 +444,64 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3), //===- Test a more complex multi-instruction match. -----------------------===// // -// R00O-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]], -// R00O-NEXT: /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]], -// R00O: /*TargetOpcode::G_SUB*//*Label [[CASE_SUB_NUM:[0-9]+]]*/ [[CASE_SUB:[0-9]+]], +// R00O-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2({{[0-9]+}}), GIMT_Encode2({{[0-9]+}}), /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ GIMT_Encode4([[DEFAULT:[0-9]+]]), +// R00O-NEXT: /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_ADD:[0-9]+]]), +// R00O: /*TargetOpcode::G_SUB*//*Label [[CASE_SUB_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_SUB:[0-9]+]]), // R00O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]] // R00O: // Label [[CASE_SUB_NUM]]: @[[CASE_SUB]] -// R00O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]], +// R00O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]), // R00O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, // R00O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // R00O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // -// R00C: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 20 // +// R00C: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ GIMT_Encode4([[PREV:[0-9]+]]), // Rule ID 20 // // R00C: // Label [[PREV_NUM]]: @[[PREV]] // -// R00C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 0 // -// R00C-NEXT: GIM_CheckFeatures, GIFBS_HasA, +// R00C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // Rule ID 0 // +// R00C-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasA), // R00N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// R00N-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB, +// R00N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB), // R00N-NEXT: // MIs[0] DstI[dst] // R00N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R00N-NEXT: // MIs[0] Operand 1 // R00N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // R00C-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] // R00N-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, -// R00C-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, +// R00C-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB), // R00N-NEXT: // MIs[1] Operand 0 // R00N-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, // R00N-NEXT: // MIs[1] src1 // R00C-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, // R00O-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, -// R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R00N-NEXT: // MIs[1] src2 // R00N-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, -// R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R00N-NEXT: // MIs[0] Operand 2 // R00N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, -// R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R00C-NEXT: GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] // R00N-NEXT: GIM_CheckNumOperands, /*MI*/2, /*Expected*/3, -// R00C-NEXT: GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SUB, +// R00C-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB), // R00N-NEXT: // MIs[2] Operand 0 // R00N-NEXT: GIM_CheckType, /*MI*/2, /*Op*/0, /*Type*/GILLT_s32, // R00N-NEXT: // MIs[2] src3 // R00C-NEXT: GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, // R00O-NEXT: GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, -// R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R00N-NEXT: // MIs[2] src4 // R00N-NEXT: GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, -// R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, -// R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, -// R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R00C-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // R00C-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, // R00C-NEXT: // (sub:{ *:[i32] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4)) => (INSNBOB:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4) -// R00C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSNBOB, -// R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// R00C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSNBOB), +// R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 // R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 // R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src3 @@ -517,7 +517,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3), // R00O-NEXT: GIM_Reject, // R00O: // Label [[DEFAULT_NUM]]: @[[DEFAULT]] // R00O-NEXT: GIM_Reject, -// R00O-NEXT: }; // Size: 9888 bytes +// R00O-NEXT: }; // Size: 1978 bytes def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4), [(set GPR32:$dst, @@ -526,36 +526,36 @@ def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, G //===- Test a simple pattern with an intrinsic. ---------------------------===// // -// R01O-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]], -// R01O-NEXT: /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]], -// R01O: /*TargetOpcode::G_INTRINSIC*//*Label [[CASE_INTRINSIC_NUM:[0-9]+]]*/ [[CASE_INTRINSIC:[0-9]+]], +// R01O-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2({{[0-9]+}}), GIMT_Encode2({{[0-9]+}}), /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ GIMT_Encode4([[DEFAULT:[0-9]+]]), +// R01O-NEXT: /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_ADD:[0-9]+]]), +// R01O: /*TargetOpcode::G_INTRINSIC*//*Label [[CASE_INTRINSIC_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_INTRINSIC:[0-9]+]]), // R01O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]] // R01O: // Label [[CASE_INTRINSIC_NUM]]: @[[CASE_INTRINSIC]] // -// R01N: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 0 // +// R01N: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ GIMT_Encode4([[PREV:[0-9]+]]), // Rule ID 0 // // R01N: // Label [[PREV_NUM]]: @[[PREV]] // -// R01C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 1 // +// R01C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // Rule ID 1 // // R01C-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // -// R01O-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mytarget_nop, +// R01O-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_nop), // R01O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, // R01O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// R01O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// R01O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // -// R01N-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC, +// R01N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC), // R01N-NEXT: // MIs[0] DstI[dst] // R01N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R01N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// R01N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R01N-NEXT: // MIs[0] Operand 1 -// R01N-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mytarget_nop, +// R01N-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_nop), // R01N-NEXT: // MIs[0] src1 // R01N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, // -// R01C-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// R01C-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R01C-NEXT: // (intrinsic_wo_chain:{ *:[i32] } [[ID:[0-9]+]]:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src1) => (MOV:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// R01C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOV, -// R01C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// R01C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOV), +// R01C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // R01C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 // R01C-NEXT: GIR_EraseFromParent, /*InsnID*/0, // R01C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, @@ -572,39 +572,39 @@ def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1), //===- Test a simple pattern with a default operand. ----------------------===// // -// R02O-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/{{[0-9]+}}, {{[0-9]+}}, /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ [[DEFAULT:[0-9]+]], -// R02O-NEXT: /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ [[CASE_ADD:[0-9]+]], -// R02O: /*TargetOpcode::G_XOR*//*Label [[CASE_XOR_NUM:[0-9]+]]*/ [[CASE_XOR:[0-9]+]], +// R02O-NEXT: GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2({{[0-9]+}}), GIMT_Encode2({{[0-9]+}}), /*)*//*default:*//*Label [[DEFAULT_NUM:[0-9]+]]*/ GIMT_Encode4([[DEFAULT:[0-9]+]]), +// R02O-NEXT: /*TargetOpcode::G_ADD*//*Label [[CASE_ADD_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_ADD:[0-9]+]]), +// R02O: /*TargetOpcode::G_XOR*//*Label [[CASE_XOR_NUM:[0-9]+]]*/ GIMT_Encode4([[CASE_XOR:[0-9]+]]), // R02O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]] // R02O: // Label [[CASE_XOR_NUM]]: @[[CASE_XOR]] -// R02O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ [[GROUP:[0-9]+]], +// R02O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]), // R02O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, // R02O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // R02O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// R02O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, -// R02O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// R02O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R02O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // -// R02N: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ [[PREV:[0-9]+]], // Rule ID 1 // +// R02N: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ GIMT_Encode4([[PREV:[0-9]+]]), // Rule ID 1 // // R02N: // Label [[PREV_NUM]]: @[[PREV]] // -// R02C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], // Rule ID 2 // +// R02C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // Rule ID 2 // // // R02N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// R02N-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR, +// R02N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR), // R02N-NEXT: // MIs[0] DstI[dst] // R02N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R02N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// R02N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R02N-NEXT: // MIs[0] src1 // R02N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// R02N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// R02N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R02N-NEXT: // MIs[0] Operand 2 // R02N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, // -// R02C-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -2 +// R02C-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-2) // R02C-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -2:{ *:[i32] }) => (XORI:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// R02C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORI, +// R02C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::XORI), // R02C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// R02C-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/-1, +// R02C-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), // R02C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 // R02C-NEXT: GIR_EraseFromParent, /*InsnID*/0, // R02C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, @@ -621,22 +621,22 @@ def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1), //===- Test a simple pattern with a default register operand. -------------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -3 +// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-3) // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -3:{ *:[i32] }) => (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XOR, -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::R0, +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::XOR), +// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 // NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, @@ -650,23 +650,23 @@ def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1), //===- Test a simple pattern with a multiple default operands. ------------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -4 +// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-4) // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -4:{ *:[i32] }) => (XORlike:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORlike, +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::XORlike), // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// NOOPT-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/-1, -// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::R0, +// NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), +// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 // NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, @@ -680,24 +680,24 @@ def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1), //===- Test a simple pattern with multiple operands with defaults. --------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -5, +// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-5), // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -5:{ *:[i32] }) => (XORManyDefaults:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::XORManyDefaults, +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::XORManyDefaults), // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// NOOPT-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/-1, -// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::R0, -// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::R0, +// NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), +// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), +// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 // NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, @@ -714,22 +714,22 @@ def XORManyDefaults : I<(outs GPR32:$dst), (ins m1Z:$src3, Z:$src2, GPR32:$src1) // This must precede the 3-register variants because constant immediates have // priority over register banks. // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_XOR, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Wm // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, +// NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORN:{ *:[i32] } R0:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ORN, -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, MyTarget::R0, +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ORN), +// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Wm // NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, @@ -742,33 +742,33 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>; //===- Test a nested instruction match. -----------------------------------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], -// NOOPT-NEXT: GIM_CheckFeatures, GIFBS_HasA, +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), +// NOOPT-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasA), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD), // NOOPT-NEXT: // MIs[1] Operand 0 // NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, // NOOPT-NEXT: // MIs[1] src1 // NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[1] src2 // NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src3 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // NOOPT-NEXT: // (mul:{ *:[i32] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src3) => (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MULADD, -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MULADD), +// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3 @@ -780,33 +780,33 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>; // We also get a second rule by commutativity. // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], -// NOOPT-NEXT: GIM_CheckFeatures, GIFBS_HasA, +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), +// NOOPT-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasA), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src3 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD), // NOOPT-NEXT: // MIs[1] Operand 0 // NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, // NOOPT-NEXT: // MIs[1] src1 // NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[1] src2 // NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // NOOPT-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src3, (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)) => (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MULADD, -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MULADD), +// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3 @@ -823,17 +823,17 @@ def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3), //===- Test a simple pattern with just a specific leaf immediate. ---------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 -// NOOPT-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 1, +// NOOPT-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(1), // NOOPT-NEXT: // 1:{ *:[i32] } => (MOV1:{ *:[i32] }) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOV1, -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOV1), +// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // NOOPT-NEXT: // GIR_Coverage, 7, @@ -844,18 +844,18 @@ def MOV1 : I<(outs GPR32:$dst), (ins), [(set GPR32:$dst, 1)]>; //===- Test a simple pattern with a leaf immediate and a predicate. -------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT, -// NOOPT-NEXT: GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_I64_Predicate_simm8, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT), +// NOOPT-NEXT: GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (imm:{ *:[i32] })<<P:Predicate_simm8>>:$imm => (MOVimm8:{ *:[i32] } (imm:{ *:[i32] }):$imm) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm8, -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm8), +// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm // NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, @@ -868,18 +868,18 @@ def MOVimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm8:$i //===- Same again but use an IntImmLeaf. ----------------------------------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT, -// NOOPT-NEXT: GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_APInt_Predicate_simm9, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT), +// NOOPT-NEXT: GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_simm9), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (imm:{ *:[i32] })<<P:Predicate_simm9>>:$imm => (MOVimm9:{ *:[i32] } (imm:{ *:[i32] }):$imm) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm9, -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm9), +// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm // NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, @@ -892,19 +892,19 @@ def MOVimm9 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm9:$i //===- Test a pattern with a custom renderer. -----------------------------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT, -// NOOPT-NEXT: GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_I64_Predicate_cimm8, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT), +// NOOPT-NEXT: GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cimm8), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (imm:{ *:[i32] })<<P:Predicate_cimm8>><<X:cimm8_xform>>:$imm => (MOVcimm8:{ *:[i32] } (cimm8_xform:{ *:[i32] } (imm:{ *:[i32] }):$imm)) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVcimm8, -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// NOOPT-NEXT: GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderImm, // imm +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVcimm8), +// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderImm), // imm // NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // NOOPT-NEXT: // GIR_Coverage, 10, @@ -915,18 +915,18 @@ def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$ //===- Test a simple pattern with a FP immediate and a predicate. ---------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCONSTANT, -// NOOPT-NEXT: GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_APFloat_Predicate_fpimmz, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCONSTANT), +// NOOPT-NEXT: GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimmz), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::FPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (fpimm:{ *:[f32] })<<P:Predicate_fpimmz>>:$imm => (MOVfpimmz:{ *:[f32] } (fpimm:{ *:[f32] }):$imm) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVfpimmz, -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVfpimmz), +// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CopyFConstantAsFPImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm // NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, @@ -936,19 +936,19 @@ def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$ //===- Test a simple pattern with inferred pointer operands. ---------------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LOAD), // NOOPT-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, -// NOOPT-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, +// NOOPT-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 // NOOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD, +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // NOOPT-NEXT: // GIR_Coverage, 11, // NOOPT-NEXT: GIR_Done, @@ -959,19 +959,19 @@ def LOAD : I<(outs GPR32:$dst), (ins GPR32:$src1), //===- Test a simple pattern with explicit pointer operands. ---------------===// -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LOAD), // NOOPT-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, -// NOOPT-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, +// NOOPT-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_p0s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src // NOOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD, +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // NOOPT-NEXT: // GIR_Coverage, 23, // NOOPT-NEXT: GIR_Done, @@ -982,19 +982,19 @@ def : Pat<(load GPR32:$src), //===- Test a simple pattern with a sextload -------------------------------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SEXTLOAD, -// NOOPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, -// NOOPT-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SEXTLOAD), +// NOOPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), +// NOOPT-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 // NOOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (SEXTLOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::SEXTLOAD, +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SEXTLOAD), // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // NOOPT-NEXT: // GIR_Coverage, 12, // NOOPT-NEXT: GIR_Done, @@ -1005,20 +1005,20 @@ def SEXTLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1), //===- Test a simple pattern with regclass operands. ----------------------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID) // NOOPT-NEXT: // MIs[0] src2 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ADD, +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD), // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // NOOPT-NEXT: // GIR_Coverage, 13, // NOOPT-NEXT: GIR_Done, @@ -1029,20 +1029,20 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), //===- Test a pattern with a tied operand in the matcher ------------------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src{{$}} // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src{{$}} // NOOPT-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, // NOOPT-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src) => (DOUBLE:{ *:[i32] } GPR32:{ *:[i32] }:$src) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::DOUBLE, -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::DOUBLE), +// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src // NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, @@ -1060,18 +1060,18 @@ def DOUBLE : I<(outs GPR32:$dst), (ins GPR32:$src), [(set GPR32:$dst, (add GPR32 // - one of operands in the pattern itself // does not introduce unexpected GIM_CheckIsSameOperand predicate. -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), // NOOPT-NEXT: // MIs[0] DstI[samename] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] samename // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // NOOPT-NEXT: // MIs[0] othername // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$samename, i32:{ *:[i32] }:$othername) => (InsnWithSpeciallyNamedDef:{ *:[i32] } i32:{ *:[i32] }:$samename, i32:{ *:[i32] }:$othername) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::InsnWithSpeciallyNamedDef, +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InsnWithSpeciallyNamedDef), // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // NOOPT-NEXT: // GIR_Coverage, 24, // NOOPT-NEXT: GIR_Done, @@ -1083,18 +1083,18 @@ def : Pat<(add i32:$samename, i32:$othername), //===- Test a simple pattern with ValueType operands. ----------------------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // NOOPT-NEXT: // MIs[0] src2 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ADD, +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD), // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // NOOPT-NEXT: // GIR_Coverage, 25, // NOOPT-NEXT: GIR_Done, @@ -1105,22 +1105,22 @@ def : Pat<(add i32:$src1, i32:$src2), //===- Test another simple pattern with regclass operands. ----------------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], -// NOOPT-NEXT: GIM_CheckFeatures, GIFBS_HasA_HasB_HasC, +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), +// NOOPT-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasA_HasB_HasC), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src2 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (MUL:{ *:[i32] } GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MUL, -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MUL), +// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 // NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, @@ -1136,18 +1136,18 @@ def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1), //===- Test a COPY_TO_REGCLASS --------------------------------------------===// // // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_BITCAST, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_BITCAST), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::FPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // NOOPT-NEXT: // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$src1) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$src1, GPR32:{ *:[i32] }) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, -// NOOPT-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// NOOPT-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // GIR_Coverage, 26, // NOOPT-NEXT: GIR_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] @@ -1157,17 +1157,17 @@ def : Pat<(i32 (bitconvert FPR32:$src1)), //===- Test a simple pattern with just a leaf immediate. ------------------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT), // NOOPT-NEXT: // MIs[0] DstI[dst] // NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (imm:{ *:[i32] }):$imm => (MOVimm:{ *:[i32] } (imm:{ *:[i32] }):$imm) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm, -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm), +// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm // NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, @@ -1182,13 +1182,13 @@ def MOVfpimmz : I<(outs FPR32:$dst), (ins f32imm:$imm), [(set FPR32:$dst, fpimmz //===- Test a pattern with an MBB operand. --------------------------------===// // -// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], +// NOOPT-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, -// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_BR, +// NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_BR), // NOOPT-NEXT: // MIs[0] target // NOOPT-NEXT: GIM_CheckIsMBB, /*MI*/0, /*Op*/0, // NOOPT-NEXT: // (br (bb:{ *:[Other] }):$target) => (BR (bb:{ *:[Other] }):$target) -// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::BR, +// NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::BR), // NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // NOOPT-NEXT: // GIR_Coverage, 18, // NOOPT-NEXT: GIR_Done, @@ -1198,5 +1198,5 @@ def BR : I<(outs), (ins unknown:$target), [(br bb:$target)]>; // NOOPT-NEXT: GIM_Reject, -// NOOPT-NEXT: }; // Size: 11408 bytes +// NOOPT-NEXT: }; // Size: 1680 bytes // NOOPT-NEXT: return MatchTable0; diff --git a/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td b/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td index 5a75cb129eec..ed43ff2f14fa 100644 --- a/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td +++ b/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td @@ -73,65 +73,65 @@ def and_or_pat : PatFrag< let PredicateCodeUsesOperands = 1; } -// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ 99, // Rule ID 7 // -// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_AND, -// CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: // MIs[0] src2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:3:z -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: // MIs[0] Operand 2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] -// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, -// CHECK-NEXT: // MIs[1] Operand 0 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: // MIs[1] src0 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: // MIs[1] src1 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_and_or_pat, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: // (and:{ *:[i32] } DOP:{ *:[i32] }:$src2:$pred:3:z, (or:{ *:[i32] } DOP:{ *:[i32] }:$src0:$pred:3:x, DOP:{ *:[i32] }:$src1:$pred:3:y))<<P:3:Predicate_and_or_pat>> => (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::AND_OR, +// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(110), // Rule ID 7 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: // MIs[0] src2 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:3:z +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: // MIs[0] Operand 2 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), +// CHECK-NEXT: // MIs[1] Operand 0 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: // MIs[1] src0 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: // MIs[1] src1 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_and_or_pat), +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: // (and:{ *:[i32] } DOP:{ *:[i32] }:$src2:$pred:3:z, (or:{ *:[i32] } DOP:{ *:[i32] }:$src0:$pred:3:x, DOP:{ *:[i32] }:$src1:$pred:3:y))<<P:3:Predicate_and_or_pat>> => (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::AND_OR), -// CHECK: GIM_Try, /*On fail goto*//*Label 1*/ 198, // Rule ID 3 // -// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_AND, -// CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: // MIs[0] Operand 1 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, -// CHECK-NEXT: // MIs[1] Operand 0 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: // MIs[1] src0 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: // MIs[1] src1 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: // MIs[0] src2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:3:z -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_and_or_pat, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: // (and:{ *:[i32] } (or:{ *:[i32] } DOP:{ *:[i32] }:$src0:$pred:3:x, DOP:{ *:[i32] }:$src1:$pred:3:y), DOP:{ *:[i32] }:$src2:$pred:3:z)<<P:3:Predicate_and_or_pat>> => (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::AND_OR, +// CHECK: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(220), // Rule ID 3 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: // MIs[0] Operand 1 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), +// CHECK-NEXT: // MIs[1] Operand 0 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: // MIs[1] src0 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: // MIs[1] src1 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: // MIs[0] src2 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:3:z +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_and_or_pat), +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: // (and:{ *:[i32] } (or:{ *:[i32] } DOP:{ *:[i32] }:$src0:$pred:3:x, DOP:{ *:[i32] }:$src1:$pred:3:y), DOP:{ *:[i32] }:$src2:$pred:3:z)<<P:3:Predicate_and_or_pat>> => (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::AND_OR), // Test commutative, standalone pattern. def : Pat< @@ -148,63 +148,63 @@ def mul_pat : PatFrag< let PredicateCodeUsesOperands = 1; } -// CHECK: GIM_Try, /*On fail goto*//*Label 2*/ 293, // Rule ID 4 // -// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL, -// CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: // MIs[0] Operand 1 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:4:x -// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, -// CHECK-NEXT: // MIs[1] Operand 0 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: // MIs[1] src0 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: // MIs[1] src1 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: // MIs[0] src2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:4:y -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_mul_pat, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: // (mul:{ *:[i32] } (or:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1):$pred:4:x, DOP:{ *:[i32] }:$src2:$pred:4:y)<<P:4:Predicate_mul_pat>> => (MUL_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MUL_OR, +// CHECK: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(326), // Rule ID 4 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: // MIs[0] Operand 1 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:4:x +// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), +// CHECK-NEXT: // MIs[1] Operand 0 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: // MIs[1] src0 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: // MIs[1] src1 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: // MIs[0] src2 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:4:y +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_mul_pat), +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: // (mul:{ *:[i32] } (or:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1):$pred:4:x, DOP:{ *:[i32] }:$src2:$pred:4:y)<<P:4:Predicate_mul_pat>> => (MUL_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MUL_OR), -// CHECK: GIM_Try, /*On fail goto*//*Label 3*/ 388, // Rule ID 8 // -// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL, -// CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: // MIs[0] src2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:4:y -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: // MIs[0] Operand 2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:4:x -// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] -// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR, -// CHECK-NEXT: // MIs[1] Operand 0 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: // MIs[1] src0 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: // MIs[1] src1 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_mul_pat, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: // (mul:{ *:[i32] } DOP:{ *:[i32] }:$src2:$pred:4:y, (or:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1):$pred:4:x)<<P:4:Predicate_mul_pat>> => (MUL_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MUL_OR, +// CHECK: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(432), // Rule ID 8 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: // MIs[0] src2 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:4:y +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: // MIs[0] Operand 2 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:4:x +// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), +// CHECK-NEXT: // MIs[1] Operand 0 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: // MIs[1] src0 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: // MIs[1] src1 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_mul_pat), +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: // (mul:{ *:[i32] } DOP:{ *:[i32] }:$src2:$pred:4:y, (or:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1):$pred:4:x)<<P:4:Predicate_mul_pat>> => (MUL_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MUL_OR), // Test commutative patterns where named operands in the source pattern are not // directly bound to PatFrag's operands. @@ -223,32 +223,32 @@ def sub3_pat : PatFrag< let PredicateCodeUsesOperands = 1; } -// CHECK: GIM_Try, /*On fail goto*//*Label 4*/ 475, // Rule ID 0 // -// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SUB, -// CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID, -// CHECK-NEXT: // MIs[0] Operand 1 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, -// CHECK-NEXT: // MIs[1] Operand 0 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: // MIs[1] src0 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x -// CHECK-NEXT: // MIs[1] src1 -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y -// CHECK-NEXT: // MIs[0] src2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:1:z -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_sub3_pat, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: // (sub:{ *:[i32] } (sub:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, i32:{ *:[i32] }:$src1:$pred:1:y), i32:{ *:[i32] }:$src2:$pred:1:z)<<P:1:Predicate_sub3_pat>> => (SUB3:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SUB3, +// CHECK: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(527), // Rule ID 0 // +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: // MIs[0] Operand 1 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB), +// CHECK-NEXT: // MIs[1] Operand 0 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: // MIs[1] src0 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x +// CHECK-NEXT: // MIs[1] src1 +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y +// CHECK-NEXT: // MIs[0] src2 +// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:1:z +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_sub3_pat), +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: // (sub:{ *:[i32] } (sub:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, i32:{ *:[i32] }:$src1:$pred:1:y), i32:{ *:[i32] }:$src2:$pred:1:z)<<P:1:Predicate_sub3_pat>> => (SUB3:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SUB3) // Test a non-commutative pattern. def SUB3 : I<(outs DRegs:$dst), @@ -269,16 +269,16 @@ def patfrags_test_pat : PatFrags< let PredicateCodeUsesOperands = 1; } -// CHECK: GIM_Try, /*On fail goto*//*Label 5*/ 562, // Rule ID 1 // +// CHECK: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(622), // Rule ID 1 // // CHECK: // (xor:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y), i32:{ *:[i32] }:$src2:$pred:2:z)<<P:2:Predicate_patfrags_test_pat>> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// CHECK: GIM_Try, /*On fail goto*//*Label 6*/ 649, // Rule ID 2 // +// CHECK: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(717), // Rule ID 2 // // CHECK: // (xor:{ *:[i32] } (sub:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y), i32:{ *:[i32] }:$src2:$pred:2:z)<<P:2:Predicate_patfrags_test_pat>> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// CHECK: GIM_Try, /*On fail goto*//*Label 7*/ 736, // Rule ID 5 // +// CHECK: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(812), // Rule ID 5 // // CHECK: // (xor:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:2:z, (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y))<<P:2:Predicate_patfrags_test_pat>> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// CHECK: GIM_Try, /*On fail goto*//*Label 8*/ 823, // Rule ID 6 // +// CHECK: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(907), // Rule ID 6 // // CHECK: // (xor:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:2:z, (sub:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y))<<P:2:Predicate_patfrags_test_pat>> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) diff --git a/llvm/test/TableGen/GlobalISelEmitterFlags.td b/llvm/test/TableGen/GlobalISelEmitterFlags.td index 1c53e1a45c26..2025a2c1048e 100644 --- a/llvm/test/TableGen/GlobalISelEmitterFlags.td +++ b/llvm/test/TableGen/GlobalISelEmitterFlags.td @@ -36,25 +36,25 @@ def : Pat< // CHECK: GIM_Try // CHECK: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR +// CHECK: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR) // CHECK: GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] -// CHECK: GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD +// CHECK: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD) // CHECK: GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1 // CHECK: GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1 // CHECK: // (srl:{ *:[i32] } (srl:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src0) // CHECK: GIR_Done // CHECK: GIM_Try // CHECK: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL +// CHECK: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL) // CHECK: GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] -// CHECK: GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_MUL +// CHECK: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL) // CHECK: GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1 // CHECK: GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1 // CHECK: // (srl:{ *:[i32] } (shl:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src0) // CHECK: GIR_Done // CHECK: GIM_Try // CHECK: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL +// CHECK: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL) // CHECK: GIM_CheckIsSameOperandIgnoreCopies, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1 // CHECK: // (sub:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src1) -// CHECK: GIR_Done
\ No newline at end of file +// CHECK: GIR_Done diff --git a/llvm/test/TableGen/GlobalISelEmitterHwModes.td b/llvm/test/TableGen/GlobalISelEmitterHwModes.td index 04f33648313b..0c826fb50beb 100644 --- a/llvm/test/TableGen/GlobalISelEmitterHwModes.td +++ b/llvm/test/TableGen/GlobalISelEmitterHwModes.td @@ -52,7 +52,7 @@ class I<dag OOps, dag IOps, list<dag> Pat> // CHECK-NEXT: bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; // CHECK-NEXT: bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; // CHECK-NEXT: bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; -// CHECK-NEXT: const int64_t *getMatchTable() const override; +// CHECK-NEXT: const uint8_t *getMatchTable() const override; // CHECK-NEXT: bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; // CHECK-NEXT: bool testSimplePredicate(unsigned PredicateID) const override; // CHECK-NEXT: void runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override; @@ -121,44 +121,44 @@ class I<dag OOps, dag IOps, list<dag> Pat> // CHECK-NEXT: return true; // CHECK-NEXT: } -// CHECK: const int64_t * +// CHECK: const uint8_t * // CHECK-LABEL: MyTargetInstructionSelector::getMatchTable() const { // CHECK-NEXT: MatchTable0[] = { //===- Test a simple pattern with inferred pointer operands. ---------------===// -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], -// CHECK-NEXT: GIM_CheckFeatures, GIFBS_HwMode0, +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), +// CHECK-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LOAD), // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, -// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, +// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // CHECK-NEXT: // MIs[0] DstI[dst] // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPRRegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // MIs[0] src1 // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPRRegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // (ld:{ *:[i64] } GPR:{ *:[i64] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i64] } GPR:{ *:[i64] }:$src1) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD, +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // CHECK-NEXT: // GIR_Coverage, 0, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], -// CHECK-NEXT: GIM_CheckFeatures, GIFBS_HwMode1, +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), +// CHECK-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LOAD), // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, -// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, +// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // CHECK-NEXT: // MIs[0] DstI[dst] // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPRRegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // MIs[0] src1 // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPRRegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // (ld:{ *:[i32] } GPR:{ *:[i32] }:$src1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i32] } GPR:{ *:[i32] }:$src1) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD, +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // CHECK-NEXT: // GIR_Coverage, 1, // CHECK-NEXT: GIR_Done, @@ -169,38 +169,38 @@ def LOAD : I<(outs GPR:$dst), (ins GPR:$src1), //===- Test a simple pattern with explicit pointer operands. ---------------===// -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], -// CHECK-NEXT: GIM_CheckFeatures, GIFBS_HwMode0, +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), +// CHECK-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode0), // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LOAD), // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, -// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, +// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // CHECK-NEXT: // MIs[0] DstI[dst] // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_p0s64, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPRRegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPRRegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // (ld:{ *:[i64] } GPR:{ *:[i64] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i64] } GPR:{ *:[i64] }:$src) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD, +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // CHECK-NEXT: // GIR_Coverage, 2, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]], -// CHECK-NEXT: GIM_CheckFeatures, GIFBS_HwMode1, +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), +// CHECK-NEXT: GIM_CheckFeatures, GIMT_Encode2(GIFBS_HwMode1), // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LOAD), // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, -// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, +// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // CHECK-NEXT: // MIs[0] DstI[dst] // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_p0s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPRRegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPRRegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // (ld:{ *:[i32] } GPR:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD:{ *:[i32] } GPR:{ *:[i32] }:$src) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD, +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // CHECK-NEXT: // GIR_Coverage, 3, // CHECK-NEXT: GIR_Done, diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td index 6a369b6a7b88..08feeccc3569 100644 --- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td +++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td @@ -8,26 +8,26 @@ include "GlobalISelEmitterCommon.td" def LOAD8 : I<(outs GPR8:$dst), (ins GPR8:$src), []>; def LOAD32 : I<(outs GPR8:$dst), (ins GPR32:$src), []>; // CHECK: Label 1: @{{[0-9]+}} -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L1_ID:[0-9]+]]*/ [[L1_AT:[0-9]+]], +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L1_ID:[0-9]+]]*/ GIMT_Encode4([[L1_AT:[0-9]+]]), // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, -// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR8RegClassID, -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L2_ID:[0-9]+]]*/ [[L2_AT:[0-9]+]], +// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR8RegClassID), +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L2_ID:[0-9]+]]*/ GIMT_Encode4([[L2_AT:[0-9]+]]), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/8, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR8RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR8RegClassID), // CHECK-NEXT: // (ld:{ *:[i8] } GPR8:{ *:[i8] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD8:{ *:[i8] } GPR8:{ *:[i8] }:$src) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD8, +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD8), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // CHECK-NEXT: // GIR_Coverage, 0, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label [[L2_ID]]: @[[L2_AT]] -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L3_ID:[0-9]+]]*/ [[L3_AT:[0-9]+]], +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L3_ID:[0-9]+]]*/ GIMT_Encode4([[L3_AT:[0-9]+]]), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (ld:{ *:[i8] } GPR32:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD32:{ *:[i8] } GPR32:{ *:[i32] }:$src) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD32, +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD32), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // CHECK-NEXT: // GIR_Coverage, 1, // CHECK-NEXT: GIR_Done, @@ -46,33 +46,33 @@ def GPR16 : RegisterClass<"MyTarget", [i16], 16, (add S0)>; def LOAD16 : I<(outs GPR16:$dst), (ins GPR16:$src), []>; def LOAD16Imm : I<(outs GPR16:$dst), (ins GPR16:$src), []>; // CHECK: // Label 2: @{{[0-9]+}} -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L1_ID:[0-9]+]]*/ [[L1_AT:[0-9]+]], +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L1_ID:[0-9]+]]*/ GIMT_Encode4([[L1_AT:[0-9]+]]), // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, -// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR16RegClassID, +// CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR16RegClassID), // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/16, -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L2_ID:[0-9]+]]*/ [[L2_AT:[0-9]+]], +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L2_ID:[0-9]+]]*/ GIMT_Encode4([[L2_AT:[0-9]+]]), // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD), // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR16RegClassID, -// CHECK-NEXT: GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 10, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR16RegClassID), +// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 10, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: // (ld:{ *:[i16] } (add:{ *:[i16] } GPR16:{ *:[i16] }:$src, 10:{ *:[i16] }))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD16Imm:{ *:[i16] } GPR16:{ *:[i16] }:$src) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::LOAD16Imm, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16Imm), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src -// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList, +// CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // CHECK-NEXT: // GIR_Coverage, 3, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label [[L2_ID]]: @[[L2_AT]] -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L3_ID:[0-9]+]]*/ [[L3_AT:[0-9]+]], -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR16RegClassID, +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L3_ID:[0-9]+]]*/ GIMT_Encode4([[L3_AT:[0-9]+]]), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR16RegClassID), // CHECK-NEXT: // (ld:{ *:[i16] } GPR16:{ *:[i16] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LOAD16:{ *:[i16] } GPR16:{ *:[i16] }:$src) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::LOAD16, +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // CHECK-NEXT: // GIR_Coverage, 2, // CHECK-NEXT: GIR_Done, diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td index 2423c3bd32d5..f58b82bb86b1 100644 --- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td +++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td @@ -6,33 +6,33 @@ include "GlobalISelEmitterCommon.td" def InstTwoOperands : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>; def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>; -// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ 219, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SELECT, +// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(255), +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SELECT), // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ 189, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(217), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2, -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ 108, // Rule ID 1 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(126), // Rule ID 1 // // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP), // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, // CHECK-NEXT: // MIs[1] Operand 1 -// CHECK-NEXT: GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, -// CHECK-NEXT: GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, +// CHECK-NEXT: GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0, // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SUB, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB), // CHECK-NEXT: GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, // CHECK-NEXT: // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::InstThreeOperands, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 @@ -41,26 +41,26 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32: // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // CHECK-NEXT: // GIR_Coverage, 1, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 2: @108 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ 188, // Rule ID 2 // +// CHECK-NEXT: // Label 2: @126 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(216), // Rule ID 2 // // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP), // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, // CHECK-NEXT: // MIs[1] Operand 1 -// CHECK-NEXT: GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, -// CHECK-NEXT: GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0, +// CHECK-NEXT: GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0, // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SUB, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB), // CHECK-NEXT: GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, // CHECK-NEXT: // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::InstThreeOperands, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 @@ -69,25 +69,24 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32: // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // CHECK-NEXT: // GIR_Coverage, 2, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 3: @188 +// CHECK-NEXT: // Label 3: @216 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 1: @189 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ 218, // Rule ID 0 // +// CHECK-NEXT: // Label 1: @217 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(254), // Rule ID 0 // // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::InstThreeOperands, +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // CHECK-NEXT: // GIR_Coverage, 0, // CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 4: @218 +// CHECK-NEXT: // Label 4: @254 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 0: @219 +// CHECK-NEXT: // Label 0: @255 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: } def : Pat<(i32 (select GPR32:$cond, GPR32:$src1, GPR32:$src2)), (InstThreeOperands GPR32:$cond, GPR32:$src1, GPR32:$src2)>; diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td index 167ab83b862b..00ece5f4ca79 100644 --- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td +++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td @@ -9,7 +9,7 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32: // Make sure the GIM_CheckIsSameOperand check is not hoisted into the common header group // CHECK: GIM_Try, /*On fail goto*//*Label 1*/ -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NOT: GIM_CheckIsSameOperand // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ // CHECK: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/1, diff --git a/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td b/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td index 0cc3485342cc..64723a0bbd4b 100644 --- a/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td +++ b/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td @@ -11,15 +11,15 @@ let TargetPrefix = "mytarget" in { // Ensure that llvm_anyptr_ty on an intrinsic results in a // GIM_CheckPointerToAny rather than a GIM_CheckType. // -// CHECK: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mytarget_anyptr, +// CHECK: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_anyptr), // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, -// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_frag_anyptr, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_frag_anyptr), // CHECK-NEXT: // (intrinsic_w_chain:{ *:[i32] } {{[0-9]+}}:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src)<<P:Predicate_frag_anyptr>> => (ANYLOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ANYLOAD, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ANYLOAD), let hasSideEffects = 1 in { def ANYLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1), [(set GPR32:$dst, (load GPR32:$src1))]>; diff --git a/llvm/test/TableGen/GlobalISelEmitterRegSequence.td b/llvm/test/TableGen/GlobalISelEmitterRegSequence.td index 34783e688399..1f2174e7e4a9 100644 --- a/llvm/test/TableGen/GlobalISelEmitterRegSequence.td +++ b/llvm/test/TableGen/GlobalISelEmitterRegSequence.td @@ -31,50 +31,50 @@ def SOME_INSN : I<(outs DRegs:$dst), (ins DOP:$src), []>; def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>; // CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SEXT, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SEXT), // CHECK-NEXT: // MIs[0] DstI[dst] // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Test::DRegsRegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Test::SRegsRegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: // (sext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (REG_SEQUENCE:{ *:[i32] } DRegs:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub1:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/MyTarget::SUBSOME_INSN, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::SUBSOME_INSN, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::REG_SEQUENCE, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, -// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, -// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Test::DRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Test::SRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, Test::SRegsRegClassID, +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::SRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(Test::SRegsRegClassID), def : Pat<(i32 (sext SOP:$src)), (REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0, (SUBSOME_INSN SOP:$src), sub1)>; -// CHECK: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ZEXT, -// CHECK: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::REG_SEQUENCE, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, -// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, -// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Test::DRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Test::SRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, Test::SRegsRegClassID, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SOME_INSN, +// CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ZEXT), +// CHECK: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::SRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(Test::SRegsRegClassID), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN), // Make sure operands are constrained when REG_SEQUENCE isn't the root instruction. def : Pat<(i32 (zext SOP:$src)), (SOME_INSN (REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0, diff --git a/llvm/test/TableGen/GlobalISelEmitterSubreg.td b/llvm/test/TableGen/GlobalISelEmitterSubreg.td index af3db1590368..b601727c9965 100644 --- a/llvm/test/TableGen/GlobalISelEmitterSubreg.td +++ b/llvm/test/TableGen/GlobalISelEmitterSubreg.td @@ -61,20 +61,20 @@ def : Pat<(sub (complex DOP:$src1, DOP:$src2), 77), // CHECK-LABEL: // (sub:{ *:[i32] } (complex:{ *:[i32] } DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2), 77:{ *:[i32] }) => (SOME_INSN2:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } DOP:{ *:[i32] }:$src1, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } DOP:{ *:[i32] }:$src2, sub1:{ *:[i32] })) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, -// CHECK-NEXT: GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/2, /*RendererID*/0, /*SubOperand*/1, /*SubRegIdx*/2, // src2 -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, Test::SRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, Test::DRegsRegClassID, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, -// CHECK-NEXT: GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/0, /*SubOperand*/0, /*SubRegIdx*/1, // src1 -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Test::SRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Test::DRegsRegClassID, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SOME_INSN2, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), +// CHECK-NEXT: GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, /*SubRegIdx*/GIMT_Encode2(2), // src2 +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), +// CHECK-NEXT: GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(1), // src1 +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN2), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, @@ -83,18 +83,18 @@ def : Pat<(sub (complex DOP:$src1, DOP:$src2), 77), def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SOP:$src, sub0)>; // CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), SOP:{ *:[i16] }:$src, sub0:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src -// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/1, +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Test::DRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Test::DRegsRegClassID -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Test::SRegsRegClassID, +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), // Test that we can import INSERT_SUBREG when it is a subinstruction of another @@ -103,20 +103,20 @@ def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF) // CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (SOME_INSN:{ *:[i32] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), SOP:{ *:[i16] }:$src, sub0:{ *:[i32] })) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src -// CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*Imm*/1, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Test::DRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Test::DRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, Test::SRegsRegClassID, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SOME_INSN, +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*Imm*/1, +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, @@ -126,10 +126,10 @@ def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF) // not a D register. def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (COPY_TO_REGCLASS SOP:$src, ERegs)), SOP:$src, sub0)>; // CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (INSERT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SOP:{ *:[i16] }:$src, ERegs:{ *:[i32] }), SOP:{ *:[i16] }:$src, sub0:{ *:[i32] }) -// CHECK: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, -// CHECK-DAG: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Test::ERegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Test::ERegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Test::SRegsRegClassID, +// CHECK: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), +// CHECK-DAG: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::ERegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::ERegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), // Test that we can import INSERT_SUBREG when its subregister source is defined // by a subinstruction. @@ -137,22 +137,22 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (SUBSOME // CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/MyTarget::SUBSOME_INSN, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, -// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/1, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Test::DRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Test::DRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Test::SRegsRegClassID, +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), // Test an EXTRACT_SUBREG that is a sub instruction. The individual // operands should be constrained to specific register classes, and @@ -161,54 +161,54 @@ def : Pat<(i16 (trunc (not DOP:$src))), (SUBSOME_INSN (EXTRACT_SUBREG DOP:$src, sub0))>; // CHECK-LABEL: // (trunc:{ *:[i16] } (xor:{ *:[i32] } DOP:{ *:[i32] }:$src, -1:{ *:[i32] })) => (SUBSOME_INSN:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i16] } DOP:{ *:[i32] }:$src, sub0:{ *:[i32] })) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, -// CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // src -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Test::SRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Test::DRegsRegClassID, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SUBSOME_INSN, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), +// CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), // Test an extract from an output instruction result (nonleaf) def : Pat<(i16 (trunc (bitreverse DOP:$src))), (EXTRACT_SUBREG (SOME_INSN DOP:$src), sub0)>; -// CHECK-LABEL: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITREVERSE, +// CHECK-LABEL: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITREVERSE), // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Test::DRegsRegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: // (trunc:{ *:[i16] } (bitreverse:{ *:[i32] } DOP:{ *:[i32] }:$src)) => (EXTRACT_SUBREG:{ *:[i16] } (SOME_INSN:{ *:[i32] } DOP:{ *:[i32] }:$src), sub0:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::SOME_INSN, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, sub0, +// CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(sub0), // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Test::SRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Test::DRegsRegClassID, +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), // EXTRACT_SUBREG is subinstruction, but also doesn't have a leaf input -// CHECK-LABEL: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CTPOP, +// CHECK-LABEL: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CTPOP), // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Test::DRegsRegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, // CHECK-NEXT: // (trunc:{ *:[i16] } (ctpop:{ *:[i32] } DOP:{ *:[i32] }:$src)) => (SUBSOME_INSN2:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i16] } (SOME_INSN:{ *:[i32] } DOP:{ *:[i32] }:$src), sub0:{ *:[i32] })) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/MyTarget::SOME_INSN, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/2, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, -// CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, sub0, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, Test::SRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, Test::DRegsRegClassID, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SUBSOME_INSN2, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), +// CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(sub0), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN2), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, def : Pat<(i16 (trunc (ctpop DOP:$src))), @@ -218,12 +218,12 @@ def : Pat<(i16 (trunc (ctpop DOP:$src))), def : Pat<(i16 (trunc DOP:$src)), (EXTRACT_SUBREG DOP:$src, sub0)>; // CHECK-LABEL: // (trunc:{ *:[i16] } DOP:{ *:[i32] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } DOP:{ *:[i32] }:$src, sub0:{ *:[i32] }) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src +// CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Test::SRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, Test::DRegsRegClassID, +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), // Test that we can import SUBREG_TO_REG @@ -231,15 +231,15 @@ def : Pat<(i32 (zext SOP:$src)), (SUBREG_TO_REG (i64 0), (SUBSOME_INSN SOP:$src), sub0)>; // CHECK-LABEL: (zext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (SUBREG_TO_REG:{ *:[i32] } 0:{ *:[i64] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/MyTarget::SUBSOME_INSN, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), +// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, +// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/0, -// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, -// CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*Imm*/1, +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, +// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1, // CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, Test::DRegsRegClassID, -// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, Test::SRegsRegClassID, +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), diff --git a/llvm/test/TableGen/GlobalISelEmitterVariadic.td b/llvm/test/TableGen/GlobalISelEmitterVariadic.td index 7d7a2ce37eef..ba6a93bd4837 100644 --- a/llvm/test/TableGen/GlobalISelEmitterVariadic.td +++ b/llvm/test/TableGen/GlobalISelEmitterVariadic.td @@ -22,30 +22,30 @@ def : Pat<(build_vector GPR32:$src1), def : Pat<(build_vector GPR32:$src1, GPR32:$src2), (TWO GPR32:$src1, GPR32:$src2)>; -// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ [[NEXT_OPCODE_LABEL:[0-9]+]], -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_BUILD_VECTOR, -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ [[NEXT_NUM_OPERANDS_LABEL_1:[0-9]+]], // Rule ID 0 // +// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4([[NEXT_OPCODE_LABEL:[0-9]+]]), +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4([[NEXT_NUM_OPERANDS_LABEL_1:[0-9]+]]), // Rule ID 0 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1) => (ONE:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ONE, +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ONE), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // CHECK-NEXT: // GIR_Coverage, 0, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label 1: @[[NEXT_NUM_OPERANDS_LABEL_1]] -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ [[NEXT_NUM_OPERANDS_LABEL_2:[0-9]+]], // Rule ID 1 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4([[NEXT_NUM_OPERANDS_LABEL_2:[0-9]+]]), // Rule ID 1 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (TWO:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::TWO, +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::TWO), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, // CHECK-NEXT: // GIR_Coverage, 1, // CHECK-NEXT: GIR_Done, diff --git a/llvm/test/TableGen/HasNoUse.td b/llvm/test/TableGen/HasNoUse.td index e817be0c1ddd..0661c2beb4d5 100644 --- a/llvm/test/TableGen/HasNoUse.td +++ b/llvm/test/TableGen/HasNoUse.td @@ -16,18 +16,18 @@ def NO_RET_ATOMIC_ADD : I<(outs), (ins GPR32Op:$src0, GPR32Op:$src1), []>; // SDAG-NEXT: if (!SDValue(N, 0).use_empty()) return false; // SDAG-NEXT: return true; -// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ATOMICRMW_ADD, +// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ATOMICRMW_ADD), // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, +// GISEL-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), // GISEL-NEXT: GIM_CheckHasNoUse, /*MI*/0, // GISEL-NEXT: // MIs[0] src0 // GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, // GISEL-NEXT: // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_atomic_load_add_no_ret_32>> => (NO_RET_ATOMIC_ADD GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1) -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::NO_RET_ATOMIC_ADD, +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::NO_RET_ATOMIC_ADD), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 -// GISEL-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, +// GISEL-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0, // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, let HasNoUse = true in diff --git a/llvm/test/TableGen/address-space-patfrags.td b/llvm/test/TableGen/address-space-patfrags.td index 8e92719e6520..27b174b4633c 100644 --- a/llvm/test/TableGen/address-space-patfrags.td +++ b/llvm/test/TableGen/address-space-patfrags.td @@ -57,12 +57,12 @@ def inst_d : Instruction { // SDAG-NEXT: return true; -// GISEL: GIM_Try, /*On fail goto*//*Label 0*/ {{[0-9]+}}, // Rule ID 0 // +// GISEL: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4({{[0-9]+}}), // Rule ID 0 // // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD, +// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LOAD), // GISEL-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, -// GISEL-NEXT: GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/123, /*AddrSpace*/455, -// GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, +// GISEL-NEXT: GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/123, /*AddrSpace*//* 455(*/0xC7, 0x03/*)*/, +// GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, def : Pat < (pat_frag_b GPR32:$src), (inst_b GPR32:$src) @@ -77,12 +77,12 @@ def : Pat < // SDAG-NEXT: return false; // SDAG-NEXT: return true; -// GISEL: GIM_Try, /*On fail goto*//*Label 1*/ {{[0-9]+}}, // Rule ID 1 // +// GISEL: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4({{[0-9]+}}), // Rule ID 1 // // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LOAD, +// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LOAD), // GISEL-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, // GISEL-NEXT: GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/2, -// GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, +// GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, def : Pat < (pat_frag_a GPR32:$src), (inst_a GPR32:$src) @@ -96,11 +96,11 @@ def truncstorei16_addrspace : PatFrag<(ops node:$val, node:$ptr), } // Test truncstore without a specific MemoryVT -// GISEL: GIM_Try, /*On fail goto*//*Label 2*/ {{[0-9]+}}, // Rule ID 2 // +// GISEL: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4({{[0-9]+}}), // Rule ID 2 // // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_STORE, +// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_STORE), // GISEL-NEXT: GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, -// GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, +// GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // GISEL-NEXT: // MIs[0] src0 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, def : Pat < @@ -109,9 +109,9 @@ def : Pat < >; // Test non-truncstore has a size equal to LLT check. -// GISEL: GIM_Try, /*On fail goto*//*Label 3*/ {{[0-9]+}}, // Rule ID 3 // +// GISEL: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4({{[0-9]+}}), // Rule ID 3 // // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_STORE, +// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_STORE), // GISEL-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, def : Pat < (store GPR32:$src0, GPR32:$src1), @@ -119,12 +119,12 @@ def : Pat < >; // Test truncstore with specific MemoryVT -// GISEL: GIM_Try, /*On fail goto*//*Label 4*/ {{[0-9]+}}, // Rule ID 4 // +// GISEL: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4({{[0-9]+}}), // Rule ID 4 // // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_STORE, +// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_STORE), // GISEL-NEXT: GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, -// GISEL-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, -// GISEL-NEXT: GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/123, /*AddrSpace*/455, +// GISEL-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), +// GISEL-NEXT: GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/123, /*AddrSpace*//* 455(*/0xC7, 0x03/*)*/, def : Pat < (truncstorei16_addrspace GPR32:$src0, GPR32:$src1), (inst_c GPR32:$src0, GPR32:$src1) diff --git a/llvm/test/TableGen/gisel-physreg-input.td b/llvm/test/TableGen/gisel-physreg-input.td index 3dbd57bc45b7..cd099c760a02 100644 --- a/llvm/test/TableGen/gisel-physreg-input.td +++ b/llvm/test/TableGen/gisel-physreg-input.td @@ -26,21 +26,21 @@ class I<dag OOps, dag IOps, list<dag> Pat> // GISEL: GIM_Try, // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD, +// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), // GISEL-NEXT: // MIs[0] DstI[dst] // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // MIs[0] src0 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // MIs[0] Operand 2 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::Special32RegClassID, +// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID), // GISEL-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src0, SPECIAL:{ *:[i32] }) => (ADD_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$src0) -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, -// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, MyTarget::SPECIAL, /*AddRegisterRegFlags*/RegState::Define, +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ADD_PHYS, +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD_PHYS), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0, @@ -54,21 +54,21 @@ def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0), // GISEL: GIM_Try, // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_MUL, +// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // GISEL-NEXT: // MIs[0] DstI[dst] // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID, +// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // MIs[0] SPECIAL // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID, +// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // MIs[0] Operand 2 // GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::Special32RegClassID, +// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID), // GISEL-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL, SPECIAL:{ *:[i32] }) => (MUL_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL) -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, -// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, MyTarget::SPECIAL, /*AddRegisterRegFlags*/RegState::Define, +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MUL_PHYS, +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MUL_PHYS), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // SPECIAL // GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0, diff --git a/llvm/test/TableGen/immarg-predicated.td b/llvm/test/TableGen/immarg-predicated.td index 87326c652356..320018010cc7 100644 --- a/llvm/test/TableGen/immarg-predicated.td +++ b/llvm/test/TableGen/immarg-predicated.td @@ -7,14 +7,14 @@ let TargetPrefix = "mytarget" in { def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; } -// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, +// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS), // GISEL-NEXT: // MIs[0] Operand 0 -// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mytarget_sleep0, +// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mytarget_sleep0), // GISEL-NEXT: // MIs[0] src // GISEL-NEXT: GIM_CheckIsImm, /*MI*/0, /*Op*/1, -// GISEL-NEXT: GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GICXXPred_I64_Predicate_tuimm9, +// GISEL-NEXT: GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tuimm9), // GISEL-NEXT: // (intrinsic_void {{[0-9]+}}:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_tuimm9>>:$src) => (SLEEP0 (timm:{ *:[i32] }):$src) -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SLEEP0, +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SLEEP0), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src def tuimm9 : TImmLeaf<i32, [{ return isUInt<9>(Imm); }]>; def SLEEP0 : I<(outs), (ins i32imm:$src), diff --git a/llvm/test/TableGen/immarg.td b/llvm/test/TableGen/immarg.td index c6f03cad137f..80849d512bee 100644 --- a/llvm/test/TableGen/immarg.td +++ b/llvm/test/TableGen/immarg.td @@ -8,13 +8,13 @@ def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; def int_mytarget_sleep1 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>; } -// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, +// GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS), // GISEL-NEXT: // MIs[0] Operand 0 -// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mytarget_sleep0, +// GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mytarget_sleep0), // GISEL-NEXT: // MIs[0] src // GISEL-NEXT: GIM_CheckIsImm, /*MI*/0, /*Op*/1, // GISEL-NEXT: // (intrinsic_void {{[0-9]+}}:{ *:[iPTR] }, (timm:{ *:[i32] }):$src) => (SLEEP0 (timm:{ *:[i32] }):$src) -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SLEEP0, +// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SLEEP0), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src def SLEEP0 : I<(outs), (ins i32imm:$src), [(int_mytarget_sleep0 timm:$src)] diff --git a/llvm/test/TableGen/predicate-patfags.td b/llvm/test/TableGen/predicate-patfags.td index 17cc74206b71..0912b05127ef 100644 --- a/llvm/test/TableGen/predicate-patfags.td +++ b/llvm/test/TableGen/predicate-patfags.td @@ -44,19 +44,19 @@ def TGTmul24_oneuse : PatFrag< // SDAG: OPC_CheckOpcode, TARGET_VAL(TargetISD::MUL24), // SDAG: OPC_CheckPredicate, 0, // Predicate_TGTmul24_oneuse -// GISEL: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, -// GISEL: GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::tgt_mul24, -// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GICXXPred_MI_Predicate_TGTmul24_oneuse, +// GISEL: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS), +// GISEL: GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::tgt_mul24), +// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_TGTmul24_oneuse), -// GISEL: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS, -// GISEL: GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::tgt_mul24, -// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GICXXPred_MI_Predicate_TGTmul24_oneuse, +// GISEL: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS), +// GISEL: GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::tgt_mul24), +// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_TGTmul24_oneuse), -// GISEL: GIM_CheckOpcode, /*MI*/1, MyTarget::G_TGT_MUL24, -// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GICXXPred_MI_Predicate_TGTmul24_oneuse, +// GISEL: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(MyTarget::G_TGT_MUL24), +// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_TGTmul24_oneuse), -// GISEL: GIM_CheckOpcode, /*MI*/1, MyTarget::G_TGT_MUL24, -// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GICXXPred_MI_Predicate_TGTmul24_oneuse, +// GISEL: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(MyTarget::G_TGT_MUL24), +// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_TGTmul24_oneuse), def inst_mad24 : I< (outs GPR32:$dst), (ins GPR32:$src0, GPR32:$src1, GPR32:$src2), diff --git a/llvm/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll b/llvm/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll index 015f52157b9e..196a104adc02 100644 --- a/llvm/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll +++ b/llvm/test/Transforms/ConstantHoisting/AArch64/large-immediate.ll @@ -1,27 +1,134 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 ; RUN: opt -mtriple=arm64-darwin-unknown -S -passes=consthoist < %s | FileCheck %s -define i128 @test1(i128 %a) nounwind { -; CHECK-LABEL: test1 -; CHECK: %const = bitcast i128 12297829382473034410122878 to i128 +define i128 @test1(i128 %a) { +; CHECK-LABEL: define i128 @test1( +; CHECK-SAME: i128 [[A:%.*]]) { +; CHECK-NEXT: [[CONST:%.*]] = bitcast i128 12297829382473034410122878 to i128 +; CHECK-NEXT: [[TMP1:%.*]] = add i128 [[A]], [[CONST]] +; CHECK-NEXT: [[TMP2:%.*]] = add i128 [[TMP1]], [[CONST]] +; CHECK-NEXT: ret i128 [[TMP2]] +; %1 = add i128 %a, 12297829382473034410122878 %2 = add i128 %1, 12297829382473034410122878 ret i128 %2 } ; Check that we don't hoist large, but cheap constants -define i512 @test2(i512 %a) nounwind { -; CHECK-LABEL: test2 -; CHECK-NOT: %const = bitcast i512 7 to i512 +define i512 @test2(i512 %a) { +; CHECK-LABEL: define i512 @test2( +; CHECK-SAME: i512 [[A:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = and i512 [[A]], 7 +; CHECK-NEXT: [[TMP2:%.*]] = or i512 [[TMP1]], 7 +; CHECK-NEXT: ret i512 [[TMP2]] +; %1 = and i512 %a, 7 %2 = or i512 %1, 7 ret i512 %2 } ; Check that we don't hoist the shift value of a shift instruction. -define i512 @test3(i512 %a) nounwind { -; CHECK-LABEL: test3 -; CHECK-NOT: %const = bitcast i512 504 to i512 +define i512 @test3(i512 %a) { +; CHECK-LABEL: define i512 @test3( +; CHECK-SAME: i512 [[A:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = shl i512 [[A]], 504 +; CHECK-NEXT: [[TMP2:%.*]] = ashr i512 [[TMP1]], 504 +; CHECK-NEXT: ret i512 [[TMP2]] +; %1 = shl i512 %a, 504 %2 = ashr i512 %1, 504 ret i512 %2 } + +; Ensure the code generator has the information necessary to simply sdiv. +define i64 @sdiv(i64 %a) { +; CHECK-LABEL: define i64 @sdiv( +; CHECK-SAME: i64 [[A:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = sdiv i64 [[A]], 4294967087 +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 4294967087 +; CHECK-NEXT: ret i64 [[TMP2]] +; + %1 = sdiv i64 %a, 4294967087 + %2 = add i64 %1, 4294967087 + ret i64 %2 +} + +; Ensure the code generator has the information necessary to simply srem. +define i64 @srem(i64 %a) { +; CHECK-LABEL: define i64 @srem( +; CHECK-SAME: i64 [[A:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = srem i64 [[A]], 4294967087 +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 4294967087 +; CHECK-NEXT: ret i64 [[TMP2]] +; + %1 = srem i64 %a, 4294967087 + %2 = add i64 %1, 4294967087 + ret i64 %2 +} + +; Ensure the code generator has the information necessary to simply udiv. +define i64 @udiv(i64 %a) { +; CHECK-LABEL: define i64 @udiv( +; CHECK-SAME: i64 [[A:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[A]], 4294967087 +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 4294967087 +; CHECK-NEXT: ret i64 [[TMP2]] +; + %1 = udiv i64 %a, 4294967087 + %2 = add i64 %1, 4294967087 + ret i64 %2 +} + +; Ensure the code generator has the information necessary to simply urem. +define i64 @urem(i64 %a) { +; CHECK-LABEL: define i64 @urem( +; CHECK-SAME: i64 [[A:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = urem i64 [[A]], 4294967087 +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 4294967087 +; CHECK-NEXT: ret i64 [[TMP2]] +; + %1 = urem i64 %a, 4294967087 + %2 = add i64 %1, 4294967087 + ret i64 %2 +} + +; Code generator will not decompose divide like operations when the divisor is +; no a constant. +define i64 @sdiv_non_const_divisor(i64 %a) { +; CHECK-LABEL: define i64 @sdiv_non_const_divisor( +; CHECK-SAME: i64 [[A:%.*]]) { +; CHECK-NEXT: [[CONST:%.*]] = bitcast i64 4294967087 to i64 +; CHECK-NEXT: [[TMP1:%.*]] = sdiv i64 [[CONST]], [[A]] +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[CONST]] +; CHECK-NEXT: ret i64 [[TMP2]] +; + %1 = sdiv i64 4294967087, %a + %2 = add i64 %1, 4294967087 + ret i64 %2 +} + +; Code generator emits divide instructions when optimising for size. +define i64 @sdiv_minsize(i64 %a) minsize { +; CHECK-LABEL: define i64 @sdiv_minsize( +; CHECK-SAME: i64 [[A:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[CONST:%.*]] = bitcast i64 4294967087 to i64 +; CHECK-NEXT: [[TMP1:%.*]] = sdiv i64 [[A]], [[CONST]] +; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[CONST]] +; CHECK-NEXT: ret i64 [[TMP2]] +; + %1 = sdiv i64 %a, 4294967087 + %2 = add i64 %1, 4294967087 + ret i64 %2 +} + +define <2 x i64> @sdiv_v2i64(<2 x i64> %a) { +; CHECK-LABEL: define <2 x i64> @sdiv_v2i64( +; CHECK-SAME: <2 x i64> [[A:%.*]]) { +; CHECK-NEXT: [[TMP1:%.*]] = sdiv <2 x i64> [[A]], <i64 4294967087, i64 4294967087> +; CHECK-NEXT: [[TMP2:%.*]] = add <2 x i64> [[TMP1]], <i64 4294967087, i64 4294967087> +; CHECK-NEXT: ret <2 x i64> [[TMP2]] +; + %1 = sdiv <2 x i64> %a, <i64 4294967087, i64 4294967087> + %2 = add <2 x i64> %1, <i64 4294967087, i64 4294967087> + ret <2 x i64> %2 +} diff --git a/llvm/test/Transforms/ConstraintElimination/debug.ll b/llvm/test/Transforms/ConstraintElimination/debug.ll index f3f0f5056135..2409af09735d 100644 --- a/llvm/test/Transforms/ConstraintElimination/debug.ll +++ b/llvm/test/Transforms/ConstraintElimination/debug.ll @@ -3,16 +3,16 @@ ; REQUIRES: asserts define i1 @test_and_ule(i4 %x, i4 %y, i4 %z) { -; CHECK: Processing fact to add to the system: ule i4 %x, %y -; CHECK-NEXT: Adding 'ule %x, %y' +; CHECK: Processing fact to add to the system: icmp ule i4 %x, %y +; CHECK-NEXT: Adding 'icmp ule i4 %x, %y' ; CHECK-NEXT: constraint: %x + -1 * %y <= 0 -; CHECK: Processing fact to add to the system: ule i4 %y, %z -; CHECK-NEXT: Adding 'ule %y, %z' +; CHECK: Processing fact to add to the system: icmp ule i4 %y, %z +; CHECK-NEXT: Adding 'icmp ule i4 %y, %z' ; CHECK-NEXT: constraint: %y + -1 * %z <= 0 ; CHECK: Checking %t.1 = icmp ule i4 %x, %z -; CHECK: Condition %t.1 = icmp ule i4 %x, %z implied by dominating constraints +; CHECK: Condition icmp ule i4 %x, %z implied by dominating constraints ; CHECK: Removing %y + -1 * %z <= 0 ; CHECK: Removing %x + -1 * %y <= 0 @@ -33,16 +33,16 @@ exit: } define i1 @test_and_ugt(i4 %x, i4 %y, i4 %z) { -; CHECK: Processing fact to add to the system: ugt i4 %x, %y -; CHECK-NEXT: Adding 'ugt %x, %y' +; CHECK: Processing fact to add to the system: icmp ugt i4 %x, %y +; CHECK-NEXT: Adding 'icmp ugt i4 %x, %y' ; CHECK-NEXT: constraint: -1 * %x + %y <= -1 -; CHECK: Processing fact to add to the system: ugt i4 %y, %z -; CHECK-NEXT: Adding 'ugt %y, %z' +; CHECK: Processing fact to add to the system: icmp ugt i4 %y, %z +; CHECK-NEXT: Adding 'icmp ugt i4 %y, %z' ; CHECK-NEXT: constraint: -1 * %y + %z <= -1 ; CHECK: Checking %f.1 = icmp ule i4 %x, %z -; CHECK: Condition ugt i4 %x, i4 %z implied by dominating constraints +; CHECK: Condition icmp ugt i4 %x, %z implied by dominating constraints ; CHECK: Removing -1 * %y + %z <= -1 ; CHECK: Removing -1 * %x + %y <= -1 diff --git a/llvm/test/Transforms/ConstraintElimination/reproducer-remarks-debug.ll b/llvm/test/Transforms/ConstraintElimination/reproducer-remarks-debug.ll index b8343aed8b4a..4fdc8e583112 100644 --- a/llvm/test/Transforms/ConstraintElimination/reproducer-remarks-debug.ll +++ b/llvm/test/Transforms/ConstraintElimination/reproducer-remarks-debug.ll @@ -4,7 +4,7 @@ target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" -; CHECK: Condition %c.2 = icmp eq ptr %a, null implied by dominating constraints +; CHECK: Condition icmp eq ptr %a, null implied by dominating constraints ; CHECK-NEXT: %a <= 0 ; CHECK-NEXT: Creating reproducer for %c.2 = icmp eq ptr %a, null ; CHECK-NEXT: found external input ptr %a diff --git a/llvm/test/Transforms/Coroutines/coro-debug-O2.ll b/llvm/test/Transforms/Coroutines/coro-debug-O2.ll index a668bd1a5219..3f9af30a92e3 100644 --- a/llvm/test/Transforms/Coroutines/coro-debug-O2.ll +++ b/llvm/test/Transforms/Coroutines/coro-debug-O2.ll @@ -1,4 +1,5 @@ ; RUN: opt < %s -passes='module(coro-early),cgscc(coro-split<reuse-storage>),function(sroa)' -S | FileCheck %s +; RUN: opt --try-experimental-debuginfo-iterators < %s -passes='module(coro-early),cgscc(coro-split<reuse-storage>),function(sroa)' -S | FileCheck %s ; Checks whether the dbg.declare for `__promise` remains valid under O2. diff --git a/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll b/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll index 7f5679e4d522..2978f85be238 100644 --- a/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll +++ b/llvm/test/Transforms/Coroutines/coro-debug-coro-frame.ll @@ -1,4 +1,5 @@ ; RUN: opt < %s -passes='module(coro-early),cgscc(coro-split,coro-split)' -S | FileCheck %s +; RUN: opt --try-experimental-debuginfo-iterators < %s -passes='module(coro-early),cgscc(coro-split,coro-split)' -S | FileCheck %s ; Checks whether the dbg.declare for `__coro_frame` are created. diff --git a/llvm/test/Transforms/Coroutines/coro-debug-dbg.values-not_used_in_frame.ll b/llvm/test/Transforms/Coroutines/coro-debug-dbg.values-not_used_in_frame.ll index 1b9a1bd63a2e..79793dc293d0 100644 --- a/llvm/test/Transforms/Coroutines/coro-debug-dbg.values-not_used_in_frame.ll +++ b/llvm/test/Transforms/Coroutines/coro-debug-dbg.values-not_used_in_frame.ll @@ -1,5 +1,6 @@ ; Tests whether resume function would remain dbg.value infomation if corresponding values are not used in the frame. ; RUN: opt < %s -passes='module(coro-early),cgscc(coro-split,coro-split)' -S | FileCheck %s +; RUN: opt --try-experimental-debuginfo-iterators < %s -passes='module(coro-early),cgscc(coro-split,coro-split)' -S | FileCheck %s ; ; This file is based on coro-debug-frame-variable.ll. ; CHECK: define internal fastcc void @f.resume(ptr noundef nonnull align 16 dereferenceable(80) %begin) !dbg ![[RESUME_FN_DBG_NUM:[0-9]+]] diff --git a/llvm/test/Transforms/Coroutines/coro-debug-dbg.values.ll b/llvm/test/Transforms/Coroutines/coro-debug-dbg.values.ll index 54cdde8ae4ac..47b2ddafcfc6 100644 --- a/llvm/test/Transforms/Coroutines/coro-debug-dbg.values.ll +++ b/llvm/test/Transforms/Coroutines/coro-debug-dbg.values.ll @@ -1,5 +1,6 @@ ; Tests whether resume function would remain dbg.value infomation. ; RUN: opt < %s -passes='module(coro-early),cgscc(coro-split,coro-split)' -S | FileCheck %s +; RUN: opt --try-experimental-debuginfo-iterators < %s -passes='module(coro-early),cgscc(coro-split,coro-split)' -S | FileCheck %s ; ; This file is based on coro-debug-frame-variable.ll. ; CHECK-LABEL: define void @f( diff --git a/llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll b/llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll index 37b4126ce373..19a89fefd526 100644 --- a/llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll +++ b/llvm/test/Transforms/Coroutines/coro-debug-frame-variable.ll @@ -1,4 +1,5 @@ ; RUN: opt < %s -passes='default<O0>' -S | FileCheck %s +; RUN: opt --try-experimental-debuginfo-iterators < %s -passes='default<O0>' -S | FileCheck %s ; Define a function 'f' that resembles the Clang frontend's output for the ; following C++ coroutine: diff --git a/llvm/test/Transforms/Coroutines/coro-debug-spill-dbg.declare.ll b/llvm/test/Transforms/Coroutines/coro-debug-spill-dbg.declare.ll index e7a271a96ead..c943ea5ca22e 100644 --- a/llvm/test/Transforms/Coroutines/coro-debug-spill-dbg.declare.ll +++ b/llvm/test/Transforms/Coroutines/coro-debug-spill-dbg.declare.ll @@ -1,6 +1,7 @@ ; Test spilling a temp generates dbg.declare in resume/destroy/cleanup functions. ; ; RUN: opt < %s -passes='cgscc(coro-split)' -S | FileCheck %s +; RUN: opt --try-experimental-debuginfo-iterators < %s -passes='cgscc(coro-split)' -S | FileCheck %s ; ; The test case simulates a coroutine method in a class. ; diff --git a/llvm/test/Transforms/Coroutines/coro-debug.ll b/llvm/test/Transforms/Coroutines/coro-debug.ll index 064693c80ad2..4792825f4ce0 100644 --- a/llvm/test/Transforms/Coroutines/coro-debug.ll +++ b/llvm/test/Transforms/Coroutines/coro-debug.ll @@ -1,5 +1,6 @@ ; Tests that debug information is sane after coro-split ; RUN: opt < %s -passes='cgscc(coro-split),simplifycfg,early-cse' -S | FileCheck %s +; RUN: opt --try-experimental-debuginfo-iterators < %s -passes='cgscc(coro-split),simplifycfg,early-cse' -S | FileCheck %s source_filename = "simple-repro.c" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/Coroutines/coro-split-dbg.ll b/llvm/test/Transforms/Coroutines/coro-split-dbg.ll index 184d4a564ab7..7d95be308a5f 100644 --- a/llvm/test/Transforms/Coroutines/coro-split-dbg.ll +++ b/llvm/test/Transforms/Coroutines/coro-split-dbg.ll @@ -1,6 +1,7 @@ ; Make sure that coro-split correctly deals with debug information. ; The test here is simply that it does not result in bad IR that will crash opt. ; RUN: opt < %s -passes='cgscc(coro-split),simplifycfg,early-cse' -disable-output +; RUN: opt --try-experimental-debuginfo-iterators < %s -passes='cgscc(coro-split),simplifycfg,early-cse' -disable-output source_filename = "coro.c" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/Coroutines/swift-async-dbg.ll b/llvm/test/Transforms/Coroutines/swift-async-dbg.ll index af7d816c1286..74edf7a3f3a5 100644 --- a/llvm/test/Transforms/Coroutines/swift-async-dbg.ll +++ b/llvm/test/Transforms/Coroutines/swift-async-dbg.ll @@ -2,6 +2,13 @@ ; RUN: opt -mtriple='x86_64' %s -S -passes='module(coro-early),cgscc(coro-split,simplifycfg)' -o - | FileCheck %s ; RUN: opt -mtriple='i386-' %s -S -passes='module(coro-early),cgscc(coro-split,simplifycfg)' -o - | FileCheck %s --check-prefix=NOENTRY ; RUN: opt -mtriple='armv7-' %s -S -passes='module(coro-early),cgscc(coro-split,simplifycfg)' -o - | FileCheck %s --check-prefix=NOENTRY + +;; Replicate those tests with non-instruction debug markers. +; RUN: opt --try-experimental-debuginfo-iterators -mtriple='arm64-' %s -S -passes='module(coro-early),cgscc(coro-split,simplifycfg)' -o - | FileCheck %s +; RUN: opt --try-experimental-debuginfo-iterators -mtriple='x86_64' %s -S -passes='module(coro-early),cgscc(coro-split,simplifycfg)' -o - | FileCheck %s +; RUN: opt --try-experimental-debuginfo-iterators -mtriple='i386-' %s -S -passes='module(coro-early),cgscc(coro-split,simplifycfg)' -o - | FileCheck %s --check-prefix=NOENTRY +; RUN: opt --try-experimental-debuginfo-iterators -mtriple='armv7-' %s -S -passes='module(coro-early),cgscc(coro-split,simplifycfg)' -o - | FileCheck %s --check-prefix=NOENTRY + ; NOENTRY-NOT: OP_llvm_entry_value target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/Transforms/CorrelatedValuePropagation/cond-using-block-value.ll b/llvm/test/Transforms/CorrelatedValuePropagation/cond-using-block-value.ll new file mode 100644 index 000000000000..d30b31d317a6 --- /dev/null +++ b/llvm/test/Transforms/CorrelatedValuePropagation/cond-using-block-value.ll @@ -0,0 +1,98 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S -passes=correlated-propagation < %s | FileCheck %s + +declare void @use(i1) + +define void @test_icmp_from_implied_cond(i32 %a, i32 %b) { +; CHECK-LABEL: define void @test_icmp_from_implied_cond( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[A_CMP:%.*]] = icmp ugt i32 [[A]], 32 +; CHECK-NEXT: br i1 [[A_CMP]], label [[END:%.*]], label [[L1:%.*]] +; CHECK: l1: +; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[B]], [[A]] +; CHECK-NEXT: br i1 [[COND]], label [[L2:%.*]], label [[END]] +; CHECK: l2: +; CHECK-NEXT: [[B_CMP1:%.*]] = icmp ult i32 [[B]], 32 +; CHECK-NEXT: call void @use(i1 [[B_CMP1]]) +; CHECK-NEXT: [[B_CMP2:%.*]] = icmp ult i32 [[B]], 31 +; CHECK-NEXT: call void @use(i1 [[B_CMP2]]) +; CHECK-NEXT: ret void +; CHECK: end: +; CHECK-NEXT: ret void +; + %a.cmp = icmp ugt i32 %a, 32 + br i1 %a.cmp, label %end, label %l1 + +l1: + %cond = icmp ult i32 %b, %a + br i1 %cond, label %l2, label %end + +l2: + %b.cmp1 = icmp ult i32 %b, 32 + call void @use(i1 %b.cmp1) + %b.cmp2 = icmp ult i32 %b, 31 + call void @use(i1 %b.cmp2) + ret void + +end: + ret void +} + +define i64 @test_sext_from_implied_cond(i32 %a, i32 %b) { +; CHECK-LABEL: define i64 @test_sext_from_implied_cond( +; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[A_CMP:%.*]] = icmp slt i32 [[A]], 0 +; CHECK-NEXT: br i1 [[A_CMP]], label [[END:%.*]], label [[L1:%.*]] +; CHECK: l1: +; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[B]], [[A]] +; CHECK-NEXT: br i1 [[COND]], label [[L2:%.*]], label [[END]] +; CHECK: l2: +; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[B]] to i64 +; CHECK-NEXT: ret i64 [[SEXT]] +; CHECK: end: +; CHECK-NEXT: ret i64 0 +; + %a.cmp = icmp slt i32 %a, 0 + br i1 %a.cmp, label %end, label %l1 + +l1: + %cond = icmp ult i32 %b, %a + br i1 %cond, label %l2, label %end + +l2: + %sext = sext i32 %b to i64 + ret i64 %sext + +end: + ret i64 0 +} + +define void @test_icmp_from_implied_range(i16 %x, i32 %b) { +; CHECK-LABEL: define void @test_icmp_from_implied_range( +; CHECK-SAME: i16 [[X:%.*]], i32 [[B:%.*]]) { +; CHECK-NEXT: [[A:%.*]] = zext i16 [[X]] to i32 +; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[B]], [[A]] +; CHECK-NEXT: br i1 [[COND]], label [[L1:%.*]], label [[END:%.*]] +; CHECK: l1: +; CHECK-NEXT: [[B_CMP1:%.*]] = icmp ult i32 [[B]], 65535 +; CHECK-NEXT: call void @use(i1 [[B_CMP1]]) +; CHECK-NEXT: [[B_CMP2:%.*]] = icmp ult i32 [[B]], 65534 +; CHECK-NEXT: call void @use(i1 [[B_CMP2]]) +; CHECK-NEXT: ret void +; CHECK: end: +; CHECK-NEXT: ret void +; + %a = zext i16 %x to i32 + %cond = icmp ult i32 %b, %a + br i1 %cond, label %l1, label %end + +l1: + %b.cmp1 = icmp ult i32 %b, 65535 + call void @use(i1 %b.cmp1) + %b.cmp2 = icmp ult i32 %b, 65534 + call void @use(i1 %b.cmp2) + ret void + +end: + ret void +} diff --git a/llvm/test/Transforms/ExpandMemCmp/AArch64/memcmp.ll b/llvm/test/Transforms/ExpandMemCmp/AArch64/memcmp.ll index 54f8c7006bb5..92439691e187 100644 --- a/llvm/test/Transforms/ExpandMemCmp/AArch64/memcmp.ll +++ b/llvm/test/Transforms/ExpandMemCmp/AArch64/memcmp.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 -; RUN: opt -S -expandmemcmp -memcmp-num-loads-per-block=1 -mtriple=aarch64-unknown-unknown < %s | FileCheck %s +; RUN: opt -S -expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=aarch64-unknown-unknown < %s | FileCheck %s +; RUN: opt -S -passes=expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=aarch64-unknown-unknown < %s | FileCheck %s declare i32 @memcmp(ptr nocapture, ptr nocapture, i64) diff --git a/llvm/test/Transforms/ExpandMemCmp/X86/bcmp.ll b/llvm/test/Transforms/ExpandMemCmp/X86/bcmp.ll index 57c91f906379..41d357728b93 100644 --- a/llvm/test/Transforms/ExpandMemCmp/X86/bcmp.ll +++ b/llvm/test/Transforms/ExpandMemCmp/X86/bcmp.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -expandmemcmp -memcmp-num-loads-per-block=1 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 +; RUN: opt -S -expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 +; RUN: opt -S -passes=expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 declare i32 @bcmp(ptr nocapture, ptr nocapture, i64) diff --git a/llvm/test/Transforms/ExpandMemCmp/X86/memcmp-x32.ll b/llvm/test/Transforms/ExpandMemCmp/X86/memcmp-x32.ll index f56d9688a01e..d71ae8be19b6 100644 --- a/llvm/test/Transforms/ExpandMemCmp/X86/memcmp-x32.ll +++ b/llvm/test/Transforms/ExpandMemCmp/X86/memcmp-x32.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -expandmemcmp -mtriple=i686-unknown-unknown -data-layout=e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128 < %s | FileCheck %s --check-prefix=X32 +; RUN: opt -S -expand-memcmp -mtriple=i686-unknown-unknown -data-layout=e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128 < %s | FileCheck %s --check-prefix=X32 +; RUN: opt -S -passes=expand-memcmp -mtriple=i686-unknown-unknown -data-layout=e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128 < %s | FileCheck %s --check-prefix=X32 declare i32 @memcmp(ptr nocapture, ptr nocapture, i32) diff --git a/llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll b/llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll index 2594f5397139..f686e2997556 100644 --- a/llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll +++ b/llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -expandmemcmp -memcmp-num-loads-per-block=1 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 --check-prefix=X64_1LD -; RUN: opt -S -expandmemcmp -memcmp-num-loads-per-block=2 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 --check-prefix=X64_2LD +; RUN: opt -S -expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 --check-prefix=X64_1LD +; RUN: opt -S -expand-memcmp -memcmp-num-loads-per-block=2 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 --check-prefix=X64_2LD +; RUN: opt -S -passes=expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 --check-prefix=X64_1LD +; RUN: opt -S -passes=expand-memcmp -memcmp-num-loads-per-block=2 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 --check-prefix=X64_2LD declare i32 @memcmp(ptr nocapture, ptr nocapture, i64) diff --git a/llvm/test/Transforms/IndirectBrExpand/basic.ll b/llvm/test/Transforms/IndirectBrExpand/basic.ll index c90ec4a3c48b..c2c73100543f 100644 --- a/llvm/test/Transforms/IndirectBrExpand/basic.ll +++ b/llvm/test/Transforms/IndirectBrExpand/basic.ll @@ -1,4 +1,5 @@ ; RUN: opt < %s -indirectbr-expand -S | FileCheck %s +; RUN: opt < %s -passes=indirectbr-expand -S | FileCheck %s ; ; REQUIRES: x86-registered-target diff --git a/llvm/test/Transforms/InstCombine/div.ll b/llvm/test/Transforms/InstCombine/div.ll index cd17d10d0e1d..80847dd588ea 100644 --- a/llvm/test/Transforms/InstCombine/div.ll +++ b/llvm/test/Transforms/InstCombine/div.ll @@ -1432,6 +1432,140 @@ define <2 x i8> @sdiv_sdiv_mul_nsw(<2 x i8> %x, <2 x i8> %y, <2 x i8> %z) { ret <2 x i8> %r } +; (X * C0) / (X * C1) --> C0 / C1 +define i8 @sdiv_mul_nsw_mul_nsw(i8 %x,i8 %y,i8 %z) { +; CHECK-LABEL: @sdiv_mul_nsw_mul_nsw( +; CHECK-NEXT: [[ADD4:%.*]] = mul nsw i8 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[ADD5:%.*]] = mul nsw i8 [[X]], [[Y:%.*]] +; CHECK-NEXT: [[DIV:%.*]] = sdiv i8 [[ADD5]], [[ADD4]] +; CHECK-NEXT: ret i8 [[DIV]] +; + %add4 = mul nsw i8 %x, %z + %add5 = mul nsw i8 %x, %y + %div = sdiv i8 %add5, %add4 + ret i8 %div +} + +define i8 @udiv_mul_nuw_mul_nuw(i8 %x,i8 %y,i8 %z) { +; CHECK-LABEL: @udiv_mul_nuw_mul_nuw( +; CHECK-NEXT: [[DIV:%.*]] = udiv i8 [[Y:%.*]], [[Z:%.*]] +; CHECK-NEXT: ret i8 [[DIV]] +; + %add4 = mul nuw i8 %x, %z + %add5 = mul nuw i8 %x, %y + %div = udiv i8 %add5, %add4 + ret i8 %div +} + +define i8 @sdiv_mul_nsw_constant_mul_nsw_constant(i8 %x) { +; CHECK-LABEL: @sdiv_mul_nsw_constant_mul_nsw_constant( +; CHECK-NEXT: ret i8 2 +; + %add4 = mul nsw i8 %x, 5 + %add5 = mul nsw i8 %x, 10 + %div = sdiv i8 %add5, %add4 + ret i8 %div +} + +define i4 @sdiv_mul_nsw_constant_mul_constant(i4 %a) { +; CHECK-LABEL: @sdiv_mul_nsw_constant_mul_constant( +; CHECK-NEXT: [[ADD4:%.*]] = mul i4 [[A:%.*]], 3 +; CHECK-NEXT: [[ADD5:%.*]] = mul nsw i4 [[A]], 6 +; CHECK-NEXT: [[DIV:%.*]] = sdiv i4 [[ADD5]], [[ADD4]] +; CHECK-NEXT: ret i4 [[DIV]] +; + %add4 = mul i4 %a, 3 + %add5 = mul nsw i4 %a, 6 + %div = sdiv i4 %add5, %add4 + ret i4 %div +} +define i4 @sdiv_mul_nsw_constant_mul_constant2(i4 %a) { +; CHECK-LABEL: @sdiv_mul_nsw_constant_mul_constant2( +; CHECK-NEXT: [[ADD4:%.*]] = sub i4 0, [[A:%.*]] +; CHECK-NEXT: [[ADD5:%.*]] = shl i4 [[A]], 3 +; CHECK-NEXT: [[DIV:%.*]] = sdiv i4 [[ADD5]], [[ADD4]] +; CHECK-NEXT: ret i4 [[DIV]] +; + %add4 = mul i4 %a, 15 + %add5 = mul nsw i4 %a, 8 + %div = sdiv i4 %add5, %add4 + ret i4 %div +} + +define i4 @sdiv_mul_nsw_constant_mul_constant3(i4 %a) { +; CHECK-LABEL: @sdiv_mul_nsw_constant_mul_constant3( +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i4 [[A:%.*]], -8 +; CHECK-NEXT: [[DIV:%.*]] = select i1 [[TMP1]], i4 1, i4 -1 +; CHECK-NEXT: ret i4 [[DIV]] +; + %add4 = mul i4 %a, 15 + %add5 = mul nsw i4 %a, 1 + %div = sdiv i4 %add5, %add4 + ret i4 %div +} + +define i4 @sdiv_mul_nsw_mul(i4 %a) { +; CHECK-LABEL: @sdiv_mul_nsw_mul( +; CHECK-NEXT: [[ADD4:%.*]] = sub i4 0, [[A:%.*]] +; CHECK-NEXT: [[ADD5:%.*]] = shl i4 [[A]], 3 +; CHECK-NEXT: [[DIV:%.*]] = sdiv i4 [[ADD5]], [[ADD4]] +; CHECK-NEXT: ret i4 [[DIV]] +; + %add4 = mul i4 %a, -1 + %add5 = mul nsw i4 %a, -8 + %div = sdiv i4 %add5, %add4 + ret i4 %div +} + +define i4 @udiv_mul_nuw_constant_mul_constant(i4 %a) { +; CHECK-LABEL: @udiv_mul_nuw_constant_mul_constant( +; CHECK-NEXT: ret i4 2 +; + %add4 = mul i4 %a, 3 + %add5 = mul nuw i4 %a, 6 + %div = udiv i4 %add5, %add4 + ret i4 %div +} + +define i4 @udiv_mul_nuw_mul_negative(i4 %a) { +; CHECK-LABEL: @udiv_mul_nuw_mul_negative( +; CHECK-NEXT: [[ADD4:%.*]] = mul i4 [[A:%.*]], -3 +; CHECK-NEXT: [[ADD5:%.*]] = shl nuw i4 [[A]], 2 +; CHECK-NEXT: [[DIV:%.*]] = udiv i4 [[ADD5]], [[ADD4]] +; CHECK-NEXT: ret i4 [[DIV]] +; + %add4 = mul i4 %a, 13 + %add5 = mul nuw i4 %a, 4 + %div = udiv i4 %add5, %add4 + ret i4 %div +} + +define i4 @sdiv_mul_nsw_mul_nsw_allones(i4 %a) { +; CHECK-LABEL: @sdiv_mul_nsw_mul_nsw_allones( +; CHECK-NEXT: [[ADD4:%.*]] = sub nsw i4 0, [[A:%.*]] +; CHECK-NEXT: [[ADD5:%.*]] = shl i4 [[A]], 3 +; CHECK-NEXT: [[DIV:%.*]] = sdiv i4 [[ADD5]], [[ADD4]] +; CHECK-NEXT: ret i4 [[DIV]] +; + %add4 = mul nsw i4 %a, -1 + %add5 = mul nsw i4 %a, -8 + %div = sdiv i4 %add5, %add4 + ret i4 %div +} + +define i4 @sdiv_mul_nsw_mul_signmask(i4 %a, i4 %c2) { +; CHECK-LABEL: @sdiv_mul_nsw_mul_signmask( +; CHECK-NEXT: [[ADD4:%.*]] = shl i4 [[A:%.*]], 3 +; CHECK-NEXT: [[ADD5:%.*]] = mul nsw i4 [[A]], [[C2:%.*]] +; CHECK-NEXT: [[DIV:%.*]] = sdiv i4 [[ADD5]], [[ADD4]] +; CHECK-NEXT: ret i4 [[DIV]] +; + %add4 = mul nsw i4 %a, -8 + %add5 = mul nsw i4 %a, %c2 + %div = sdiv i4 %add5, %add4 + ret i4 %div +} + define i32 @sdiv_sub1(i32 %arg) { ; CHECK-LABEL: @sdiv_sub1( ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[ARG:%.*]], -2147483648 diff --git a/llvm/test/Transforms/LICM/variant-aainfo.ll b/llvm/test/Transforms/LICM/variant-aainfo.ll new file mode 100644 index 000000000000..8ad497ea4439 --- /dev/null +++ b/llvm/test/Transforms/LICM/variant-aainfo.ll @@ -0,0 +1,59 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -S -passes=licm | FileCheck %s + +; See https://discourse.llvm.org/t/rfc-dont-merge-memory-locations-in-aliassettracker/73336 +; pairwise TBAA indicates NoAlias of load/store ptr at %s with store i32 at %0 +; yet LICM fails to promote load/store ptr %s out of the loop + +define void @_Z4testP1S(ptr %s) { +; CHECK-LABEL: define void @_Z4testP1S( +; CHECK-SAME: ptr [[S:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[FOR_BODY:%.*]] +; CHECK: for.cond.cleanup: +; CHECK-NEXT: ret void +; CHECK: for.body: +; CHECK-NEXT: [[I_05:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S]], align 4, !tbaa [[TBAA0:![0-9]+]] +; CHECK-NEXT: store i32 [[I_05]], ptr [[TMP0]], align 4, !tbaa [[TBAA5:![0-9]+]] +; CHECK-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i32 1 +; CHECK-NEXT: store ptr [[ADD_PTR_I]], ptr [[S]], align 4, !tbaa [[TBAA7:![0-9]+]] +; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_05]], 1 +; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], 100 +; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY]] +; +entry: + br label %for.body + +for.cond.cleanup: ; preds = %for.body + ret void + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %0 = load ptr, ptr %s, align 4, !tbaa !0 + store i32 %i.05, ptr %0, align 4, !tbaa !5 + %add.ptr.i = getelementptr inbounds i32, ptr %0, i32 1 + store ptr %add.ptr.i, ptr %s, align 4, !tbaa !7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.cond.cleanup, label %for.body +} + +!0 = !{!1, !2, i64 0} +!1 = !{!"_ZTS1S", !2, i64 0} +!2 = !{!"any pointer", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C++ TBAA"} +!5 = !{!6, !6, i64 0} +!6 = !{!"int", !3, i64 0} +!7 = !{!2, !2, i64 0} +;. +; CHECK: [[TBAA0]] = !{[[META1:![0-9]+]], [[META2:![0-9]+]], i64 0} +; CHECK: [[META1]] = !{!"_ZTS1S", [[META2]], i64 0} +; CHECK: [[META2]] = !{!"any pointer", [[META3:![0-9]+]], i64 0} +; CHECK: [[META3]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0} +; CHECK: [[META4]] = !{!"Simple C++ TBAA"} +; CHECK: [[TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0} +; CHECK: [[META6]] = !{!"int", [[META3]], i64 0} +; CHECK: [[TBAA7]] = !{[[META2]], [[META2]], i64 0} +;. diff --git a/llvm/test/Transforms/Util/trivial-auto-var-init-call.ll b/llvm/test/Transforms/Util/trivial-auto-var-init-call.ll index f34aa3e9f679..c12648a6b3d8 100644 --- a/llvm/test/Transforms/Util/trivial-auto-var-init-call.ll +++ b/llvm/test/Transforms/Util/trivial-auto-var-init-call.ll @@ -1,4 +1,5 @@ ; RUN: opt -passes=annotation-remarks -o /dev/null -S -pass-remarks-output=%t.opt.yaml %s -pass-remarks-missed=annotation-remarks 2>&1 | FileCheck %s +; RUN: opt --try-experimental-debuginfo-iterators -passes=annotation-remarks -o /dev/null -S -pass-remarks-output=%t.opt.yaml %s -pass-remarks-missed=annotation-remarks 2>&1 | FileCheck %s ; RUN: cat %t.opt.yaml | FileCheck -check-prefix=YAML %s ; Emit remarks for memcpy, memmove, memset, bzero. diff --git a/llvm/test/Transforms/Util/trivial-auto-var-init-store.ll b/llvm/test/Transforms/Util/trivial-auto-var-init-store.ll index d3355efe2efc..2a7eb638edf6 100644 --- a/llvm/test/Transforms/Util/trivial-auto-var-init-store.ll +++ b/llvm/test/Transforms/Util/trivial-auto-var-init-store.ll @@ -1,4 +1,5 @@ ; RUN: opt -passes=annotation-remarks -o /dev/null -S -pass-remarks-output=%t.opt.yaml %s -pass-remarks-missed=annotation-remarks 2>&1 | FileCheck %s +; RUN: opt --try-experimental-debuginfo-iterators -passes=annotation-remarks -o /dev/null -S -pass-remarks-output=%t.opt.yaml %s -pass-remarks-missed=annotation-remarks 2>&1 | FileCheck %s ; RUN: cat %t.opt.yaml | FileCheck -check-prefix=YAML %s ; Emit a remark that reports a store. diff --git a/llvm/test/tools/llvm-objdump/XCOFF/disassemble-abs.test b/llvm/test/tools/llvm-objdump/XCOFF/disassemble-abs.test new file mode 100644 index 000000000000..c1b76e155284 --- /dev/null +++ b/llvm/test/tools/llvm-objdump/XCOFF/disassemble-abs.test @@ -0,0 +1,158 @@ +## Object files assembled on AIX from the following source: +## .csect [PR] +##.main: +## .globl .main +## .extern .function +## bla .function +## btla .function +## ba 0x1234 +## ba -32 +## bta 0x2348 +## bta -256 +# +# RUN: yaml2obj %s --docnum=1 -o %t32.o +# RUN: llvm-objdump -d %t32.o | FileCheck %s +# +# CHECK: : file format aixcoff-rs6000 +# CHECK: Disassembly of section .text: +# CHECK: 00000000 <.main>: +# CHECK: 0: 48 00 00 03 bla 0x0 +# CHECK-NEXT: 4: 41 80 00 03 btla 0, 0x0 +# CHECK-NEXT: 8: 48 00 12 36 ba 0x1234 +# CHECK-NEXT: c: 4b ff ff e2 ba 0xffffffe0 +# CHECK-NEXT: 10: 41 80 23 4a bta 0, 0x2348 +# CHECK-NEXT: 14: 41 80 ff 02 bta 0, 0xffffff00 + +--- !XCOFF +FileHeader: + MagicNumber: 0x1DF + NumberOfSections: 1 + CreationTime: 1700148622 + OffsetToSymbolTable: 0x68 + EntriesInSymbolTable: 8 + AuxiliaryHeaderSize: 0 + Flags: 0x0 +Sections: + - Name: .text + Address: 0x0 + Size: 0x18 + FileOffsetToData: 0x3C + FileOffsetToRelocations: 0x54 + FileOffsetToLineNumbers: 0x0 + NumberOfRelocations: 0x2 + NumberOfLineNumbers: 0x0 + Flags: [ STYP_TEXT ] + SectionData: 4800000341800003480012364BFFFFE24180234A4180FF02 + Relocations: + - Address: 0x0 + Symbol: 0x2 + Info: 0x99 + Type: 0x18 + - Address: 0x6 + Symbol: 0x2 + Info: 0x8F + Type: 0x18 +Symbols: + - Name: .file + Value: 0x0 + Section: N_DEBUG + Type: 0xC03 + StorageClass: C_FILE + NumberOfAuxEntries: 1 + - Name: .function + Value: 0x0 + Section: N_UNDEF + Type: 0x0 + StorageClass: C_EXT + NumberOfAuxEntries: 1 + - Name: '' + Value: 0x0 + Section: .text + Type: 0x0 + StorageClass: C_HIDEXT + NumberOfAuxEntries: 1 + - Name: .main + Value: 0x0 + Section: .text + Type: 0x0 + StorageClass: C_EXT + NumberOfAuxEntries: 1 +StringTable: {} +... + +# RUN: yaml2obj %s --docnum=2 -o %t64.o +# RUN: llvm-objdump -d %t64.o | FileCheck --check-prefixes=CHECK64 %s +# + +# CHECK64: : file format aix5coff64-rs6000 +# CHECK64: Disassembly of section .text: +# CHECK64: 0000000000000000 <.main>: +# CHECK64-NEXT: 0: 48 00 00 03 bla 0x0 +# CHECK64-NEXT: 4: 41 80 00 03 btla 0, 0x0 +# CHECK64-NEXT: 8: 48 00 12 36 ba 0x1234 +# CHECK64-NEXT: c: 4b ff ff e2 ba 0xffffffffffffffe0 +# CHECK64-NEXT: 10: 41 80 23 4a bta 0, 0x2348 +# CHECK64-NEXT: 14: 41 80 ff 02 bta 0, 0xffffffffffffff00 +# +--- !XCOFF +FileHeader: + MagicNumber: 0x1F7 + NumberOfSections: 1 + CreationTime: 1701859282 + AuxiliaryHeaderSize: 0 + Flags: 0x0 +Sections: + - Name: .text + Address: 0x0 + Size: 0x18 + FileOffsetToData: 0x60 + FileOffsetToRelocations: 0x78 + FileOffsetToLineNumbers: 0x0 + NumberOfRelocations: 0x2 + NumberOfLineNumbers: 0x0 + Flags: [ STYP_TEXT ] + SectionData: 4800000341800003480012364BFFFFE24180234A4180FF02 + Relocations: + - Address: 0x0 + Symbol: 0x1 + Info: 0x99 + Type: 0x18 + - Address: 0x6 + Symbol: 0x1 + Info: 0x8F + Type: 0x18 +Symbols: + - Name: .file + Section: N_DEBUG + StorageClass: C_FILE + NumberOfAuxEntries: 0 + - Name: .function + Section: N_UNDEF + StorageClass: C_EXT + NumberOfAuxEntries: 1 + AuxEntries: + - Type: AUX_CSECT + StorageMappingClass: XMC_PR + SymbolAlignmentAndType: 0 + - Name: '' + Section: .text + StorageClass: C_HIDEXT + NumberOfAuxEntries: 1 + AuxEntries: + - Type: AUX_CSECT + StorageMappingClass: XMC_PR + SymbolAlignmentAndType: 1 + - Name: .main + Section: .text + StorageClass: C_EXT + NumberOfAuxEntries: 1 + AuxEntries: + - Type: AUX_CSECT + StorageMappingClass: XMC_PR + SymbolAlignmentAndType: 2 +StringTable: + Strings: + - .file + - .function + - .text + - .main diff --git a/llvm/test/tools/llvm-readobj/ELF/AArch64/aarch64-note-gnu-property.s b/llvm/test/tools/llvm-readobj/ELF/AArch64/aarch64-note-gnu-property.s index 872a3f150fdf..377e6f93448c 100644 --- a/llvm/test/tools/llvm-readobj/ELF/AArch64/aarch64-note-gnu-property.s +++ b/llvm/test/tools/llvm-readobj/ELF/AArch64/aarch64-note-gnu-property.s @@ -5,7 +5,7 @@ // GNU: Displaying notes found in: .note.gnu.property // GNU-NEXT: Owner Data size Description // GNU-NEXT: GNU 0x00000010 NT_GNU_PROPERTY_TYPE_0 (property note) -// GNU-NEXT: Properties: aarch64 feature: BTI, PAC +// GNU-NEXT: Properties: aarch64 feature: BTI, PAC, GCS // LLVM: Notes [ // LLVM-NEXT: NoteSection { @@ -17,7 +17,7 @@ // LLVM-NEXT: Data size: 0x10 // LLVM-NEXT: Type: NT_GNU_PROPERTY_TYPE_0 (property note) // LLVM-NEXT: Property [ -// LLVM-NEXT: aarch64 feature: BTI, PAC +// LLVM-NEXT: aarch64 feature: BTI, PAC, GCS // LLVM-NEXT: ] // LLVM-NEXT: } // LLVM-NEXT: } @@ -30,9 +30,9 @@ .asciz "GNU" /* Name */ .p2align 3 begin: - /* BTI and PAC property note */ + /* BTI, PAC, and GCS property note */ .long 0xc0000000 /* Type: GNU_PROPERTY_AARCH64_FEATURE_1_AND */ .long 4 /* Data size */ - .long 3 /* BTI and PAC */ + .long 7 /* BTI, PAC, GCS */ .p2align 3 /* Align to 8 byte for 64 bit */ end: diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp b/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp index 2d396df7337f..7bb0218ed533 100644 --- a/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp +++ b/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp @@ -25,6 +25,7 @@ #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/Program.h" #include "llvm/Support/Signals.h" +#include "llvm/Support/SystemZ/zOSSupport.h" #ifdef __linux__ #ifdef HAVE_LIBPFM diff --git a/llvm/tools/llvm-exegesis/lib/Error.cpp b/llvm/tools/llvm-exegesis/lib/Error.cpp index d29c41385670..e7e153ac20ea 100644 --- a/llvm/tools/llvm-exegesis/lib/Error.cpp +++ b/llvm/tools/llvm-exegesis/lib/Error.cpp @@ -9,6 +9,7 @@ #include "Error.h" #ifdef LLVM_ON_UNIX +#include "llvm/Support/SystemZ/zOSSupport.h" #include <string.h> #endif // LLVM_ON_UNIX diff --git a/llvm/tools/llvm-readobj/ELFDumper.cpp b/llvm/tools/llvm-readobj/ELFDumper.cpp index 23f35fa6dfdb..3cf7c5a3b189 100644 --- a/llvm/tools/llvm-readobj/ELFDumper.cpp +++ b/llvm/tools/llvm-readobj/ELFDumper.cpp @@ -57,6 +57,7 @@ #include "llvm/Support/RISCVAttributeParser.h" #include "llvm/Support/RISCVAttributes.h" #include "llvm/Support/ScopedPrinter.h" +#include "llvm/Support/SystemZ/zOSSupport.h" #include "llvm/Support/raw_ostream.h" #include <algorithm> #include <cinttypes> @@ -5129,6 +5130,7 @@ static std::string getGNUProperty(uint32_t Type, uint32_t DataSize, if (Type == GNU_PROPERTY_AARCH64_FEATURE_1_AND) { DumpBit(GNU_PROPERTY_AARCH64_FEATURE_1_BTI, "BTI"); DumpBit(GNU_PROPERTY_AARCH64_FEATURE_1_PAC, "PAC"); + DumpBit(GNU_PROPERTY_AARCH64_FEATURE_1_GCS, "GCS"); } else { DumpBit(GNU_PROPERTY_X86_FEATURE_1_IBT, "IBT"); DumpBit(GNU_PROPERTY_X86_FEATURE_1_SHSTK, "SHSTK"); diff --git a/llvm/tools/llvm-readobj/ObjDumper.cpp b/llvm/tools/llvm-readobj/ObjDumper.cpp index 6dde3725b4d6..59060ac217e3 100644 --- a/llvm/tools/llvm-readobj/ObjDumper.cpp +++ b/llvm/tools/llvm-readobj/ObjDumper.cpp @@ -18,6 +18,7 @@ #include "llvm/Support/Error.h" #include "llvm/Support/FormatVariadic.h" #include "llvm/Support/ScopedPrinter.h" +#include "llvm/Support/SystemZ/zOSSupport.h" #include "llvm/Support/raw_ostream.h" #include <map> diff --git a/llvm/tools/obj2yaml/macho2yaml.cpp b/llvm/tools/obj2yaml/macho2yaml.cpp index c006c0d2cbea..cdd871e8c1d6 100644 --- a/llvm/tools/obj2yaml/macho2yaml.cpp +++ b/llvm/tools/obj2yaml/macho2yaml.cpp @@ -15,6 +15,7 @@ #include "llvm/Support/Error.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/LEB128.h" +#include "llvm/Support/SystemZ/zOSSupport.h" #include <string.h> // for memcpy diff --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp index 62081fc01b13..b6068513d230 100644 --- a/llvm/tools/opt/opt.cpp +++ b/llvm/tools/opt/opt.cpp @@ -356,7 +356,7 @@ static bool shouldPinPassToLegacyPM(StringRef Pass) { "expand-reductions", "indirectbr-expand", "generic-to-nvvm", - "expandmemcmp", + "expand-memcmp", "loop-reduce", "lower-amx-type", "lower-amx-intrinsics", @@ -422,7 +422,7 @@ int main(int argc, char **argv) { // supported. initializeExpandLargeDivRemLegacyPassPass(Registry); initializeExpandLargeFpConvertLegacyPassPass(Registry); - initializeExpandMemCmpPassPass(Registry); + initializeExpandMemCmpLegacyPassPass(Registry); initializeScalarizeMaskedMemIntrinLegacyPassPass(Registry); initializeSelectOptimizePass(Registry); initializeCallBrPreparePass(Registry); @@ -434,7 +434,7 @@ int main(int argc, char **argv) { initializeSjLjEHPreparePass(Registry); initializePreISelIntrinsicLoweringLegacyPassPass(Registry); initializeGlobalMergePass(Registry); - initializeIndirectBrExpandPassPass(Registry); + initializeIndirectBrExpandLegacyPassPass(Registry); initializeInterleavedLoadCombinePass(Registry); initializeInterleavedAccessPass(Registry); initializeUnreachableBlockElimLegacyPassPass(Registry); diff --git a/llvm/unittests/Support/CMakeLists.txt b/llvm/unittests/Support/CMakeLists.txt index e1bf793536b6..df35a7b7f362 100644 --- a/llvm/unittests/Support/CMakeLists.txt +++ b/llvm/unittests/Support/CMakeLists.txt @@ -103,6 +103,7 @@ add_llvm_unittest(SupportTests raw_ostream_test.cpp raw_pwrite_stream_test.cpp raw_sha1_ostream_test.cpp + raw_socket_stream_test.cpp xxhashTest.cpp DEPENDS diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index 549964eed555..3de14907899e 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -736,7 +736,7 @@ R"(All available -march extensions for RISC-V xventanacondops 1.0 Experimental extensions - zicfilp 0.2 This is a long dummy description + zicfilp 0.4 This is a long dummy description zicond 1.0 zacas 1.0 zfbfmin 0.8 diff --git a/llvm/unittests/Support/raw_socket_stream_test.cpp b/llvm/unittests/Support/raw_socket_stream_test.cpp new file mode 100644 index 000000000000..53eb86ae45d2 --- /dev/null +++ b/llvm/unittests/Support/raw_socket_stream_test.cpp @@ -0,0 +1,52 @@ +#include "llvm/ADT/SmallString.h" +#include "llvm/Config/llvm-config.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/FileUtilities.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Testing/Support/Error.h" +#include "gtest/gtest.h" +#include <future> +#include <iostream> +#include <stdlib.h> + +using namespace llvm; + +namespace { + +TEST(raw_socket_streamTest, CLIENT_TO_SERVER_AND_SERVER_TO_CLIENT) { + SmallString<100> SocketPath; + llvm::sys::fs::createUniquePath("test_raw_socket_stream.sock", SocketPath, + true); + + char Bytes[8]; + + Expected<ListeningSocket> MaybeServerListener = + ListeningSocket::createUnix(SocketPath); + ASSERT_THAT_EXPECTED(MaybeServerListener, llvm::Succeeded()); + + ListeningSocket ServerListener = std::move(*MaybeServerListener); + + Expected<std::unique_ptr<raw_socket_stream>> MaybeClient = + raw_socket_stream::createConnectedUnix(SocketPath); + ASSERT_THAT_EXPECTED(MaybeClient, llvm::Succeeded()); + + raw_socket_stream &Client = **MaybeClient; + + Expected<std::unique_ptr<raw_socket_stream>> MaybeServer = + ServerListener.accept(); + ASSERT_THAT_EXPECTED(MaybeServer, llvm::Succeeded()); + + raw_socket_stream &Server = **MaybeServer; + + Client << "01234567"; + Client.flush(); + + ssize_t BytesRead = Server.read(Bytes, 8); + + std::string string(Bytes, 8); + + ASSERT_EQ(8, BytesRead); + ASSERT_EQ("01234567", string); +} +} // namespace
\ No newline at end of file diff --git a/llvm/utils/TableGen/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/GlobalISelMatchTable.cpp index 481f3f16e013..349598266aa9 100644 --- a/llvm/utils/TableGen/GlobalISelMatchTable.cpp +++ b/llvm/utils/TableGen/GlobalISelMatchTable.cpp @@ -11,6 +11,7 @@ #include "CodeGenRegisters.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/LEB128.h" #include "llvm/Support/ScopedPrinter.h" #include "llvm/Support/raw_ostream.h" #include "llvm/TableGen/Error.h" @@ -39,10 +40,46 @@ std::string getEnumNameForPredicate(const TreePredicateFn &Predicate) { std::string getMatchOpcodeForImmPredicate(const TreePredicateFn &Predicate) { return "GIM_Check" + Predicate.getImmTypeIdentifier().str() + "ImmPredicate"; } + +// GIMT_Encode2/4/8 +constexpr StringLiteral EncodeMacroName = "GIMT_Encode"; + } // namespace //===- Helpers ------------------------------------------------------------===// +void emitEncodingMacrosDef(raw_ostream &OS) { + OS << "#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__\n" + << "#define " << EncodeMacroName << "2(Val)" + << " uint8_t(Val), uint8_t((uint16_t)Val >> 8)\n" + << "#define " << EncodeMacroName << "4(Val)" + << " uint8_t(Val), uint8_t((uint32_t)Val >> 8), " + "uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 24)\n" + << "#define " << EncodeMacroName << "8(Val)" + << " uint8_t(Val), uint8_t((uint64_t)Val >> 8), " + "uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 24), " + "uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 40), " + "uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 56)\n" + << "#else\n" + << "#define " << EncodeMacroName << "2(Val)" + << " uint8_t((uint16_t)Val >> 8), uint8_t(Val)\n" + << "#define " << EncodeMacroName << "4(Val)" + << " uint8_t((uint32_t)Val >> 24), uint8_t((uint32_t)Val >> 16), " + "uint8_t((uint32_t)Val >> 8), uint8_t(Val)\n" + << "#define " << EncodeMacroName << "8(Val)" + << " uint8_t((uint64_t)Val >> 56), uint8_t((uint64_t)Val >> 48), " + "uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 32), " + "uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 16), " + "uint8_t((uint64_t)Val >> 8), uint8_t(Val)\n" + << "#endif\n"; +} + +void emitEncodingMacrosUndef(raw_ostream &OS) { + OS << "#undef " << EncodeMacroName << "2\n" + << "#undef " << EncodeMacroName << "4\n" + << "#undef " << EncodeMacroName << "8\n"; +} + std::string getNameForFeatureBitset(const std::vector<Record *> &FeatureBitset, int HwModeIdx) { std::string Name = "GIFBS"; @@ -111,6 +148,12 @@ template std::vector<Matcher *> optimizeRules<SwitchMatcher>( ArrayRef<Matcher *> Rules, std::vector<std::unique_ptr<Matcher>> &MatcherStorage); +static std::string getEncodedEmitStr(StringRef NamedValue, unsigned NumBytes) { + if (NumBytes == 2 || NumBytes == 4 || NumBytes == 8) + return (EncodeMacroName + Twine(NumBytes) + "(" + NamedValue + ")").str(); + llvm_unreachable("Unsupported number of bytes!"); +} + //===- Global Data --------------------------------------------------------===// std::set<LLTCodeGen> KnownTypes; @@ -127,7 +170,11 @@ void MatchTableRecord::emit(raw_ostream &OS, bool LineBreakIsNextAfterThis, if (Flags & MTRF_Comment) OS << (UseLineComment ? "// " : "/*"); - OS << EmitStr; + if (NumElements > 1 && !(Flags & (MTRF_PreEncoded | MTRF_Comment))) + OS << getEncodedEmitStr(EmitStr, NumElements); + else + OS << EmitStr; + if (Flags & MTRF_Label) OS << ": @" << Table.getLabelIndex(LabelID); @@ -137,7 +184,9 @@ void MatchTableRecord::emit(raw_ostream &OS, bool LineBreakIsNextAfterThis, if (Flags & MTRF_JumpTarget) { if (Flags & MTRF_Comment) OS << " "; - OS << Table.getLabelIndex(LabelID); + // TODO: Could encode this AOT to speed up build of generated file + OS << getEncodedEmitStr(llvm::to_string(Table.getLabelIndex(LabelID)), + NumElements); } if (Flags & MTRF_CommaFollows) { @@ -172,33 +221,66 @@ MatchTableRecord MatchTable::Opcode(StringRef Opcode, int IndentAdjust) { MatchTableRecord::MTRF_CommaFollows | ExtraFlags); } -MatchTableRecord MatchTable::NamedValue(StringRef NamedValue) { - return MatchTableRecord(std::nullopt, NamedValue, 1, +MatchTableRecord MatchTable::NamedValue(unsigned NumBytes, + StringRef NamedValue) { + return MatchTableRecord(std::nullopt, NamedValue, NumBytes, MatchTableRecord::MTRF_CommaFollows); } -MatchTableRecord MatchTable::NamedValue(StringRef NamedValue, +MatchTableRecord MatchTable::NamedValue(unsigned NumBytes, StringRef NamedValue, int64_t RawValue) { - return MatchTableRecord(std::nullopt, NamedValue, 1, + return MatchTableRecord(std::nullopt, NamedValue, NumBytes, MatchTableRecord::MTRF_CommaFollows, RawValue); } -MatchTableRecord MatchTable::NamedValue(StringRef Namespace, +MatchTableRecord MatchTable::NamedValue(unsigned NumBytes, StringRef Namespace, StringRef NamedValue) { return MatchTableRecord(std::nullopt, (Namespace + "::" + NamedValue).str(), - 1, MatchTableRecord::MTRF_CommaFollows); + NumBytes, MatchTableRecord::MTRF_CommaFollows); } -MatchTableRecord MatchTable::NamedValue(StringRef Namespace, +MatchTableRecord MatchTable::NamedValue(unsigned NumBytes, StringRef Namespace, StringRef NamedValue, int64_t RawValue) { return MatchTableRecord(std::nullopt, (Namespace + "::" + NamedValue).str(), - 1, MatchTableRecord::MTRF_CommaFollows, RawValue); + NumBytes, MatchTableRecord::MTRF_CommaFollows, + RawValue); +} + +MatchTableRecord MatchTable::IntValue(unsigned NumBytes, int64_t IntValue) { + assert(isUIntN(NumBytes * 8, IntValue) || isIntN(NumBytes * 8, IntValue)); + auto Str = llvm::to_string(IntValue); + if (NumBytes == 1 && IntValue < 0) + Str = "uint8_t(" + Str + ")"; + // TODO: Could optimize this directly to save the compiler some work when + // building the file + return MatchTableRecord(std::nullopt, Str, NumBytes, + MatchTableRecord::MTRF_CommaFollows); } -MatchTableRecord MatchTable::IntValue(int64_t IntValue) { - return MatchTableRecord(std::nullopt, llvm::to_string(IntValue), 1, - MatchTableRecord::MTRF_CommaFollows); +MatchTableRecord MatchTable::ULEB128Value(uint64_t IntValue) { + uint8_t Buffer[10]; + unsigned Len = encodeULEB128(IntValue, Buffer); + + // Simple case (most common) + if (Len == 1) { + return MatchTableRecord(std::nullopt, llvm::to_string((unsigned)Buffer[0]), + 1, MatchTableRecord::MTRF_CommaFollows); + } + + // Print it as, e.g. /* -123456 (*/, 0xC0, 0xBB, 0x78 /*)*/ + std::string Str; + raw_string_ostream OS(Str); + OS << "/* " << llvm::to_string(IntValue) << "(*/"; + for (unsigned K = 0; K < Len; ++K) { + if (K) + OS << ", "; + OS << "0x" << llvm::toHex({Buffer[K]}); + } + OS << "/*)*/"; + return MatchTableRecord(std::nullopt, Str, Len, + MatchTableRecord::MTRF_CommaFollows | + MatchTableRecord::MTRF_PreEncoded); } MatchTableRecord MatchTable::Label(unsigned LabelID) { @@ -209,7 +291,7 @@ MatchTableRecord MatchTable::Label(unsigned LabelID) { } MatchTableRecord MatchTable::JumpTarget(unsigned LabelID) { - return MatchTableRecord(LabelID, "Label " + llvm::to_string(LabelID), 1, + return MatchTableRecord(LabelID, "Label " + llvm::to_string(LabelID), 4, MatchTableRecord::MTRF_JumpTarget | MatchTableRecord::MTRF_Comment | MatchTableRecord::MTRF_CommaFollows); @@ -219,7 +301,7 @@ void MatchTable::emitUse(raw_ostream &OS) const { OS << "MatchTable" << ID; } void MatchTable::emitDeclaration(raw_ostream &OS) const { unsigned Indentation = 4; - OS << " constexpr static int64_t MatchTable" << ID << "[] = {"; + OS << " constexpr static uint8_t MatchTable" << ID << "[] = {"; LineBreak.emit(OS, true, *this); OS << std::string(Indentation, ' '); @@ -243,7 +325,7 @@ void MatchTable::emitDeclaration(raw_ostream &OS) const { if (I->Flags & MatchTableRecord::MTRF_Outdent) Indentation -= 2; } - OS << "}; // Size: " << (CurrentSize * 8) << " bytes\n"; + OS << "}; // Size: " << CurrentSize << " bytes\n"; } MatchTable MatchTable::buildTable(ArrayRef<Matcher *> Rules, bool WithCoverage, @@ -542,14 +624,14 @@ void SwitchMatcher::emitPredicateSpecificOpcodes(const PredicateMatcher &P, if (const auto *Condition = dyn_cast<InstructionOpcodeMatcher>(&P)) { Table << MatchTable::Opcode("GIM_SwitchOpcode") << MatchTable::Comment("MI") - << MatchTable::IntValue(Condition->getInsnVarID()); + << MatchTable::ULEB128Value(Condition->getInsnVarID()); return; } if (const auto *Condition = dyn_cast<LLTOperandMatcher>(&P)) { Table << MatchTable::Opcode("GIM_SwitchType") << MatchTable::Comment("MI") - << MatchTable::IntValue(Condition->getInsnVarID()) + << MatchTable::ULEB128Value(Condition->getInsnVarID()) << MatchTable::Comment("Op") - << MatchTable::IntValue(Condition->getOpIdx()); + << MatchTable::ULEB128Value(Condition->getOpIdx()); return; } @@ -574,8 +656,8 @@ void SwitchMatcher::emit(MatchTable &Table) { emitPredicateSpecificOpcodes(*Condition, Table); - Table << MatchTable::Comment("[") << MatchTable::IntValue(LowerBound) - << MatchTable::IntValue(UpperBound) << MatchTable::Comment(")") + Table << MatchTable::Comment("[") << MatchTable::IntValue(2, LowerBound) + << MatchTable::IntValue(2, UpperBound) << MatchTable::Comment(")") << MatchTable::Comment("default:") << MatchTable::JumpTarget(Default); int64_t J = LowerBound; @@ -583,7 +665,7 @@ void SwitchMatcher::emit(MatchTable &Table) { for (unsigned I = 0, E = Values.size(); I < E; ++I) { auto V = *VI++; while (J++ < V.getRawValue()) - Table << MatchTable::IntValue(0); + Table << MatchTable::IntValue(4, 0); V.turnIntoComment(); Table << MatchTable::LineBreak << V << MatchTable::JumpTarget(LabelIDs[I]); } @@ -865,14 +947,14 @@ void RuleMatcher::emit(MatchTable &Table) { if (!RequiredFeatures.empty() || HwModeIdx >= 0) { Table << MatchTable::Opcode("GIM_CheckFeatures") << MatchTable::NamedValue( - getNameForFeatureBitset(RequiredFeatures, HwModeIdx)) + 2, getNameForFeatureBitset(RequiredFeatures, HwModeIdx)) << MatchTable::LineBreak; } if (!RequiredSimplePredicates.empty()) { for (const auto &Pred : RequiredSimplePredicates) { Table << MatchTable::Opcode("GIM_CheckSimplePredicate") - << MatchTable::NamedValue(Pred) << MatchTable::LineBreak; + << MatchTable::NamedValue(2, Pred) << MatchTable::LineBreak; } } @@ -899,7 +981,7 @@ void RuleMatcher::emit(MatchTable &Table) { for (const auto &InsnID : InsnIDs) { // Reject the difficult cases until we have a more accurate check. Table << MatchTable::Opcode("GIM_CheckIsSafeToFold") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) << MatchTable::LineBreak; // FIXME: Emit checks to determine it's _actually_ safe to fold and/or @@ -948,8 +1030,8 @@ void RuleMatcher::emit(MatchTable &Table) { assert((Table.isWithCoverage() ? !Table.isCombiner() : true) && "Combiner tables don't support coverage!"); if (Table.isWithCoverage()) - Table << MatchTable::Opcode("GIR_Coverage") << MatchTable::IntValue(RuleID) - << MatchTable::LineBreak; + Table << MatchTable::Opcode("GIR_Coverage") + << MatchTable::IntValue(4, RuleID) << MatchTable::LineBreak; else if (!Table.isCombiner()) Table << MatchTable::Comment(("GIR_Coverage, " + Twine(RuleID) + ",").str()) << MatchTable::LineBreak; @@ -1035,12 +1117,13 @@ void SameOperandMatcher::emitPredicateOpcodes(MatchTable &Table, Table << MatchTable::Opcode(IgnoreCopies ? "GIM_CheckIsSameOperandIgnoreCopies" : "GIM_CheckIsSameOperand") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("OpIdx") << MatchTable::IntValue(OpIdx) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("OpIdx") << MatchTable::ULEB128Value(OpIdx) << MatchTable::Comment("OtherMI") - << MatchTable::IntValue(OtherInsnVarID) + << MatchTable::ULEB128Value(OtherInsnVarID) << MatchTable::Comment("OtherOpIdx") - << MatchTable::IntValue(OtherOM.getOpIdx()) << MatchTable::LineBreak; + << MatchTable::ULEB128Value(OtherOM.getOpIdx()) + << MatchTable::LineBreak; } //===- LLTOperandMatcher --------------------------------------------------===// @@ -1050,8 +1133,8 @@ std::map<LLTCodeGen, unsigned> LLTOperandMatcher::TypeIDValues; MatchTableRecord LLTOperandMatcher::getValue() const { const auto VI = TypeIDValues.find(Ty); if (VI == TypeIDValues.end()) - return MatchTable::NamedValue(getTy().getCxxEnumValue()); - return MatchTable::NamedValue(getTy().getCxxEnumValue(), VI->second); + return MatchTable::NamedValue(1, getTy().getCxxEnumValue()); + return MatchTable::NamedValue(1, getTy().getCxxEnumValue(), VI->second); } bool LLTOperandMatcher::hasValue() const { @@ -1063,8 +1146,8 @@ bool LLTOperandMatcher::hasValue() const { void LLTOperandMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckType") << MatchTable::Comment("MI") - << MatchTable::IntValue(InsnVarID) << MatchTable::Comment("Op") - << MatchTable::IntValue(OpIdx) << MatchTable::Comment("Type") + << MatchTable::ULEB128Value(InsnVarID) << MatchTable::Comment("Op") + << MatchTable::ULEB128Value(OpIdx) << MatchTable::Comment("Type") << getValue() << MatchTable::LineBreak; } @@ -1073,10 +1156,10 @@ void LLTOperandMatcher::emitPredicateOpcodes(MatchTable &Table, void PointerToAnyOperandMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckPointerToAny") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx) - << MatchTable::Comment("SizeInBits") << MatchTable::IntValue(SizeInBits) - << MatchTable::LineBreak; + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) + << MatchTable::Comment("SizeInBits") + << MatchTable::ULEB128Value(SizeInBits) << MatchTable::LineBreak; } //===- RecordNamedOperandMatcher ------------------------------------------===// @@ -1084,9 +1167,9 @@ void PointerToAnyOperandMatcher::emitPredicateOpcodes(MatchTable &Table, void RecordNamedOperandMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_RecordNamedOperand") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx) - << MatchTable::Comment("StoreIdx") << MatchTable::IntValue(StoreIdx) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) + << MatchTable::Comment("StoreIdx") << MatchTable::ULEB128Value(StoreIdx) << MatchTable::Comment("Name : " + Name) << MatchTable::LineBreak; } @@ -1096,9 +1179,9 @@ void RecordRegisterType::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { assert(Idx < 0 && "Temp types always have negative indexes!"); Table << MatchTable::Opcode("GIM_RecordRegType") << MatchTable::Comment("MI") - << MatchTable::IntValue(InsnVarID) << MatchTable::Comment("Op") - << MatchTable::IntValue(OpIdx) << MatchTable::Comment("TempTypeIdx") - << MatchTable::IntValue(Idx) << MatchTable::LineBreak; + << MatchTable::ULEB128Value(InsnVarID) << MatchTable::Comment("Op") + << MatchTable::ULEB128Value(OpIdx) << MatchTable::Comment("TempTypeIdx") + << MatchTable::IntValue(1, Idx) << MatchTable::LineBreak; } //===- ComplexPatternOperandMatcher ---------------------------------------===// @@ -1107,10 +1190,10 @@ void ComplexPatternOperandMatcher::emitPredicateOpcodes( MatchTable &Table, RuleMatcher &Rule) const { unsigned ID = getAllocatedTemporariesBaseID(); Table << MatchTable::Opcode("GIM_CheckComplexPattern") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx) - << MatchTable::Comment("Renderer") << MatchTable::IntValue(ID) - << MatchTable::NamedValue(("GICP_" + TheDef.getName()).str()) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) + << MatchTable::Comment("Renderer") << MatchTable::IntValue(2, ID) + << MatchTable::NamedValue(2, ("GICP_" + TheDef.getName()).str()) << MatchTable::LineBreak; } @@ -1128,10 +1211,10 @@ bool RegisterBankOperandMatcher::isIdentical(const PredicateMatcher &B) const { void RegisterBankOperandMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckRegBankForClass") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) << MatchTable::Comment("RC") - << MatchTable::NamedValue(RC.getQualifiedIdName()) + << MatchTable::NamedValue(2, RC.getQualifiedIdName()) << MatchTable::LineBreak; } @@ -1140,8 +1223,8 @@ void RegisterBankOperandMatcher::emitPredicateOpcodes(MatchTable &Table, void MBBOperandMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckIsMBB") << MatchTable::Comment("MI") - << MatchTable::IntValue(InsnVarID) << MatchTable::Comment("Op") - << MatchTable::IntValue(OpIdx) << MatchTable::LineBreak; + << MatchTable::ULEB128Value(InsnVarID) << MatchTable::Comment("Op") + << MatchTable::ULEB128Value(OpIdx) << MatchTable::LineBreak; } //===- ImmOperandMatcher --------------------------------------------------===// @@ -1149,18 +1232,20 @@ void MBBOperandMatcher::emitPredicateOpcodes(MatchTable &Table, void ImmOperandMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckIsImm") << MatchTable::Comment("MI") - << MatchTable::IntValue(InsnVarID) << MatchTable::Comment("Op") - << MatchTable::IntValue(OpIdx) << MatchTable::LineBreak; + << MatchTable::ULEB128Value(InsnVarID) << MatchTable::Comment("Op") + << MatchTable::ULEB128Value(OpIdx) << MatchTable::LineBreak; } //===- ConstantIntOperandMatcher ------------------------------------------===// void ConstantIntOperandMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { - Table << MatchTable::Opcode("GIM_CheckConstantInt") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx) - << MatchTable::IntValue(Value) << MatchTable::LineBreak; + const bool IsInt8 = isInt<8>(Value); + Table << MatchTable::Opcode(IsInt8 ? "GIM_CheckConstantInt8" + : "GIM_CheckConstantInt") + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) + << MatchTable::IntValue(IsInt8 ? 1 : 8, Value) << MatchTable::LineBreak; } //===- LiteralIntOperandMatcher -------------------------------------------===// @@ -1168,9 +1253,9 @@ void ConstantIntOperandMatcher::emitPredicateOpcodes(MatchTable &Table, void LiteralIntOperandMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckLiteralInt") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx) - << MatchTable::IntValue(Value) << MatchTable::LineBreak; + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) + << MatchTable::IntValue(8, Value) << MatchTable::LineBreak; } //===- CmpPredicateOperandMatcher -----------------------------------------===// @@ -1178,10 +1263,11 @@ void LiteralIntOperandMatcher::emitPredicateOpcodes(MatchTable &Table, void CmpPredicateOperandMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckCmpPredicate") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) << MatchTable::Comment("Predicate") - << MatchTable::NamedValue("CmpInst", PredName) << MatchTable::LineBreak; + << MatchTable::NamedValue(2, "CmpInst", PredName) + << MatchTable::LineBreak; } //===- IntrinsicIDOperandMatcher ------------------------------------------===// @@ -1189,9 +1275,9 @@ void CmpPredicateOperandMatcher::emitPredicateOpcodes(MatchTable &Table, void IntrinsicIDOperandMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckIntrinsicID") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx) - << MatchTable::NamedValue("Intrinsic::" + II->EnumName) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) + << MatchTable::NamedValue(2, "Intrinsic::" + II->EnumName) << MatchTable::LineBreak; } @@ -1200,10 +1286,10 @@ void IntrinsicIDOperandMatcher::emitPredicateOpcodes(MatchTable &Table, void OperandImmPredicateMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckImmOperandPredicate") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("MO") << MatchTable::IntValue(OpIdx) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("MO") << MatchTable::ULEB128Value(OpIdx) << MatchTable::Comment("Predicate") - << MatchTable::NamedValue(getEnumNameForPredicate(Predicate)) + << MatchTable::NamedValue(2, getEnumNameForPredicate(Predicate)) << MatchTable::LineBreak; } @@ -1304,9 +1390,9 @@ MatchTableRecord InstructionOpcodeMatcher::getInstValue(const CodeGenInstruction *I) const { const auto VI = OpcodeValues.find(I); if (VI != OpcodeValues.end()) - return MatchTable::NamedValue(I->Namespace, I->TheDef->getName(), + return MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName(), VI->second); - return MatchTable::NamedValue(I->Namespace, I->TheDef->getName()); + return MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName()); } void InstructionOpcodeMatcher::initOpcodeValuesMap( @@ -1324,9 +1410,9 @@ MatchTableRecord InstructionOpcodeMatcher::getValue() const { const CodeGenInstruction *I = Insts[0]; const auto VI = OpcodeValues.find(I); if (VI != OpcodeValues.end()) - return MatchTable::NamedValue(I->Namespace, I->TheDef->getName(), + return MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName(), VI->second); - return MatchTable::NamedValue(I->Namespace, I->TheDef->getName()); + return MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName()); } void InstructionOpcodeMatcher::emitPredicateOpcodes(MatchTable &Table, @@ -1334,7 +1420,7 @@ void InstructionOpcodeMatcher::emitPredicateOpcodes(MatchTable &Table, StringRef CheckType = Insts.size() == 1 ? "GIM_CheckOpcode" : "GIM_CheckOpcodeIsEither"; Table << MatchTable::Opcode(CheckType) << MatchTable::Comment("MI") - << MatchTable::IntValue(InsnVarID); + << MatchTable::ULEB128Value(InsnVarID); for (const CodeGenInstruction *I : Insts) Table << getInstValue(I); @@ -1381,9 +1467,9 @@ StringRef InstructionOpcodeMatcher::getOperandType(unsigned OpIdx) const { void InstructionNumOperandsMatcher::emitPredicateOpcodes( MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckNumOperands") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("Expected") << MatchTable::IntValue(NumOperands) - << MatchTable::LineBreak; + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("Expected") + << MatchTable::ULEB128Value(NumOperands) << MatchTable::LineBreak; } //===- InstructionImmPredicateMatcher -------------------------------------===// @@ -1399,9 +1485,9 @@ bool InstructionImmPredicateMatcher::isIdentical( void InstructionImmPredicateMatcher::emitPredicateOpcodes( MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode(getMatchOpcodeForImmPredicate(Predicate)) - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) << MatchTable::Comment("Predicate") - << MatchTable::NamedValue(getEnumNameForPredicate(Predicate)) + << MatchTable::NamedValue(2, getEnumNameForPredicate(Predicate)) << MatchTable::LineBreak; } @@ -1425,8 +1511,9 @@ void AtomicOrderingMMOPredicateMatcher::emitPredicateOpcodes( Opcode = "GIM_CheckAtomicOrderingWeakerThan"; Table << MatchTable::Opcode(Opcode) << MatchTable::Comment("MI") - << MatchTable::IntValue(InsnVarID) << MatchTable::Comment("Order") - << MatchTable::NamedValue(("(int64_t)AtomicOrdering::" + Order).str()) + << MatchTable::ULEB128Value(InsnVarID) << MatchTable::Comment("Order") + << MatchTable::NamedValue(1, + ("(uint8_t)AtomicOrdering::" + Order).str()) << MatchTable::LineBreak; } @@ -1435,9 +1522,9 @@ void AtomicOrderingMMOPredicateMatcher::emitPredicateOpcodes( void MemorySizePredicateMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckMemorySizeEqualTo") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("MMO") << MatchTable::IntValue(MMOIdx) - << MatchTable::Comment("Size") << MatchTable::IntValue(Size) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("MMO") << MatchTable::ULEB128Value(MMOIdx) + << MatchTable::Comment("Size") << MatchTable::IntValue(4, Size) << MatchTable::LineBreak; } @@ -1454,14 +1541,14 @@ bool MemoryAddressSpacePredicateMatcher::isIdentical( void MemoryAddressSpacePredicateMatcher::emitPredicateOpcodes( MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckMemoryAddressSpace") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) << MatchTable::Comment("MMO") - << MatchTable::IntValue(MMOIdx) + << MatchTable::ULEB128Value(MMOIdx) // Encode number of address spaces to expect. << MatchTable::Comment("NumAddrSpace") - << MatchTable::IntValue(AddrSpaces.size()); + << MatchTable::ULEB128Value(AddrSpaces.size()); for (unsigned AS : AddrSpaces) - Table << MatchTable::Comment("AddrSpace") << MatchTable::IntValue(AS); + Table << MatchTable::Comment("AddrSpace") << MatchTable::ULEB128Value(AS); Table << MatchTable::LineBreak; } @@ -1479,9 +1566,9 @@ bool MemoryAlignmentPredicateMatcher::isIdentical( void MemoryAlignmentPredicateMatcher::emitPredicateOpcodes( MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckMemoryAlignment") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("MMO") << MatchTable::IntValue(MMOIdx) - << MatchTable::Comment("MinAlign") << MatchTable::IntValue(MinAlign) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("MMO") << MatchTable::ULEB128Value(MMOIdx) + << MatchTable::Comment("MinAlign") << MatchTable::ULEB128Value(MinAlign) << MatchTable::LineBreak; } @@ -1501,9 +1588,9 @@ void MemoryVsLLTSizePredicateMatcher::emitPredicateOpcodes( Relation == EqualTo ? "GIM_CheckMemorySizeEqualToLLT" : Relation == GreaterThan ? "GIM_CheckMemorySizeGreaterThanLLT" : "GIM_CheckMemorySizeLessThanLLT") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("MMO") << MatchTable::IntValue(MMOIdx) - << MatchTable::Comment("OpIdx") << MatchTable::IntValue(OpIdx) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("MMO") << MatchTable::ULEB128Value(MMOIdx) + << MatchTable::Comment("OpIdx") << MatchTable::ULEB128Value(OpIdx) << MatchTable::LineBreak; } @@ -1516,7 +1603,7 @@ void VectorSplatImmPredicateMatcher::emitPredicateOpcodes( else Table << MatchTable::Opcode("GIM_CheckIsBuildVectorAllZeros"); - Table << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID); + Table << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID); Table << MatchTable::LineBreak; } @@ -1536,8 +1623,8 @@ bool GenericInstructionPredicateMatcher::isIdentical( void GenericInstructionPredicateMatcher::emitPredicateOpcodes( MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIM_CheckCxxInsnPredicate") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::Comment("FnId") << MatchTable::NamedValue(EnumVal) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::Comment("FnId") << MatchTable::NamedValue(2, EnumVal) << MatchTable::LineBreak; } @@ -1555,8 +1642,9 @@ bool MIFlagsInstructionPredicateMatcher::isIdentical( void MIFlagsInstructionPredicateMatcher::emitPredicateOpcodes( MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode(CheckNot ? "GIM_MIFlagsNot" : "GIM_MIFlags") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) - << MatchTable::NamedValue(join(Flags, " | ")) << MatchTable::LineBreak; + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) + << MatchTable::NamedValue(4, join(Flags, " | ")) + << MatchTable::LineBreak; } //===- InstructionMatcher -------------------------------------------------===// @@ -1700,9 +1788,10 @@ void InstructionOperandMatcher::emitCaptureOpcodes(MatchTable &Table, const bool IgnoreCopies = Flags & GISF_IgnoreCopies; Table << MatchTable::Opcode(IgnoreCopies ? "GIM_RecordInsnIgnoreCopies" : "GIM_RecordInsn") - << MatchTable::Comment("DefineMI") << MatchTable::IntValue(NewInsnVarID) - << MatchTable::Comment("MI") << MatchTable::IntValue(getInsnVarID()) - << MatchTable::Comment("OpIdx") << MatchTable::IntValue(getOpIdx()) + << MatchTable::Comment("DefineMI") + << MatchTable::ULEB128Value(NewInsnVarID) << MatchTable::Comment("MI") + << MatchTable::ULEB128Value(getInsnVarID()) + << MatchTable::Comment("OpIdx") << MatchTable::ULEB128Value(getOpIdx()) << MatchTable::Comment("MIs[" + llvm::to_string(NewInsnVarID) + "]") << MatchTable::LineBreak; } @@ -1732,9 +1821,11 @@ void CopyRenderer::emitRenderOpcodes(MatchTable &Table, const OperandMatcher &Operand = Rule.getOperandMatcher(SymbolicName); unsigned OldInsnVarID = Rule.getInsnVarID(Operand.getInstructionMatcher()); Table << MatchTable::Opcode("GIR_Copy") << MatchTable::Comment("NewInsnID") - << MatchTable::IntValue(NewInsnID) << MatchTable::Comment("OldInsnID") - << MatchTable::IntValue(OldInsnVarID) << MatchTable::Comment("OpIdx") - << MatchTable::IntValue(Operand.getOpIdx()) + << MatchTable::ULEB128Value(NewInsnID) + << MatchTable::Comment("OldInsnID") + << MatchTable::ULEB128Value(OldInsnVarID) + << MatchTable::Comment("OpIdx") + << MatchTable::ULEB128Value(Operand.getOpIdx()) << MatchTable::Comment(SymbolicName) << MatchTable::LineBreak; } @@ -1745,9 +1836,11 @@ void CopyPhysRegRenderer::emitRenderOpcodes(MatchTable &Table, const OperandMatcher &Operand = Rule.getPhysRegOperandMatcher(PhysReg); unsigned OldInsnVarID = Rule.getInsnVarID(Operand.getInstructionMatcher()); Table << MatchTable::Opcode("GIR_Copy") << MatchTable::Comment("NewInsnID") - << MatchTable::IntValue(NewInsnID) << MatchTable::Comment("OldInsnID") - << MatchTable::IntValue(OldInsnVarID) << MatchTable::Comment("OpIdx") - << MatchTable::IntValue(Operand.getOpIdx()) + << MatchTable::ULEB128Value(NewInsnID) + << MatchTable::Comment("OldInsnID") + << MatchTable::ULEB128Value(OldInsnVarID) + << MatchTable::Comment("OpIdx") + << MatchTable::ULEB128Value(Operand.getOpIdx()) << MatchTable::Comment(PhysReg->getName()) << MatchTable::LineBreak; } @@ -1758,11 +1851,14 @@ void CopyOrAddZeroRegRenderer::emitRenderOpcodes(MatchTable &Table, const OperandMatcher &Operand = Rule.getOperandMatcher(SymbolicName); unsigned OldInsnVarID = Rule.getInsnVarID(Operand.getInstructionMatcher()); Table << MatchTable::Opcode("GIR_CopyOrAddZeroReg") - << MatchTable::Comment("NewInsnID") << MatchTable::IntValue(NewInsnID) + << MatchTable::Comment("NewInsnID") + << MatchTable::ULEB128Value(NewInsnID) << MatchTable::Comment("OldInsnID") - << MatchTable::IntValue(OldInsnVarID) << MatchTable::Comment("OpIdx") - << MatchTable::IntValue(Operand.getOpIdx()) + << MatchTable::ULEB128Value(OldInsnVarID) + << MatchTable::Comment("OpIdx") + << MatchTable::ULEB128Value(Operand.getOpIdx()) << MatchTable::NamedValue( + 2, (ZeroRegisterDef->getValue("Namespace") ? ZeroRegisterDef->getValueAsString("Namespace") : ""), @@ -1778,9 +1874,10 @@ void CopyConstantAsImmRenderer::emitRenderOpcodes(MatchTable &Table, unsigned OldInsnVarID = Rule.getInsnVarID(InsnMatcher); Table << MatchTable::Opcode(Signed ? "GIR_CopyConstantAsSImm" : "GIR_CopyConstantAsUImm") - << MatchTable::Comment("NewInsnID") << MatchTable::IntValue(NewInsnID) + << MatchTable::Comment("NewInsnID") + << MatchTable::ULEB128Value(NewInsnID) << MatchTable::Comment("OldInsnID") - << MatchTable::IntValue(OldInsnVarID) + << MatchTable::ULEB128Value(OldInsnVarID) << MatchTable::Comment(SymbolicName) << MatchTable::LineBreak; } @@ -1791,9 +1888,10 @@ void CopyFConstantAsFPImmRenderer::emitRenderOpcodes(MatchTable &Table, InstructionMatcher &InsnMatcher = Rule.getInstructionMatcher(SymbolicName); unsigned OldInsnVarID = Rule.getInsnVarID(InsnMatcher); Table << MatchTable::Opcode("GIR_CopyFConstantAsFPImm") - << MatchTable::Comment("NewInsnID") << MatchTable::IntValue(NewInsnID) + << MatchTable::Comment("NewInsnID") + << MatchTable::ULEB128Value(NewInsnID) << MatchTable::Comment("OldInsnID") - << MatchTable::IntValue(OldInsnVarID) + << MatchTable::ULEB128Value(OldInsnVarID) << MatchTable::Comment(SymbolicName) << MatchTable::LineBreak; } @@ -1804,12 +1902,14 @@ void CopySubRegRenderer::emitRenderOpcodes(MatchTable &Table, const OperandMatcher &Operand = Rule.getOperandMatcher(SymbolicName); unsigned OldInsnVarID = Rule.getInsnVarID(Operand.getInstructionMatcher()); Table << MatchTable::Opcode("GIR_CopySubReg") - << MatchTable::Comment("NewInsnID") << MatchTable::IntValue(NewInsnID) + << MatchTable::Comment("NewInsnID") + << MatchTable::ULEB128Value(NewInsnID) << MatchTable::Comment("OldInsnID") - << MatchTable::IntValue(OldInsnVarID) << MatchTable::Comment("OpIdx") - << MatchTable::IntValue(Operand.getOpIdx()) + << MatchTable::ULEB128Value(OldInsnVarID) + << MatchTable::Comment("OpIdx") + << MatchTable::ULEB128Value(Operand.getOpIdx()) << MatchTable::Comment("SubRegIdx") - << MatchTable::IntValue(SubReg->EnumValue) + << MatchTable::IntValue(2, SubReg->EnumValue) << MatchTable::Comment(SymbolicName) << MatchTable::LineBreak; } @@ -1818,15 +1918,16 @@ void CopySubRegRenderer::emitRenderOpcodes(MatchTable &Table, void AddRegisterRenderer::emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIR_AddRegister") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID); + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID); if (RegisterDef->getName() != "zero_reg") { Table << MatchTable::NamedValue( + 2, (RegisterDef->getValue("Namespace") ? RegisterDef->getValueAsString("Namespace") : ""), RegisterDef->getName()); } else { - Table << MatchTable::NamedValue(Target.getRegNamespace(), "NoRegister"); + Table << MatchTable::NamedValue(2, Target.getRegNamespace(), "NoRegister"); } Table << MatchTable::Comment("AddRegisterRegFlags"); @@ -1834,9 +1935,9 @@ void AddRegisterRenderer::emitRenderOpcodes(MatchTable &Table, // really needed for a physical register reference. We can pack the // register and flags in a single field. if (IsDef) - Table << MatchTable::NamedValue("RegState::Define"); + Table << MatchTable::NamedValue(2, "RegState::Define"); else - Table << MatchTable::IntValue(0); + Table << MatchTable::IntValue(2, 0); Table << MatchTable::LineBreak; } @@ -1844,37 +1945,69 @@ void AddRegisterRenderer::emitRenderOpcodes(MatchTable &Table, void TempRegRenderer::emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const { + const bool NeedsFlags = (SubRegIdx || IsDef); if (SubRegIdx) { assert(!IsDef); Table << MatchTable::Opcode("GIR_AddTempSubRegister"); } else - Table << MatchTable::Opcode("GIR_AddTempRegister"); + Table << MatchTable::Opcode(NeedsFlags ? "GIR_AddTempRegister" + : "GIR_AddSimpleTempRegister"); - Table << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) - << MatchTable::Comment("TempRegID") << MatchTable::IntValue(TempRegID) - << MatchTable::Comment("TempRegFlags"); + Table << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) + << MatchTable::Comment("TempRegID") + << MatchTable::ULEB128Value(TempRegID); + if (!NeedsFlags) { + Table << MatchTable::LineBreak; + return; + } + + Table << MatchTable::Comment("TempRegFlags"); if (IsDef) { SmallString<32> RegFlags; RegFlags += "RegState::Define"; if (IsDead) RegFlags += "|RegState::Dead"; - Table << MatchTable::NamedValue(RegFlags); + Table << MatchTable::NamedValue(2, RegFlags); } else - Table << MatchTable::IntValue(0); + Table << MatchTable::IntValue(2, 0); if (SubRegIdx) - Table << MatchTable::NamedValue(SubRegIdx->getQualifiedName()); + Table << MatchTable::NamedValue(2, SubRegIdx->getQualifiedName()); Table << MatchTable::LineBreak; } +//===- ImmRenderer --------------------------------------------------------===// + +void ImmRenderer::emitAddImm(MatchTable &Table, RuleMatcher &RM, + unsigned InsnID, int64_t Imm, StringRef ImmName) { + const bool IsInt8 = isInt<8>(Imm); + + Table << MatchTable::Opcode(IsInt8 ? "GIR_AddImm8" : "GIR_AddImm") + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) + << MatchTable::Comment(ImmName) + << MatchTable::IntValue(IsInt8 ? 1 : 8, Imm) << MatchTable::LineBreak; +} + +void ImmRenderer::emitRenderOpcodes(MatchTable &Table, + RuleMatcher &Rule) const { + if (CImmLLT) { + assert(Table.isCombiner() && + "ConstantInt immediate are only for combiners!"); + Table << MatchTable::Opcode("GIR_AddCImm") << MatchTable::Comment("InsnID") + << MatchTable::ULEB128Value(InsnID) << MatchTable::Comment("Type") + << *CImmLLT << MatchTable::Comment("Imm") + << MatchTable::IntValue(8, Imm) << MatchTable::LineBreak; + } else + emitAddImm(Table, Rule, InsnID, Imm); +} + //===- SubRegIndexRenderer ------------------------------------------------===// void SubRegIndexRenderer::emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const { - Table << MatchTable::Opcode("GIR_AddImm") << MatchTable::Comment("InsnID") - << MatchTable::IntValue(InsnID) << MatchTable::Comment("SubRegIndex") - << MatchTable::IntValue(SubRegIdx->EnumValue) << MatchTable::LineBreak; + ImmRenderer::emitAddImm(Table, Rule, InsnID, SubRegIdx->EnumValue, + "SubRegIndex"); } //===- RenderComplexPatternOperand ----------------------------------------===// @@ -1885,15 +2018,15 @@ void RenderComplexPatternOperand::emitRenderOpcodes(MatchTable &Table, SubOperand ? (SubReg ? "GIR_ComplexSubOperandSubRegRenderer" : "GIR_ComplexSubOperandRenderer") : "GIR_ComplexRenderer") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) << MatchTable::Comment("RendererID") - << MatchTable::IntValue(RendererID); + << MatchTable::IntValue(2, RendererID); if (SubOperand) Table << MatchTable::Comment("SubOperand") - << MatchTable::IntValue(*SubOperand); + << MatchTable::ULEB128Value(*SubOperand); if (SubReg) Table << MatchTable::Comment("SubRegIdx") - << MatchTable::IntValue(SubReg->EnumValue); + << MatchTable::IntValue(2, SubReg->EnumValue); Table << MatchTable::Comment(SymbolicName) << MatchTable::LineBreak; } @@ -1904,11 +2037,12 @@ void CustomRenderer::emitRenderOpcodes(MatchTable &Table, InstructionMatcher &InsnMatcher = Rule.getInstructionMatcher(SymbolicName); unsigned OldInsnVarID = Rule.getInsnVarID(InsnMatcher); Table << MatchTable::Opcode("GIR_CustomRenderer") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) << MatchTable::Comment("OldInsnID") - << MatchTable::IntValue(OldInsnVarID) << MatchTable::Comment("Renderer") - << MatchTable::NamedValue("GICR_" + - Renderer.getValueAsString("RendererFn").str()) + << MatchTable::ULEB128Value(OldInsnVarID) + << MatchTable::Comment("Renderer") + << MatchTable::NamedValue( + 2, "GICR_" + Renderer.getValueAsString("RendererFn").str()) << MatchTable::Comment(SymbolicName) << MatchTable::LineBreak; } @@ -1918,14 +2052,14 @@ void CustomOperandRenderer::emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const { const OperandMatcher &OpdMatcher = Rule.getOperandMatcher(SymbolicName); Table << MatchTable::Opcode("GIR_CustomOperandRenderer") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) << MatchTable::Comment("OldInsnID") - << MatchTable::IntValue(OpdMatcher.getInsnVarID()) + << MatchTable::ULEB128Value(OpdMatcher.getInsnVarID()) << MatchTable::Comment("OpIdx") - << MatchTable::IntValue(OpdMatcher.getOpIdx()) + << MatchTable::ULEB128Value(OpdMatcher.getOpIdx()) << MatchTable::Comment("OperandRenderer") - << MatchTable::NamedValue("GICR_" + - Renderer.getValueAsString("RendererFn").str()) + << MatchTable::NamedValue( + 2, "GICR_" + Renderer.getValueAsString("RendererFn").str()) << MatchTable::Comment(SymbolicName) << MatchTable::LineBreak; } @@ -1934,7 +2068,7 @@ void CustomOperandRenderer::emitRenderOpcodes(MatchTable &Table, void CustomCXXAction::emitActionOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIR_CustomAction") - << MatchTable::NamedValue(FnEnumName) << MatchTable::LineBreak; + << MatchTable::NamedValue(2, FnEnumName) << MatchTable::LineBreak; } //===- BuildMIAction ------------------------------------------------------===// @@ -1977,23 +2111,23 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table, const auto AddMIFlags = [&]() { for (const InstructionMatcher *IM : CopiedFlags) { Table << MatchTable::Opcode("GIR_CopyMIFlags") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) << MatchTable::Comment("OldInsnID") - << MatchTable::IntValue(IM->getInsnVarID()) + << MatchTable::ULEB128Value(IM->getInsnVarID()) << MatchTable::LineBreak; } if (!SetFlags.empty()) { Table << MatchTable::Opcode("GIR_SetMIFlags") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) - << MatchTable::NamedValue(join(SetFlags, " | ")) + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) + << MatchTable::NamedValue(4, join(SetFlags, " | ")) << MatchTable::LineBreak; } if (!UnsetFlags.empty()) { Table << MatchTable::Opcode("GIR_UnsetMIFlags") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) - << MatchTable::NamedValue(join(UnsetFlags, " | ")) + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) + << MatchTable::NamedValue(4, join(UnsetFlags, " | ")) << MatchTable::LineBreak; } }; @@ -2004,11 +2138,11 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table, unsigned RecycleInsnID = Rule.getInsnVarID(*Matched); Table << MatchTable::Opcode("GIR_MutateOpcode") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) << MatchTable::Comment("RecycleInsnID") - << MatchTable::IntValue(RecycleInsnID) + << MatchTable::ULEB128Value(RecycleInsnID) << MatchTable::Comment("Opcode") - << MatchTable::NamedValue(I->Namespace, I->TheDef->getName()) + << MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName()) << MatchTable::LineBreak; if (!I->ImplicitDefs.empty() || !I->ImplicitUses.empty()) { @@ -2018,10 +2152,11 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table, : ""; const bool IsDead = DeadImplicitDefs.contains(Def); Table << MatchTable::Opcode("GIR_AddImplicitDef") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) - << MatchTable::NamedValue(Namespace, Def->getName()) - << (IsDead ? MatchTable::NamedValue("RegState", "Dead") - : MatchTable::IntValue(0)) + << MatchTable::Comment("InsnID") + << MatchTable::ULEB128Value(InsnID) + << MatchTable::NamedValue(2, Namespace, Def->getName()) + << (IsDead ? MatchTable::NamedValue(2, "RegState", "Dead") + : MatchTable::IntValue(2, 0)) << MatchTable::LineBreak; } for (auto *Use : I->ImplicitUses) { @@ -2029,8 +2164,9 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table, ? Use->getValueAsString("Namespace") : ""; Table << MatchTable::Opcode("GIR_AddImplicitUse") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) - << MatchTable::NamedValue(Namespace, Use->getName()) + << MatchTable::Comment("InsnID") + << MatchTable::ULEB128Value(InsnID) + << MatchTable::NamedValue(2, Namespace, Use->getName()) << MatchTable::LineBreak; } } @@ -2043,8 +2179,8 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table, // mutation due to commutative operations. Table << MatchTable::Opcode("GIR_BuildMI") << MatchTable::Comment("InsnID") - << MatchTable::IntValue(InsnID) << MatchTable::Comment("Opcode") - << MatchTable::NamedValue(I->Namespace, I->TheDef->getName()) + << MatchTable::ULEB128Value(InsnID) << MatchTable::Comment("Opcode") + << MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName()) << MatchTable::LineBreak; for (const auto &Renderer : OperandRenderers) Renderer->emitRenderOpcodes(Table, Rule); @@ -2055,17 +2191,14 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table, if (DeadImplicitDefs.contains(Def)) { Table << MatchTable::Opcode("GIR_SetImplicitDefDead") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) << MatchTable::Comment( ("OpIdx for " + Namespace + "::" + Def->getName() + "").str()) - << MatchTable::IntValue(OpIdx) << MatchTable::LineBreak; + << MatchTable::ULEB128Value(OpIdx) << MatchTable::LineBreak; } } if (I->mayLoad || I->mayStore) { - Table << MatchTable::Opcode("GIR_MergeMemOperands") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) - << MatchTable::Comment("MergeInsnID's"); // Emit the ID's for all the instructions that are matched by this rule. // TODO: Limit this to matched instructions that mayLoad/mayStore or have // some other means of having a memoperand. Also limit this to @@ -2073,14 +2206,20 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table, // example, (G_SEXT (G_LOAD x)) that results in separate load and // sign-extend instructions shouldn't put the memoperand on the // sign-extend since it has no effect there. + std::vector<unsigned> MergeInsnIDs; for (const auto &IDMatcherPair : Rule.defined_insn_vars()) MergeInsnIDs.push_back(IDMatcherPair.second); llvm::sort(MergeInsnIDs); + + Table << MatchTable::Opcode("GIR_MergeMemOperands") + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) + << MatchTable::Comment("NumInsns") + << MatchTable::IntValue(1, MergeInsnIDs.size()) + << MatchTable::Comment("MergeInsnID's"); for (const auto &MergeInsnID : MergeInsnIDs) - Table << MatchTable::IntValue(MergeInsnID); - Table << MatchTable::NamedValue("GIU_MergeMemOperands_EndOfList") - << MatchTable::LineBreak; + Table << MatchTable::ULEB128Value(MergeInsnID); + Table << MatchTable::LineBreak; } AddMIFlags(); @@ -2097,9 +2236,9 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table, void BuildConstantAction::emitActionOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIR_BuildConstant") - << MatchTable::Comment("TempRegID") << MatchTable::IntValue(TempRegID) - << MatchTable::Comment("Val") << MatchTable::IntValue(Val) - << MatchTable::LineBreak; + << MatchTable::Comment("TempRegID") + << MatchTable::ULEB128Value(TempRegID) << MatchTable::Comment("Val") + << MatchTable::IntValue(8, Val) << MatchTable::LineBreak; } //===- EraseInstAction ----------------------------------------------------===// @@ -2111,7 +2250,7 @@ void EraseInstAction::emitActionOpcodes(MatchTable &Table, RuleMatcher &Rule, return; Table << MatchTable::Opcode("GIR_EraseFromParent") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) << MatchTable::LineBreak; } @@ -2128,10 +2267,12 @@ void ReplaceRegAction::emitAdditionalPredicates(MatchTable &Table, return; Table << MatchTable::Opcode("GIM_CheckCanReplaceReg") - << MatchTable::Comment("OldInsnID") << MatchTable::IntValue(OldInsnID) - << MatchTable::Comment("OldOpIdx") << MatchTable::IntValue(OldOpIdx) - << MatchTable::Comment("NewInsnId") << MatchTable::IntValue(NewInsnId) - << MatchTable::Comment("NewOpIdx") << MatchTable::IntValue(NewOpIdx) + << MatchTable::Comment("OldInsnID") + << MatchTable::ULEB128Value(OldInsnID) + << MatchTable::Comment("OldOpIdx") << MatchTable::ULEB128Value(OldOpIdx) + << MatchTable::Comment("NewInsnId") + << MatchTable::ULEB128Value(NewInsnId) + << MatchTable::Comment("NewOpIdx") << MatchTable::ULEB128Value(NewOpIdx) << MatchTable::LineBreak; } @@ -2139,17 +2280,22 @@ void ReplaceRegAction::emitActionOpcodes(MatchTable &Table, RuleMatcher &Rule) const { if (TempRegID != (unsigned)-1) { Table << MatchTable::Opcode("GIR_ReplaceRegWithTempReg") - << MatchTable::Comment("OldInsnID") << MatchTable::IntValue(OldInsnID) - << MatchTable::Comment("OldOpIdx") << MatchTable::IntValue(OldOpIdx) - << MatchTable::Comment("TempRegID") << MatchTable::IntValue(TempRegID) - << MatchTable::LineBreak; + << MatchTable::Comment("OldInsnID") + << MatchTable::ULEB128Value(OldInsnID) + << MatchTable::Comment("OldOpIdx") + << MatchTable::ULEB128Value(OldOpIdx) + << MatchTable::Comment("TempRegID") + << MatchTable::ULEB128Value(TempRegID) << MatchTable::LineBreak; } else { Table << MatchTable::Opcode("GIR_ReplaceReg") - << MatchTable::Comment("OldInsnID") << MatchTable::IntValue(OldInsnID) - << MatchTable::Comment("OldOpIdx") << MatchTable::IntValue(OldOpIdx) - << MatchTable::Comment("NewInsnId") << MatchTable::IntValue(NewInsnId) - << MatchTable::Comment("NewOpIdx") << MatchTable::IntValue(NewOpIdx) - << MatchTable::LineBreak; + << MatchTable::Comment("OldInsnID") + << MatchTable::ULEB128Value(OldInsnID) + << MatchTable::Comment("OldOpIdx") + << MatchTable::ULEB128Value(OldOpIdx) + << MatchTable::Comment("NewInsnId") + << MatchTable::ULEB128Value(NewInsnId) + << MatchTable::Comment("NewOpIdx") + << MatchTable::ULEB128Value(NewOpIdx) << MatchTable::LineBreak; } } @@ -2158,9 +2304,9 @@ void ReplaceRegAction::emitActionOpcodes(MatchTable &Table, void ConstrainOperandToRegClassAction::emitActionOpcodes( MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIR_ConstrainOperandRC") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) - << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx) - << MatchTable::NamedValue(RC.getQualifiedIdName()) + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) + << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) + << MatchTable::NamedValue(2, RC.getQualifiedIdName()) << MatchTable::LineBreak; } @@ -2169,8 +2315,9 @@ void ConstrainOperandToRegClassAction::emitActionOpcodes( void MakeTempRegisterAction::emitActionOpcodes(MatchTable &Table, RuleMatcher &Rule) const { Table << MatchTable::Opcode("GIR_MakeTempReg") - << MatchTable::Comment("TempRegID") << MatchTable::IntValue(TempRegID) - << MatchTable::Comment("TypeID") << Ty << MatchTable::LineBreak; + << MatchTable::Comment("TempRegID") + << MatchTable::ULEB128Value(TempRegID) << MatchTable::Comment("TypeID") + << Ty << MatchTable::LineBreak; } } // namespace gi diff --git a/llvm/utils/TableGen/GlobalISelMatchTable.h b/llvm/utils/TableGen/GlobalISelMatchTable.h index 469390d73123..7cb5345f51f8 100644 --- a/llvm/utils/TableGen/GlobalISelMatchTable.h +++ b/llvm/utils/TableGen/GlobalISelMatchTable.h @@ -59,6 +59,9 @@ using GISelFlags = std::uint16_t; //===- Helper functions ---------------------------------------------------===// +void emitEncodingMacrosDef(raw_ostream &OS); +void emitEncodingMacrosUndef(raw_ostream &OS); + std::string getNameForFeatureBitset(const std::vector<Record *> &FeatureBitset, int HwModeIdx); @@ -119,6 +122,9 @@ struct MatchTableRecord { /// Causes the formatter to remove a level of indentation after emitting the /// record. MTRF_Outdent = 0x40, + /// Causes the formatter to not use encoding macros to emit this multi-byte + /// value. + MTRF_PreEncoded = 0x80, }; /// When MTRF_Label or MTRF_JumpTarget is used, indicates a label id to @@ -194,12 +200,15 @@ public: static MatchTableRecord LineBreak; static MatchTableRecord Comment(StringRef Comment); static MatchTableRecord Opcode(StringRef Opcode, int IndentAdjust = 0); - static MatchTableRecord NamedValue(StringRef NamedValue); - static MatchTableRecord NamedValue(StringRef NamedValue, int64_t RawValue); - static MatchTableRecord NamedValue(StringRef Namespace, StringRef NamedValue); - static MatchTableRecord NamedValue(StringRef Namespace, StringRef NamedValue, + static MatchTableRecord NamedValue(unsigned NumBytes, StringRef NamedValue); + static MatchTableRecord NamedValue(unsigned NumBytes, StringRef NamedValue, int64_t RawValue); - static MatchTableRecord IntValue(int64_t IntValue); + static MatchTableRecord NamedValue(unsigned NumBytes, StringRef Namespace, + StringRef NamedValue); + static MatchTableRecord NamedValue(unsigned NumBytes, StringRef Namespace, + StringRef NamedValue, int64_t RawValue); + static MatchTableRecord IntValue(unsigned NumBytes, int64_t IntValue); + static MatchTableRecord ULEB128Value(uint64_t IntValue); static MatchTableRecord Label(unsigned LabelID); static MatchTableRecord JumpTarget(unsigned LabelID); @@ -301,9 +310,9 @@ private: inline MatchTable &operator<<(MatchTable &Table, const LLTCodeGenOrTempType &Ty) { if (Ty.isLLTCodeGen()) - Table << MatchTable::NamedValue(Ty.getLLTCodeGen().getCxxEnumValue()); + Table << MatchTable::NamedValue(1, Ty.getLLTCodeGen().getCxxEnumValue()); else - Table << MatchTable::IntValue(Ty.getTempTypeIdx()); + Table << MatchTable::IntValue(1, Ty.getTempTypeIdx()); return Table; } @@ -1669,7 +1678,7 @@ public: void emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const override { Table << MatchTable::Opcode("GIM_CheckHasNoUse") - << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID) + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) << MatchTable::LineBreak; } }; @@ -2066,21 +2075,10 @@ public: return R->getKind() == OR_Imm; } - void emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const override { - if (CImmLLT) { - assert(Table.isCombiner() && - "ConstantInt immediate are only for combiners!"); - Table << MatchTable::Opcode("GIR_AddCImm") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) - << MatchTable::Comment("Type") << *CImmLLT - << MatchTable::Comment("Imm") << MatchTable::IntValue(Imm) - << MatchTable::LineBreak; - } else { - Table << MatchTable::Opcode("GIR_AddImm") << MatchTable::Comment("InsnID") - << MatchTable::IntValue(InsnID) << MatchTable::Comment("Imm") - << MatchTable::IntValue(Imm) << MatchTable::LineBreak; - } - } + static void emitAddImm(MatchTable &Table, RuleMatcher &RM, unsigned InsnID, + int64_t Imm, StringRef ImmName = "Imm"); + + void emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const override; }; /// Adds an enum value for a subreg index to the instruction being built. @@ -2366,7 +2364,7 @@ public: void emitActionOpcodes(MatchTable &Table, RuleMatcher &Rule) const override { Table << MatchTable::Opcode("GIR_ConstrainSelectedInstOperands") - << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID) + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) << MatchTable::LineBreak; } }; diff --git a/llvm/utils/TableGen/GlobalISelMatchTableExecutorEmitter.cpp b/llvm/utils/TableGen/GlobalISelMatchTableExecutorEmitter.cpp index c6cd3240a94e..5697899a915a 100644 --- a/llvm/utils/TableGen/GlobalISelMatchTableExecutorEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelMatchTableExecutorEmitter.cpp @@ -164,11 +164,14 @@ void GlobalISelMatchTableExecutorEmitter::emitTypeObjects( void GlobalISelMatchTableExecutorEmitter::emitMatchTable( raw_ostream &OS, const MatchTable &Table) { - OS << "const int64_t *" << getClassName() << "::getMatchTable() const {\n"; + emitEncodingMacrosDef(OS); + OS << "const uint8_t *" << getClassName() << "::getMatchTable() const {\n"; Table.emitDeclaration(OS); OS << " return "; Table.emitUse(OS); OS << ";\n}\n"; + emitEncodingMacrosUndef(OS); + OS << "\n"; } void GlobalISelMatchTableExecutorEmitter::emitExecutorImpl( @@ -187,7 +190,9 @@ void GlobalISelMatchTableExecutorEmitter::emitExecutorImpl( emitCustomOperandRenderers(OS, CustomOperandRenderers); emitAdditionalImpl(OS); emitRunCustomAction(OS); + emitMatchTable(OS, Table); + OS << "#endif // ifdef " << IfDefName << "\n\n"; } @@ -226,7 +231,7 @@ void GlobalISelMatchTableExecutorEmitter::emitTemporariesDecl( "const override;\n" << " bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat " "&Imm) const override;\n" - << " const int64_t *getMatchTable() const override;\n" + << " const uint8_t *getMatchTable() const override;\n" << " bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI" ", const MatcherState &State) " "const override;\n" diff --git a/llvm/utils/TableGen/README.md b/llvm/utils/TableGen/README.md index 3bee6555566a..ab3657d07d66 100644 --- a/llvm/utils/TableGen/README.md +++ b/llvm/utils/TableGen/README.md @@ -35,6 +35,7 @@ Resources for learning the language: * [TableGen Overview](https://llvm.org/docs/TableGen/index.html) * [Programmer's reference guide](https://llvm.org/docs/TableGen/ProgRef.html) * [Tutorial](jupyter/tablegen_tutorial_part_1.ipynb) +* [Tools for Learning LLVM TableGen](https://blog.llvm.org/posts/2023-12-07-tools-for-learning-llvm-tablegen/) * [Lessons in TableGen](https://www.youtube.com/watch?v=45gmF77JFBY) (video), [slides](https://archive.fosdem.org/2019/schedule/event/llvm_tablegen/attachments/slides/3304/export/events/attachments/llvm_tablegen/slides/3304/tablegen.pdf) * [Improving Your TableGen Descriptions](https://www.youtube.com/watch?v=dIEVUlsiktQ) diff --git a/llvm/utils/count/CMakeLists.txt b/llvm/utils/count/CMakeLists.txt index 4e0d371334e4..cfd1f4a85d8a 100644 --- a/llvm/utils/count/CMakeLists.txt +++ b/llvm/utils/count/CMakeLists.txt @@ -1,3 +1,7 @@ +set(LLVM_LINK_COMPONENTS + support +) + add_llvm_utility(count count.c ) diff --git a/llvm/utils/count/count.c b/llvm/utils/count/count.c index 7149c14a63ab..300be2aa8a18 100644 --- a/llvm/utils/count/count.c +++ b/llvm/utils/count/count.c @@ -6,10 +6,18 @@ * \*===----------------------------------------------------------------------===*/ -#include <stdlib.h> +#include "llvm/Support/AutoConvert.h" #include <stdio.h> +#include <stdlib.h> int main(int argc, char **argv) { +#ifdef __MVS__ + if (enableAutoConversion(fileno(stdin)) == -1) + fprintf(stderr, "Setting conversion on stdin failed\n"); + + if (enableAutoConversion(fileno(stderr)) == -1) + fprintf(stdout, "Setting conversion on stderr failed\n"); +#endif size_t Count, NumLines, NumRead; char Buffer[4096], *End; diff --git a/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn index 6dcf0fc08a34..3debc48a4bb9 100644 --- a/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn @@ -50,6 +50,13 @@ clang_tablegen("arm_cde") { output_name = "arm_cde.h" } +# Generate arm__vector_types.h +clang_tablegen("arm_vector_types") { + args = [ "-gen-arm-vector-type" ] + td_file = "//clang/include/clang/Basic/arm_neon.td" + output_name = "arm_vector_types.h" +} + # Generate riscv_vector.h clang_tablegen("riscv_vector") { args = [ "-gen-riscv-vector-header" ] @@ -67,6 +74,7 @@ copy("tablegen_headers") { ":arm_neon", ":arm_sme_draft_spec_subject_to_change", ":arm_sve", + ":arm_vector_types", ":riscv_vector", ] sources = [] diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn index 5cc9ec5889d4..4ad2b7ea6f7a 100644 --- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn +++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn @@ -34,6 +34,7 @@ if (current_toolchain == default_toolchain) { "_LIBCPP_HAS_NO_LOCALIZATION=", "_LIBCPP_HAS_NO_WIDE_CHARACTERS=", "_LIBCPP_HAS_NO_STD_MODULES=", + "_LIBCPP_INSTRUMENTED_WITH_ASAN=", "_LIBCPP_ABI_DEFINES=", "_LIBCPP_HARDENING_MODE_DEFAULT=_LIBCPP_HARDENING_MODE_NONE", "_LIBCPP_PSTL_CPU_BACKEND_LIBDISPATCH=", diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn index 6d518446fca2..f85bf8f9940f 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn @@ -141,6 +141,7 @@ static_library("LLVMAMDGPUCodeGen") { "AMDGPUCtorDtorLowering.cpp", "AMDGPUExportClustering.cpp", "AMDGPUFrameLowering.cpp", + "AMDGPUGlobalISelDivergenceLowering.cpp", "AMDGPUGlobalISelUtils.cpp", "AMDGPUHSAMetadataStreamer.cpp", "AMDGPUIGroupLP.cpp", diff --git a/llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn index fddee579547c..c6d40aeebbbe 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn @@ -106,6 +106,7 @@ unittest("SupportTests") { "raw_ostream_test.cpp", "raw_pwrite_stream_test.cpp", "raw_sha1_ostream_test.cpp", + "raw_socket_stream_test.cpp", "xxhashTest.cpp", ] } diff --git a/mlir/include/mlir/Analysis/Presburger/Matrix.h b/mlir/include/mlir/Analysis/Presburger/Matrix.h index 4d9f13832e06..89fad85c0c33 100644 --- a/mlir/include/mlir/Analysis/Presburger/Matrix.h +++ b/mlir/include/mlir/Analysis/Presburger/Matrix.h @@ -265,6 +265,11 @@ public: // does not exist, which happens iff det = 0. // Assert-fails if the matrix is not square. Fraction determinant(FracMatrix *inverse = nullptr) const; + + // Computes the Gram-Schmidt orthogonalisation + // of the rows of matrix (cubic time). + // The rows of the matrix must be linearly independent. + FracMatrix gramSchmidt() const; }; } // namespace presburger diff --git a/mlir/include/mlir/Analysis/Presburger/Utils.h b/mlir/include/mlir/Analysis/Presburger/Utils.h index a451ae8bf557..20af0bfcd62b 100644 --- a/mlir/include/mlir/Analysis/Presburger/Utils.h +++ b/mlir/include/mlir/Analysis/Presburger/Utils.h @@ -276,6 +276,11 @@ SmallVector<MPInt, 8> getNegatedCoeffs(ArrayRef<MPInt> coeffs); /// a_1 x_1 + ... + a_n x_ + c < 0, i.e., -a_1 x_1 - ... - a_n x_ - c - 1 >= 0, /// since all the variables are constrained to be integers. SmallVector<MPInt, 8> getComplementIneq(ArrayRef<MPInt> ineq); + +/// Compute the dot product of two vectors. +/// The vectors must have the same sizes. +Fraction dotProduct(ArrayRef<Fraction> a, ArrayRef<Fraction> b); + } // namespace presburger } // namespace mlir diff --git a/mlir/include/mlir/Dialect/ArmSME/Transforms/CMakeLists.txt b/mlir/include/mlir/Dialect/ArmSME/Transforms/CMakeLists.txt index 38f48757b774..509f3fc2519c 100644 --- a/mlir/include/mlir/Dialect/ArmSME/Transforms/CMakeLists.txt +++ b/mlir/include/mlir/Dialect/ArmSME/Transforms/CMakeLists.txt @@ -3,5 +3,6 @@ mlir_tablegen(Passes.h.inc -gen-pass-decls -name ArmSME) mlir_tablegen(PassesEnums.h.inc -gen-enum-decls) mlir_tablegen(PassesEnums.cpp.inc -gen-enum-defs) add_public_tablegen_target(MLIRArmSMETransformsIncGen) +add_dependencies(mlir-headers MLIRArmSMETransformsIncGen) add_mlir_doc(Passes ArmSMEPasses ./ -gen-pass-doc) diff --git a/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td b/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td index 02238f0a18ba..4266ac5b0c8c 100644 --- a/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td +++ b/mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td @@ -20,6 +20,9 @@ def ArmStreamingMode : I32EnumAttr<"ArmStreamingMode", "Armv9 Streaming SVE mode // StreamingLocally: PSTATE.SM is kept internal and the callee manages it // on entry/exit. I32EnumAttrCase<"StreamingLocally", 2, "arm_locally_streaming">, + // StreamingCompatible: the function may be entered in either + // non-streaming mode (PSTATE.SM=0) or in streaming mode (PSTATE.SM=1) + I32EnumAttrCase<"StreamingCompatible", 3, "arm_streaming_compatible">, ]>{ let cppNamespace = "mlir::arm_sme"; let genSpecializedAttr = 0; @@ -61,7 +64,11 @@ def EnableArmStreaming clEnumValN(mlir::arm_sme::ArmStreamingMode::StreamingLocally, "streaming-locally", "Streaming mode is internal to the function, callee " - "manages PSTATE.SM on entry/exit.") + "manages PSTATE.SM on entry/exit."), + clEnumValN(mlir::arm_sme::ArmStreamingMode::StreamingCompatible, + "streaming-compatible", + "Function supports both streaming and non-streaming " + "modes.") )}]>, Option<"zaMode", "za-mode", "mlir::arm_sme::ArmZaMode", /*default=*/"mlir::arm_sme::ArmZaMode::Disabled", diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td index 6975b18ab7f8..f36ec0d02cf7 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td @@ -424,9 +424,9 @@ def LLVM_DIGlobalVariableExpressionAttr def LLVM_DIGlobalVariable : LLVM_Attr<"DIGlobalVariable", "di_global_variable", /*traits=*/[], "DINodeAttr"> { let parameters = (ins - "DIScopeAttr":$scope, - "StringAttr":$name, - "StringAttr":$linkageName, + OptionalParameter<"DIScopeAttr">:$scope, + OptionalParameter<"StringAttr">:$name, + OptionalParameter<"StringAttr">:$linkageName, "DIFileAttr":$file, "unsigned":$line, "DITypeAttr":$type, diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td index d7690b84807f..9e65898154bd 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td @@ -1411,6 +1411,7 @@ def LLVM_LLVMFuncOp : LLVM_Op<"func", [ DefaultValuedAttr<Visibility, "mlir::LLVM::Visibility::Default">:$visibility_, OptionalAttr<UnitAttr>:$arm_streaming, OptionalAttr<UnitAttr>:$arm_locally_streaming, + OptionalAttr<UnitAttr>:$arm_streaming_compatible, OptionalAttr<UnitAttr>:$arm_new_za, OptionalAttr<StrAttr>:$section, OptionalAttr<UnnamedAddr>:$unnamed_addr, diff --git a/mlir/include/mlir/Dialect/Math/IR/MathOps.td b/mlir/include/mlir/Dialect/Math/IR/MathOps.td index 9742d3d936df..b9daa91b28a9 100644 --- a/mlir/include/mlir/Dialect/Math/IR/MathOps.td +++ b/mlir/include/mlir/Dialect/Math/IR/MathOps.td @@ -327,7 +327,26 @@ def Math_AcosOp : Math_FloatUnaryOp<"acos"> { let hasFolder = 1; } +//===----------------------------------------------------------------------===// +// CoshOp +//===----------------------------------------------------------------------===// +def Math_CoshOp : Math_FloatUnaryOp<"cosh"> { + let summary = "hyperbolic cosine of the specified value"; + let description = [{ + The `cosh` operation computes the hyperbolic cosine. It takes one operand + of floating point type (i.e., scalar, tensor or vector) and returns one + result of the same type. It has no standard attributes. + + Example: + + ```mlir + // Scalar hyperbolic cosine value. + %a = math.cosh %b : f64 + ``` + }]; + let hasFolder = 1; +} //===----------------------------------------------------------------------===// // SinOp diff --git a/mlir/lib/Analysis/Presburger/IntegerRelation.cpp b/mlir/lib/Analysis/Presburger/IntegerRelation.cpp index 3724df5abccc..0109384f1689 100644 --- a/mlir/lib/Analysis/Presburger/IntegerRelation.cpp +++ b/mlir/lib/Analysis/Presburger/IntegerRelation.cpp @@ -449,6 +449,12 @@ void IntegerRelation::swapVar(unsigned posA, unsigned posB) { if (posA == posB) return; + VarKind kindA = space.getVarKindAt(posA); + VarKind kindB = space.getVarKindAt(posB); + unsigned relativePosA = posA - getVarKindOffset(kindA); + unsigned relativePosB = posB - getVarKindOffset(kindB); + space.swapVar(kindA, kindB, relativePosA, relativePosB); + inequalities.swapColumns(posA, posB); equalities.swapColumns(posA, posB); } diff --git a/mlir/lib/Analysis/Presburger/Matrix.cpp b/mlir/lib/Analysis/Presburger/Matrix.cpp index fe461a1f9581..1fcc6d072b44 100644 --- a/mlir/lib/Analysis/Presburger/Matrix.cpp +++ b/mlir/lib/Analysis/Presburger/Matrix.cpp @@ -466,8 +466,8 @@ FracMatrix FracMatrix::identity(unsigned dimension) { FracMatrix::FracMatrix(IntMatrix m) : FracMatrix(m.getNumRows(), m.getNumColumns()) { - for (unsigned i = 0; i < m.getNumRows(); i++) - for (unsigned j = 0; j < m.getNumColumns(); j++) + for (unsigned i = 0, r = m.getNumRows(); i < r; i++) + for (unsigned j = 0, c = m.getNumColumns(); j < c; j++) this->at(i, j) = m.at(i, j); } @@ -554,4 +554,26 @@ Fraction FracMatrix::determinant(FracMatrix *inverse) const { determinant *= m.at(i, i); return determinant; +} + +FracMatrix FracMatrix::gramSchmidt() const { + // Create a copy of the argument to store + // the orthogonalised version. + FracMatrix orth(*this); + + // For each vector (row) in the matrix, subtract its unit + // projection along each of the previous vectors. + // This ensures that it has no component in the direction + // of any of the previous vectors. + for (unsigned i = 1, e = getNumRows(); i < e; i++) { + for (unsigned j = 0; j < i; j++) { + Fraction jNormSquared = dotProduct(orth.getRow(j), orth.getRow(j)); + assert(jNormSquared != 0 && "some row became zero! Inputs to this " + "function must be linearly independent."); + Fraction projectionScale = + dotProduct(orth.getRow(i), orth.getRow(j)) / jNormSquared; + orth.addToRow(j, i, -projectionScale); + } + } + return orth; }
\ No newline at end of file diff --git a/mlir/lib/Analysis/Presburger/Utils.cpp b/mlir/lib/Analysis/Presburger/Utils.cpp index 612712a1d907..5e267d2045bc 100644 --- a/mlir/lib/Analysis/Presburger/Utils.cpp +++ b/mlir/lib/Analysis/Presburger/Utils.cpp @@ -529,3 +529,12 @@ SmallVector<int64_t, 8> presburger::getInt64Vec(ArrayRef<MPInt> range) { std::transform(range.begin(), range.end(), result.begin(), int64FromMPInt); return result; } + +Fraction presburger::dotProduct(ArrayRef<Fraction> a, ArrayRef<Fraction> b) { + assert(a.size() == b.size() && + "dot product is only valid for vectors of equal sizes!"); + Fraction sum = 0; + for (unsigned i = 0, e = a.size(); i < e; i++) + sum += a[i] * b[i]; + return sum; +}
\ No newline at end of file diff --git a/mlir/lib/Conversion/MathToLibm/MathToLibm.cpp b/mlir/lib/Conversion/MathToLibm/MathToLibm.cpp index 27c2cb935207..6e30c07de4d5 100644 --- a/mlir/lib/Conversion/MathToLibm/MathToLibm.cpp +++ b/mlir/lib/Conversion/MathToLibm/MathToLibm.cpp @@ -168,6 +168,7 @@ void mlir::populateMathToLibmConversionPatterns(RewritePatternSet &patterns) { populatePatternsForOp<math::CbrtOp>(patterns, ctx, "cbrtf", "cbrt"); populatePatternsForOp<math::CeilOp>(patterns, ctx, "ceilf", "ceil"); populatePatternsForOp<math::CosOp>(patterns, ctx, "cosf", "cos"); + populatePatternsForOp<math::CoshOp>(patterns, ctx, "coshf", "cosh"); populatePatternsForOp<math::ErfOp>(patterns, ctx, "erff", "erf"); populatePatternsForOp<math::ExpM1Op>(patterns, ctx, "expm1f", "expm1"); populatePatternsForOp<math::FloorOp>(patterns, ctx, "floorf", "floor"); diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp index d9f52d769293..6e9019f932aa 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp @@ -632,8 +632,7 @@ struct LLVMInlinerInterface : public DialectInlinerInterface { bool wouldBeCloned) const final { if (!wouldBeCloned) return false; - auto callOp = dyn_cast<LLVM::CallOp>(call); - if (!callOp) { + if (!isa<LLVM::CallOp>(call)) { LLVM_DEBUG(llvm::dbgs() << "Cannot inline: call is not an LLVM::CallOp\n"); return false; @@ -684,40 +683,8 @@ struct LLVMInlinerInterface : public DialectInlinerInterface { return true; } - /// Conservative allowlist of operations supported so far. bool isLegalToInline(Operation *op, Region *, bool, IRMapping &) const final { - if (isPure(op)) - return true; - // clang-format off - if (isa<LLVM::AllocaOp, - LLVM::AssumeOp, - LLVM::AtomicRMWOp, - LLVM::AtomicCmpXchgOp, - LLVM::CallOp, - LLVM::CallIntrinsicOp, - LLVM::DbgDeclareOp, - LLVM::DbgLabelOp, - LLVM::DbgValueOp, - LLVM::FenceOp, - LLVM::InlineAsmOp, - LLVM::LifetimeEndOp, - LLVM::LifetimeStartOp, - LLVM::LoadOp, - LLVM::MemcpyOp, - LLVM::MemcpyInlineOp, - LLVM::MemmoveOp, - LLVM::MemsetOp, - LLVM::NoAliasScopeDeclOp, - LLVM::StackRestoreOp, - LLVM::StackSaveOp, - LLVM::StoreOp, - LLVM::UnreachableOp>(op)) - return true; - // clang-format on - LLVM_DEBUG(llvm::dbgs() - << "Cannot inline: unhandled side effecting operation \"" - << op->getName() << "\"\n"); - return false; + return true; } /// Handle the given inlined return by replacing it with a branch. This diff --git a/mlir/lib/Dialect/Math/IR/MathOps.cpp b/mlir/lib/Dialect/Math/IR/MathOps.cpp index 066a21c76f7d..6b8c3a53a422 100644 --- a/mlir/lib/Dialect/Math/IR/MathOps.cpp +++ b/mlir/lib/Dialect/Math/IR/MathOps.cpp @@ -145,6 +145,24 @@ OpFoldResult math::CosOp::fold(FoldAdaptor adaptor) { } //===----------------------------------------------------------------------===// +// CoshOp folder +//===----------------------------------------------------------------------===// + +OpFoldResult math::CoshOp::fold(FoldAdaptor adaptor) { + return constFoldUnaryOpConditional<FloatAttr>( + adaptor.getOperands(), [](const APFloat &a) -> std::optional<APFloat> { + switch (a.getSizeInBits(a.getSemantics())) { + case 64: + return APFloat(cosh(a.convertToDouble())); + case 32: + return APFloat(coshf(a.convertToFloat())); + default: + return {}; + } + }); +} + +//===----------------------------------------------------------------------===// // SinOp folder //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Target/LLVMIR/DebugImporter.cpp b/mlir/lib/Target/LLVMIR/DebugImporter.cpp index 13b81d134cbe..afc6918eae97 100644 --- a/mlir/lib/Target/LLVMIR/DebugImporter.cpp +++ b/mlir/lib/Target/LLVMIR/DebugImporter.cpp @@ -118,12 +118,19 @@ DebugImporter::translateImpl(llvm::DILexicalBlockFile *node) { DIGlobalVariableAttr DebugImporter::translateImpl(llvm::DIGlobalVariable *node) { + // Names of DIGlobalVariables can be empty. MLIR models them as null, instead + // of empty strings, so this special handling is necessary. + auto convertToStringAttr = [&](StringRef name) -> StringAttr { + if (name.empty()) + return {}; + return StringAttr::get(context, node->getName()); + }; return DIGlobalVariableAttr::get( context, translate(node->getScope()), - StringAttr::get(context, node->getName()), - StringAttr::get(context, node->getLinkageName()), - translate(node->getFile()), node->getLine(), translate(node->getType()), - node->isLocalToUnit(), node->isDefinition(), node->getAlignInBits()); + convertToStringAttr(node->getName()), + convertToStringAttr(node->getLinkageName()), translate(node->getFile()), + node->getLine(), translate(node->getType()), node->isLocalToUnit(), + node->isDefinition(), node->getAlignInBits()); } DILocalVariableAttr DebugImporter::translateImpl(llvm::DILocalVariable *node) { diff --git a/mlir/lib/Target/LLVMIR/ModuleImport.cpp b/mlir/lib/Target/LLVMIR/ModuleImport.cpp index 7c51ee7420f9..ec2692f58695 100644 --- a/mlir/lib/Target/LLVMIR/ModuleImport.cpp +++ b/mlir/lib/Target/LLVMIR/ModuleImport.cpp @@ -1637,6 +1637,7 @@ static void processMemoryEffects(llvm::Function *func, LLVMFuncOp funcOp) { static constexpr std::array ExplicitAttributes{ StringLiteral("aarch64_pstate_sm_enabled"), StringLiteral("aarch64_pstate_sm_body"), + StringLiteral("aarch64_pstate_sm_compatible"), StringLiteral("aarch64_pstate_za_new"), StringLiteral("vscale_range"), StringLiteral("frame-pointer"), @@ -1709,6 +1710,8 @@ void ModuleImport::processFunctionAttributes(llvm::Function *func, funcOp.setArmStreaming(true); else if (func->hasFnAttribute("aarch64_pstate_sm_body")) funcOp.setArmLocallyStreaming(true); + else if (func->hasFnAttribute("aarch64_pstate_sm_compatible")) + funcOp.setArmStreamingCompatible(true); if (func->hasFnAttribute("aarch64_pstate_za_new")) funcOp.setArmNewZa(true); diff --git a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp index d6afe354178d..3dd082aae193 100644 --- a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp @@ -795,7 +795,8 @@ LogicalResult ModuleTranslation::convertGlobals() { // Get the compile unit (scope) of the the global variable. if (llvm::DICompileUnit *compileUnit = - dyn_cast<llvm::DICompileUnit>(diGlobalVar->getScope())) { + dyn_cast_if_present<llvm::DICompileUnit>( + diGlobalVar->getScope())) { // Update the compile unit with this incoming global variable expression // during the finalizing step later. allGVars[compileUnit].push_back(diGlobalExpr); @@ -964,6 +965,8 @@ LogicalResult ModuleTranslation::convertOneFunction(LLVMFuncOp func) { llvmFunc->addFnAttr("aarch64_pstate_sm_enabled"); else if (func.getArmLocallyStreaming()) llvmFunc->addFnAttr("aarch64_pstate_sm_body"); + else if (func.getArmStreamingCompatible()) + llvmFunc->addFnAttr("aarch64_pstate_sm_compatible"); if (func.getArmNewZa()) llvmFunc->addFnAttr("aarch64_pstate_za_new"); diff --git a/mlir/lib/Transforms/Utils/FoldUtils.cpp b/mlir/lib/Transforms/Utils/FoldUtils.cpp index 056a681718e1..136c4d2216b8 100644 --- a/mlir/lib/Transforms/Utils/FoldUtils.cpp +++ b/mlir/lib/Transforms/Utils/FoldUtils.cpp @@ -340,28 +340,39 @@ OperationFolder::tryGetOrCreateConstant(ConstantMap &uniquedConstants, /// child fused locations are the same---this to avoid breaking cases where /// metadata matter. static Location FlattenFusedLocationRecursively(const Location loc) { - if (auto fusedLoc = dyn_cast<FusedLoc>(loc)) { - SetVector<Location> flattenedLocs; - Attribute metadata = fusedLoc.getMetadata(); - - for (const Location &unflattenedLoc : fusedLoc.getLocations()) { - Location flattenedLoc = FlattenFusedLocationRecursively(unflattenedLoc); - auto flattenedFusedLoc = dyn_cast<FusedLoc>(flattenedLoc); - - if (flattenedFusedLoc && (!flattenedFusedLoc.getMetadata() || - flattenedFusedLoc.getMetadata() == metadata)) { - ArrayRef<Location> nestedLocations = flattenedFusedLoc.getLocations(); - flattenedLocs.insert(nestedLocations.begin(), nestedLocations.end()); - } else { - flattenedLocs.insert(flattenedLoc); - } + auto fusedLoc = dyn_cast<FusedLoc>(loc); + if (!fusedLoc) + return loc; + + SetVector<Location> flattenedLocs; + Attribute metadata = fusedLoc.getMetadata(); + ArrayRef<Location> unflattenedLocs = fusedLoc.getLocations(); + bool hasAnyNestedLocChanged = false; + + for (const Location &unflattenedLoc : unflattenedLocs) { + Location flattenedLoc = FlattenFusedLocationRecursively(unflattenedLoc); + + auto flattenedFusedLoc = dyn_cast<FusedLoc>(flattenedLoc); + if (flattenedFusedLoc && (!flattenedFusedLoc.getMetadata() || + flattenedFusedLoc.getMetadata() == metadata)) { + hasAnyNestedLocChanged = true; + ArrayRef<Location> nestedLocations = flattenedFusedLoc.getLocations(); + flattenedLocs.insert(nestedLocations.begin(), nestedLocations.end()); + } else { + if (flattenedLoc != unflattenedLoc) + hasAnyNestedLocChanged = true; + + flattenedLocs.insert(flattenedLoc); } + } - return FusedLoc::get(loc->getContext(), flattenedLocs.takeVector(), - fusedLoc.getMetadata()); + if (!hasAnyNestedLocChanged && + unflattenedLocs.size() == flattenedLocs.size()) { + return loc; } - return loc; + return FusedLoc::get(loc->getContext(), flattenedLocs.takeVector(), + fusedLoc.getMetadata()); } void OperationFolder::appendFoldedLocation(Operation *retainedOp, diff --git a/mlir/test/Conversion/MathToLibm/convert-to-libm.mlir b/mlir/test/Conversion/MathToLibm/convert-to-libm.mlir index f0c4512cbfdc..eb9226dee261 100644 --- a/mlir/test/Conversion/MathToLibm/convert-to-libm.mlir +++ b/mlir/test/Conversion/MathToLibm/convert-to-libm.mlir @@ -24,6 +24,8 @@ // CHECK-DAG: @truncf(f32) -> f32 attributes {llvm.readnone} // CHECK-DAG: @cos(f64) -> f64 attributes {llvm.readnone} // CHECK-DAG: @cosf(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @cosh(f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @coshf(f32) -> f32 attributes {llvm.readnone} // CHECK-DAG: @sin(f64) -> f64 attributes {llvm.readnone} // CHECK-DAG: @sinf(f32) -> f32 attributes {llvm.readnone} // CHECK-DAG: @floor(f64) -> f64 attributes {llvm.readnone} @@ -127,6 +129,18 @@ func.func @tanh_caller(%float: f32, %double: f64) -> (f32, f64) { return %float_result, %double_result : f32, f64 } +// CHECK-LABEL: func @cosh_caller +// CHECK-SAME: %[[FLOAT:.*]]: f32 +// CHECK-SAME: %[[DOUBLE:.*]]: f64 +func.func @cosh_caller(%float: f32, %double: f64) -> (f32, f64) { + // CHECK-DAG: %[[FLOAT_RESULT:.*]] = call @coshf(%[[FLOAT]]) : (f32) -> f32 + %float_result = math.cosh %float : f32 + // CHECK-DAG: %[[DOUBLE_RESULT:.*]] = call @cosh(%[[DOUBLE]]) : (f64) -> f64 + %double_result = math.cosh %double : f64 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] + return %float_result, %double_result : f32, f64 +} + // CHECK-LABEL: func @atan2_caller // CHECK-SAME: %[[FLOAT:.*]]: f32 // CHECK-SAME: %[[DOUBLE:.*]]: f64 diff --git a/mlir/test/Dialect/ArmSME/enable-arm-streaming.mlir b/mlir/test/Dialect/ArmSME/enable-arm-streaming.mlir index b1188acbc0b2..6b58d8fdc41b 100644 --- a/mlir/test/Dialect/ArmSME/enable-arm-streaming.mlir +++ b/mlir/test/Dialect/ArmSME/enable-arm-streaming.mlir @@ -1,5 +1,6 @@ // RUN: mlir-opt %s -enable-arm-streaming -verify-diagnostics | FileCheck %s // RUN: mlir-opt %s -enable-arm-streaming=streaming-mode=streaming-locally -verify-diagnostics | FileCheck %s -check-prefix=CHECK-LOCALLY +// RUN: mlir-opt %s -enable-arm-streaming=streaming-mode=streaming-compatible -verify-diagnostics | FileCheck %s -check-prefix=CHECK-COMPATIBLE // RUN: mlir-opt %s -enable-arm-streaming=za-mode=new-za -verify-diagnostics | FileCheck %s -check-prefix=CHECK-ENABLE-ZA // RUN: mlir-opt %s -enable-arm-streaming=only-if-required-by-ops -verify-diagnostics | FileCheck %s -check-prefix=IF-REQUIRED @@ -7,6 +8,8 @@ // CHECK-SAME: attributes {arm_streaming} // CHECK-LOCALLY-LABEL: @arm_streaming // CHECK-LOCALLY-SAME: attributes {arm_locally_streaming} +// CHECK-COMPATIBLE-LABEL: @arm_streaming +// CHECK-COMPATIBLE-SAME: attributes {arm_streaming_compatible} // CHECK-ENABLE-ZA-LABEL: @arm_streaming // CHECK-ENABLE-ZA-SAME: attributes {arm_new_za, arm_streaming} func.func @arm_streaming() { return } @@ -15,6 +18,8 @@ func.func @arm_streaming() { return } // CHECK-SAME: attributes {enable_arm_streaming_ignore} // CHECK-LOCALLY-LABEL: @not_arm_streaming // CHECK-LOCALLY-SAME: attributes {enable_arm_streaming_ignore} +// CHECK-COMPATIBLE-LABEL: @not_arm_streaming +// CHECK-COMPATIBLE-SAME: attributes {enable_arm_streaming_ignore} // CHECK-ENABLE-ZA-LABEL: @not_arm_streaming // CHECK-ENABLE-ZA-SAME: attributes {enable_arm_streaming_ignore} func.func @not_arm_streaming() attributes {enable_arm_streaming_ignore} { return } diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir index dcd780b23161..c781d5e0af84 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir @@ -1,8 +1,8 @@ // RUN: mlir-opt %s \ // RUN: -transform-interpreter -test-transform-dialect-erase-schedule \ // RUN: -one-shot-bufferize="bufferize-function-boundaries" -canonicalize \ -// RUN: -enable-arm-streaming="streaming-mode=streaming-locally za-mode=new-za" \ // RUN: -convert-vector-to-arm-sme -allocate-arm-sme-tiles -convert-arm-sme-to-scf \ +// RUN: -enable-arm-streaming="streaming-mode=streaming-locally za-mode=new-za only-if-required-by-ops" \ // RUN: -convert-vector-to-scf -cse -arm-sve-legalize-vector-storage \ // RUN: -convert-arm-sme-to-llvm \ // RUN: -convert-vector-to-llvm=enable-arm-sve \ @@ -21,7 +21,7 @@ func.func @matmul_transpose_a(%A : tensor<?x?xf32>, %B : tensor<?x?xf32>, %C : t return } -func.func @main() attributes { enable_arm_streaming_ignore } { +func.func @main() { %c0 = arith.constant 0 : i32 %c7 = arith.constant 7 : index diff --git a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir index db5b09877040..31c3202c3fc5 100644 --- a/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir +++ b/mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul.mlir @@ -1,8 +1,8 @@ // RUN: mlir-opt %s \ // RUN: -transform-interpreter -test-transform-dialect-erase-schedule \ // RUN: -canonicalize \ -// RUN: -enable-arm-streaming="streaming-mode=streaming-locally za-mode=new-za" \ // RUN: -convert-vector-to-arm-sme -allocate-arm-sme-tiles -convert-arm-sme-to-scf \ +// RUN: -enable-arm-streaming="streaming-mode=streaming-locally za-mode=new-za only-if-required-by-ops" \ // RUN: -convert-vector-to-scf -cse -arm-sve-legalize-vector-storage \ // RUN: -convert-arm-sme-to-llvm \ // RUN: -convert-vector-to-llvm=enable-arm-sve \ @@ -21,7 +21,7 @@ func.func @matmul(%A : tensor<?x?xf32>, %B : tensor<?x?xf32>, %C : tensor<?x?xf3 return } -func.func @main() attributes { enable_arm_streaming_ignore } { +func.func @main() { %c0 = arith.constant 0 : i32 %c7 = arith.constant 7 : index diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-read-2d.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-read-2d.mlir index 4ca61a089bdf..839aed2e840c 100644 --- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-read-2d.mlir +++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-read-2d.mlir @@ -1,7 +1,7 @@ // DEFINE: %{entry_point} = entry // DEFINE: %{compile} = mlir-opt %s \ -// DEFINE: -enable-arm-streaming="streaming-mode=streaming-locally za-mode=new-za" \ // DEFINE: -convert-vector-to-arm-sme -convert-arm-sme-to-scf -allocate-arm-sme-tiles \ +// DEFINE: -enable-arm-streaming="streaming-mode=streaming-locally za-mode=new-za only-if-required-by-ops" \ // DEFINE: -convert-arm-sme-to-llvm -cse -canonicalize \ // DEFINE: -test-lower-to-llvm // DEFINE: %{run} = %mcr_aarch64_cmd \ @@ -140,7 +140,7 @@ func.func @get_svl() -> index { return %vscale : index } -func.func @entry() attributes { enable_arm_streaming_ignore } { +func.func @entry() { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index %c2 = arith.constant 2 : index diff --git a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-write-2d.mlir b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-write-2d.mlir index 14dca2d4d708..84246606daa8 100644 --- a/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-write-2d.mlir +++ b/mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-write-2d.mlir @@ -1,7 +1,7 @@ // DEFINE: %{entry_point} = entry // DEFINE: %{compile} = mlir-opt %s \ -// DEFINE: -enable-arm-streaming="streaming-mode=streaming-locally za-mode=new-za" \ // DEFINE: -convert-vector-to-arm-sme -convert-arm-sme-to-scf -allocate-arm-sme-tiles \ +// DEFINE: -enable-arm-streaming="streaming-mode=streaming-locally za-mode=new-za only-if-required-by-ops" \ // DEFINE: -convert-arm-sme-to-llvm -cse -canonicalize \ // DEFINE: -test-lower-to-llvm // DEFINE: %{run} = %mcr_aarch64_cmd \ @@ -102,7 +102,7 @@ func.func @get_svl() -> index { return %vscale : index } -func.func @entry() attributes { enable_arm_streaming_ignore } { +func.func @entry() { %c0 = arith.constant 0 : index %c2 = arith.constant 2 : index %c4 = arith.constant 4 : index diff --git a/mlir/test/Target/LLVMIR/Import/function-attributes.ll b/mlir/test/Target/LLVMIR/Import/function-attributes.ll index bf9d746f6c0b..f76e72938096 100644 --- a/mlir/test/Target/LLVMIR/Import/function-attributes.ll +++ b/mlir/test/Target/LLVMIR/Import/function-attributes.ll @@ -212,6 +212,14 @@ define void @locally_streaming_func() "aarch64_pstate_sm_body" { // ----- +; CHECK-LABEL: @streaming_compatible_func +; CHECK-SAME: attributes {arm_streaming_compatible} +define void @streaming_compatible_func() "aarch64_pstate_sm_compatible" { + ret void +} + +// ----- + ; CHECK-LABEL: @section_func ; CHECK-SAME: attributes {section = ".section.name"} define void @section_func() section ".section.name" { diff --git a/mlir/test/Target/LLVMIR/Import/global-variables.ll b/mlir/test/Target/LLVMIR/Import/global-variables.ll index 56045d1ac18b..ab930084323c 100644 --- a/mlir/test/Target/LLVMIR/Import/global-variables.ll +++ b/mlir/test/Target/LLVMIR/Import/global-variables.ll @@ -270,3 +270,27 @@ define void @bar() { !7 = !DIGlobalVariableExpression(var: !6, expr: !DIExpression(DW_OP_constu, 3, DW_OP_plus)) !100 = !{i32 2, !"Debug Info Version", i32 3} !llvm.module.flags = !{!100} + +; // ----- + +; Nameless and scopeless global variable. + +; CHECK-DAG: #[[FILE:.*]] = #llvm.di_file +; CHECK-DAG: #[[COMPOSITE_TYPE:.*]] = #llvm.di_composite_type +; CHECK-DAG: #[[GLOBAL_VAR:.*]] = #llvm.di_global_variable<file = #[[FILE]], line = 268, type = #[[COMPOSITE_TYPE]], isLocalToUnit = true, isDefined = true> +; CHECK-DAG: #[[GLOBAL_VAR_EXPR:.*]] = #llvm.di_global_variable_expression<var = #[[GLOBAL_VAR]], expr = <>> + +; CHECK-DAG: llvm.mlir.global external constant @".str.1"() {addr_space = 0 : i32, dbg_expr = #[[GLOBAL_VAR_EXPR]]} + +@.str.1 = external constant [10 x i8], !dbg !0 + +!llvm.module.flags = !{!7} + +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) +!1 = distinct !DIGlobalVariable(scope: null, file: !2, line: 268, type: !3, isLocal: true, isDefinition: true) +!2 = !DIFile(filename: "source.c", directory: "/path/to/file") +!3 = !DICompositeType(tag: DW_TAG_array_type, baseType: !4, size: 80, elements: !6) +!4 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !5) +!5 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) +!6 = !{} +!7 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/mlir/test/Target/LLVMIR/llvmir-debug.mlir b/mlir/test/Target/LLVMIR/llvmir-debug.mlir index fe7f1b96d323..1133f57d6b61 100644 --- a/mlir/test/Target/LLVMIR/llvmir-debug.mlir +++ b/mlir/test/Target/LLVMIR/llvmir-debug.mlir @@ -292,6 +292,24 @@ llvm.mlir.global external @global_with_expr_2() {addr_space = 0 : i32, dbg_expr // ----- +// Nameless and scopeless global constant. + +// CHECK-LABEL: @.str.1 = external constant [10 x i8] +// CHECK-SAME: !dbg ![[GLOBAL_VAR_EXPR:.*]] +// CHECK-DAG: ![[GLOBAL_VAR_EXPR]] = !DIGlobalVariableExpression(var: ![[GLOBAL_VAR:.*]], expr: !DIExpression()) +// CHECK-DAG: ![[GLOBAL_VAR]] = distinct !DIGlobalVariable(scope: null, file: !{{[0-9]+}}, line: 268, type: !{{[0-9]+}}, isLocal: true, isDefinition: true) + +#di_basic_type = #llvm.di_basic_type<tag = DW_TAG_base_type, name = "char", sizeInBits = 8, encoding = DW_ATE_signed_char> +#di_file = #llvm.di_file<"file.c" in "/path/to/file"> +#di_derived_type = #llvm.di_derived_type<tag = DW_TAG_const_type, baseType = #di_basic_type> +#di_composite_type = #llvm.di_composite_type<tag = DW_TAG_array_type, baseType = #di_derived_type, sizeInBits = 80> +#di_global_variable = #llvm.di_global_variable<file = #di_file, line = 268, type = #di_composite_type, isLocalToUnit = true, isDefined = true> +#di_global_variable_expression = #llvm.di_global_variable_expression<var = #di_global_variable, expr = <>> + +llvm.mlir.global external constant @".str.1"() {addr_space = 0 : i32, dbg_expr = #di_global_variable_expression} : !llvm.array<10 x i8> + +// ----- + // CHECK-DAG: ![[FILE1:.*]] = !DIFile(filename: "foo1.mlir", directory: "/test/") #di_file_1 = #llvm.di_file<"foo1.mlir" in "/test/"> // CHECK-DAG: ![[FILE2:.*]] = !DIFile(filename: "foo2.mlir", directory: "/test/") diff --git a/mlir/test/Target/LLVMIR/llvmir.mlir b/mlir/test/Target/LLVMIR/llvmir.mlir index d9e7b790dd80..13e61b6ce10b 100644 --- a/mlir/test/Target/LLVMIR/llvmir.mlir +++ b/mlir/test/Target/LLVMIR/llvmir.mlir @@ -2306,6 +2306,20 @@ llvm.func @locally_streaming_func() attributes {arm_locally_streaming} { // ----- // +// arm_streaming_compatible attribute. +// + +// CHECK-LABEL: @streaming_compatible_func +// CHECK: #[[ATTR:[0-9]*]] +llvm.func @streaming_compatible_func() attributes {arm_streaming_compatible} { + llvm.return +} + +// CHECK: attributes #[[ATTR]] = { "aarch64_pstate_sm_compatible" } + +// ----- + +// // Zero-initialize operation. // diff --git a/mlir/unittests/Analysis/Presburger/IntegerRelationTest.cpp b/mlir/unittests/Analysis/Presburger/IntegerRelationTest.cpp index 287f7c7c5654..f390296da648 100644 --- a/mlir/unittests/Analysis/Presburger/IntegerRelationTest.cpp +++ b/mlir/unittests/Analysis/Presburger/IntegerRelationTest.cpp @@ -8,6 +8,7 @@ #include "mlir/Analysis/Presburger/IntegerRelation.h" #include "Parser.h" +#include "mlir/Analysis/Presburger/PresburgerSpace.h" #include "mlir/Analysis/Presburger/Simplex.h" #include <gmock/gmock.h> @@ -167,3 +168,42 @@ TEST(IntegerRelationTest, symbolicLexmax) { EXPECT_TRUE(lexmax3.unboundedDomain.isIntegerEmpty()); EXPECT_TRUE(lexmax3.lexopt.isEqual(expectedLexmax3)); } + +TEST(IntegerRelationTest, swapVar) { + PresburgerSpace space = PresburgerSpace::getRelationSpace(2, 1, 2, 0); + space.resetIds(); + + int identifiers[6] = {0, 1, 2, 3, 4}; + + // Attach identifiers to domain identifiers. + space.getId(VarKind::Domain, 0) = Identifier(&identifiers[0]); + space.getId(VarKind::Domain, 1) = Identifier(&identifiers[1]); + + // Attach identifiers to range identifiers. + space.getId(VarKind::Range, 0) = Identifier(&identifiers[2]); + + // Attach identifiers to symbol identifiers. + space.getId(VarKind::Symbol, 0) = Identifier(&identifiers[3]); + space.getId(VarKind::Symbol, 1) = Identifier(&identifiers[4]); + + IntegerRelation rel = + parseRelationFromSet("(x, y, z)[N, M] : (z - x - y == 0, x >= 0, N - x " + ">= 0, y >= 0, M - y >= 0)", + 2); + rel.setSpace(space); + // Swap (Domain 0, Range 0) + rel.swapVar(0, 2); + // Swap (Domain 1, Symbol 1) + rel.swapVar(1, 4); + + PresburgerSpace swappedSpace = rel.getSpace(); + + EXPECT_TRUE(swappedSpace.getId(VarKind::Domain, 0) + .isEqual(space.getId(VarKind::Range, 0))); + EXPECT_TRUE(swappedSpace.getId(VarKind::Domain, 1) + .isEqual(space.getId(VarKind::Symbol, 1))); + EXPECT_TRUE(swappedSpace.getId(VarKind::Range, 0) + .isEqual(space.getId(VarKind::Domain, 0))); + EXPECT_TRUE(swappedSpace.getId(VarKind::Symbol, 1) + .isEqual(space.getId(VarKind::Domain, 1))); +} diff --git a/mlir/unittests/Analysis/Presburger/MatrixTest.cpp b/mlir/unittests/Analysis/Presburger/MatrixTest.cpp index d05b05e004c5..508d4fa369c1 100644 --- a/mlir/unittests/Analysis/Presburger/MatrixTest.cpp +++ b/mlir/unittests/Analysis/Presburger/MatrixTest.cpp @@ -310,3 +310,71 @@ TEST(MatrixTest, intInverse) { EXPECT_EQ(det, 0); } + +TEST(MatrixTest, gramSchmidt) { + FracMatrix mat = + makeFracMatrix(3, 5, + {{Fraction(3, 1), Fraction(4, 1), Fraction(5, 1), + Fraction(12, 1), Fraction(19, 1)}, + {Fraction(4, 1), Fraction(5, 1), Fraction(6, 1), + Fraction(13, 1), Fraction(20, 1)}, + {Fraction(7, 1), Fraction(8, 1), Fraction(9, 1), + Fraction(16, 1), Fraction(24, 1)}}); + + FracMatrix gramSchmidt = makeFracMatrix( + 3, 5, + {{Fraction(3, 1), Fraction(4, 1), Fraction(5, 1), Fraction(12, 1), + Fraction(19, 1)}, + {Fraction(142, 185), Fraction(383, 555), Fraction(68, 111), + Fraction(13, 185), Fraction(-262, 555)}, + {Fraction(53, 463), Fraction(27, 463), Fraction(1, 463), + Fraction(-181, 463), Fraction(100, 463)}}); + + FracMatrix gs = mat.gramSchmidt(); + + EXPECT_EQ_FRAC_MATRIX(gs, gramSchmidt); + for (unsigned i = 0; i < 3u; i++) + for (unsigned j = i + 1; j < 3u; j++) + EXPECT_EQ(dotProduct(gs.getRow(i), gs.getRow(j)), 0); + + mat = makeFracMatrix(3, 3, + {{Fraction(20, 1), Fraction(17, 1), Fraction(10, 1)}, + {Fraction(20, 1), Fraction(18, 1), Fraction(6, 1)}, + {Fraction(15, 1), Fraction(14, 1), Fraction(10, 1)}}); + + gramSchmidt = makeFracMatrix( + 3, 3, + {{Fraction(20, 1), Fraction(17, 1), Fraction(10, 1)}, + {Fraction(460, 789), Fraction(1180, 789), Fraction(-2926, 789)}, + {Fraction(-2925, 3221), Fraction(3000, 3221), Fraction(750, 3221)}}); + + gs = mat.gramSchmidt(); + + EXPECT_EQ_FRAC_MATRIX(gs, gramSchmidt); + for (unsigned i = 0; i < 3u; i++) + for (unsigned j = i + 1; j < 3u; j++) + EXPECT_EQ(dotProduct(gs.getRow(i), gs.getRow(j)), 0); + + mat = makeFracMatrix( + 4, 4, + {{Fraction(1, 26), Fraction(13, 12), Fraction(34, 13), Fraction(7, 10)}, + {Fraction(40, 23), Fraction(34, 1), Fraction(11, 19), Fraction(15, 1)}, + {Fraction(21, 22), Fraction(10, 9), Fraction(4, 11), Fraction(14, 11)}, + {Fraction(35, 22), Fraction(1, 15), Fraction(5, 8), Fraction(30, 1)}}); + + gs = mat.gramSchmidt(); + + // The integers involved are too big to construct the actual matrix. + // but we can check that the result is linearly independent. + ASSERT_FALSE(mat.determinant(nullptr) == 0); + + for (unsigned i = 0; i < 4u; i++) + for (unsigned j = i + 1; j < 4u; j++) + EXPECT_EQ(dotProduct(gs.getRow(i), gs.getRow(j)), 0); + + mat = FracMatrix::identity(/*dim=*/10); + + gs = mat.gramSchmidt(); + + EXPECT_EQ_FRAC_MATRIX(gs, FracMatrix::identity(10)); +}
\ No newline at end of file diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel index 477e59e366d1..7770284e5543 100644 --- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel @@ -1801,6 +1801,7 @@ cc_library( ":BinaryFormat", ":BitReader", ":BitWriter", + ":CFGuard", ":CodeGenTypes", ":Core", ":DebugInfoCodeView", @@ -2551,6 +2552,7 @@ cc_library( deps = [ ":AggressiveInstCombine", ":Analysis", + ":CFGuard", ":CodeGen", ":Core", ":Coroutines", @@ -5003,6 +5005,7 @@ cc_binary( "utils/count/*.h", ]), stamp = 0, + deps = [":Support"], ) cc_binary( |