diff options
author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2024-04-27 20:26:09 +0200 |
---|---|---|
committer | GitHub <noreply@github.com> | 2024-04-27 20:26:09 +0200 |
commit | 738c135ee09de66a26805530d314c2f28d1eca02 (patch) | |
tree | 58d36cb0b09a42cf048518f7d0f9931f82a2c4a9 | |
parent | ff03f23be8bc6df701efd9e1093779fbcf382d87 (diff) |
SystemZ: Add more tests for fp128 atomics (#90269)
These did not have proper floating point uses so weren't representative
samples. The bitcast inserted by lowering could be absorbed by the
load/store on the source/use.
-rw-r--r-- | llvm/test/CodeGen/SystemZ/atomic-load-08.ll | 48 | ||||
-rw-r--r-- | llvm/test/CodeGen/SystemZ/atomic-store-08.ll | 51 | ||||
-rw-r--r-- | llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll | 42 |
3 files changed, 137 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-08.ll b/llvm/test/CodeGen/SystemZ/atomic-load-08.ll index 4d914e3ea0e1..83050ef87591 100644 --- a/llvm/test/CodeGen/SystemZ/atomic-load-08.ll +++ b/llvm/test/CodeGen/SystemZ/atomic-load-08.ll @@ -2,8 +2,8 @@ ; loads with a bitcast, and this test case gets converted into that form as ; well by the AtomicExpand pass. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefixes=CHECK,BASE %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck -check-prefixes=CHECK,Z13 %s define void @f1(ptr %ret, ptr %src) { ; CHECK-LABEL: f1: @@ -17,6 +17,34 @@ define void @f1(ptr %ret, ptr %src) { ret void } +define void @f1_fpuse(ptr %ret, ptr %src) { +; CHECK-LABEL: f1_fpuse: +; CHECK: # %bb.0: +; BASE-NEXT: aghi %r15, -176 +; BASE-NEXT: .cfi_def_cfa_offset 336 + +; CHECK-NEXT: lpq %r0, 0(%r3) + +; BASE-NEXT: stg %r1, 168(%r15) +; BASE-NEXT: stg %r0, 160(%r15) +; BASE-NEXT: ld %f0, 160(%r15) +; BASE-NEXT: ld %f2, 168(%r15) + +; Z13-NEXT: vlvgp %v0, %r0, %r1 +; Z13-NEXT: vrepg %v2, %v0, 1 + +; CHECK-NEXT: axbr %f0, %f0 +; CHECK-NEXT: std %f0, 0(%r2) +; CHECK-NEXT: std %f2, 8(%r2) +; BASE-NEXT: aghi %r15, 176 +; CHECK-NEXT: br %r14 + + %val = load atomic fp128, ptr %src seq_cst, align 16 + %use = fadd fp128 %val, %val + store fp128 %use, ptr %ret, align 8 + ret void +} + define void @f2(ptr %ret, ptr %src) { ; CHECK-LABEL: f2: ; CHECK: brasl %r14, __atomic_load@PLT @@ -24,3 +52,19 @@ define void @f2(ptr %ret, ptr %src) { store fp128 %val, ptr %ret, align 8 ret void } + +define void @f2_fpuse(ptr %ret, ptr %src) { +; CHECK-LABEL: f2_fpuse: +; CHECK: brasl %r14, __atomic_load@PLT +; CHECK-NEXT: ld %f0, 160(%r15) +; CHECK-NEXT: ld %f2, 168(%r15) +; CHECK-NEXT: axbr %f0, %f0 +; CHECK-NEXT: std %f0, 0(%r13) +; CHECK-NEXT: std %f2, 8(%r13) +; CHECK-NEXT: lmg %r13, %r15, 280(%r15) +; CHECK-NEXT: br %r14 + %val = load atomic fp128, ptr %src seq_cst, align 8 + %use = fadd fp128 %val, %val + store fp128 %use, ptr %ret, align 8 + ret void +} diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-08.ll b/llvm/test/CodeGen/SystemZ/atomic-store-08.ll index f7f4f4d967db..4d1693477f01 100644 --- a/llvm/test/CodeGen/SystemZ/atomic-store-08.ll +++ b/llvm/test/CodeGen/SystemZ/atomic-store-08.ll @@ -1,8 +1,8 @@ ; Test long double atomic stores. The atomic store is converted to i128 by ; the AtomicExpand pass. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefixes=CHECK,BASE %s +; xUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck -check-prefixes=CHECK,Z13 %s define void @f1(ptr %dst, ptr %src) { ; CHECK-LABEL: f1: @@ -17,6 +17,29 @@ define void @f1(ptr %dst, ptr %src) { ret void } +define void @f1_fpsrc(ptr %dst, ptr %src) { +; CHECK-LABEL: f1_fpsrc: +; CHECK: # %bb.0: +; CHECK-NEXT: ld %f0, 0(%r3) +; CHECK-NEXT: ld %f2, 8(%r3) +; CHECK-NEXT: axbr %f0, %f0 + +; BASE-NEXT: lgdr %r1, %f2 +; BASE-NEXT: lgdr %r0, %f0 + +; Z13-NEXT: vmrhg %v0, %v0, %v2 +; Z13-NEXT: vlgvg %r1, %v0, 1 +; Z13-NEXT: vlgvg %r0, %v0, 0 + +; CHECK-NEXT: stpq %r0, 0(%r2) +; CHECK-NEXT: bcr 15, %r0 +; CHECK-NEXT: br %r14 + %val = load fp128, ptr %src, align 8 + %add = fadd fp128 %val, %val + store atomic fp128 %add, ptr %dst seq_cst, align 16 + ret void +} + define void @f2(ptr %dst, ptr %src) { ; CHECK-LABEL: f2: ; CHECK: brasl %r14, __atomic_store@PLT @@ -24,3 +47,27 @@ define void @f2(ptr %dst, ptr %src) { store atomic fp128 %val, ptr %dst seq_cst, align 8 ret void } + +define void @f2_fpuse(ptr %dst, ptr %src) { +; CHECK-LABEL: f2_fpuse: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r14, %r15, 112(%r15) +; CHECK-NEXT: .cfi_offset %r14, -48 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: aghi %r15, -176 +; CHECK-NEXT: .cfi_def_cfa_offset 336 +; CHECK-NEXT: ld %f0, 0(%r3) +; CHECK-NEXT: ld %f2, 8(%r3) +; CHECK-NEXT: lgr %r3, %r2 +; CHECK-NEXT: axbr %f0, %f0 +; CHECK-NEXT: la %r4, 160(%r15) +; CHECK-NEXT: lghi %r2, 16 +; CHECK-NEXT: lhi %r5, 5 +; CHECK-NEXT: std %f0, 160(%r15) +; CHECK-NEXT: std %f2, 168(%r15) +; CHECK-NEXT: brasl %r14, __atomic_store@PLT + %val = load fp128, ptr %src, align 8 + %add = fadd fp128 %val, %val + store atomic fp128 %add, ptr %dst seq_cst, align 8 + ret void +} diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll index 18fa89e6ca6c..f5d8dc092a7e 100644 --- a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll +++ b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll @@ -26,3 +26,45 @@ define void @f1(ptr align 16 %ret, ptr align 16 %src, ptr align 16 %b) { store fp128 %res, ptr %ret, align 16 ret void } + +define void @f1_fpuse(ptr align 16 %ret, ptr align 16 %src, ptr align 16 %b) { +; CHECK-LABEL: f1_fpuse: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r12, %r15, 96(%r15) +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: aghi %r15, -176 +; CHECK-NEXT: .cfi_def_cfa_offset 336 +; CHECK-NEXT: ld %f0, 0(%r4) +; CHECK-NEXT: ld %f2, 8(%r4) +; CHECK-NEXT: lg %r0, 8(%r3) +; CHECK-NEXT: lg %r1, 0(%r3) +; CHECK-NEXT: axbr %f0, %f0 +; CHECK-NEXT: lgdr %r5, %f2 +; CHECK-NEXT: lgdr %r4, %f0 +; CHECK-NEXT: .LBB1_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: lgr %r12, %r1 +; CHECK-NEXT: lgr %r13, %r0 +; CHECK-NEXT: cdsg %r12, %r4, 0(%r3) +; CHECK-NEXT: lgr %r0, %r13 +; CHECK-NEXT: lgr %r1, %r12 +; CHECK-NEXT: jl .LBB1_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r1, 160(%r15) +; CHECK-NEXT: stg %r0, 168(%r15) +; CHECK-NEXT: ld %f0, 160(%r15) +; CHECK-NEXT: ld %f2, 168(%r15) +; CHECK-NEXT: axbr %f0, %f0 +; CHECK-NEXT: std %f0, 0(%r2) +; CHECK-NEXT: std %f2, 8(%r2) +; CHECK-NEXT: lmg %r12, %r15, 272(%r15) +; CHECK-NEXT: br %r14 + %val = load fp128, ptr %b, align 16 + %add.src = fadd fp128 %val, %val + %res = atomicrmw xchg ptr %src, fp128 %add.src seq_cst + %res.x2 = fadd fp128 %res, %res + store fp128 %res.x2, ptr %ret, align 16 + ret void +} |