diff options
author | Pengcheng Wang <wangpengcheng.pp@bytedance.com> | 2024-04-28 11:32:37 +0800 |
---|---|---|
committer | GitHub <noreply@github.com> | 2024-04-28 11:32:37 +0800 |
commit | f86d264dfdd6d1fa2fc6f933c9ae7b5db50a770b (patch) | |
tree | d26a9f1798cee1b7a846cf31fb49762efc53d87c | |
parent | 7037878d2b4afbda436ec61008ac907bd782bdd8 (diff) |
[RISCV] Add subtarget features for profiles
This may simplify the usage of tools like `opt`, `llc`, etc.
Reviewers: michaelmaitland, 4vtomat, preames, asb
Reviewed By: michaelmaitland, preames, 4vtomat
Pull Request: https://github.com/llvm/llvm-project/pull/84877
-rw-r--r-- | llvm/lib/Target/RISCV/RISCV.td | 6 | ||||
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVProfiles.td | 204 | ||||
-rw-r--r-- | llvm/test/CodeGen/RISCV/attributes.ll | 25 |
3 files changed, 235 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 9fb84efd5b6f..09f496574d64 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -15,6 +15,12 @@ include "llvm/Target/Target.td" include "RISCVFeatures.td" //===----------------------------------------------------------------------===// +// RISC-V profiles supported. +//===----------------------------------------------------------------------===// + +include "RISCVProfiles.td" + +//===----------------------------------------------------------------------===// // Named operands for CSR instructions. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td new file mode 100644 index 000000000000..5c13710faf65 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVProfiles.td @@ -0,0 +1,204 @@ +//===------ RISCVProfiles.td - RISC-V Profiles -------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +class RISCVProfile<string name, list<SubtargetFeature> features> + : SubtargetFeature<name, "Is" # NAME, "true", + "RISC-V " # name # " profile", features>; + +defvar RVI20U32Features = [Feature32Bit, FeatureStdExtI]; +defvar RVI20U64Features = [Feature64Bit, FeatureStdExtI]; + +defvar RVA20U64Features = [Feature64Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZicntr, + FeatureStdExtZiccif, + FeatureStdExtZiccrse, + FeatureStdExtZiccamoa, + FeatureStdExtZa128rs, + FeatureStdExtZicclsm]; + +defvar RVA20S64Features = !listconcat(RVA20U64Features, + [FeatureStdExtZifencei, + FeatureStdExtSvbare, + FeatureStdExtSvade, + FeatureStdExtSsccptr, + FeatureStdExtSstvecd, + FeatureStdExtSstvala]); + +defvar RVA22U64Features = [Feature64Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZicntr, + FeatureStdExtZiccif, + FeatureStdExtZiccrse, + FeatureStdExtZiccamoa, + FeatureStdExtZicclsm, + FeatureStdExtZa64rs, + FeatureStdExtZihpm, + FeatureStdExtZihintpause, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZic64b, + FeatureStdExtZicbom, + FeatureStdExtZicbop, + FeatureStdExtZicboz, + FeatureStdExtZfhmin, + FeatureStdExtZkt]; + +defvar RVA22S64Features = !listconcat(RVA22U64Features, + [FeatureStdExtZifencei, + FeatureStdExtSvbare, + FeatureStdExtSvade, + FeatureStdExtSsccptr, + FeatureStdExtSstvecd, + FeatureStdExtSstvala, + FeatureStdExtSscounterenw, + FeatureStdExtSvpbmt, + FeatureStdExtSvinval]); + +defvar RVA23U64Features = [Feature64Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZicntr, + FeatureStdExtZihpm, + FeatureStdExtZiccif, + FeatureStdExtZiccrse, + FeatureStdExtZiccamoa, + FeatureStdExtZicclsm, + FeatureStdExtZa64rs, + FeatureStdExtZihintpause, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZic64b, + FeatureStdExtZicbom, + FeatureStdExtZicbop, + FeatureStdExtZicboz, + FeatureStdExtZfhmin, + FeatureStdExtZkt, + FeatureStdExtV, + FeatureStdExtZvfhmin, + FeatureStdExtZvbb, + FeatureStdExtZvkt, + FeatureStdExtZihintntl, + FeatureStdExtZicond, + FeatureStdExtZimop, + FeatureStdExtZcmop, + FeatureStdExtZcb, + FeatureStdExtZfa, + FeatureStdExtZawrs]; + +defvar RVA23S64Features = !listconcat(RVA23U64Features, + [FeatureStdExtZifencei, + FeatureStdExtSvbare, + FeatureStdExtSvade, + FeatureStdExtSsccptr, + FeatureStdExtSstvecd, + FeatureStdExtSstvala, + FeatureStdExtSscounterenw, + FeatureStdExtSvpbmt, + FeatureStdExtSvinval, + FeatureStdExtSvnapot, + FeatureStdExtSstc, + FeatureStdExtSscofpmf, + FeatureStdExtSsnpm, + FeatureStdExtSsu64xl, + FeatureStdExtH, + FeatureStdExtSsstateen, + FeatureStdExtShcounterenw, + FeatureStdExtShvstvala, + FeatureStdExtShtvala, + FeatureStdExtShvstvecd, + FeatureStdExtShvsatpa, + FeatureStdExtShgatpa]); + +defvar RVB23U64Features = [Feature64Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZicntr, + FeatureStdExtZihpm, + FeatureStdExtZiccif, + FeatureStdExtZiccrse, + FeatureStdExtZiccamoa, + FeatureStdExtZicclsm, + FeatureStdExtZa64rs, + FeatureStdExtZihintpause, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZic64b, + FeatureStdExtZicbom, + FeatureStdExtZicbop, + FeatureStdExtZicboz, + FeatureStdExtZkt, + FeatureStdExtZihintntl, + FeatureStdExtZicond, + FeatureStdExtZimop, + FeatureStdExtZcmop, + FeatureStdExtZcb, + FeatureStdExtZfa, + FeatureStdExtZawrs]; + +defvar RVB23S64Features = !listconcat(RVB23U64Features, + [FeatureStdExtZifencei, + FeatureStdExtSvnapot, + FeatureStdExtSvbare, + FeatureStdExtSvade, + FeatureStdExtSsccptr, + FeatureStdExtSstvecd, + FeatureStdExtSstvala, + FeatureStdExtSscounterenw, + FeatureStdExtSvpbmt, + FeatureStdExtSvinval, + FeatureStdExtSstc, + FeatureStdExtSscofpmf, + FeatureStdExtSsu64xl]); + +defvar RVM23U32Features = [Feature32Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZicond, + FeatureStdExtZihintpause, + FeatureStdExtZihintntl, + FeatureStdExtZce, + FeatureStdExtZicbop, + FeatureStdExtZimop, + FeatureStdExtZcmop]; + +def RVI20U32 : RISCVProfile<"rvi20u32", RVI20U32Features>; +def RVI20U64 : RISCVProfile<"rvi20u64", RVI20U64Features>; +def RVA20U64 : RISCVProfile<"rva20u64", RVA20U64Features>; +def RVA20S64 : RISCVProfile<"rva20s64", RVA20S64Features>; +def RVA22U64 : RISCVProfile<"rva22u64", RVA22U64Features>; +def RVA22S64 : RISCVProfile<"rva22s64", RVA22S64Features>; +def RVA23U64 : RISCVProfile<"rva23u64", RVA23U64Features>; +def RVA23S64 : RISCVProfile<"rva23s64", RVA23S64Features>; +def RVB23U64 : RISCVProfile<"rvb23u64", RVB23U64Features>; +def RVB23S64 : RISCVProfile<"rvb23s64", RVB23S64Features>; +def RVM23U32 : RISCVProfile<"rvm23u32", RVM23U32Features>; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 141d5ea41828..7bd3440c9dc0 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -256,6 +256,19 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s +; Tests for profile features. +; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s +; RUN: llc -mtriple=riscv64 -mattr=+rvi20u64 %s -o - | FileCheck --check-prefix=RVI20U64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva20u64 %s -o - | FileCheck --check-prefix=RVA20U64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva20s64 %s -o - | FileCheck --check-prefix=RVA20S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva22u64 %s -o - | FileCheck --check-prefix=RVA22U64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva22s64 %s -o - | FileCheck --check-prefix=RVA22S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva23u64 %s -o - | FileCheck --check-prefix=RVA23U64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva23s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rvb23u64 %s -o - | FileCheck --check-prefix=RVB23U64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rvb23s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s +; RUN: llc -mtriple=riscv32 -mattr=+rvm23u32 %s -o - | FileCheck --check-prefix=RVM23U32 %s + ; CHECK: .attribute 4, 16 ; RV32M: .attribute 5, "rv32i2p1_m2p0" @@ -512,6 +525,18 @@ ; RV64SUPM: .attribute 5, "rv64i2p1_supm0p8" ; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0" +; RVI20U32: .attribute 5, "rv32i2p1" +; RVI20U64: .attribute 5, "rv64i2p1" +; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_za128rs1p0" +; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_za128rs1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0" +; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" +; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0" +; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm0p8_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" +; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +; RVM23U32: .attribute 5, "rv32i2p1_m2p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0" + define i32 @addi(i32 %a) { %1 = add i32 %a, 1 ret i32 %1 |