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authorJaved Absar <javed.absar@arm.com>2017-07-18 10:19:48 +0000
committerJaved Absar <javed.absar@arm.com>2017-07-18 10:19:48 +0000
commit937f85f25c67b5210104795463f73ad4546e7a7d (patch)
tree34e54260a25da2e64201e01d42558259b861a7c2 /include
parent465af92acd90ba606fad38c3d78b8b988f1ad52c (diff)
[ARM|CodeGen] Improve the code in FastISel
Cleaned up the code in FastISel a bit. Had to add make_range to MCInstrDesc as that was needed and seems missing. Reviewed by: @t.p.northover Differential Revision: https://reviews.llvm.org/D35494 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308291 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r--include/llvm/MC/MCInstrDesc.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/include/llvm/MC/MCInstrDesc.h b/include/llvm/MC/MCInstrDesc.h
index 340d8253b8c9..9150a8b5c80a 100644
--- a/include/llvm/MC/MCInstrDesc.h
+++ b/include/llvm/MC/MCInstrDesc.h
@@ -209,6 +209,15 @@ public:
/// well.
unsigned getNumOperands() const { return NumOperands; }
+ using const_opInfo_iterator = const MCOperandInfo *;
+
+ const_opInfo_iterator opInfo_begin() const { return OpInfo; }
+ const_opInfo_iterator opInfo_end() const { return OpInfo + NumOperands; }
+
+ iterator_range<const_opInfo_iterator> operands() const {
+ return make_range(opInfo_begin(), opInfo_end());
+ }
+
/// \brief Return the number of MachineOperands that are register
/// definitions. Register definitions always occur at the start of the
/// machine operand list. This is the number of "outs" in the .td file,