diff options
author | Alex Bradbury <asb@lowrisc.org> | 2018-01-03 08:53:05 +0000 |
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committer | Alex Bradbury <asb@lowrisc.org> | 2018-01-03 08:53:05 +0000 |
commit | d32868dc00137460b19d8554d94bbf63f2e24e4e (patch) | |
tree | 70d4f2b9580a1277d894d114c6e14f1c7eab255a /include | |
parent | caeab26ff8462ab82091fb0089c4c876c97e99fd (diff) |
Thread MCSubtargetInfo through Target::createMCAsmBackend
Currently it's not possible to access MCSubtargetInfo from a TgtMCAsmBackend.
D20830 threaded an MCSubtargetInfo reference through
MCAsmBackend::relaxInstruction, but this isn't the only function that would
benefit from access. This patch removes the Triple and CPUString arguments
from createMCAsmBackend and replaces them with MCSubtargetInfo.
This patch just changes the interface without making any intentional
functional changes. Once in, several cleanups are possible:
* Get rid of the awkward MCSubtargetInfo handling in ARMAsmBackend
* Support 16-bit instructions when valid in MipsAsmBackend::writeNopData
* Get rid of the CPU string parsing in X86AsmBackend and just use a SubtargetFeature for HasNopl
* Emit 16-bit nops in RISCVAsmBackend::writeNopData if the compressed instruction set extension is enabled (see D41221)
This change initially exposed PR35686, which has since been resolved in r321026.
Differential Revision: https://reviews.llvm.org/D41349
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321692 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/Support/TargetRegistry.h | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/include/llvm/Support/TargetRegistry.h b/include/llvm/Support/TargetRegistry.h index bd096e2f74f6..cc0d55722c8b 100644 --- a/include/llvm/Support/TargetRegistry.h +++ b/include/llvm/Support/TargetRegistry.h @@ -123,8 +123,8 @@ public: using AsmPrinterCtorTy = AsmPrinter *(*)( TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer); using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T, + const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, const MCTargetOptions &Options); using MCAsmParserCtorTy = MCTargetAsmParser *(*)( const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII, @@ -383,13 +383,12 @@ public: /// createMCAsmBackend - Create a target specific assembly parser. /// /// \param TheTriple The target triple string. - MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI, - StringRef TheTriple, StringRef CPU, - const MCTargetOptions &Options) - const { + MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI, + const MCTargetOptions &Options) const { if (!MCAsmBackendCtorFn) return nullptr; - return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU, Options); + return MCAsmBackendCtorFn(*this, STI, MRI, Options); } /// createMCAsmParser - Create a target specific assembly parser. @@ -1106,10 +1105,10 @@ template <class MCAsmBackendImpl> struct RegisterMCAsmBackend { } private: - static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI, - const Triple &TheTriple, StringRef CPU, + static MCAsmBackend *Allocator(const Target &T, const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI, const MCTargetOptions &Options) { - return new MCAsmBackendImpl(T, MRI, TheTriple, CPU); + return new MCAsmBackendImpl(T, STI, MRI); } }; |