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authorHans Wennborg <hans@hanshq.net>2017-08-22 17:44:59 +0000
committerHans Wennborg <hans@hanshq.net>2017-08-22 17:44:59 +0000
commit9347fa6ce8be09d54431705d1604c74f409ef560 (patch)
tree5b2904447fcd95f7ef4cdefe2b750cac279da6be /lib/Target
parenteb7354c3b1163ff060c181ff3b49d4a7a24efe5b (diff)
Merging r311263:
------------------------------------------------------------------------ r311263 | ctopper | 2017-08-19 15:02:02 -0700 (Sat, 19 Aug 2017) | 1 line [AVX512] Use alignedstore256 in a pattern that's emitting a 256-bit movaps from an extract subvector operation. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@311478 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/X86/X86InstrAVX512.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td
index 0e654a380e7c..0ae960e7d566 100644
--- a/lib/Target/X86/X86InstrAVX512.td
+++ b/lib/Target/X86/X86InstrAVX512.td
@@ -3619,8 +3619,8 @@ let Predicates = [HasVLX] in {
def : Pat<(alignedstore256 (v4f64 (extract_subvector
(v8f64 VR512:$src), (iPTR 0))), addr:$dst),
(VMOVAPDZ256mr addr:$dst, (v4f64 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
- def : Pat<(alignedstore (v8f32 (extract_subvector
- (v16f32 VR512:$src), (iPTR 0))), addr:$dst),
+ def : Pat<(alignedstore256 (v8f32 (extract_subvector
+ (v16f32 VR512:$src), (iPTR 0))), addr:$dst),
(VMOVAPSZ256mr addr:$dst, (v8f32 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
def : Pat<(alignedstore256 (v4i64 (extract_subvector
(v8i64 VR512:$src), (iPTR 0))), addr:$dst),