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| author | Hans Wennborg <hans@hanshq.net> | 2017-08-23 20:03:43 +0000 |
|---|---|---|
| committer | Hans Wennborg <hans@hanshq.net> | 2017-08-23 20:03:43 +0000 |
| commit | a8f7dd91f2af0f28318ec7d232b41db13905d9cf (patch) | |
| tree | 1451550bf2b9aeedba5a43e030d4a15d5b55ae52 /lib/Target | |
| parent | f018f9fea556677c15df970fd5b3f029136a715e (diff) | |
Merging r311572:
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r311572 | ctopper | 2017-08-23 09:41:02 -0700 (Wed, 23 Aug 2017) | 9 lines
[AVX512] Don't create SHRUNKBLEND SDNodes for 512-bit vectors
There are no 512-bit blend instructions so we shouldn't create SHRUNKBLEND for them.
On a side note, it looks like there may be a missed opportunity for constant folding TESTM when LHS and RHS are equal.
This fixes PR34139.
Differential Revision: https://reviews.llvm.org/D36992
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@311593 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 9c9eccfbb655..193ee8de6192 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -30629,6 +30629,9 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG, // Byte blends are only available in AVX2 if (VT == MVT::v32i8 && !Subtarget.hasAVX2()) return SDValue(); + // There are no 512-bit blend instructions that use sign bits. + if (VT.is512BitVector()) + return SDValue(); assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); APInt DemandedMask(APInt::getSignMask(BitWidth)); |